; -------------------------------------------------------------------------------- ; @Title: S32G2 On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2024-03-13 KRZ ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: Generated (TRACE32, build: 167562.), based on: ; S32G274A_A53.svd (Ver. 2.2), S32G274A_M7.svd (Ver. 2.2) ; @Core: Cortex-A53, Cortex-M7F ; @Chip: S32G233A-A53, S32G233A-M0-0, S32G233A-M0-1, S32G233A-M0-2 ; S32G233A-M0-3, S32G233A-M7, S32G234M-M0-0, S32G234M-M0-1 ; S32G234M-M0-2, S32G234M-M0-3, S32G234M-M7, S32G254A-A53 ; S32G254A-M0-0, S32G254A-M0-1, S32G254A-M0-2, S32G254A-M0-3 ; S32G254A-M7, S32G274A-A53, S32G274A-M0-0, S32G274A-M0-1 ; S32G274A-M0-2, S32G274A-M0-3, S32G274A-M7 ; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; Copyright 2016-2023 NXP ; ; NXP Confidential. This software is owned or controlled by NXP and may ; only be used strictly in accordance with the applicable license terms. ; By expressly accepting such terms or by downloading, installing, ; activating and/or otherwise using the software, you are agreeing that ; you have read, and that you agree to comply with and are bound by, ; such license terms. If you do not agree to be bound by the applicable ; license terms, then you may not retain, install, activate or otherwise ; use the software. ; -------------------------------------------------------------------------------- ; $Id: pers32g2.per 17627 2024-03-13 12:49:55Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (CORENAME()=="CORTEXM7F") tree.close "Core Registers (Cortex-M7F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes" bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes" bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes" textline " " bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..." bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..." bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes" textline " " bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes" bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes" bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes" textline " " bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes" bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes" textline "" group.long 0x10++0x03 line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" group.long 0x14++0x07 line.long 0x00 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x04 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPUID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..." group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control and State Register" bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active" setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" textline " " rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled" rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt" textline " " rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent" hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key" rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian" bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration and Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored" bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled" bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x13 line.long 0x00 "HFSR,HardFault Status Register" eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred" eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred" eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred" eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred" eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred" line.long 0x08 "MMFAR,MemManage Fault Address Register" line.long 0x0C "BFAR,BusFault Address Register" line.long 0x10 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Triggered Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" tree "Memory System" width 10. rgroup.long 0xD78++0x0B line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..." bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..." textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..." bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..." bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..." textline " " bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..." bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..." bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..." line.long 0x04 "CTR,Cache Type Register" bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..." bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..." textline " " bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CCSIDR,Cache Size ID Register" bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported" bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported" bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported" textline " " bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported" hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1" hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1" textline " " bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512" group.long 0xD84++0x03 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..." bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction" wgroup.long 0xF50++0x03 line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification" wgroup.long 0xF58++0x1F line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU" line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)" line.long 0x08 "DCISW,Data cache invalidate by set/way" line.long 0x0C "DCCMVAU,Data cache by address to PoU" line.long 0x10 "DCCMVAC,Data cache clean by address to PoC" line.long 0x14 "DCCSW,Data cache clean by set/way" line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC" line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way" group.long 0xF90++0x13 line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register" bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled" bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register" bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled" bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x08 "AHBPCR,AHBP control register" bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..." bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled" line.long 0x0C "CACR,L1 Cache Control Register" bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled" bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes" bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled" line.long 0x10 "AHBSCR,AHB Slave Control Register" bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion" bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI" group.long 0xFA8++0x03 line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register" bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR" bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred" bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred" group.long 0xFB0++0x03 line.long 0x00 "IEBR0,Instruction Error bank Register 0" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFB4++0x03 line.long 0x00 "IEBR1,Instruction Error bank Register 1" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFB8++0x03 line.long 0x00 "DEBR0,Data Error bank Register 0" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFBC++0x03 line.long 0x00 "DEBR1,Data Error bank Register 1" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" tree.end tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end tree "CoreSight Identification Registers" width 6. rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM7F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" newline bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" newline bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" newline bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x0B line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." newline bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." newline bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." newline bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." line.long 0x08 "MVFR2,Media and FP Feature Register 2" bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..." width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x03 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" newline if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" newline rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" newline bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" newline bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" newline bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" newline bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count register" line.long 0x08 "DWT_CPICNT,CPI Count register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" newline group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXA53") tree "Core Registers (Cortex-A53)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x0 line.long 0x0 "MIDR_EL1,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" newline hexmask.long.word 0x0 4.--15. 0x1 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field" newline bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.quad SPR:0x30006++0x0 line.long 0x0 "REVIDR_EL1,Revision ID Register" rgroup.quad SPR:0x30014++0x00 line.long 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30015++0x00 line.long 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad SPR:0x30016++0x00 line.long 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad SPR:0x30017++0x00 line.long 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,Reserved,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.long 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30071++0x00 line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1" endif rgroup.quad SPR:0x30020++0x00 line.long 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.quad SPR:0x30021++0x00 line.long 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30022++0x00 line.long 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30023++0x00 line.long 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30024++0x00 line.long 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30025++0x00 line.long 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30061++0x00 line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1" endif rgroup.quad SPR:0x30010++0x00 line.long 0x00 "ID_PFR0_EL1,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30011++0x00 line.long 0x00 "ID_PFR1_EL1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..." bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..." newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30041++0x00 line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1" endif if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x30012++0x00 line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x30012++0x00 line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30051++0x00 line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1" rgroup.quad spr:0x30054++0x00 line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0" rgroup.quad spr:0x30055++0x00 line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1" endif rgroup.quad SPR:0x30013++0x00 line.long 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0" rgroup.quad SPR:0x31007++0x00 line.long 0x00 "AIDR_EL1,Auxiliary ID Register" rgroup.quad SPR:0x33007++0x00 line.long 0x00 "DCZID_EL0,Data Cache Zero ID" bitfld.long 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited" bitfld.long 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" group.quad SPR:0x30100++0x0 line.long 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.long 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.long 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x34100++0x0 line.long 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x36100++0x0 line.long 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" rgroup.quad SPR:0x30101++0x0 line.long 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)" group.quad SPR:0x34101++0x0 line.long 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x36101++0x0 line.long 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x30102++0x00 line.long 0x00 "CPACR_EL1,Architectural Feature Access Control Register" bitfld.long 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..." bitfld.long 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped" group.quad SPR:0x36110++0x0 line.long 0x0 "SCR_EL3,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled" bitfld.long 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" tree.open "Exception Syndrome Registers" if (CORENAME()=="CORTEXA57") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif elif (CORENAME()=="CORTEXA53") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SES,System Error Source" "Processor,System,External," newline hexmask.long.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif endif tree.end newline if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address" rgroup.quad SPR:0x30C10++0x00 line.long 0x00 "ISR_EL1,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.quad SPR:0x36C02++0x00 line.long 0x00 "RMR_EL3,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]" endif group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID Register" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID Register" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID Register" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID Register" tree.end tree "Memory Management Unit" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB" newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad SPR:0x34300++0x00 line.long 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif rgroup.quad SPR:0x30510++0x00 line.long 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" rgroup.quad SPR:0x34510++0x00 line.long 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" rgroup.quad SPR:0x36510++0x00 line.long 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" rgroup.quad SPR:0x30511++0x00 line.long 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" rgroup.quad SPR:0x34511++0x00 line.long 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" rgroup.quad SPR:0x36511++0x00 line.long 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..." newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" newline bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" rgroup.quad spr:0x30A30++0x00 line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)" rgroup.quad spr:0x34A30++0x00 line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)" rgroup.quad spr:0x36A30++0x00 line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)" tree.end newline group.quad SPR:0x30D01++0x00 line.long 0x0 "CONTEXTIDR_EL1,Context ID Register" tree.end tree "Virtualization Extensions" group.quad SPR:0x34000++0x0 line.long 0x0 "VPIDR_EL2,Virtualization Processor ID Register" if (CORENAME()=="CORTEXA57") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" endif group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34111++0x00 line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34111++0x00 line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6" endif group.quad SPR:0x34112++0x00 line.long 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x36131++0x00 line.long 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes" bitfld.long 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" group.quad SPR:0x36112++0x00 line.long 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x34113++0x00 line.long 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..." bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped" bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped" newline bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped" bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped" bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped" newline bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped" bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped" bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped" newline bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped" bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped" bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped" newline bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped" bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped" bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped" rgroup.quad SPR:0x34117++0x00 line.long 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34212++0x00 line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.long 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34212++0x00 line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..." bitfld.long 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..." bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits" tree.end tree "Cache Control and Configuration" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif group.quad SPR:0x32000++0x0 line.long 0x0 "CSSELR_EL1,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x31001++0x0 line.long 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Read-Allocate" "Reserved,Supported" newline bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x31001++0x0 line.long 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "1Reserved,Reserved,64 bytes,?..." endif tree "Level 1 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x30F10++0x00 line.long 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register" group.quad SPR:0x30F11++0x00 line.long 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register" group.quad SPR:0x30F12++0x00 line.long 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register" group.quad SPR:0x30F13++0x00 line.long 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register" group.quad SPR:0x30F00++0x00 line.long 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register" group.quad SPR:0x30F01++0x00 line.long 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register" group.quad SPR:0x30F02++0x00 line.long 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register" group.quad SPR:0x30F03++0x00 line.long 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register" group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" newline bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" newline bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" newline bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" newline bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" newline bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" newline bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8" bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" endif if (CORENAME()=="CORTEXA57") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" endif tree.end tree "Level 2 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x31B02++0x0 line.long 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented" newline rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..." bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" newline bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.quad SPR:0x31B03++0x0 line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" newline bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" newline bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" newline bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x31B02++0x0 line.long 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.quad SPR:0x31B03++0x0 line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3" bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled" bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled" newline bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.quad SPR:0x339C0++0x00 line.long 0x0 "PMCR_EL0,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad SPR:0x339C1++0x00 line.long 0x00 "PMCNTENSET_EL0,Count Enable Set Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.quad SPR:0x339C2++0x00 line.long 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Event Counter 27 clear bit" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Event Counter 26 clear bit" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 clear bit" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Event Counter 23 clear bit" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 clear bit" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Event Counter 21 clear bit" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Event Counter 19 clear bit" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 clear bit" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 clear bit" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Event Counter 16 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.quad SPR:0x339C3++0x00 line.long 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled" wgroup.quad SPR:0x339C4++0x00 line.long 0x00 "PMSWINC_EL0,Performance Monitor Software Increment" bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment" newline bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment" bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment" newline bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment" bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment" newline bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment" bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment" newline bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment" newline bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment" bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.quad SPR:0x339C5++0x00 line.long 0x00 "PMSELR_EL0,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x339C6++0x0 line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" newline bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" newline bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x339C6++0x0 line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" newline bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" newline bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" newline bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" newline bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" newline bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" newline bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" newline bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" endif rgroup.quad SPR:0x339C7++0x0 line.long 0x00 "PMCEID1_EL0,Common Event Identification Register 1" bitfld.long 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented" tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register" group.quad SPR:0x339D1++0x00 line.long 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" group.quad SPR:0x339D2++0x00 line.long 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register" group.quad SPR:0x339E0++0x00 line.long 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.quad SPR:0x309E1++0x00 line.long 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad SPR:0x309E2++0x00 line.long 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.quad SPR:0x339E3++0x00 line.long 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register" group.quad SPR:(0x33E80+0x0)++0x00 line.long 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad SPR:(0x33EC0+0x0)++0x00 line.long 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x1)++0x00 line.long 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad SPR:(0x33EC0+0x1)++0x00 line.long 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x2)++0x00 line.long 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad SPR:(0x33EC0+0x2)++0x00 line.long 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x3)++0x00 line.long 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad SPR:(0x33EC0+0x3)++0x00 line.long 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x4)++0x00 line.long 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad SPR:(0x33EC0+0x4)++0x00 line.long 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x5)++0x00 line.long 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad SPR:(0x33EC0+0x5)++0x00 line.long 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:0x33EF7++0x00 line.long 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad SPR:0x33E00++0x00 line.long 0x00 "CNTFRQ_EL0,Counter Frequency Register" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register" group.quad SPR:0x30E10++0x00 line.long 0x00 "CNTKCTL_EL1,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x33E20++0x00 line.long 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register" group.quad SPR:0x33E21++0x00 line.long 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad SPR:0x33E30++0x00 line.long 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register" group.quad SPR:0x33E31++0x00 line.long 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register" group.quad SPR:0x34E10++0x00 line.long 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x34E20++0x00 line.long 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register" group.quad SPR:0x34E21++0x00 line.long 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register" group.quad SPR:0x37E20++0x00 line.long 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register" group.quad SPR:0x37E21++0x00 line.long 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.q(spr:0x30CB6))&0x10000000000)==0x00) wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)" rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register" bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register" if (((per.q(spr:0x30CC4))&0x3800)==0x00) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" elif (((per.q(spr:0x30CC4))&0x3800)==0x800) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" endif hgroup.quad spr:0x30C80++0x00 hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad SPR:0x30CC6++0x00 line.long 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x30CC7++0x00 line.long 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)" bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x36CC7++0x00 line.long 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)" bitfld.long 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad SPR:0x30460++0x00 line.long 0x00 "ICC_PMR_EL1,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad SPR:0x30CB3++0x00 line.long 0x00 "ICC_RPR_EL1,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" if (((per.q(spr:0x30CB7))&0x10000000000)==0x00) wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated." else wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif if (((per.q(spr:0x30CB5))&0x10000000000)==0x00) wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad SPR:0x30CC5++0x00 line.long 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x34C95++0x00 line.long 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x36CC5++0x00 line.long 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" tree.end tree "AArch64 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.quad SPR:0x34C80++0x00 line.long 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" if (CORENAME()=="CORTEXA53") group.quad SPR:0x34C90++0x00 line.long 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" endif tree.end newline rgroup.quad SPR:0x34CB3++0x00 line.long 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.quad SPR:0x34CB5++0x00 line.long 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.quad SPR:0x34CB0++0x00 line.long 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif rgroup.quad SPR:0x34CB2++0x00 line.long 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.quad SPR:0x34CB7++0x00 line.long 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.quad SPR:0x34C94++0x00 line.long 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register" rgroup.quad SPR:0x34CB1++0x00 line.long 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" rgroup.quad SPR:0x23010++0x00 line.long 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad SPR:0x20020++0x00 line.long 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register" bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" rgroup.quad SPR:0x23050++0x00 line.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" wgroup.quad SPR:0x23050++0x00 line.long 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad SPR:0x24070++0x00 line.long 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.long 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High" newline bitfld.long 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High" bitfld.long 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High" newline bitfld.long 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High" bitfld.long 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High" bitfld.long 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High" bitfld.long 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High" group.quad SPR:0x20002++0x00 line.long 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20022++0x00 line.long 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Save/restore bit" "Low,High" bitfld.long 0x00 26. "TXU,Save/restore bit" "Low,High" newline bitfld.long 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3" bitfld.long 0x00 21. "TDA,Save/restore bit" "Low,High" bitfld.long 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.long 0x00 14. "HDE,Save/restore bit" "Low,High" newline bitfld.long 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.long 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled" bitfld.long 0x00 6. "ERR,Save/restore bit" "Low,High" bitfld.long 0x00 0. "SS,Software step control" "Disabled,Enabled" group.quad SPR:0x20032++0x00 line.long 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20062++0x00 line.long 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad SPR:0x20104++0x00 line.long 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.long 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad SPR:0x20114++0x00 line.long 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.long 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.long 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..." group.quad SPR:0x20134++0x00 line.long 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad SPR:0x20144++0x00 line.long 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes" group.quad SPR:0x20786++0x00 line.long 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad SPR:0x20796++0x00 line.long 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.quad SPR:0x207E6++0x00 line.long 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" group.quad SPR:0x33450++0x00 line.long 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" group.quad spr:0x33451++0x00 line.quad 0x00 "DLR_EL0,Debug Link Register" tree.end tree "Breakpoint Registers" if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x0)++0x0 line.long 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x10)++0x0 line.long 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x20)++0x0 line.long 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x30)++0x0 line.long 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x40)++0x0 line.long 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x50)++0x0 line.long 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0" line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1" line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2" line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3" line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0000++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif if corename()=="CORTEXA57" rgroup.long c15:0x0300++0x0 line.long 0x0 "TLBTR,TLB Type Register" endif if corename()=="CORTEXA57" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4" elif corename()=="CORTEXA53" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..." hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.long c15:0x0600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,ID_MMFR4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if corename()=="CORTEXA57" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif group.long c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" if corename()=="CORTEXA57" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" elif corename()=="CORTEXA53" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented" endif group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" tree.end tree "System Control and Configuration" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" else group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" endif group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" newline bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" newline bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" newline bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" newline bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" newline bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" newline bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" newline bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" endif if corename()=="CORTEXA57" group.long c15:0x0201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes" newline bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" elif corename()=="CORTEXA53" group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full" newline bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full" endif group.long c15:0x0011++0x0 line.long 0x00 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" if corename()=="CORTEXA57" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" elif corename()=="CORTEXA53" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" endif rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif endif if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" if corename()=="CORTEXA57" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]" elif corename()=="CORTEXA53" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]" endif group.long c15:0x000D++0x00 line.long 0x00 "FCSEIDR,FCSE Process ID register" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register" tree.end tree "Memory Management Unit" if corename()=="CORTEXA57" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) // MPIDR[31]==1 case is missing here for TTBR0 and TTBR1 group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" endif if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" endif elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" else group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address" bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address" bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" endif endif if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" else group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" endif tree.open "Memory Attribute Indirection Registers" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" newline bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline endif tree.end newline if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" else group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier" endif tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x0 line.long 0x00 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" if corename()=="CORTEXA57" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" newline bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" newline bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" newline bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted" newline bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" newline bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" elif corename()=="CORTEXA53" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" newline bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" newline bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" newline bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" newline bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" newline bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted" bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override" newline bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override" newline bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" newline bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" endif group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..." newline bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" newline bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..." newline hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13" bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High" bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register" group.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address" tree.open "Hypervisor Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" tree.end newline group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT" newline bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." if corename()=="CORTEXA57" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." endif rgroup.long c15:0x1700++0x0 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" newline bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..." group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" tree "Level 1 memory system" if corename()=="CORTEXA57" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x030F++0x00 line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register" wgroup.long c15:0x04F++0x00 line.long 0x00 "RAMINDEX,RAM Index Operation Register" elif corename()=="CORTEXA53" rgroup.long c15:0x300F++0x00 line.long 0x00 "CDBGDR0,Cache Debug Data Register 0" rgroup.long c15:0x310F++0x00 line.long 0x00 "CDBGDR1,Cache Debug Data Register 1" rgroup.long c15:0x320F++0x00 line.long 0x00 "CDBGDR2,Cache Debug Data Register 2" rgroup.long c15:0x330F++0x00 line.long 0x00 "CDBGDR3,Cache Debug Data Register 3" wgroup.long c15:0x302F++0x00 line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register" wgroup.long c15:0x312F++0x00 line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register" wgroup.long c15:0x304F++0x00 line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register" wgroup.long c15:0x314F++0x00 line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register" wgroup.long c15:0x324F++0x00 line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register" endif tree.end tree "Level 2 memory system" if corename()=="CORTEXA57" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" newline rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported" bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled" rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" newline rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present" newline bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" newline rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" newline bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" newline bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" newline bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" newline bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" newline bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif corename()=="CORTEXA53" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" newline rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" newline group.long c15:0x1c9++0x00 line.long 0x00 "PMNCNTENSET,Count Enable Set Register " bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled" eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled" eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled" eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled" eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow" eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow" eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow" eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow" newline eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow" eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow" eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow" eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow" eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow" newline eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow" eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow" eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow" eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow" eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow" newline eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow" eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow" eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow" eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow" eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow" newline eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow" eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow" eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow" eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow" eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow" newline eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow" eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" newline eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment" bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment" newline bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment" bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment" newline bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment" bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment" newline bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment" bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment" bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment" newline bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" newline bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x40)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x40)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x40)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x40)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x40)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x40)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported" rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register" if (((per.l(c15:0x4CC))&0x3800)==0x00) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" elif (((per.l(c15:0x4CC))&0x3800)==0x800) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" endif hgroup.long c15:0x008C++0x00 hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" in hgroup.long c15:0x00CC++0x00 hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" in group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" if corename()=="CORTEXA53" group.long c15:0x459C++0x00 line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" endif group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x459C++0x00 line.long 0x00 "ICH_SRE,Hypervisor System Register" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" if corename()=="CORTEXA57" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" elif corename()=="CORTEXA53" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" newline bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number" endif rgroup.long c14:0x0060++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" group.long c14:0x0070++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.long c14:0x0200++0x0 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" group.long c14:0x0220++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." rgroup.long c14:0x0010++0x0 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." wgroup.long c14:0x0230++0x0 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" group.long c14:0x0050++0x0 line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)" group.long c14:0x0687++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.long c14:0x06E7++0x0 line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented" newline bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1" newline bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1" rgroup.long c14:0x0707++0x0 line.long 0x0 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..." bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..." newline bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..." bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented" newline bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address" hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address" bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid" newline bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid" rgroup.quad c14:0x10020++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." if (((per.l(c14:0x0411))&0x2)==0x2) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else hgroup.long c14:0x0260++0x00 hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register" bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High" tree.end tree "Breakpoint Registers" if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x0)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x10)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x20)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x30)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x40)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x50)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" group.long c14:0x0141++0x0 line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" group.long c14:0x0151++0x0 line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" tree.end tree "Watchpoint Control Registers" group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0" line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1" line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2" line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3" line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP tree.end endif tree "IVT Table (QSPI)" base ad:0x00 width 58. group.long 0x00++0x03 line.long 0x00 "IVT header,Header Showing The Start Of The IVT" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag" newline hexmask.long.word 0x00 8.--23. 1. " LEN ,Length" newline hexmask.long.byte 0x00 0.--7. 1. " VER ,Version" group.long 0x08++0x27 line.long 0x00 "Self-Test DCD pointer,Pointer to the start of the configuration data used for BIST" line.long 0x04 "Self-Test DCD pointer (backup),Pointer to the start of the backup configuration data used for BIST" line.long 0x08 "DCD_pointer,Pointer to the start of DCD configuration data" line.long 0x0C "DCD_pointer (backup),Pointer to the start of backup DCD configuration data" line.long 0x10 "HSE_H firmware flash memory start pointer,Pointer to the start of the HSE_H firmware in flash memory" line.long 0x14 "HSE_H firmware flash memory start pointer (backup),Pointer to the start of the backup HSE_H firmware in flash memory" line.long 0x18 "Application_boot code flash memory start pointer,Pointer to the start of the application boot code in flash memory" line.long 0x1C "Application_boot code flash memory start pointer (backup),Pointer to the start of the backup application boot code in flash memory" line.long 0x20 "Boot_configuration word,Configuration data used to select the boot configuration" bitfld.long 0x20 3. " BOOT_SEQ ,Secure boot mode" "Non-secure,Secure" newline bitfld.long 0x20 2. " SWT ,Boot target watchdog" "Disabled,Enabled" newline bitfld.long 0x20 0.--1. " BOOT_TARGET ,Boot target" "Cortex-M7_0,Cortex-A53_0,?..." line.long 0x24 "Life cycle configuration word,Configuration data used for advancing life cycle" bitfld.long 0x24 1. " IN_FIELD ,Advances life cycle state to IN_FIELD" "Disabled,Enabled" newline bitfld.long 0x24 0. " OEM_PROD ,Advances life cycle state to OEM_PROD" "Disabled,Enabled" repeat 8. (increment 0x34 0x04) (increment 0. 1.) group.long $1++0x03 line.long 0x00 "HSE_H firmware $2,Defined by the HSE_H firmware specification" repeat.end newline repeat 4. (increment 0xF0 0x04) (increment 0. 1.) group.long $1++0x03 line.long 0x00 "GMAC$2,Galois Message Authentication Code of first 240 bytes of IVT image structure" repeat.end tree "DCD Registers" base ad:((per.l(ad:0x00+0x10))&0xFFFFFFFF) width 26. group.long 0x00++0x03 line.long 0x00 "DCD header,Header to signify start of DCD data" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag" hexmask.long.word 0x00 8.--23. 1. " LEN ,Length" hexmask.long.byte 0x00 0.--7. 1. " VER ,Version" group.byte 0x04++0x01 "DCD data" line.byte 0x00 "Write Data Parameters,Write data command parameters" bitfld.byte 0x00 4. " Data Set ,Status bit showing whether bits at target were successfully overwritten" "Not overwritten,Overwritten" bitfld.byte 0x00 3. " Data Mask ,Enables overwriting of bits at target address" "All bits,Specific bits" bitfld.byte 0x00 0.--2. " Bytes ,Width of target location(s) in bytes" ",1 byte,2 bytes,,4 bytes,?..." line.byte 0x01 "Check Data Parameters,Check data command parameters" bitfld.byte 0x01 4. " Data Set ,Enables bit checking at target address" "Ignored,Checked" bitfld.byte 0x01 3. " Data Mask ,Enables partial/complete checking of bits when the Data Set field is set to 1" "All bits,Specific bits" bitfld.byte 0x01 0.--2. " Bytes ,Size of target locations in bytes." ",1 byte,2 bytes,,4 bytes,?..." base ad:(((per.l(ad:((per.l(ad:0x00+0x10))&0xFFFFFFFF))>>8)&0xFFFF)+0x04) group.long 0x000++0x03 line.long 0x00 "GMAC,Cryptographic hash for DCD header and complete DCD data using IVTDCD key" width 0x0B tree.end tree "DCD Self-Test Registers" base ad:((per.l(ad:0x00+0x08))&0xFFFFFFFF) width 26. group.long 0x00++0x03 line.long 0x00 "DCD SelfTest header,Header to signify start of DCD SelfTest data" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag" hexmask.long.word 0x00 8.--23. 1. " LEN ,Length" hexmask.long.byte 0x00 0.--7. 1. " VER ,Version" group.byte 0x04++0x01 "DCD data" line.byte 0x00 "Write Data Parameters,Write data command parameters" bitfld.byte 0x00 4. " Data Set ,Status bit showing whether bits at target were successfully overwritten" "Not overwritten,Overwritten" bitfld.byte 0x00 3. " Data Mask ,Enables overwriting of bits at target address" "All bits,Specific bits" bitfld.byte 0x00 0.--2. " Bytes ,Width of target location(s) in bytes" ",1 byte,2 bytes,,4 bytes,?..." line.byte 0x01 "Check Data Parameters,Check data command parameters" bitfld.byte 0x01 4. " Data Set ,Enables bit checking at target address" "Ignored,Checked" bitfld.byte 0x01 3. " Data Mask ,Enables partial/complete checking of bits when the Data Set field is set to 1" "All bits,Specific bits" bitfld.byte 0x01 0.--2. " Bytes ,Size of target locations in bytes." ",1 byte,2 bytes,,4 bytes,?..." base ad:(((per.l(ad:((per.l(ad:0x00)+0x08)&0xFFFFFFFF))>>8)&0xFFFF)+0x04) group.long 0x00++0x03 line.long 0x00 "GMAC,Cryptographic hash for DCD header and complete DCD data using IVTDCD key" width 0x0B tree.end tree "BOOT Registers" base ad:((per.l(ad:0x00+0x20))&0xFFFFFFFF) width 24. if (((per.l(ad:0x00+0x28)&0x08)==0)) group.long 0x00++0x0F "Application boot" line.long 0x00 "Image header,Marks start of application image" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag" newline hexmask.long.byte 0x00 0.--7. 1. " Version ,Version" line.long 0x04 "RAM start pointer,Pointer to the first RAM address to which BootROM must load application boot code" line.long 0x08 "RAM entry pointer,Pointer to out of RESET start of boot target core. For Cortex-M7 it corresponds to VTOR. For A53 it corresponds to start of code execution" line.long 0x0C "Code length word,Length of code section of the image" group.long 0x40++0x03 line.long 0x00 "Code,Code can be any size up to the maximum size of system SRAM" sif cpuis("Cortex-M7") group.long 0x00++0x0B "Serial boot" line.long 0x00 "Image header,Marks start of serial boot code image" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag" hexmask.long.byte 0x00 0.--7. 1. " Version ,Version" line.long 0x04 "RAM start pointer,Pointer to the first RAM address to which BootROM must load serial boot code" line.long 0x08 "RAM entry pointer,Pointer to out of RESET start of boot target core. For Cortex-M7 it corresponds to VTOR" group.long 0x40++0x03 line.long 0x00 "Code,Code can be any size up to the maximum size of system SRAM" endif else sif cpuis("CortexM7") group.long 0x00++0x17 "Serial boot" line.long 0x00 "Image header,Marks start of serial boot code image" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag" hexmask.long.byte 0x00 0.--7. 1. " Version ,Version" line.long 0x04 "RAM start pointer,Pointer to the first RAM address to which BootROM must load serial boot code" line.long 0x08 "RAM entry pointer,Pointer to out of RESET start of boot target core. For Cortex-M7 it corresponds to VTOR" line.long 0x0C "Code length word,Length of code section of the image." line.long 0x10 "Auth mode,Authentication mode" line.long 0x14 "NSKPUB Key Selector,NSK public key selector" group.long 0x40++0x03 line.long 0x00 "Code,Code can be any size up to the maximum size of system SRAM." repeat 64. (increment 0x1040 0x04)(increment 0. 1.) group.long $1++0x03 line.long 0x00 "CSKPUB$2,Customer Public key for RSA authentication $2" repeat.end repeat 64. (increment 0x1140 0x04) (increment 0. 1.) group.long $1++0x03 line.long 0x00 "CSK Signature $2,RSA signature for CSKPUB authentication $2" repeat.end group.long 0x1240++0x03 line.long 0x00 "Code,Code can be any size up to the maximum size of SRAM" base ad:per.l(ad:((per.l(ad:0x00+0x20))&0xFFFFFFFF)+0x0C) repeat 64. (increment 0x1240 0x04) (increment 0. 1.) group.long ($1+0x0C)++0x03 line.long 0x00 "Public key Signature $2,Public key signature for image authentication $2" repeat.end endif endif width 0x0B tree.end width 0x0B tree.end tree "A53_GPR (A53 Cluster General Purpose Registers)" base ad:0x4007C400 group.long 0x0++0x7 line.long 0x0 "GPR00,GPR00" bitfld.long 0x0 24.--26. "CA53_COUNTER_CLK_DIV_VAL,CA53 System Counter Clock Divide Value" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "CA53_1_CORE1_VINITHI,VINITHI Of Core1 Of Cluster1" "0,1" newline bitfld.long 0x0 20. "CA53_1_CORE0_VINITHI,VINITHI Of Core0 Of Cluster1" "0,1" bitfld.long 0x0 19. "CA53_0_CORE1_VINITHI,VINITHI Of Core1 Of Cluster0" "0,1" newline bitfld.long 0x0 18. "CA53_0_CORE0_VINITHI,VINITHI Of Core0 Of Cluster0" "0,1" bitfld.long 0x0 17. "CA53_1_CORE1_CFGTE,CFGTE Of Core1 Of Cluster1" "0,1" newline bitfld.long 0x0 16. "CA53_1_CORE0_CFGTE,CFGTE Of Core0 Of Cluster1" "0,1" bitfld.long 0x0 15. "CA53_1_CORE1_CFGEND,CFGEND Of Core1 Of Cluster1" "0,1" newline bitfld.long 0x0 14. "CA53_1_CORE0_CFGEND,CFGEND Of Core0 Of Cluster1" "0,1" bitfld.long 0x0 13. "CA53_0_CORE1_CFGTE,CFGTE Of Core1 Of Cluster0" "0,1" newline bitfld.long 0x0 12. "CA53_0_CORE0_CFGTE,CFGTE Of Core0 Of Cluster0" "0,1" bitfld.long 0x0 11. "CA53_0_CORE1_CFGEND,CFGEND Of Core1 Of Cluster0" "0,1" newline bitfld.long 0x0 10. "CA53_0_CORE0_CFGEND,CFGEND Of Core0 Of Cluster0" "0,1" bitfld.long 0x0 9. "CA53_1_BROADCASTOUTER,BROADCASTOUTER Of Cluster1" "0,1" newline bitfld.long 0x0 8. "CA53_1_BROADCASTINNER,BROADCASTINNER Of Cluster1" "0,1" bitfld.long 0x0 7. "CA53_1_BROADCASTCACHEMAINT,BROADCASTCACHEMAINT Of Cluster1" "0,1" newline bitfld.long 0x0 6. "CA53_0_BROADCASTOUTER,BROADCASTOUTER Of Cluster0" "0,1" bitfld.long 0x0 5. "CA53_0_BROADCASTINNER,BROADCASTINNER Of Cluster0" "0,1" newline bitfld.long 0x0 4. "CA53_0_BROADCASTCACHEMAINT,BROADCASTCACHEMAINT Of Cluster0" "0,1" bitfld.long 0x0 3. "CA53_1_CORE1_AA64nAA32,AA64nAA32 Of Core1 Of Cluster1" "0,1" newline bitfld.long 0x0 2. "CA53_1_CORE0_AA64nAA32,AA64nAA32 Of Core0 Of Cluster1" "0,1" bitfld.long 0x0 1. "CA53_0_CORE1_AA64nAA32,AA64nAA32 Of Core1 Of Cluster0" "0,1" newline bitfld.long 0x0 0. "CA53_0_CORE0_AA64nAA32,AA64nAA32 Of Core0 Of Cluster0" "0,1" line.long 0x4 "GPR01,GPR01" bitfld.long 0x4 27. "CA53_1_CORE1_CP15SDISABLE,CP15SDISABLE Of Core1 Of Cluster1" "0,1" bitfld.long 0x4 26. "CA53_1_CORE0_CP15SDISABLE,CP15SDISABLE Of Core0 Of Cluster1" "0,1" newline bitfld.long 0x4 25. "CA53_0_CORE1_CP15SDISABLE,CP15SDISABLE Of Core1 Of Cluster0" "0,1" bitfld.long 0x4 24. "CA53_0_CORE0_CP15SDISABLE,CP15SDISABLE Of Core0 Of Cluster0" "0,1" newline bitfld.long 0x4 9. "CLUSTER1_CG_EN,Cluster1 Clock Gating Enable" "0: Disable,1: Enable" bitfld.long 0x4 8. "CLUSTER0_CG_EN,Cluster0 Clock Gating Enable" "0: Disable,1: Enable" newline bitfld.long 0x4 1. "WFE_EVT_CA53_CLUSTER1,WFE Event for Cortex-A53 Cluster1" "0,1" bitfld.long 0x4 0. "WFE_EVT_CA53_CLUSTER0,WFE Event For Cortex-A53 Cluster0" "0,1" group.long 0x18++0x7 line.long 0x0 "GPR06,GPR06" bitfld.long 0x0 1.--2. "GIC500_LOCKSTEP_EN,Lockstep Mode For GIC500" "0: Lockstep disabled with GIC0 enabled and GIC1..,1: Lockstep disabled with GIC0 disabled and GIC1..,2: Lockstep enabled,3: Lockstep enabled" bitfld.long 0x0 0. "CA53_LOCKSTEP_EN,Lockstep Mode For Cortex-A53 Clusters" "0: Disable,1: Enable" line.long 0x4 "GPR07,GPR07" hexmask.long.byte 0x4 24.--31. 1. "CA53_1_CLUSTERIDAFF2,Cluster ID Affinity Level 2 For Cortex-A53 Cluster1" hexmask.long.byte 0x4 16.--23. 1. "CA53_1_CLUSTERIDAFF1,Cluster ID Affinity Level 1 For Cortex-A53 Cluster1" newline hexmask.long.byte 0x4 8.--15. 1. "CA53_0_CLUSTERIDAFF2,Cluster ID Affinity Level 2 For Cortex-A53 Cluster0" hexmask.long.byte 0x4 0.--7. 1. "CA53_0_CLUSTERIDAFF1,Cluster ID Affinity Level 1 For Cortex-A53 Cluster0" rgroup.long 0x20++0x3 line.long 0x0 "GPR08,GPR08" bitfld.long 0x0 27. "CA53_1_CORE1_STANDBYWFI_STATUS,STANDBYWFI Status Of Core1 Of Cluster1" "0: Not in STANDBYWFI state,1: In STANDBYWFI state" bitfld.long 0x0 26. "CA53_1_CORE0_STANDBYWFI_STATUS,STANDBYWFI Status Of Core0 Of Cluster1" "0: Not in STANDBYWFI state,1: In STANDBYWFI state" newline bitfld.long 0x0 25. "CA53_0_CORE1_STANDBYWFI_STATUS,STANDBYWFI Status Of Core1 Of Cluster0" "0: Not in STANDBYWFI state,1: In STANDBYWFI state" bitfld.long 0x0 24. "CA53_0_CORE0_STANDBYWFI_STATUS,STANDBYWFI Status Of Core0 Of Cluster0" "0: Not in STANDBYWFI state,1: In STANDBYWFI state" newline bitfld.long 0x0 19. "CA53_1_CORE1_STANDBYWFE_STATUS,STANDBYWFE Status Of Core1 Of Cluster1" "0: Not in STANDBYWFE state,1: In STANDBYWFE state" bitfld.long 0x0 18. "CA53_1_CORE0_STANDBYWFE_STATUS,STANDBYWFE Status Of Core0 Of Cluster1" "0: Not in STANDBYWFE state,1: In STANDBYWFE state" newline bitfld.long 0x0 17. "CA53_0_CORE1_STANDBYWFE_STATUS,STANDBYWFE Status Of Core1 Of Cluster0" "0: Not in STANDBYWFE state,1: In STANDBYWFE state" bitfld.long 0x0 16. "CA53_0_CORE0_STANDBYWFE_STATUS,STANDBYWFE Status Of Core0 Of Cluster0" "0: Not in STANDBYWFE state,1: In STANDBYWFE state" newline bitfld.long 0x0 9. "CLUSTER1_STANDBYWFIL2_STATUS,STANDBYWFIL2 Status Of Cortex-A53 Cluster1" "0: Not in STANDBYWFIL2 state,1: In STANDBYWFIL2 state" bitfld.long 0x0 8. "CLUSTER0_STANDBYWFIL2_STATUS,STANDBYWFIL2 Status Of Cortex-A53 Cluster0" "0: Not in STANDBYWFIL2 state,1: In STANDBYWFIL2 state" newline bitfld.long 0x0 3. "CA53_1_CORE1_WARM_RESET_STATUS,Warm Reset Status Of Core1 Of Cluster1" "0: Reset in progress,1: Reset request completed" bitfld.long 0x0 2. "CA53_1_CORE0_WARM_RESET_STATUS,Warm Reset Status Of Core0 Of Cluster1" "0: Reset in progress,1: Reset request completed" newline bitfld.long 0x0 1. "CA53_0_CORE1_WARM_RESET_STATUS,Warm Reset Status Of Core1 of Cluster0" "0: Reset in progress,1: Reset request completed" bitfld.long 0x0 0. "CA53_0_CORE0_WARM_RESET_STATUS,Warm Reset Status Of Core0 Of Cluster0" "0: Reset in progress,1: Reset request completed" group.long 0x24++0x3 line.long 0x0 "GPR09,GPR09" hexmask.long.byte 0x0 24.--31. 1. "CA53_1_CORE1_RVBARADDR_39_32,Uppermost Byte Of 40-bit Reset Vector Base Address Of Core1 Of Cortex-A53 cluster1" hexmask.long.byte 0x0 16.--23. 1. "CA53_1_CORE0_RVBARADDR_39_32,Uppermost Byte Of 40-bit Reset Vector Base Address Of Core0 Of Cortex-A53 Cluster1" newline hexmask.long.byte 0x0 8.--15. 1. "CA53_0_CORE1_RVBARADDR_39_32,Uppermost Byte Of 40-bit Reset Vector Base Address Of Core1 Of Cortex-A53 Cluster0" hexmask.long.byte 0x0 0.--7. 1. "CA53_0_CORE0_RVBARADDR_39_32,Uppermost Byte Of 40-bit Reset Vector Base Address Of Core0 Of Cortex-A53 Cluster0" rgroup.long 0x28++0x2F line.long 0x0 "GPR10,Cluster0 Core0 CPUMERRSR High" hexmask.long 0x0 0.--31. 1. "CA53_0_CORE0_CPUMERRSR_HIGH_BITS,Upper 32 bits Of CPUMERRSR Of Cortex-A53 Cluster0 Core0" line.long 0x4 "GPR11,Cluster0 Core0 CPUMERRSR Low" hexmask.long 0x4 0.--31. 1. "CA53_0_CORE0_CPUMERRSR_LOW_BITS,Lower 32 Bits Of CPUMERRSR Of Cortex-A53 Cluster0 Core0" line.long 0x8 "GPR12,Cluster0 Core1 CPUMERRSR High" hexmask.long 0x8 0.--31. 1. "CA53_0_CORE1_CPUMERRSR_HIGH_BITS,Upper 32 bits Of CPUMERRSR Of Cortex-A53 Cluster0 Core1" line.long 0xC "GPR13,Cluster0 Core1 CPUMERRSR Low" hexmask.long 0xC 0.--31. 1. "CA53_0_CORE1_CPUMERRSR_LOW_BITS,Lower 32 bits Of CPUMERRSR Of Cortex-A53 Cluster0 Core1" line.long 0x10 "GPR14,Cluster1 Core0 CPUMERRSR High" hexmask.long 0x10 0.--31. 1. "CA53_1_CORE0_CPUMERRSR_HIGH_BITS,Upper 32 bits Of CPUMERRSR Of Cortex-A53 Cluster1 Core0" line.long 0x14 "GPR15,Cluster1 Core0 CPUMERRSR Low" hexmask.long 0x14 0.--31. 1. "CA53_1_CORE0_CPUMERRSR_LOW_BITS,Lower 32 bits Of CPUMERRSR Of Cortex-A53 Cluster1 Core0" line.long 0x18 "GPR16,Cluster1 Core1 CPUMERRSR High" hexmask.long 0x18 0.--31. 1. "CA53_1_CORE1_CPUMERRSR_HIGH_BITS,Upper 32 bits Of CPUMERRSR Of Cortex-A53 Cluster1 Core1" line.long 0x1C "GPR17,Cluster1 Core1 CPUMERRSR Low" hexmask.long 0x1C 0.--31. 1. "CA53_1_CORE1_CPUMERRSR_LOW_BITS,Lower 32 bits Of CPUMERRSR Of Cortex-A53 Cluster1 Core1" line.long 0x20 "GPR18,Cluster0 L2MERRSR High" hexmask.long 0x20 0.--31. 1. "CA53_0_L2MERRSR_HIGH_BITS,Upper 32 Bits Of L2MERRSR Of Cortex-A53 Cluster0" line.long 0x24 "GPR19,Cluster0 L2MERRSR Low" hexmask.long 0x24 0.--31. 1. "CA53_0_L2MERRSR_LOW_BITS,Lower 32 Bits Of L2MERRSR of Cortex-A53 Cluster0" line.long 0x28 "GPR20,Cluster1 L2MERRSR High" hexmask.long 0x28 0.--31. 1. "CA53_1_L2MERRSR_HIGH_BITS,Upper 32 Bits Of L2MERRSR Of Cortex-A53 Cluster1" line.long 0x2C "GPR21,GPR21" hexmask.long 0x2C 0.--31. 1. "CA53_1_L2MERRSR_LOW_BITS,Lower 32 Bits Of L2MERRSR Register of Cortex-A53 Cluster1" tree.end tree "ADC (Analog-to-Digital Converter)" base ad:0x0 tree "ADC_0" base ad:0x401F8000 group.long 0x0++0x7 line.long 0x0 "MCR,Main Configuration" bitfld.long 0x0 31. "OWREN,Overwrite Enable" "0: Older valid conversion data is not overwritten..,1: Newer conversion result is always overwritten.." bitfld.long 0x0 30. "WLSIDE,Write Left Side" "0: Write right-aligned conversion data (from 11 to 0),1: Write left-aligned conversion data (from 15 to 4)" newline bitfld.long 0x0 29. "MODE,Normal Scan Mode Select" "0: One-Shot Operation mode: configuration for one..,1: Scan Operation mode: configuration for.." bitfld.long 0x0 27. "TRGEN,External Trigger Enable" "0: External trigger is disabled,1: Enables the external trigger to start a conversion" newline bitfld.long 0x0 26. "EDGE,Trigger Edge Select" "0: Falling edge is trigger,1: Rising edge is trigger" bitfld.long 0x0 24. "NSTART,Normal Conversion Start" "0,1" newline bitfld.long 0x0 22. "JTRGEN,Injection External Trigger Enable" "0: Injected conversion not started by external..,1: Injected conversion started by external trigger" bitfld.long 0x0 21. "JEDGE,Injection Trigger Edge Selection" "0: Falling edge is trigger,1: Rising edge is trigger" newline bitfld.long 0x0 20. "JSTART,Start Injection Conversion" "0,1" bitfld.long 0x0 17. "CTUEN,Cross Trigger Unit Enable" "0: The CTU is disabled and the triggered injected..,1: The CTU is enabled and the triggered injected.." newline bitfld.long 0x0 16. "CTU_MODE,Cross Trigger Unit Mode" "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "STCL,Self-Testing Configuration Lock" "0: Not locked,1: Locked" newline bitfld.long 0x0 14. "CALSTART,Calibration Start" "0: No effect,1: Start calibration" bitfld.long 0x0 13. "AVGEN,Average Enable" "0: Disable,1: Enable (default)" newline bitfld.long 0x0 11.--12. "NRSMPL,Number of Averaging Samples" "0: 16,1: 32,2: 128,3: 512" bitfld.long 0x0 9.--10. "TSAMP,Sample Time for Calibration" "0: 22 cycles of AD_CLK (default),1: 8 cycles of AD_CLK,2: 16 cycle of AD_CLK,3: 32 cycle of AD_CLK" newline bitfld.long 0x0 8. "ADCLKSE,Analog Clock Frequency Select" "0: AD_CLK frequency is half,1: AD_CLK frequency is equal to bus clock frequency" bitfld.long 0x0 7. "ABORTCHAIN,Abort Conversion Chain" "0: Chain conversion has been aborted or chain..,1: Abort current chain conversion." newline bitfld.long 0x0 6. "ABORT,Abort Conversion" "0: Channel conversion has been aborted or channel..,1: Abort current channel conversion." bitfld.long 0x0 5. "ACKO,Auto-Clock-Off Mode Enable" "0: Auto-Clock-Off feature is disabled,1: Auto-Clock-Off feature is enabled" newline bitfld.long 0x0 0. "PWDN,Power-Down Enable" "0: When ADC status is in Power-down mode..,1: Request to enter Power-down mode." line.long 0x4 "MSR,Main Status" rbitfld.long 0x4 31. "CALIBRTD,Calibration Status" "0: Uncalibrated or calibration unsuccessful,1: Calibrated or calibration successful" eventfld.long 0x4 30. "CALFAIL,Calibration Failed" "0: Calibration passed (must be checked with CALBUSY..,1: Calibration failed" newline rbitfld.long 0x4 29. "CALBUSY,Calibration Busy" "0: ADC is ready for use,1: ADC is busy in a calibration process" rbitfld.long 0x4 24. "NSTART,Normal Conversion Status" "0: Normal conversion is not in process,1: Normal conversion is in process" newline rbitfld.long 0x4 23. "JABORT,Injected Conversion Abort Status" "0: Injected conversion has not been aborted,1: Injected conversion has been aborted" rbitfld.long 0x4 20. "JSTART,Injected Conversion Status" "0: Injected conversion is not in process,1: Injected conversion is in process" newline rbitfld.long 0x4 18. "SELF_TEST_S,Self-Test Status" "0: Self-test conversion is not in process,1: Self-test conversion is in process" rbitfld.long 0x4 16. "CTUSTART,CTU Conversion Status" "0,1" newline hexmask.long.byte 0x4 9.--15. 1. "CHADDR,Channel Address" rbitfld.long 0x4 5. "ACKO,Auto-Clock-Off Enable" "0: Auto-Clock-Off feature is not enabled,1: Auto-Clock-Off feature is enabled" newline rbitfld.long 0x4 0.--2. "ADCSTATUS,ADC Status" "0: Idle,1: Power-down,2: Wait state (waiting to start conversion after..,3: Busy in calibration,4: Sample,?,6: Conversion,?" group.long 0x10++0xB line.long 0x0 "ISR,Interrupt Status" eventfld.long 0x0 4. "EOCTU,End of CTU Conversion" "0: CTU end of conversion has not occurred,1: CTU end of conversion has occurred" eventfld.long 0x0 3. "JEOC,Injected Channel End of Conversion" "0: Injected channel end of conversion has not..,1: Injected channel end of conversion has occurred" newline eventfld.long 0x0 2. "JECH,Injected End of Conversion Chain" "0: Injected channel end of conversion chain has not..,1: Injected channel end of conversion chain has.." eventfld.long 0x0 1. "EOC,End of Channel Conversion" "0: Channel end of conversion has not occurred,1: Channel end of conversion has occurred" newline eventfld.long 0x0 0. "ECH,End of Conversion Chain" "0: End of conversion chain has not occurred,1: End of conversion chain has occurred" line.long 0x4 "CEOCFR0,Channel Pending 0" eventfld.long 0x4 7. "EOC_CH7,Channel 7 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 6. "EOC_CH6,Channel 6 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 5. "EOC_CH5,Channel 5 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 4. "EOC_CH4,Channel 4 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 3. "EOC_CH3,Channel 3 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 2. "EOC_CH2,Channel 2 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 1. "EOC_CH1,Channel 1 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 0. "EOC_CH0,Channel 0 EOC Status" "0: Conversion not complete,1: Conversion complete" line.long 0x8 "CEOCFR1,Channel Pending 1" eventfld.long 0x8 7. "EOC_CH39,Channel 39 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 6. "EOC_CH38,Channel 38 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 5. "EOC_CH37,Channel 37 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 4. "EOC_CH36,Channel 36 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 3. "EOC_CH35,Channel 35 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 2. "EOC_CH34,Channel 34 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 1. "EOC_CH33,Channel 33 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 0. "EOC_CH32,Channel 32 EOC Status" "0: Conversion not complete,1: Conversion complete" group.long 0x20++0xB line.long 0x0 "IMR,Interrupt Mask" bitfld.long 0x0 4. "MSKEOCTU,End of CTU Conversion Interrupt Mask" "0: EOCTU interrupt disabled,1: EOCTU interrupt enabled" bitfld.long 0x0 3. "MSKJEOC,End of Injected Conversion Interrupt Mask" "0: End of injected conversion interrupt disabled,1: End of injected conversion interrupt enabled" newline bitfld.long 0x0 2. "MSKJECH,End of Injected Chain Conversion Interrupt Mask" "0: End of injected chain conversion interrupt..,1: End of injected chain conversion interrupt enabled" bitfld.long 0x0 1. "MSKEOC,End of Conversion Interrupt Mask" "0: End of conversion interrupt disabled,1: End of conversion interrupt enabled" newline bitfld.long 0x0 0. "MSKECH,End of Chain Conversion Interrupt Mask" "0: End of chain conversion interrupt disabled,1: End of chain conversion interrupt enabled" line.long 0x4 "CIMR0,Channel Interrupt Mask 0" bitfld.long 0x4 7. "CIM7,Channel 7 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "CIM6,Channel 6 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "CIM5,Channel 5 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "CIM4,Channel 4 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "CIM3,Channel 3 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "CIM2,Channel 2 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "CIM1,Channel 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "CIM0,Channel 0 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "CIMR1,Channel Interrupt Mask 1" bitfld.long 0x8 7. "CIM39,Channel 39 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x8 6. "CIM38,Channel 38 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 5. "CIM37,Channel 37 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x8 4. "CIM36,Channel 36 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 3. "CIM35,Channel 35 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x8 2. "CIM34,Channel 34 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 1. "CIM33,Channel 33 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x8 0. "CIM32,Channel 32 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" group.long 0x30++0x7 line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status" eventfld.long 0x0 15. "WDG7H,Channel 7 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 14. "WDG7L,Channel 7 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 13. "WDG6H,Channel 6 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 12. "WDG6L,Channel 6 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 11. "WDG5H,Channel 5 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 10. "WDG5L,Channel 5 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 9. "WDG4H,Channel 4 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 8. "WDG4L,Channel 4 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 7. "WDG3H,Channel 3 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 6. "WDG3L,Channel 3 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 5. "WDG2H,Channel 2 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 4. "WDG2L,Channel 2 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 3. "WDG1H,Channel 1 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 2. "WDG1L,Channel 1 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 1. "WDG0H,Channel 0 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 0. "WDG0L,Channel 0 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask" bitfld.long 0x4 15. "MSKWDG7H,Channel 7 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 14. "MSKWDG7L,Channel 7 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 13. "MSKWDG6H,Channel 6 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 12. "MSKWDG6L,Channel 6 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 11. "MSKWDG5H,Channel 5 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 10. "MSKWDG5L,Channel 5 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 9. "MSKWDG4H,Channel 4 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 8. "MSKWDG4L,Channel 4 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 7. "MSKWDG3H,Channel 3 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 6. "MSKWDG3L,Channel 3 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 5. "MSKWDG2H,Channel 2 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 4. "MSKWDG2L,Channel 2 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 3. "MSKWDG1H,Channel 1 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 2. "MSKWDG1L,Channel 1 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 1. "MSKWDG0H,Channel 0 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 0. "MSKWDG0L,Channel 0 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" group.long 0x40++0xB line.long 0x0 "DMAE,DMAE" bitfld.long 0x0 1. "DCLR,DMA Clear Sequence Enable" "0: DMA request cleared by acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA Global Enable" "0: DMA feature is disabled,1: DMA feature is enabled" line.long 0x4 "DMAR0,DMA 0" bitfld.long 0x4 7. "DMA7,Channel 7 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x4 6. "DMA6,Channel 6 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x4 5. "DMA5,Channel 5 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x4 4. "DMA4,Channel 4 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x4 3. "DMA3,Channel 3 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x4 2. "DMA2,Channel 2 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x4 1. "DMA1,Channel 1 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x4 0. "DMA0,Channel 0 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" line.long 0x8 "DMAR1,DMA 1" bitfld.long 0x8 7. "DMA39,Channel 39 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x8 6. "DMA38,Channel 38 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x8 5. "DMA37,Channel 37 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x8 4. "DMA36,Channel 36 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x8 3. "DMA35,Channel 35 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x8 2. "DMA34,Channel 34 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x8 1. "DMA33,Channel 33 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x8 0. "DMA32,Channel 32 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" group.long 0x60++0xF line.long 0x0 "THRHLR0,Analog Watchdog Threshold 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x0 0.--11. 1. "THRL,Low Threshold" line.long 0x4 "THRHLR1,Analog Watchdog Threshold 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x4 0.--11. 1. "THRL,Low Threshold" line.long 0x8 "THRHLR2,Analog Watchdog Threshold 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x8 0.--11. 1. "THRL,Low Threshold" line.long 0xC "THRHLR3,Analog Watchdog Threshold 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0xC 0.--11. 1. "THRL,Low Threshold" group.long 0x80++0xB line.long 0x0 "PSCR,Presampling Control" bitfld.long 0x0 3.--4. "PREVAL1,Internal Presampling Voltage Selection." "0,1,2,3" bitfld.long 0x0 1.--2. "PREVAL0,Internal Presampling Voltage Selection" "0,1,2,3" newline bitfld.long 0x0 0. "PRECONV,Convert Presampled Value" "0: Presampling is followed by sampling then..,1: Presampling is followed by the conversion." line.long 0x4 "PSR0,Presampling 0" bitfld.long 0x4 7. "PRES7,Presampling Enable for Channel 7" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x4 6. "PRES6,Presampling Enable for Channel 6" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x4 5. "PRES5,Presampling Enable for Channel 5" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x4 4. "PRES4,Presampling Enable for Channel 4" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x4 3. "PRES3,Presampling Enable for Channel 3" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x4 2. "PRES2,Presampling Enable for Channel 2" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x4 1. "PRES1,Presampling Enable for Channel 1" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x4 0. "PRES0,Presampling Enable for Channel 0" "0: Presampling is disabled,1: Presampling is enabled" line.long 0x8 "PSR1,Presampling 1" bitfld.long 0x8 7. "PRES39,Presampling Enable for Channel 39" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x8 6. "PRES38,Presampling Enable for Channel 38" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x8 5. "PRES37,Presampling Enable for Channel 37" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x8 4. "PRES36,Presampling Enable for Channel 36" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x8 3. "PRES35,Presampling Enable for Channel 35" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x8 2. "PRES34,Presampling Enable for Channel 34" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x8 1. "PRES33,Presampling Enable for Channel 33" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x8 0. "PRES32,Presampling Enable for Channel 32" "0: Presampling is disabled,1: Presampling is enabled" group.long 0x94++0x7 line.long 0x0 "CTR0,Conversion Timing 0" hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,Sampling Phase Duration" line.long 0x4 "CTR1,Conversion Timing 1" hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,Sampling Phase Duration" group.long 0xA4++0x7 line.long 0x0 "NCMR0,Normal Conversion Mask 0" bitfld.long 0x0 7. "CH7,Normal Conversion Mask for Channel 7" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x0 6. "CH6,Normal Conversion Mask for Channel 6" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x0 5. "CH5,Normal Conversion Mask for Channel 5" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x0 4. "CH4,Normal Conversion Mask for Channel 4" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x0 3. "CH3,Normal Conversion Mask for Channel 3" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x0 2. "CH2,Normal Conversion Mask for Channel 2" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x0 1. "CH1,Normal Conversion Mask for Channel 1" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x0 0. "CH0,Normal Conversion Mask for Channel 0" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" line.long 0x4 "NCMR1,Normal Conversion Mask 1" bitfld.long 0x4 7. "CH39,Normal Conversion Mask for Channel 39" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x4 6. "CH38,Normal Conversion Mask for Channel 38" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x4 5. "CH37,Normal Conversion Mask for Channel 37" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x4 4. "CH36,Normal Conversion Mask for Channel 36" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x4 3. "CH35,Normal Conversion Mask for Channel 35" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x4 2. "CH34,Normal Conversion Mask for Channel 34" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x4 1. "CH33,Normal Conversion Mask for Channel 33" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x4 0. "CH32,Normal Conversion Mask for Channel 32" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" group.long 0xB4++0x7 line.long 0x0 "JCMR0,Injected Conversion Mask 0" bitfld.long 0x0 7. "CH7,Injected Conversion Mask for Channel 7" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x0 6. "CH6,Injected Conversion Mask for Channel 6" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x0 5. "CH5,Injected Conversion Mask for Channel 5" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x0 4. "CH4,Injected Conversion Mask for Channel 4" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x0 3. "CH3,Injected Conversion Mask for Channel 3" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x0 2. "CH2,Injected Conversion Mask for Channel 2" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x0 1. "CH1,Injected Conversion Mask for Channel 1" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x0 0. "CH0,Injected Conversion Mask for Channel 0" "0: Injected conversion is disabled,1: Injected conversion is enabled" line.long 0x4 "JCMR1,Injected Conversion Mask 1" bitfld.long 0x4 7. "CH39,Injected Conversion Mask for Channel 39" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x4 6. "CH38,Injected Conversion Mask for Channel 38" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x4 5. "CH37,Injected Conversion Mask for Channel 37" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x4 4. "CH36,Injected Conversion Mask for Channel 36" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x4 3. "CH35,Injected Conversion Mask for Channel 35" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x4 2. "CH34,Injected Conversion Mask for Channel 34" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x4 1. "CH33,Injected Conversion Mask for Channel 33" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x4 0. "CH32,Injected Conversion Mask for Channel 32" "0: Injected conversion is disabled,1: Injected conversion is enabled" group.long 0xC0++0x3 line.long 0x0 "USROFSGN,User OFFSET and Gain" hexmask.long.word 0x0 16.--25. 1. "GAINUSER,User-Defined Gain Value" hexmask.long.byte 0x0 0.--7. 1. "OFFSUSER,User Defined Offset" group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay" hexmask.long.byte 0x0 0.--7. 1. "PDED,Power Down Exist Delay" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x100)++0x3 line.long 0x0 "PCDR[$1],Precision Channel n Data" bitfld.long 0x0 19. "VALID,Conversion Data Valid" "0: Not valid data,1: Valid data" bitfld.long 0x0 18. "OVERW,Data Overwrite" "0: Data not overwritten,1: Data overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Mode of Conversion Status" "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" hexmask.long.word 0x0 0.--11. 1. "CDATA,Channel Converted Data" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x180)++0x3 line.long 0x0 "ICDR$1,Internal Channel n Data" bitfld.long 0x0 19. "VALID,Conversion Data Valid" "0: Not valid data,1: Valid data" bitfld.long 0x0 18. "OVERW,Data Overwrite" "0: Data not overwritten,1: Data overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Mode of Conversion Status" "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" hexmask.long.word 0x0 0.--11. 1. "CDATA,Channel Converted Data" repeat.end group.long 0x280++0xF line.long 0x0 "THRHLR4,Analog Watchdog Threshold 4" hexmask.long.word 0x0 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x0 0.--11. 1. "THRL,Low Threshold" line.long 0x4 "THRHLR5,Analog Watchdog Threshold 5" hexmask.long.word 0x4 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x4 0.--11. 1. "THRL,Low Threshold" line.long 0x8 "THRHLR6,Analog Watchdog Threshold 6" hexmask.long.word 0x8 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x8 0.--11. 1. "THRL,Low Threshold" line.long 0xC "THRHLR7,Analog Watchdog Threshold 7" hexmask.long.word 0xC 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0xC 0.--11. 1. "THRL,Low Threshold" group.long 0x2B0++0x3 line.long 0x0 "CWSELR0,Channel Watchdog Select 0" bitfld.long 0x0 28.--30. "WSEL_CH7,Channel Watchdog Select for Channel 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "WSEL_CH6,Channel Watchdog Select for Channel 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WSEL_CH5,Channel Watchdog Select for Channel 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "WSEL_CH4,Channel Watchdog Select for Channel 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "WSEL_CH3,Channel Watchdog Select for Channel 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "WSEL_CH2,Channel Watchdog Select for Channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "WSEL_CH1,Channel Watchdog Select for Channel 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "WSEL_CH0,Channel Watchdog Select for Channel 0" "0,1,2,3,4,5,6,7" group.long 0x2C0++0x3 line.long 0x0 "CWSELR4,Channel Watchdog Select 4" bitfld.long 0x0 28.--30. "WSEL_CH39,Channel Watchdog Select for Channel 39" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "WSEL_CH38,Channel Watchdog Select for Channel 38" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WSEL_CH37,Channel Watchdog Select for Channel 37" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "WSEL_CH36,Channel Watchdog Select for Channel 36" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "WSEL_CH35,Channel Watchdog Select for Channel 35" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "WSEL_CH34,Channel Watchdog Select for Channel 34" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "WSEL_CH33,Channel Watchdog Select for Channel 33" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "WSEL_CH32,Channel Watchdog Select for Channel 32" "0,1,2,3,4,5,6,7" group.long 0x2E0++0x7 line.long 0x0 "CWENR0,Channel Watchdog Enable 0" bitfld.long 0x0 7. "CWEN7,Watchdog Enable for Channel 7" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x0 6. "CWEN6,Watchdog Enable for Channel 6" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x0 5. "CWEN5,Watchdog Enable for Channel 5" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x0 4. "CWEN4,Watchdog Enable for Channel 4" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x0 3. "CWEN3,Watchdog Enable for Channel 3" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x0 2. "CWEN2,Watchdog Enable for Channel 2" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x0 1. "CWEN1,Watchdog Enable for Channel 1" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x0 0. "CWEN0,Watchdog Enable for Channel 0" "0: Watchdog is disabled,1: Watchdog is enabled" line.long 0x4 "CWENR1,Channel Watchdog Enable 1" bitfld.long 0x4 7. "CWEN39,Watchdog Enable for Channel 39" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x4 6. "CWEN38,Watchdog Enable for Channel 38" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x4 5. "CWEN37,Watchdog Enable for Channel 37" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x4 4. "CWEN36,Watchdog Enable for Channel 36" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x4 3. "CWEN35,Watchdog Enable for Channel 35" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x4 2. "CWEN34,Watchdog Enable for Channel 34" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x4 1. "CWEN33,Watchdog Enable for Channel 33" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x4 0. "CWEN32,Watchdog Enable for Channel 32" "0: Watchdog is disabled,1: Watchdog is enabled" group.long 0x2F0++0x7 line.long 0x0 "AWORR0,Analog Watchdog Out of Range 0" eventfld.long 0x0 7. "AWOR_CH7,Analog Watchdog Out of Range for Channel 7" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x0 6. "AWOR_CH6,Analog Watchdog Out of Range for Channel 6" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x0 5. "AWOR_CH5,Analog Watchdog Out of Range for Channel 5" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x0 4. "AWOR_CH4,Analog Watchdog Out of Range for Channel 4" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x0 3. "AWOR_CH3,Analog Watchdog Out of Range for Channel 3" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x0 2. "AWOR_CH2,Analog Watchdog Out of Range for Channel 2" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x0 1. "AWOR_CH1,Analog Watchdog Out of Range for Channel 1" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x0 0. "AWOR_CH0,Analog Watchdog Out of Range for Channel 0" "0: Converted data is in range,1: Converted data is out of range" line.long 0x4 "AWORR1,Analog Watchdog Out of Range 1" eventfld.long 0x4 7. "AWOR_CH39,Analog Watchdog Out of Range for Channel 39" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x4 6. "AWOR_CH38,Analog Watchdog Out of Range for Channel 38" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x4 5. "AWOR_CH37,Analog Watchdog Out of Range for Channel 37" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x4 4. "AWOR_CH36,Analog Watchdog Out of Range for Channel 36" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x4 3. "AWOR_CH35,Analog Watchdog Out of Range for Channel 35" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x4 2. "AWOR_CH34,Analog Watchdog Out of Range for Channel 34" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x4 1. "AWOR_CH33,Analog Watchdog Out of Range for Channel 33" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x4 0. "AWOR_CH32,Analog Watchdog Out of Range for Channel 32" "0: Converted data is in range,1: Converted data is out of range" group.long 0x340++0x13 line.long 0x0 "STCR1,Self-Test Configuration 1" hexmask.long.byte 0x0 24.--31. 1. "INPSAMP_C,Sampling Configuration for Algorithm C" hexmask.long.byte 0x0 8.--15. 1. "INPSAMP_S,Sampling Configuration for Algorithm S" line.long 0x4 "STCR2,Self-Test Configuration 2" bitfld.long 0x4 27. "MSKWDSERR,Watchdog Sequence Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "SERR,Error Fault Injection Field (write-only)" "0,1" newline bitfld.long 0x4 25. "MSKWDTERR,Watchdog Timer Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 23. "MSKST_EOC,Self-Test EOC Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 18. "MSKWDG_EOA_C,End of Algorithm C Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "MSKWDG_EOA_S,End of Algorithm S Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "MSKERR_C,Error on Algorithm C Channel Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 13. "MSKERR_S2,Error on Algorithm S2 Channel Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "MSKERR_S1,Error on Algorithm S1 Channel Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 11. "MSKERR_S0,Error on Algorithm S0 Channel Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "EN,Self-testing channel enable" "0: Disable,1: Enable" bitfld.long 0x4 4. "FMA_WDSERR,Fault mapping for Watchdog Sequence Error" "0: NCF mapping,1: CF mapping" newline bitfld.long 0x4 3. "FMA_WDTERR,Fault mapping for watchdog timer error" "0: NCF mapping,1: CF mapping" bitfld.long 0x4 2. "FMA_C,Fault mapping for algorithm C" "0: NCF mapping,1: CF mapping" newline bitfld.long 0x4 0. "FMA_S,Fault mapping for BGAP algorithm" "0: Non-Critical Fault (NCF) mapping,1: Critical Fault (CF) mapping" line.long 0x8 "STCR3,Self-Test Configuration 3" bitfld.long 0x8 8.--9. "ALG,Self-Test Algorithm Select" "0: Algorithm S,?,2: Algorithm C,3: Algorithm S (for One-Shot Operation mode);.." hexmask.long.byte 0x8 0.--4. 1. "MSTEP,Self-Test Step Select" line.long 0xC "STBRR,Self-Test Baud Rate" bitfld.long 0xC 16.--18. "WDT,Watchdog Timer Value" "0: 0.1 ms ((0008h * Prescaler) cycles at 80 MHz),1: 0.5 ms ((0027h * Prescaler) cycles at 80 MHz),2: 1 ms ((004Eh * Prescaler) cycles at 80 MHz),3: 2 ms ((009Ch * Prescaler) cycles at 80 MHz),4: 5 ms ((0187h * Prescaler) cycles at 80 MHz),5: 10 ms ((030Dh * Prescaler) cycles at 80 MHz),6: 20 ms (061Ah * Prescaler) cycles at 80 MHz),7: 50 ms (0F42h *Prescaler) cycles at 80 MHz)" hexmask.long.byte 0xC 0.--7. 1. "BR,Algorithm Baud Rate" line.long 0x10 "STSR1,Self-Test Status 1" eventfld.long 0x10 27. "WDSERR,Watchdog Sequence Errors" "0: No failure,1: Failure occurred" eventfld.long 0x10 25. "WDTERR,Watchdog Timer Error" "0: No failure,1: Failure occurred" newline eventfld.long 0x10 24. "OVERWR,Overwrite Error" "0: No overwrite error,1: Overwrite error occurred" eventfld.long 0x10 23. "ST_EOC,Self-Test EOC" "0: Self-test end of conversion is not complete,1: Self-test end of conversion is complete" newline eventfld.long 0x10 18. "WDG_EOA_C,Watchdog End of Algorithm C" "0: Self-test end of Algorithm C conversion is not..,1: Self-test end of Algorithm C conversion is.." eventfld.long 0x10 16. "WDG_EOA_S,Watchdog End of Algorithm S" "0: Self-test end of Algorithm S conversion is not..,1: Self-test end of Algorithm S conversion is.." newline eventfld.long 0x10 15. "ERR_C,Algorithm C Error" "0: No Algorithm C error,1: Algorithm C error occurred" eventfld.long 0x10 13. "ERR_S2,Algorithm S2 Error" "0: No error occurred on the sampled signal,1: Error occurred on the sampled signal" newline eventfld.long 0x10 12. "ERR_S1,Algorithm S1 Error" "0: No VDD ERROR,1: VDD ERROR occurred" eventfld.long 0x10 11. "ERR_S0,Algorithm S0 Error" "0: No VREF error,1: VREF error occurred" newline hexmask.long.byte 0x10 5.--9. 1. "STEP_C,Algorithm C Step Number Error" rgroup.long 0x354++0xB line.long 0x0 "STSR2,Self-Test Status 2" bitfld.long 0x0 31. "OVFL,Overflow Bit" "0: Not Overflow,1: Overflow" hexmask.long.word 0x0 16.--27. 1. "DATA1,Test Channel Converted Data when ERR_S1 Occurred" newline hexmask.long.word 0x0 0.--11. 1. "DATA0,Test Channel Converted Data when ERR_S1 Occurred" line.long 0x4 "STSR3,Self-Test Status 3" hexmask.long.word 0x4 16.--27. 1. "DATA1,Test Channel Converted Data when ERR_C Occurred" hexmask.long.word 0x4 0.--11. 1. "DATA0,Test Channel Converted Data when ERR_S0 Occurred" line.long 0x8 "STSR4,Self-Test Status 4" hexmask.long.word 0x8 16.--27. 1. "DATA1,Test Channel Converted Data When ERR_C Occurred" rgroup.long 0x370++0x7 line.long 0x0 "STDR1,Self-Test Data 1" bitfld.long 0x0 19. "VALID,Valid Data" "0: Data not valid,1: Data valid" bitfld.long 0x0 18. "OWERWR,Overwrite Data" "0: Data not overwritten,1: Data overwritten" newline hexmask.long.word 0x0 0.--11. 1. "TCDATA,Test Channel Converted Data" line.long 0x4 "STDR2,Self-Test Data 2" hexmask.long.word 0x4 20.--31. 1. "FDATA,Fractional Data" bitfld.long 0x4 19. "VALID,Valid Data" "0: Data not valid,1: Data valid" newline bitfld.long 0x4 18. "OVERWR,Overwrite Data" "0: Data not overwritten,1: Data overwritten" hexmask.long.word 0x4 0.--11. 1. "IDATA,Integer Data" group.long 0x380++0xF line.long 0x0 "STAW0R,Self-Test Analog Watchdog 0" bitfld.long 0x0 31. "AWDE,Analog Watchdog Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 30. "WDTE,Watchdog timer enable (related to the Algorithm S)" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 16.--27. 1. "THRH,High Threshold Value for Algorithm S Step0" hexmask.long.word 0x0 0.--11. 1. "THRL,Low Threshold Value for Algorithm S Step0" line.long 0x4 "STAW1AR,Self-Test Analog Watchdog 1A" bitfld.long 0x4 31. "AWDE,Analog Watchdog Enable" "0: Disabled,1: Enabled" hexmask.long.word 0x4 16.--27. 1. "THRH,High Threshold Value for Algorithm S Step1" newline hexmask.long.word 0x4 0.--11. 1. "THRL,Low Threshold Value for Algorithm S Step1" line.long 0x8 "STAW1BR,Self-Test Analog Watchdog 1B" hexmask.long.word 0x8 16.--27. 1. "THRH,High Threshold Value for Algorithm S Step1" hexmask.long.word 0x8 0.--11. 1. "THRL,Low Threshold Value for Algorithm S Step1" line.long 0xC "STAW2R,Self-Test Analog Watchdog 2" bitfld.long 0xC 31. "AWDE,Analog Watchdog Enable" "0: Disabled,1: Enabled" hexmask.long.word 0xC 0.--11. 1. "THRL,Threshold level low" rgroup.long 0x390++0x3 line.long 0x0 "STAW3R,Self-Test Analog Watchdog 3" group.long 0x394++0x7 line.long 0x0 "STAW4R,Self-Test Analog Watchdog 4" bitfld.long 0x0 31. "AWDE,Analog Watchdog Enable (Related to Algorithm C)" "0: Disabled,1: Enabled" bitfld.long 0x0 30. "WDTE,Watchdog Timer Enable (Related to Algorithm C)." "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 16.--27. 1. "THRH,High Threshold Value for Step0 of Algorithm C" hexmask.long.word 0x0 0.--11. 1. "THRL,Low Threshold Value for Step0 of Algorithm C" line.long 0x4 "STAW5R,Self-Test Analog Watchdog 5" hexmask.long.word 0x4 16.--27. 1. "THRH,High Threshold Value for Step N of Algorithm C (N = 1 to CS-1)." hexmask.long.word 0x4 0.--11. 1. "THRL,Low Threshold Value for Step0 of Algorithm C." rgroup.long 0x39C++0x3 line.long 0x0 "CALSTAT,Calibration Status" hexmask.long.word 0x0 16.--31. 1. "TEST_RESULT,TEST_RESULT" bitfld.long 0x0 13. "STAT_14,Status of Calibration Step 14" "0: Calibration step pass,1: Calibration step fail" newline bitfld.long 0x0 12. "STAT_13,Status of Calibration Step 13" "0: Calculated gain within range,1: Calculated gain out of range" bitfld.long 0x0 11. "STAT_12,Status of Calibration Step 12" "0: Test passed,1: Test failed" newline bitfld.long 0x0 10. "STAT_11,Status of Calibration Step 11" "0: Test passed,1: Test failed" bitfld.long 0x0 9. "STAT_10,Status of Calibration Step 10" "0: Test passed,1: Test failed" newline bitfld.long 0x0 8. "STAT_9,Status of Calibration Step 9" "0: Test passed,1: Test failed" bitfld.long 0x0 7. "STAT_8,Status of Calibration Step 8" "0: Test passed,1: Test failed" newline bitfld.long 0x0 6. "STAT_7,Status of Calibration Step 7" "0: Test passed,1: Test failed" bitfld.long 0x0 5. "STAT_6,Status of Calibration Step 6" "0: Test passed,1: Test failed" newline bitfld.long 0x0 4. "STAT_5,Status of Calibration Step 5" "0: Test passed,1: Test failed" bitfld.long 0x0 3. "STAT_4,Status of calibration step 4" "0: Test passed,1: Test failed" newline bitfld.long 0x0 2. "STAT_3,Status of Calibration Step 3" "0: Test passed,1: Test failed" bitfld.long 0x0 1. "STAT_2,Status of Calibration Step 2" "0: Test passed,1: Test failed" newline bitfld.long 0x0 0. "STAT_1,Status of Calibration Step 1" "0: Test passed,1: Test failed" tree.end tree "ADC_1" base ad:0x402E8000 group.long 0x0++0x7 line.long 0x0 "MCR,Main Configuration" bitfld.long 0x0 31. "OWREN,Overwrite Enable" "0: Older valid conversion data is not overwritten..,1: Newer conversion result is always overwritten.." bitfld.long 0x0 30. "WLSIDE,Write Left Side" "0: Write right-aligned conversion data (from 11 to 0),1: Write left-aligned conversion data (from 15 to 4)" newline bitfld.long 0x0 29. "MODE,Normal Scan Mode Select" "0: One-Shot Operation mode: configuration for one..,1: Scan Operation mode: configuration for.." bitfld.long 0x0 27. "TRGEN,External Trigger Enable" "0: External trigger is disabled,1: Enables the external trigger to start a conversion" newline bitfld.long 0x0 26. "EDGE,Trigger Edge Select" "0: Falling edge is trigger,1: Rising edge is trigger" bitfld.long 0x0 24. "NSTART,Normal Conversion Start" "0,1" newline bitfld.long 0x0 22. "JTRGEN,Injection External Trigger Enable" "0: Injected conversion not started by external..,1: Injected conversion started by external trigger" bitfld.long 0x0 21. "JEDGE,Injection Trigger Edge Selection" "0: Falling edge is trigger,1: Rising edge is trigger" newline bitfld.long 0x0 20. "JSTART,Start Injection Conversion" "0,1" bitfld.long 0x0 17. "CTUEN,Cross Trigger Unit Enable" "0: The CTU is disabled and the triggered injected..,1: The CTU is enabled and the triggered injected.." newline bitfld.long 0x0 16. "CTU_MODE,Cross Trigger Unit Mode" "0: CTU control mode is selected,1: CTU trigger mode is selected" bitfld.long 0x0 15. "STCL,Self-Testing Configuration Lock" "0: Not locked,1: Locked" newline bitfld.long 0x0 14. "CALSTART,Calibration Start" "0: No effect,1: Start calibration" bitfld.long 0x0 13. "AVGEN,Average Enable" "0: Disable,1: Enable (default)" newline bitfld.long 0x0 11.--12. "NRSMPL,Number of Averaging Samples" "0: 16,1: 32,2: 128,3: 512" bitfld.long 0x0 9.--10. "TSAMP,Sample Time for Calibration" "0: 22 cycles of AD_CLK (default),1: 8 cycles of AD_CLK,2: 16 cycle of AD_CLK,3: 32 cycle of AD_CLK" newline bitfld.long 0x0 8. "ADCLKSE,Analog Clock Frequency Select" "0: AD_CLK frequency is half,1: AD_CLK frequency is equal to bus clock frequency" bitfld.long 0x0 7. "ABORTCHAIN,Abort Conversion Chain" "0: Chain conversion has been aborted or chain..,1: Abort current chain conversion." newline bitfld.long 0x0 6. "ABORT,Abort Conversion" "0: Channel conversion has been aborted or channel..,1: Abort current channel conversion." bitfld.long 0x0 5. "ACKO,Auto-Clock-Off Mode Enable" "0: Auto-Clock-Off feature is disabled,1: Auto-Clock-Off feature is enabled" newline bitfld.long 0x0 0. "PWDN,Power-Down Enable" "0: When ADC status is in Power-down mode..,1: Request to enter Power-down mode." line.long 0x4 "MSR,Main Status" rbitfld.long 0x4 31. "CALIBRTD,Calibration Status" "0: Uncalibrated or calibration unsuccessful,1: Calibrated or calibration successful" eventfld.long 0x4 30. "CALFAIL,Calibration Failed" "0: Calibration passed (must be checked with CALBUSY..,1: Calibration failed" newline rbitfld.long 0x4 29. "CALBUSY,Calibration Busy" "0: ADC is ready for use,1: ADC is busy in a calibration process" rbitfld.long 0x4 24. "NSTART,Normal Conversion Status" "0: Normal conversion is not in process,1: Normal conversion is in process" newline rbitfld.long 0x4 23. "JABORT,Injected Conversion Abort Status" "0: Injected conversion has not been aborted,1: Injected conversion has been aborted" rbitfld.long 0x4 20. "JSTART,Injected Conversion Status" "0: Injected conversion is not in process,1: Injected conversion is in process" newline rbitfld.long 0x4 18. "SELF_TEST_S,Self-Test Status" "0: Self-test conversion is not in process,1: Self-test conversion is in process" rbitfld.long 0x4 16. "CTUSTART,CTU Conversion Status" "0,1" newline hexmask.long.byte 0x4 9.--15. 1. "CHADDR,Channel Address" rbitfld.long 0x4 5. "ACKO,Auto-Clock-Off Enable" "0: Auto-Clock-Off feature is not enabled,1: Auto-Clock-Off feature is enabled" newline rbitfld.long 0x4 0.--2. "ADCSTATUS,ADC Status" "0: Idle,1: Power-down,2: Wait state (waiting to start conversion after..,3: Busy in calibration,4: Sample,?,6: Conversion,?" group.long 0x10++0xB line.long 0x0 "ISR,Interrupt Status" eventfld.long 0x0 4. "EOCTU,End of CTU Conversion" "0: CTU end of conversion has not occurred,1: CTU end of conversion has occurred" eventfld.long 0x0 3. "JEOC,Injected Channel End of Conversion" "0: Injected channel end of conversion has not..,1: Injected channel end of conversion has occurred" newline eventfld.long 0x0 2. "JECH,Injected End of Conversion Chain" "0: Injected channel end of conversion chain has not..,1: Injected channel end of conversion chain has.." eventfld.long 0x0 1. "EOC,End of Channel Conversion" "0: Channel end of conversion has not occurred,1: Channel end of conversion has occurred" newline eventfld.long 0x0 0. "ECH,End of Conversion Chain" "0: End of conversion chain has not occurred,1: End of conversion chain has occurred" line.long 0x4 "CEOCFR0,Channel Pending 0" eventfld.long 0x4 7. "EOC_CH7,Channel 7 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 6. "EOC_CH6,Channel 6 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 5. "EOC_CH5,Channel 5 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 4. "EOC_CH4,Channel 4 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 3. "EOC_CH3,Channel 3 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 2. "EOC_CH2,Channel 2 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 1. "EOC_CH1,Channel 1 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 0. "EOC_CH0,Channel 0 EOC Status" "0: Conversion not complete,1: Conversion complete" line.long 0x8 "CEOCFR1,Channel Pending 1" eventfld.long 0x8 7. "EOC_CH39,Channel 39 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 6. "EOC_CH38,Channel 38 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 5. "EOC_CH37,Channel 37 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 4. "EOC_CH36,Channel 36 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 3. "EOC_CH35,Channel 35 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 2. "EOC_CH34,Channel 34 EOC Status" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 1. "EOC_CH33,Channel 33 EOC Status" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 0. "EOC_CH32,Channel 32 EOC Status" "0: Conversion not complete,1: Conversion complete" group.long 0x20++0xB line.long 0x0 "IMR,Interrupt Mask" bitfld.long 0x0 4. "MSKEOCTU,End of CTU Conversion Interrupt Mask" "0: EOCTU interrupt disabled,1: EOCTU interrupt enabled" bitfld.long 0x0 3. "MSKJEOC,End of Injected Conversion Interrupt Mask" "0: End of injected conversion interrupt disabled,1: End of injected conversion interrupt enabled" newline bitfld.long 0x0 2. "MSKJECH,End of Injected Chain Conversion Interrupt Mask" "0: End of injected chain conversion interrupt..,1: End of injected chain conversion interrupt enabled" bitfld.long 0x0 1. "MSKEOC,End of Conversion Interrupt Mask" "0: End of conversion interrupt disabled,1: End of conversion interrupt enabled" newline bitfld.long 0x0 0. "MSKECH,End of Chain Conversion Interrupt Mask" "0: End of chain conversion interrupt disabled,1: End of chain conversion interrupt enabled" line.long 0x4 "CIMR0,Channel Interrupt Mask 0" bitfld.long 0x4 7. "CIM7,Channel 7 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "CIM6,Channel 6 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "CIM5,Channel 5 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "CIM4,Channel 4 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "CIM3,Channel 3 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "CIM2,Channel 2 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "CIM1,Channel 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "CIM0,Channel 0 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x8 "CIMR1,Channel Interrupt Mask 1" bitfld.long 0x8 7. "CIM39,Channel 39 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x8 6. "CIM38,Channel 38 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 5. "CIM37,Channel 37 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x8 4. "CIM36,Channel 36 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 3. "CIM35,Channel 35 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x8 2. "CIM34,Channel 34 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 1. "CIM33,Channel 33 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x8 0. "CIM32,Channel 32 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" group.long 0x30++0x7 line.long 0x0 "WTISR,Watchdog Threshold Interrupt Status" eventfld.long 0x0 15. "WDG7H,Channel 7 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 14. "WDG7L,Channel 7 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 13. "WDG6H,Channel 6 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 12. "WDG6L,Channel 6 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 11. "WDG5H,Channel 5 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 10. "WDG5L,Channel 5 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 9. "WDG4H,Channel 4 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 8. "WDG4L,Channel 4 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 7. "WDG3H,Channel 3 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 6. "WDG3L,Channel 3 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 5. "WDG2H,Channel 2 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 4. "WDG2L,Channel 2 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 3. "WDG1H,Channel 1 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 2. "WDG1L,Channel 1 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" newline eventfld.long 0x0 1. "WDG0H,Channel 0 Watchdog High Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" eventfld.long 0x0 0. "WDG0L,Channel 0 Watchdog Low Threshold Interrupt" "0: Interrupt not asserted,1: Interrupt asserted" line.long 0x4 "WTIMR,Watchdog Threshold Interrupt Mask" bitfld.long 0x4 15. "MSKWDG7H,Channel 7 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 14. "MSKWDG7L,Channel 7 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 13. "MSKWDG6H,Channel 6 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 12. "MSKWDG6L,Channel 6 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 11. "MSKWDG5H,Channel 5 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 10. "MSKWDG5L,Channel 5 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 9. "MSKWDG4H,Channel 4 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 8. "MSKWDG4L,Channel 4 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 7. "MSKWDG3H,Channel 3 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 6. "MSKWDG3L,Channel 3 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 5. "MSKWDG2H,Channel 2 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 4. "MSKWDG2L,Channel 2 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 3. "MSKWDG1H,Channel 1 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 2. "MSKWDG1L,Channel 1 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.long 0x4 1. "MSKWDG0H,Channel 0 Watchdog High Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.long 0x4 0. "MSKWDG0L,Channel 0 Watchdog Low Threshold Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled" group.long 0x40++0xB line.long 0x0 "DMAE,DMAE" bitfld.long 0x0 1. "DCLR,DMA Clear Sequence Enable" "0: DMA request cleared by acknowledge from DMA..,1: DMA request cleared on read of data registers" bitfld.long 0x0 0. "DMAEN,DMA Global Enable" "0: DMA feature is disabled,1: DMA feature is enabled" line.long 0x4 "DMAR0,DMA 0" bitfld.long 0x4 7. "DMA7,Channel 7 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x4 6. "DMA6,Channel 6 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x4 5. "DMA5,Channel 5 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x4 4. "DMA4,Channel 4 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x4 3. "DMA3,Channel 3 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x4 2. "DMA2,Channel 2 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x4 1. "DMA1,Channel 1 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x4 0. "DMA0,Channel 0 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" line.long 0x8 "DMAR1,DMA 1" bitfld.long 0x8 7. "DMA39,Channel 39 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x8 6. "DMA38,Channel 38 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x8 5. "DMA37,Channel 37 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x8 4. "DMA36,Channel 36 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x8 3. "DMA35,Channel 35 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x8 2. "DMA34,Channel 34 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" newline bitfld.long 0x8 1. "DMA33,Channel 33 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" bitfld.long 0x8 0. "DMA32,Channel 32 DMA Enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled" group.long 0x60++0xF line.long 0x0 "THRHLR0,Analog Watchdog Threshold 0" hexmask.long.word 0x0 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x0 0.--11. 1. "THRL,Low Threshold" line.long 0x4 "THRHLR1,Analog Watchdog Threshold 1" hexmask.long.word 0x4 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x4 0.--11. 1. "THRL,Low Threshold" line.long 0x8 "THRHLR2,Analog Watchdog Threshold 2" hexmask.long.word 0x8 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x8 0.--11. 1. "THRL,Low Threshold" line.long 0xC "THRHLR3,Analog Watchdog Threshold 3" hexmask.long.word 0xC 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0xC 0.--11. 1. "THRL,Low Threshold" group.long 0x80++0xB line.long 0x0 "PSCR,Presampling Control" bitfld.long 0x0 3.--4. "PREVAL1,Internal Presampling Voltage Selection." "0,1,2,3" bitfld.long 0x0 1.--2. "PREVAL0,Internal Presampling Voltage Selection" "0,1,2,3" newline bitfld.long 0x0 0. "PRECONV,Convert Presampled Value" "0: Presampling is followed by sampling then..,1: Presampling is followed by the conversion." line.long 0x4 "PSR0,Presampling 0" bitfld.long 0x4 7. "PRES7,Presampling Enable for Channel 7" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x4 6. "PRES6,Presampling Enable for Channel 6" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x4 5. "PRES5,Presampling Enable for Channel 5" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x4 4. "PRES4,Presampling Enable for Channel 4" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x4 3. "PRES3,Presampling Enable for Channel 3" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x4 2. "PRES2,Presampling Enable for Channel 2" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x4 1. "PRES1,Presampling Enable for Channel 1" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x4 0. "PRES0,Presampling Enable for Channel 0" "0: Presampling is disabled,1: Presampling is enabled" line.long 0x8 "PSR1,Presampling 1" bitfld.long 0x8 7. "PRES39,Presampling Enable for Channel 39" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x8 6. "PRES38,Presampling Enable for Channel 38" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x8 5. "PRES37,Presampling Enable for Channel 37" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x8 4. "PRES36,Presampling Enable for Channel 36" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x8 3. "PRES35,Presampling Enable for Channel 35" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x8 2. "PRES34,Presampling Enable for Channel 34" "0: Presampling is disabled,1: Presampling is enabled" newline bitfld.long 0x8 1. "PRES33,Presampling Enable for Channel 33" "0: Presampling is disabled,1: Presampling is enabled" bitfld.long 0x8 0. "PRES32,Presampling Enable for Channel 32" "0: Presampling is disabled,1: Presampling is enabled" group.long 0x94++0x7 line.long 0x0 "CTR0,Conversion Timing 0" hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,Sampling Phase Duration" line.long 0x4 "CTR1,Conversion Timing 1" hexmask.long.byte 0x4 0.--7. 1. "INPSAMP,Sampling Phase Duration" group.long 0xA4++0x7 line.long 0x0 "NCMR0,Normal Conversion Mask 0" bitfld.long 0x0 7. "CH7,Normal Conversion Mask for Channel 7" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x0 6. "CH6,Normal Conversion Mask for Channel 6" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x0 5. "CH5,Normal Conversion Mask for Channel 5" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x0 4. "CH4,Normal Conversion Mask for Channel 4" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x0 3. "CH3,Normal Conversion Mask for Channel 3" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x0 2. "CH2,Normal Conversion Mask for Channel 2" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x0 1. "CH1,Normal Conversion Mask for Channel 1" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x0 0. "CH0,Normal Conversion Mask for Channel 0" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" line.long 0x4 "NCMR1,Normal Conversion Mask 1" bitfld.long 0x4 7. "CH39,Normal Conversion Mask for Channel 39" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x4 6. "CH38,Normal Conversion Mask for Channel 38" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x4 5. "CH37,Normal Conversion Mask for Channel 37" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x4 4. "CH36,Normal Conversion Mask for Channel 36" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x4 3. "CH35,Normal Conversion Mask for Channel 35" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x4 2. "CH34,Normal Conversion Mask for Channel 34" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" newline bitfld.long 0x4 1. "CH33,Normal Conversion Mask for Channel 33" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" bitfld.long 0x4 0. "CH32,Normal Conversion Mask for Channel 32" "0: Normal Conversion is disabled,1: Normal Conversion is enabled" group.long 0xB4++0x7 line.long 0x0 "JCMR0,Injected Conversion Mask 0" bitfld.long 0x0 7. "CH7,Injected Conversion Mask for Channel 7" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x0 6. "CH6,Injected Conversion Mask for Channel 6" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x0 5. "CH5,Injected Conversion Mask for Channel 5" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x0 4. "CH4,Injected Conversion Mask for Channel 4" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x0 3. "CH3,Injected Conversion Mask for Channel 3" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x0 2. "CH2,Injected Conversion Mask for Channel 2" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x0 1. "CH1,Injected Conversion Mask for Channel 1" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x0 0. "CH0,Injected Conversion Mask for Channel 0" "0: Injected conversion is disabled,1: Injected conversion is enabled" line.long 0x4 "JCMR1,Injected Conversion Mask 1" bitfld.long 0x4 7. "CH39,Injected Conversion Mask for Channel 39" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x4 6. "CH38,Injected Conversion Mask for Channel 38" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x4 5. "CH37,Injected Conversion Mask for Channel 37" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x4 4. "CH36,Injected Conversion Mask for Channel 36" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x4 3. "CH35,Injected Conversion Mask for Channel 35" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x4 2. "CH34,Injected Conversion Mask for Channel 34" "0: Injected conversion is disabled,1: Injected conversion is enabled" newline bitfld.long 0x4 1. "CH33,Injected Conversion Mask for Channel 33" "0: Injected conversion is disabled,1: Injected conversion is enabled" bitfld.long 0x4 0. "CH32,Injected Conversion Mask for Channel 32" "0: Injected conversion is disabled,1: Injected conversion is enabled" group.long 0xC0++0x3 line.long 0x0 "USROFSGN,User OFFSET and Gain" hexmask.long.word 0x0 16.--25. 1. "GAINUSER,User-Defined Gain Value" hexmask.long.byte 0x0 0.--7. 1. "OFFSUSER,User Defined Offset" group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay" hexmask.long.byte 0x0 0.--7. 1. "PDED,Power Down Exist Delay" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x100)++0x3 line.long 0x0 "PCDR[$1],Precision Channel n Data" bitfld.long 0x0 19. "VALID,Conversion Data Valid" "0: Not valid data,1: Valid data" bitfld.long 0x0 18. "OVERW,Data Overwrite" "0: Data not overwritten,1: Data overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Mode of Conversion Status" "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" hexmask.long.word 0x0 0.--11. 1. "CDATA,Channel Converted Data" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x180)++0x3 line.long 0x0 "ICDR$1,Internal Channel n Data" bitfld.long 0x0 19. "VALID,Conversion Data Valid" "0: Not valid data,1: Valid data" bitfld.long 0x0 18. "OVERW,Data Overwrite" "0: Data not overwritten,1: Data overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Mode of Conversion Status" "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?" hexmask.long.word 0x0 0.--11. 1. "CDATA,Channel Converted Data" repeat.end group.long 0x280++0xF line.long 0x0 "THRHLR4,Analog Watchdog Threshold 4" hexmask.long.word 0x0 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x0 0.--11. 1. "THRL,Low Threshold" line.long 0x4 "THRHLR5,Analog Watchdog Threshold 5" hexmask.long.word 0x4 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x4 0.--11. 1. "THRL,Low Threshold" line.long 0x8 "THRHLR6,Analog Watchdog Threshold 6" hexmask.long.word 0x8 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0x8 0.--11. 1. "THRL,Low Threshold" line.long 0xC "THRHLR7,Analog Watchdog Threshold 7" hexmask.long.word 0xC 16.--27. 1. "THRH,High Threshold" hexmask.long.word 0xC 0.--11. 1. "THRL,Low Threshold" group.long 0x2B0++0x3 line.long 0x0 "CWSELR0,Channel Watchdog Select 0" bitfld.long 0x0 28.--30. "WSEL_CH7,Channel Watchdog Select for Channel 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "WSEL_CH6,Channel Watchdog Select for Channel 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WSEL_CH5,Channel Watchdog Select for Channel 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "WSEL_CH4,Channel Watchdog Select for Channel 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "WSEL_CH3,Channel Watchdog Select for Channel 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "WSEL_CH2,Channel Watchdog Select for Channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "WSEL_CH1,Channel Watchdog Select for Channel 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "WSEL_CH0,Channel Watchdog Select for Channel 0" "0,1,2,3,4,5,6,7" group.long 0x2C0++0x3 line.long 0x0 "CWSELR4,Channel Watchdog Select 4" bitfld.long 0x0 28.--30. "WSEL_CH39,Channel Watchdog Select for Channel 39" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "WSEL_CH38,Channel Watchdog Select for Channel 38" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WSEL_CH37,Channel Watchdog Select for Channel 37" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "WSEL_CH36,Channel Watchdog Select for Channel 36" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "WSEL_CH35,Channel Watchdog Select for Channel 35" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "WSEL_CH34,Channel Watchdog Select for Channel 34" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "WSEL_CH33,Channel Watchdog Select for Channel 33" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "WSEL_CH32,Channel Watchdog Select for Channel 32" "0,1,2,3,4,5,6,7" group.long 0x2E0++0x7 line.long 0x0 "CWENR0,Channel Watchdog Enable 0" bitfld.long 0x0 7. "CWEN7,Watchdog Enable for Channel 7" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x0 6. "CWEN6,Watchdog Enable for Channel 6" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x0 5. "CWEN5,Watchdog Enable for Channel 5" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x0 4. "CWEN4,Watchdog Enable for Channel 4" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x0 3. "CWEN3,Watchdog Enable for Channel 3" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x0 2. "CWEN2,Watchdog Enable for Channel 2" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x0 1. "CWEN1,Watchdog Enable for Channel 1" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x0 0. "CWEN0,Watchdog Enable for Channel 0" "0: Watchdog is disabled,1: Watchdog is enabled" line.long 0x4 "CWENR1,Channel Watchdog Enable 1" bitfld.long 0x4 7. "CWEN39,Watchdog Enable for Channel 39" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x4 6. "CWEN38,Watchdog Enable for Channel 38" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x4 5. "CWEN37,Watchdog Enable for Channel 37" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x4 4. "CWEN36,Watchdog Enable for Channel 36" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x4 3. "CWEN35,Watchdog Enable for Channel 35" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x4 2. "CWEN34,Watchdog Enable for Channel 34" "0: Watchdog is disabled,1: Watchdog is enabled" newline bitfld.long 0x4 1. "CWEN33,Watchdog Enable for Channel 33" "0: Watchdog is disabled,1: Watchdog is enabled" bitfld.long 0x4 0. "CWEN32,Watchdog Enable for Channel 32" "0: Watchdog is disabled,1: Watchdog is enabled" group.long 0x2F0++0x7 line.long 0x0 "AWORR0,Analog Watchdog Out of Range 0" eventfld.long 0x0 7. "AWOR_CH7,Analog Watchdog Out of Range for Channel 7" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x0 6. "AWOR_CH6,Analog Watchdog Out of Range for Channel 6" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x0 5. "AWOR_CH5,Analog Watchdog Out of Range for Channel 5" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x0 4. "AWOR_CH4,Analog Watchdog Out of Range for Channel 4" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x0 3. "AWOR_CH3,Analog Watchdog Out of Range for Channel 3" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x0 2. "AWOR_CH2,Analog Watchdog Out of Range for Channel 2" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x0 1. "AWOR_CH1,Analog Watchdog Out of Range for Channel 1" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x0 0. "AWOR_CH0,Analog Watchdog Out of Range for Channel 0" "0: Converted data is in range,1: Converted data is out of range" line.long 0x4 "AWORR1,Analog Watchdog Out of Range 1" eventfld.long 0x4 7. "AWOR_CH39,Analog Watchdog Out of Range for Channel 39" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x4 6. "AWOR_CH38,Analog Watchdog Out of Range for Channel 38" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x4 5. "AWOR_CH37,Analog Watchdog Out of Range for Channel 37" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x4 4. "AWOR_CH36,Analog Watchdog Out of Range for Channel 36" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x4 3. "AWOR_CH35,Analog Watchdog Out of Range for Channel 35" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x4 2. "AWOR_CH34,Analog Watchdog Out of Range for Channel 34" "0: Converted data is in range,1: Converted data is out of range" newline eventfld.long 0x4 1. "AWOR_CH33,Analog Watchdog Out of Range for Channel 33" "0: Converted data is in range,1: Converted data is out of range" eventfld.long 0x4 0. "AWOR_CH32,Analog Watchdog Out of Range for Channel 32" "0: Converted data is in range,1: Converted data is out of range" group.long 0x340++0x13 line.long 0x0 "STCR1,Self-Test Configuration 1" hexmask.long.byte 0x0 24.--31. 1. "INPSAMP_C,Sampling Configuration for Algorithm C" hexmask.long.byte 0x0 8.--15. 1. "INPSAMP_S,Sampling Configuration for Algorithm S" line.long 0x4 "STCR2,Self-Test Configuration 2" bitfld.long 0x4 27. "MSKWDSERR,Watchdog Sequence Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "SERR,Error Fault Injection Field (write-only)" "0,1" newline bitfld.long 0x4 25. "MSKWDTERR,Watchdog Timer Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 23. "MSKST_EOC,Self-Test EOC Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 18. "MSKWDG_EOA_C,End of Algorithm C Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "MSKWDG_EOA_S,End of Algorithm S Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "MSKERR_C,Error on Algorithm C Channel Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 13. "MSKERR_S2,Error on Algorithm S2 Channel Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "MSKERR_S1,Error on Algorithm S1 Channel Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 11. "MSKERR_S0,Error on Algorithm S0 Channel Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "EN,Self-testing channel enable" "0: Disable,1: Enable" bitfld.long 0x4 4. "FMA_WDSERR,Fault mapping for Watchdog Sequence Error" "0: NCF mapping,1: CF mapping" newline bitfld.long 0x4 3. "FMA_WDTERR,Fault mapping for watchdog timer error" "0: NCF mapping,1: CF mapping" bitfld.long 0x4 2. "FMA_C,Fault mapping for algorithm C" "0: NCF mapping,1: CF mapping" newline bitfld.long 0x4 0. "FMA_S,Fault mapping for BGAP algorithm" "0: Non-Critical Fault (NCF) mapping,1: Critical Fault (CF) mapping" line.long 0x8 "STCR3,Self-Test Configuration 3" bitfld.long 0x8 8.--9. "ALG,Self-Test Algorithm Select" "0: Algorithm S,?,2: Algorithm C,3: Algorithm S (for One-Shot Operation mode);.." hexmask.long.byte 0x8 0.--4. 1. "MSTEP,Self-Test Step Select" line.long 0xC "STBRR,Self-Test Baud Rate" bitfld.long 0xC 16.--18. "WDT,Watchdog Timer Value" "0: 0.1 ms ((0008h * Prescaler) cycles at 80 MHz),1: 0.5 ms ((0027h * Prescaler) cycles at 80 MHz),2: 1 ms ((004Eh * Prescaler) cycles at 80 MHz),3: 2 ms ((009Ch * Prescaler) cycles at 80 MHz),4: 5 ms ((0187h * Prescaler) cycles at 80 MHz),5: 10 ms ((030Dh * Prescaler) cycles at 80 MHz),6: 20 ms (061Ah * Prescaler) cycles at 80 MHz),7: 50 ms (0F42h *Prescaler) cycles at 80 MHz)" hexmask.long.byte 0xC 0.--7. 1. "BR,Algorithm Baud Rate" line.long 0x10 "STSR1,Self-Test Status 1" eventfld.long 0x10 27. "WDSERR,Watchdog Sequence Errors" "0: No failure,1: Failure occurred" eventfld.long 0x10 25. "WDTERR,Watchdog Timer Error" "0: No failure,1: Failure occurred" newline eventfld.long 0x10 24. "OVERWR,Overwrite Error" "0: No overwrite error,1: Overwrite error occurred" eventfld.long 0x10 23. "ST_EOC,Self-Test EOC" "0: Self-test end of conversion is not complete,1: Self-test end of conversion is complete" newline eventfld.long 0x10 18. "WDG_EOA_C,Watchdog End of Algorithm C" "0: Self-test end of Algorithm C conversion is not..,1: Self-test end of Algorithm C conversion is.." eventfld.long 0x10 16. "WDG_EOA_S,Watchdog End of Algorithm S" "0: Self-test end of Algorithm S conversion is not..,1: Self-test end of Algorithm S conversion is.." newline eventfld.long 0x10 15. "ERR_C,Algorithm C Error" "0: No Algorithm C error,1: Algorithm C error occurred" eventfld.long 0x10 13. "ERR_S2,Algorithm S2 Error" "0: No error occurred on the sampled signal,1: Error occurred on the sampled signal" newline eventfld.long 0x10 12. "ERR_S1,Algorithm S1 Error" "0: No VDD ERROR,1: VDD ERROR occurred" eventfld.long 0x10 11. "ERR_S0,Algorithm S0 Error" "0: No VREF error,1: VREF error occurred" newline hexmask.long.byte 0x10 5.--9. 1. "STEP_C,Algorithm C Step Number Error" rgroup.long 0x354++0xB line.long 0x0 "STSR2,Self-Test Status 2" bitfld.long 0x0 31. "OVFL,Overflow Bit" "0: Not Overflow,1: Overflow" hexmask.long.word 0x0 16.--27. 1. "DATA1,Test Channel Converted Data when ERR_S1 Occurred" newline hexmask.long.word 0x0 0.--11. 1. "DATA0,Test Channel Converted Data when ERR_S1 Occurred" line.long 0x4 "STSR3,Self-Test Status 3" hexmask.long.word 0x4 16.--27. 1. "DATA1,Test Channel Converted Data when ERR_C Occurred" hexmask.long.word 0x4 0.--11. 1. "DATA0,Test Channel Converted Data when ERR_S0 Occurred" line.long 0x8 "STSR4,Self-Test Status 4" hexmask.long.word 0x8 16.--27. 1. "DATA1,Test Channel Converted Data When ERR_C Occurred" rgroup.long 0x370++0x7 line.long 0x0 "STDR1,Self-Test Data 1" bitfld.long 0x0 19. "VALID,Valid Data" "0: Data not valid,1: Data valid" bitfld.long 0x0 18. "OWERWR,Overwrite Data" "0: Data not overwritten,1: Data overwritten" newline hexmask.long.word 0x0 0.--11. 1. "TCDATA,Test Channel Converted Data" line.long 0x4 "STDR2,Self-Test Data 2" hexmask.long.word 0x4 20.--31. 1. "FDATA,Fractional Data" bitfld.long 0x4 19. "VALID,Valid Data" "0: Data not valid,1: Data valid" newline bitfld.long 0x4 18. "OVERWR,Overwrite Data" "0: Data not overwritten,1: Data overwritten" hexmask.long.word 0x4 0.--11. 1. "IDATA,Integer Data" group.long 0x380++0xF line.long 0x0 "STAW0R,Self-Test Analog Watchdog 0" bitfld.long 0x0 31. "AWDE,Analog Watchdog Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 30. "WDTE,Watchdog timer enable (related to the Algorithm S)" "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 16.--27. 1. "THRH,High Threshold Value for Algorithm S Step0" hexmask.long.word 0x0 0.--11. 1. "THRL,Low Threshold Value for Algorithm S Step0" line.long 0x4 "STAW1AR,Self-Test Analog Watchdog 1A" bitfld.long 0x4 31. "AWDE,Analog Watchdog Enable" "0: Disabled,1: Enabled" hexmask.long.word 0x4 16.--27. 1. "THRH,High Threshold Value for Algorithm S Step1" newline hexmask.long.word 0x4 0.--11. 1. "THRL,Low Threshold Value for Algorithm S Step1" line.long 0x8 "STAW1BR,Self-Test Analog Watchdog 1B" hexmask.long.word 0x8 16.--27. 1. "THRH,High Threshold Value for Algorithm S Step1" hexmask.long.word 0x8 0.--11. 1. "THRL,Low Threshold Value for Algorithm S Step1" line.long 0xC "STAW2R,Self-Test Analog Watchdog 2" bitfld.long 0xC 31. "AWDE,Analog Watchdog Enable" "0: Disabled,1: Enabled" hexmask.long.word 0xC 0.--11. 1. "THRL,Threshold level low" rgroup.long 0x390++0x3 line.long 0x0 "STAW3R,Self-Test Analog Watchdog 3" group.long 0x394++0x7 line.long 0x0 "STAW4R,Self-Test Analog Watchdog 4" bitfld.long 0x0 31. "AWDE,Analog Watchdog Enable (Related to Algorithm C)" "0: Disabled,1: Enabled" bitfld.long 0x0 30. "WDTE,Watchdog Timer Enable (Related to Algorithm C)." "0: Disabled,1: Enabled" newline hexmask.long.word 0x0 16.--27. 1. "THRH,High Threshold Value for Step0 of Algorithm C" hexmask.long.word 0x0 0.--11. 1. "THRL,Low Threshold Value for Step0 of Algorithm C" line.long 0x4 "STAW5R,Self-Test Analog Watchdog 5" hexmask.long.word 0x4 16.--27. 1. "THRH,High Threshold Value for Step N of Algorithm C (N = 1 to CS-1)." hexmask.long.word 0x4 0.--11. 1. "THRL,Low Threshold Value for Step0 of Algorithm C." rgroup.long 0x39C++0x3 line.long 0x0 "CALSTAT,Calibration Status" hexmask.long.word 0x0 16.--31. 1. "TEST_RESULT,TEST_RESULT" bitfld.long 0x0 13. "STAT_14,Status of Calibration Step 14" "0: Calibration step pass,1: Calibration step fail" newline bitfld.long 0x0 12. "STAT_13,Status of Calibration Step 13" "0: Calculated gain within range,1: Calculated gain out of range" bitfld.long 0x0 11. "STAT_12,Status of Calibration Step 12" "0: Test passed,1: Test failed" newline bitfld.long 0x0 10. "STAT_11,Status of Calibration Step 11" "0: Test passed,1: Test failed" bitfld.long 0x0 9. "STAT_10,Status of Calibration Step 10" "0: Test passed,1: Test failed" newline bitfld.long 0x0 8. "STAT_9,Status of Calibration Step 9" "0: Test passed,1: Test failed" bitfld.long 0x0 7. "STAT_8,Status of Calibration Step 8" "0: Test passed,1: Test failed" newline bitfld.long 0x0 6. "STAT_7,Status of Calibration Step 7" "0: Test passed,1: Test failed" bitfld.long 0x0 5. "STAT_6,Status of Calibration Step 6" "0: Test passed,1: Test failed" newline bitfld.long 0x0 4. "STAT_5,Status of Calibration Step 5" "0: Test passed,1: Test failed" bitfld.long 0x0 3. "STAT_4,Status of calibration step 4" "0: Test passed,1: Test failed" newline bitfld.long 0x0 2. "STAT_3,Status of Calibration Step 3" "0: Test passed,1: Test failed" bitfld.long 0x0 1. "STAT_2,Status of Calibration Step 2" "0: Test passed,1: Test failed" newline bitfld.long 0x0 0. "STAT_1,Status of Calibration Step 1" "0: Test passed,1: Test failed" tree.end tree.end tree "ATP (Aurora Trace Port)" base ad:0x51033000 group.long 0x0++0xB line.long 0x0 "PLLC,PLL Control" bitfld.long 0x0 31. "PLLPD,PLL Reset" "0: Analog PLL reset is deasserted.,1: Analog PLL reset is asserted." line.long 0x4 "PLLS,PLL Status" eventfld.long 0x4 3. "LOL,PLL Loss of Lock Status" "0: No loss-of-lock detected.,1: Loss-of-lock detected." rbitfld.long 0x4 2. "LOCK,PLL Lock Status" "0: PLL unlocked.,1: PLL locked." line.long 0x8 "PLLDIV,PLL Divider" hexmask.long.byte 0x8 16.--21. 1. "ODIV1,PLL Output Division Factor 1" bitfld.long 0x8 12.--14. "RDIV,PLL Input Clock Predivider" "0: Divide by 1,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,5: Divide by 5,6: Divide by 6,7: Divide by 7" newline hexmask.long.byte 0x8 0.--7. 1. "MFID,PLL Multiplication Factor Integer Divider" group.long 0x18++0x3 line.long 0x0 "PLLCAL_2,PLL Calibration 2" bitfld.long 0x0 17.--18. "CALDPER,Calibration DAC Period" "0: Not allowed,1: Not allowed,2: 64 DAC settling time (in terms of number of PLL..,3: Not allowed" group.long 0x20++0x3 line.long 0x0 "PLLCKMUX,PLL Clock MUX" bitfld.long 0x0 0.--1. "REFCLKSEL,Reference Clock Selection" "0: 100 MHz LVDS reference clock (AURORA_EXT_CLK),1: 40 MHz crystal oscillator clock (FXOSC_CLK),?,?" rgroup.long 0x300++0x3 line.long 0x0 "ALS,AL Status" bitfld.long 0x0 10.--12. "TXCFG,TX Lane Configuration" "?,1: 2 TX lanes.,?,3: 4 TX lanes.,?,?,?,?" bitfld.long 0x0 9. "PRST,Channel Partner Reset" "0: No reset of channel partner.,1: Channel partner has reset (causes AL to reset as.." newline bitfld.long 0x0 2.--3. "TS,Training Status" "0: Training has not completed any stage.,1: AL has successfully completed symbol lock and..,2: AL has successfully completed channel bonding.,3: AL has successfully completed verification." bitfld.long 0x0 1. "CS,Channel Status" "0: Aurora channel not ready.,1: Aurora channel ready." newline bitfld.long 0x0 0. "AS,Aurora Status" "0: Aurora not enabled.,1: Aurora enabled." group.long 0x308++0x7 line.long 0x0 "ALGC,AL General Control" bitfld.long 0x0 31. "RST,Aurora Channel Reset" "0,1" bitfld.long 0x0 14. "PCRST,Protocol Converter Reset" "0,1" newline bitfld.long 0x0 3. "CRCEN,CRC Enable" "0: CRC generation is disabled for TX data.,1: CRC is inserted for TX frames." bitfld.long 0x0 2. "CCOEN,Clock Compensation Override Enable" "0: Clock compensation counter times out at 7427..,1: Clock compensation counter times out at 1280.." line.long 0x4 "ALTC,AL Training Control" bitfld.long 0x4 31. "STE,Static Training Enable" "?,1: Static (timer based) training method is used for.." bitfld.long 0x4 30. "AHD,Hold in Align" "0: Follows Aurora training sequence,1: AL remains in align until this bit is cleared." newline bitfld.long 0x4 29. "BHD,Hold in Bond" "0: Follows Aurora training sequence,1: AL remains in bond until this bit is cleared." bitfld.long 0x4 28. "VHD,Hold in Verify" "0: Follows Aurora training sequence,1: AL remains in verify until this bit is cleared." newline hexmask.long.byte 0x4 19.--22. 1. "ATC,Align Timer Count" hexmask.long.byte 0x4 10.--13. 1. "BTC,Bond Timer Count" newline hexmask.long.byte 0x4 0.--3. 1. "VTC,Verify Timer Count" group.long 0x440++0xB line.long 0x0 "LVDSTX,LVDS TX IO Configuration" bitfld.long 0x0 16. "PADS_TX_CONF_EN,PADS TX Configuration Enable" "0: PADS TX configuration disabled,1: PADS TX configuration enabled" hexmask.long.byte 0x0 12.--15. 1. "TX_CONF,LVDS PADS TX Control Configuration" newline bitfld.long 0x0 5.--6. "PREMPH,Pre-Emphasis Configuration" "0,1,2,3" bitfld.long 0x0 2. "TX_TREF_EN,TX LVDS Termination Reference Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "CREF_EN,Current Reference Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "TXAMODE,TX Aurora pad mode enable" "0: Disable,1: Enable" line.long 0x4 "LVDSRX,LVDS RX IO Configuration" bitfld.long 0x4 16. "RX_TREF_EN,RX LVDS Termination Reference Enable" "0: Disable,1: Enable" bitfld.long 0x4 3. "RXCB,RX LVDS Current Boost" "0: Current reference is 100 uA.,1: Current reference is 1 mA." newline bitfld.long 0x4 1. "RXICE,RX Input Clock Enable" "0: Disable input buffer,1: Enable input buffer" line.long 0x8 "LVDSTXOBE,LVDS TX OBE Configuration" bitfld.long 0x8 3. "OBETX3,TX-3 Aurora pad output buffer enable" "0: Disable,1: Enable" bitfld.long 0x8 2. "OBETX2,TX-2 Aurora pad output buffer enable" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "OBETX1,TX-1 Aurora pad output buffer enable" "0: Disable,1: Enable" bitfld.long 0x8 0. "OBETX0,TX-0 Aurora pad output buffer enable" "0: Disable,1: Enable" group.long 0x480++0x3 line.long 0x0 "CIAC,CIA Control" bitfld.long 0x0 29. "TPIU_CLK_DISABLE,TPIU clock disable" "0: Enable,1: Disable" bitfld.long 0x0 28. "TPIU_CLK_SEL,TPIU clock mux select signal" "0: FIRC,1: AURORA_CLK clock" newline bitfld.long 0x0 9. "DBYTER,TPIU data bytes is reversed" "0: Disable byte reversal,1: Enable byte reversal" bitfld.long 0x0 8. "DBITR,TPIU data bit reversal in a byte selection." "0: Disable bit reversal,1: Enable bit reversal" newline bitfld.long 0x0 4.--6. "TPIUCM,TPIU Control Mode" "0: Continuous and format mode.,1: Normal mode. Only trace data is captured.,?,?,?,?,?,7: Trace disable mode." hexmask.long.byte 0x0 0.--3. 1. "NUM_LANE,Number of Aurora Lanes" group.long 0x488++0x3 line.long 0x0 "ATPE,Aurora Trace Port Enable" bitfld.long 0x0 1. "APHYEN,Aurora PHY Enable 0-AP Disable 1-AP Enable" "0,1" bitfld.long 0x0 0. "ATPEN,Aurora Trace Port Enable" "0: Disable,1: Enable" rgroup.long 0xF00++0x3 line.long 0x0 "ITCTRL,Integration Mode Control" bitfld.long 0x0 0. "IME,The bit field is always 0 indicating ATP only supports functional mode." "0,1" rgroup.long 0xFA0++0xF line.long 0x0 "CLAIMSET,Claim Tag Set" hexmask.long 0x0 0.--31. 1. "SET,This field is always 0 indicating no claim tag is implemented." line.long 0x4 "CLAIMCLR,Claim Tag Clear" hexmask.long 0x4 0.--31. 1. "CLR,This field is always 0 indicating no effect on claim tag." line.long 0x8 "DEVAFF0,Device Affinity 0" hexmask.long 0x8 0.--31. 1. "DEVAFF0,Value of this field is set to 24h." line.long 0xC "DEVAFF1,Device Affinity 1" hexmask.long 0xC 0.--31. 1. "DEVAFF1,Value of this field is set to 24h." wgroup.long 0xFB0++0x3 line.long 0x0 "LAR,Lock Access Register" hexmask.long 0x0 0.--31. 1. "KEY,The value of this register must match with the expected key when the most significant bit of address is 0 (core access)" rgroup.long 0xFB4++0x1F line.long 0x0 "LSR,Lock Status Register" bitfld.long 0x0 2. "nTT,Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit." "0,1" bitfld.long 0x0 1. "SLK,Software Lock Status. Returns the present lock status of the device." "0: Lock matched and write operations are permitted.,1: Lock not matched and write operations are not.." newline bitfld.long 0x0 0. "SLI,This field is always 1 and indicates that Software Lock control mechanism exists for this device." "0,1" line.long 0x4 "AUTHSTATUS,Authentication Status" hexmask.long.byte 0x4 0.--7. 1. "AUTHSTATUS,This field is always 0 indicating that debug level authentication status is not supported." line.long 0x8 "DEVARCH,Device Architecture" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Defines the architect of the component." bitfld.long 0x8 20. "PRESENT,Indicates the presence of this register." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "REVISION,Architecture revision" hexmask.long.word 0x8 0.--15. 1. "ARCHID,Architecture ID" line.long 0xC "DEVID2,Device Configuration 2" hexmask.long 0xC 0.--31. 1. "DEVID2,The value of the field is always 0." line.long 0x10 "DEVID1,Device Configuration 1" hexmask.long 0x10 0.--31. 1. "DEVID1,The value of the field is always 0." line.long 0x14 "DEVID,Device Configuration" hexmask.long 0x14 0.--31. 1. "DEVID,The value of the field is always 0." line.long 0x18 "DEVTYPE,Device Type Identifier" hexmask.long.byte 0x18 4.--7. 1. "SUB,Sub Type" hexmask.long.byte 0x18 0.--3. 1. "MAJOR,Major Type" line.long 0x1C "PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x1C 4.--7. 1. "SIZE,4KB Count" hexmask.long.byte 0x1C 0.--3. 1. "DES_2,JEP106 Continuation Code" rgroup.long 0xFE0++0x1F line.long 0x0 "PIDR0,Peripheral Identification Register 0" hexmask.long.byte 0x0 0.--7. 1. "PART_0,Part number bits[7:0]" line.long 0x4 "PIDR1,Peripheral Identification Register 1" hexmask.long.byte 0x4 4.--7. 1. "DES_0,JEP106 identification code bits[3:0]" hexmask.long.byte 0x4 0.--3. 1. "PART_1,Part number bits[11:8]" line.long 0x8 "PIDR2,Peripheral Identification Register 2" hexmask.long.byte 0x8 4.--7. 1. "REVISION,Revision" bitfld.long 0x8 3. "JEDEC,This bit is always set which indicates that a JEDEC assigned value is used." "0,1" newline bitfld.long 0x8 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7" line.long 0xC "PIDR3,Peripheral Identification Register 3" hexmask.long.byte 0xC 4.--7. 1. "CMOD,Customer Modified" hexmask.long.byte 0xC 0.--3. 1. "REVAND,RevAnd" line.long 0x10 "CIDR0,Component Identification Register 0" hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble" line.long 0x14 "CIDR1,Component Identification Register 1" hexmask.long.byte 0x14 4.--7. 1. "CLASS,Component class" hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1,Preamble" line.long 0x18 "CIDR2,Component Identification Register 2" hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble" line.long 0x1C "CIDR3,Component Identification Register 3" hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble" tree.end tree "BOOT" base ad:0x4007C900 rgroup.long 0x0++0x7 line.long 0x0 "BOOT_GPR_BMR1,Boot Configuration 1" hexmask.long 0x0 0.--31. 1. "BOOT_CFG,Boot Configuration" line.long 0x4 "BOOT_GPR_BMR2,Boot Configuration 2" bitfld.long 0x4 25. "BOOTMOD1,Boot Mode Pin 1" "0,1" bitfld.long 0x4 24. "BOOTMOD2,Boot Mode Pin 2" "0,1" bitfld.long 0x4 4. "FUSE_SEL,Select Boot from Fuses" "0,1" tree.end tree "CAIU (Coherent Agent Interface Unit)" base ad:0x0 tree "CAIU0" base ad:0x50400000 group.long 0x0++0x3 line.long 0x0 "CAIUTC,CAIU Transaction Control" bitfld.long 0x0 1. "ISOLEN,Agent Isolation Enable" "0,1" bitfld.long 0x0 0. "TRANSEN,Agent Transaction Enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CAIUTA,CAIU Transaction Activity" bitfld.long 0x0 2. "COHACTV,Coherent Transaction Active" "0,1" bitfld.long 0x0 1. "SNPACTV,Snoop Transaction Active" "0,1" bitfld.long 0x0 0. "TRANSACTV,Transaction Active" "0,1" group.long 0x100++0xF line.long 0x0 "CAIUCEC,CAIU Correctable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Correctable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Correctable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Correctable Error Detection Enable" "0: Disable correctable error detection and logging..,1: Enable correctable error detection and logging.." line.long 0x4 "CAIUCES,CAIU Correctable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "CAIUCELR0,CAIU Correctable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry or Set" line.long 0xC "CAIUCELR1,CAIU Correctable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x124++0x3 line.long 0x0 "CAIUCESA,CAIU Correctable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" group.long 0x140++0xF line.long 0x0 "CAIUUEC,CAIU Uncorrectable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Uncorrectable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Uncorrectable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Uncorrectable Error Detection Enable" "0: Disable uncorrectable error detection and..,1: Enable uncorrectable error detection and logging.." line.long 0x4 "CAIUUES,CAIU Uncorrectable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "CAIUUELR0,CAIU Uncorrectable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry or Set" line.long 0xC "CAIUUELR1,CAIU Uncorrectable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x164++0x3 line.long 0x0 "CAIUUESA,CAIU Uncorrectable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "CAIUID,CAIU Identification" hexmask.long.byte 0x0 20.--24. 1. "SFID,Snoop Filter Identifier" hexmask.long.byte 0x0 16.--19. 1. "TYPE,Type" bitfld.long 0x0 15. "CA,Caching Agent" "0: CAI is not represented as a caching agent,1: CAI is represented as a caching agent" hexmask.long.byte 0x0 8.--14. 1. "CAIID,CAI Identifier" newline hexmask.long.byte 0x0 0.--7. 1. "IMPLVER,Implementation Version" tree.end tree "CAIU1" base ad:0x50401000 group.long 0x0++0x3 line.long 0x0 "CAIUTC,CAIU Transaction Control" bitfld.long 0x0 1. "ISOLEN,Agent Isolation Enable" "0,1" bitfld.long 0x0 0. "TRANSEN,Agent Transaction Enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CAIUTA,CAIU Transaction Activity" bitfld.long 0x0 2. "COHACTV,Coherent Transaction Active" "0,1" bitfld.long 0x0 1. "SNPACTV,Snoop Transaction Active" "0,1" bitfld.long 0x0 0. "TRANSACTV,Transaction Active" "0,1" group.long 0x100++0xF line.long 0x0 "CAIUCEC,CAIU Correctable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Correctable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Correctable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Correctable Error Detection Enable" "0: Disable correctable error detection and logging..,1: Enable correctable error detection and logging.." line.long 0x4 "CAIUCES,CAIU Correctable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "CAIUCELR0,CAIU Correctable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry or Set" line.long 0xC "CAIUCELR1,CAIU Correctable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x124++0x3 line.long 0x0 "CAIUCESA,CAIU Correctable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" group.long 0x140++0xF line.long 0x0 "CAIUUEC,CAIU Uncorrectable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Uncorrectable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Uncorrectable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Uncorrectable Error Detection Enable" "0: Disable uncorrectable error detection and..,1: Enable uncorrectable error detection and logging.." line.long 0x4 "CAIUUES,CAIU Uncorrectable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "CAIUUELR0,CAIU Uncorrectable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry or Set" line.long 0xC "CAIUUELR1,CAIU Uncorrectable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x164++0x3 line.long 0x0 "CAIUUESA,CAIU Uncorrectable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "CAIUID,CAIU Identification" hexmask.long.byte 0x0 20.--24. 1. "SFID,Snoop Filter Identifier" hexmask.long.byte 0x0 16.--19. 1. "TYPE,Type" bitfld.long 0x0 15. "CA,Caching Agent" "0: CAI is not represented as a caching agent,1: CAI is represented as a caching agent" hexmask.long.byte 0x0 8.--14. 1. "CAIID,CAI Identifier" newline hexmask.long.byte 0x0 0.--7. 1. "IMPLVER,Implementation Version" tree.end tree.end tree "CCTI_FAULT_CTRL" base ad:0x50500000 rgroup.long 0x0++0x2B line.long 0x0 "COREID,Core ID" hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Core Checksum" hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Core Type ID" line.long 0x4 "REVISIONID,Revision ID" hexmask.long.tbyte 0x4 8.--31. 1. "NOCID,NoC ID" hexmask.long.byte 0x4 0.--7. 1. "USERID,User ID" line.long 0x8 "MISSION_FAULT0,Mission Fault 0" hexmask.long 0x8 0.--31. 1. "MISSIONFAULT0,Mission Fault" line.long 0xC "MISSION_FAULT1,Mission Fault 1" hexmask.long 0xC 0.--31. 1. "MISSIONFAULT1,Mission Fault" line.long 0x10 "MISSION_FAULT2,Mission Fault 2" hexmask.long 0x10 0.--31. 1. "MISSIONFAULT2,Mission Fault" line.long 0x14 "MISSION_FAULT3,Mission Fault 3" hexmask.long 0x14 0.--31. 1. "MISSIONFAULT3,Mission Fault" line.long 0x18 "LATENT_FAULT0,Latent Fault 0" hexmask.long 0x18 0.--31. 1. "LATENTFAULT0,Latent Fault" line.long 0x1C "LATENT_FAULT1,Latent Fault 1" hexmask.long 0x1C 0.--31. 1. "LATENTFAULT1,Latent Fault" line.long 0x20 "LATENT_FAULT2,Latent Fault 2" hexmask.long 0x20 0.--31. 1. "LATENTFAULT2,Latent Fault" line.long 0x24 "LATENT_FAULT3,Latent Fault 3" hexmask.long 0x24 0.--31. 1. "LATENTFAULT3,Latent Fault" line.long 0x28 "FAULTS,Faults" bitfld.long 0x28 1. "MISSIONFAULT,Mission Fault" "0,1" bitfld.long 0x28 0. "LATENTFAULT,Latent Fault" "0,1" group.long 0x2C++0xB line.long 0x0 "INTEN,Interrupt Enable" bitfld.long 0x0 1. "MISSIONFAULTEN,Mission Fault Interrupt Enable" "0,1" bitfld.long 0x0 0. "BISTDONEEN,BIST Done Interrupt Enable" "0,1" line.long 0x4 "INTCLR,Interrupt Clear" eventfld.long 0x4 1. "MISSIONFAULTCLR,Clear Mission Fault" "0,1" eventfld.long 0x4 0. "LATENTFAULTCLR,Clear Latent Fault" "0,1" line.long 0x8 "BISTCTL,BIST Control" eventfld.long 0x8 1. "BISTDONECLR,Clear BIST Done" "0,1" eventfld.long 0x8 0. "BISTSTART,Start BIST Sequence" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "BIST_DONE,BIST Done" bitfld.long 0x0 1. "MISSIONMODE,Mission Mode Status" "0,1" bitfld.long 0x0 0. "BISTDONE,BIST Done Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "BIST_TO1,BIST Timeout 1" hexmask.long.word 0x0 0.--15. 1. "BISTTO1,BIST Timeout" line.long 0x4 "BIST_TO2,BIST Timeout 2" hexmask.long.byte 0x4 0.--7. 1. "BISTTO2,BIST Timeout" tree.end tree "CM7_GPR (CORTEXM7 Cluster General Purpose Registers)" base ad:0x0 tree "CM7_GPR_0" base ad:0x4007C100 group.long 0x0++0x3 line.long 0x0 "CORTEXM7_GPR0,Cortex-M7 GPR0" bitfld.long 0x0 1. "CM7_CPU_EVENT_GENERATE,Cortex-M7 Event Generate" "0: Do not set event,1: Set event" bitfld.long 0x0 0. "CM7_CPU_WAIT,Cortex-M7 CPU Wait" "0: Do not assert wait,1: Assert wait" tree.end tree "CM7_GPR_1" base ad:0x4007C200 group.long 0x0++0x3 line.long 0x0 "CORTEXM7_GPR0,Cortex-M7 GPR0" bitfld.long 0x0 1. "CM7_CPU_EVENT_GENERATE,Cortex-M7 Event Generate" "0: Do not set event,1: Set event" bitfld.long 0x0 0. "CM7_CPU_WAIT,Cortex-M7 CPU Wait" "0: Do not assert wait,1: Assert wait" tree.end tree "CM7_GPR_2" base ad:0x4007C300 group.long 0x0++0x3 line.long 0x0 "CORTEXM7_GPR0,Cortex-M7 GPR0" bitfld.long 0x0 1. "CM7_CPU_EVENT_GENERATE,Cortex-M7 Event Generate" "0: Do not set event,1: Set event" bitfld.long 0x0 0. "CM7_CPU_WAIT,Cortex-M7 CPU Wait" "0: Do not assert wait,1: Assert wait" tree.end tree.end tree "CMIU (Coherent Memory Interface Unit)" base ad:0x504C0000 rgroup.long 0x4++0x3 line.long 0x0 "CMIUTA,CMIU Transaction Activity" bitfld.long 0x0 0. "TRANSACTV,Transaction Active" "0,1" group.long 0x100++0xF line.long 0x0 "CMIUCEC,CMIU Correctable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Correctable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Correctable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Correctable Error Detection Enable" "0: Disable correctable error detection and logging..,1: Enable correctable error detection and logging.." line.long 0x4 "CMIUCES,CMIU Correctable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "CMIUCELR0,CMIU Correctable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry or Set" line.long 0xC "CMIUCELR1,CMIU Correctable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x124++0x3 line.long 0x0 "CMIUCESA,CMIU Correctable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" group.long 0x140++0xF line.long 0x0 "CMIUUEC,CMIU Uncorrectable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Uncorrectable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Uncorrectable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Uncorrectable Error Detection Enable" "0: Disable uncorrectable error detection and..,1: Enable uncorrectable error detection and logging.." line.long 0x4 "CMIUUES,CMIU Uncorrectable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "CMIUUELR0,CMIU Uncorrectable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry (or Set)" line.long 0xC "CMIUUELR1,CMIU Uncorrectable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x164++0x3 line.long 0x0 "CMIUUESA,CMIU Uncorrectable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "CMIUID,CMIU Identification Register" hexmask.long.byte 0x0 8.--12. 1. "CMIID,Coherent Memory Interface Identifier" hexmask.long.byte 0x0 0.--7. 1. "IMPLVER,Implementation Version" tree.end tree "CMU_FC (Clock Monitoring Unit-Frequency Check)" base ad:0x0 tree "CMU_FC_0" base ad:0x4005C000 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_5" base ad:0x4005C0A0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_6" base ad:0x4005C0C0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_7" base ad:0x4005C0E0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_8" base ad:0x4005C100 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_9" base ad:0x4005C120 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_10" base ad:0x4005C140 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_11" base ad:0x4005C160 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_12" base ad:0x4005C180 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_13" base ad:0x4005C1A0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_14" base ad:0x4005C1C0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_15" base ad:0x4005C1E0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_16" base ad:0x4005C200 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_17" base ad:0x4005C220 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_18" base ad:0x4005C240 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_20" base ad:0x4005C280 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_21" base ad:0x4005C2A0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_22" base ad:0x4005C2C0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_27" base ad:0x4005C360 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_28" base ad:0x4005C380 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_39" base ad:0x4005C4E0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_46" base ad:0x4005C5C0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_47" base ad:0x4005C5E0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_48" base ad:0x4005C600 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_49" base ad:0x4005C620 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_50" base ad:0x4005C640 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree "CMU_FC_51" base ad:0x4005C660 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" tree.end tree.end tree "CMU_FM (Clock Monitoring Unit - Frequency Meter)" base ad:0x0 tree "CMU_FM_1" base ad:0x4005C020 group.long 0x0++0xB line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FME,Frequency Meter Enable" "0: Stops frequency metering,1: Starts frequency metering" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference Clock Count" line.long 0x8 "SR,Status Register" hexmask.long.tbyte 0x8 8.--31. 1. "MET_CNT,Meter Clock Count" rbitfld.long 0x8 4. "RS,Run Status" "0: Frequency meter stopped,1: Frequency meter running" eventfld.long 0x8 1. "FMTO,Frequency Meter Time Out" "0,1" eventfld.long 0x8 0. "FMC,Frequency Meter Operation Complete" "0,1" tree.end tree "CMU_FM_2" base ad:0x4005C040 group.long 0x0++0xB line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FME,Frequency Meter Enable" "0: Stops frequency metering,1: Starts frequency metering" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference Clock Count" line.long 0x8 "SR,Status Register" hexmask.long.tbyte 0x8 8.--31. 1. "MET_CNT,Meter Clock Count" rbitfld.long 0x8 4. "RS,Run Status" "0: Frequency meter stopped,1: Frequency meter running" eventfld.long 0x8 1. "FMTO,Frequency Meter Time Out" "0,1" eventfld.long 0x8 0. "FMC,Frequency Meter Operation Complete" "0,1" tree.end tree "CMU_FM_3" base ad:0x4005C060 group.long 0x0++0xB line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FME,Frequency Meter Enable" "0: Stops frequency metering,1: Starts frequency metering" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference Clock Count" line.long 0x8 "SR,Status Register" hexmask.long.tbyte 0x8 8.--31. 1. "MET_CNT,Meter Clock Count" rbitfld.long 0x8 4. "RS,Run Status" "0: Frequency meter stopped,1: Frequency meter running" eventfld.long 0x8 1. "FMTO,Frequency Meter Time Out" "0,1" eventfld.long 0x8 0. "FMC,Frequency Meter Operation Complete" "0,1" tree.end tree "CMU_FM_4" base ad:0x4005C080 group.long 0x0++0xB line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FME,Frequency Meter Enable" "0: Stops frequency metering,1: Starts frequency metering" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference Clock Count" line.long 0x8 "SR,Status Register" hexmask.long.tbyte 0x8 8.--31. 1. "MET_CNT,Meter Clock Count" rbitfld.long 0x8 4. "RS,Run Status" "0: Frequency meter stopped,1: Frequency meter running" eventfld.long 0x8 1. "FMTO,Frequency Meter Time Out" "0,1" eventfld.long 0x8 0. "FMC,Frequency Meter Operation Complete" "0,1" tree.end tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x40190000 group.long 0x0++0x3 line.long 0x0 "CFG1,Configuration Register" hexmask.long.byte 0x0 8.--11. 1. "POLYG_EXT,Polynomial Selection Extend" bitfld.long 0x0 5. "SWAP_BYTEWISE,Swap CRC_INP byte-wise" "0: Do not swap,1: Perform byte-wise swap on CRC_INP input data.." newline bitfld.long 0x0 4. "SWAP_BITWISE,Swap CRC_INP bit-wise" "0: Do not swap,1: Perform bit-wise swap on CRC_INP input data.." bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8-H2F AUTOSAR polynomial" newline bitfld.long 0x0 1. "SWAP,Swap selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." bitfld.long 0x0 0. "INV,Inversion selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40190000 ad:0x40190010 ad:0x40190020) tree "CHANNEL_EXT[$1]" base $2 group.long ($2+0x108)++0x3 line.long 0x0 "CSTAT_EXT,Current Status Extend Register" hexmask.long 0x0 0.--31. 1. "CSTAT_EXT,CRC signature status Extension for CRC64" rgroup.long ($2+0x10C)++0x3 line.long 0x0 "OUTP_EXT,Output Extend Register" hexmask.long 0x0 0.--31. 1. "OUTP_EXT,Final CRC signature Extension for CRC64" tree.end repeat.end base ad:0x40190000 group.long 0x4++0x7 line.long 0x0 "INP1,Input Register" hexmask.long 0x0 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x4 "CSTAT1,Current Status Register" hexmask.long 0x4 0.--31. 1. "CSTAT,CRC signature status" rgroup.long 0xC++0x3 line.long 0x0 "OUTP1,Output Register" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x10++0xB line.long 0x0 "CFG2,Configuration Register" hexmask.long.byte 0x0 8.--11. 1. "POLYG_EXT,Polynomial Selection Extend" bitfld.long 0x0 5. "SWAP_BYTEWISE,Swap CRC_INP byte-wise" "0: Do not swap,1: Perform byte-wise swap on CRC_INP input data.." newline bitfld.long 0x0 4. "SWAP_BITWISE,Swap CRC_INP bit-wise" "0: Do not swap,1: Perform bit-wise swap on CRC_INP input data.." bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8-H2F AUTOSAR polynomial" newline bitfld.long 0x0 1. "SWAP,Swap selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." bitfld.long 0x0 0. "INV,Inversion selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP2,Input Register" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT2,Current Status Register" hexmask.long 0x8 0.--31. 1. "CSTAT,CRC signature status" rgroup.long 0x1C++0x3 line.long 0x0 "OUTP2,Output Register" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" group.long 0x20++0xB line.long 0x0 "CFG3,Configuration Register" hexmask.long.byte 0x0 8.--11. 1. "POLYG_EXT,Polynomial Selection Extend" bitfld.long 0x0 5. "SWAP_BYTEWISE,Swap CRC_INP byte-wise" "0: Do not swap,1: Perform byte-wise swap on CRC_INP input data.." newline bitfld.long 0x0 4. "SWAP_BITWISE,Swap CRC_INP bit-wise" "0: Do not swap,1: Perform bit-wise swap on CRC_INP input data.." bitfld.long 0x0 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8-H2F AUTOSAR polynomial" newline bitfld.long 0x0 1. "SWAP,Swap selection" "0: No swap selection applied on the CRC_OUTP content,1: Swap selection (MSB to LSB LSB to MSB) applied.." bitfld.long 0x0 0. "INV,Inversion selection" "0: No inversion selection applied on the CRC_OUTP..,1: Inversion selection (bit x bit) applied on the.." line.long 0x4 "INP3,Input Register" hexmask.long 0x4 0.--31. 1. "INP,Input data for the CRC computation" line.long 0x8 "CSTAT3,Current Status Register" hexmask.long 0x8 0.--31. 1. "CSTAT,CRC signature status" rgroup.long 0x2C++0x3 line.long 0x0 "OUTP3,Output Register" hexmask.long 0x0 0.--31. 1. "OUTP,Final CRC signature" tree.end tree "CSR (Coherent Subsystem)" base ad:0x504FF000 group.long 0x40++0x3 line.long 0x0 "CSADSE0,Coherent Subsystem ACE DVM Snoop Enable" bitfld.long 0x0 1. "DVMSNPEN1,ACE DVM Snoop Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "DVMSNPEN0,ACE DVM Snoop Enable n" "0: Disable,1: Enable" rgroup.long 0x50++0x3 line.long 0x0 "CSADSA,Coherent Subsystem ACE DVM Snoop Activity" bitfld.long 0x0 1. "DVMSNPACTV1,ACE DVM Snoop Active" "0,1" bitfld.long 0x0 0. "DVMSNPACTV0,ACE DVM Snoop Active" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CSCEIS0,Coherent Subsystem Correctable Error Interrupt Status" bitfld.long 0x0 1. "ERRINTVLD1,Error Interrupt Valid" "0,1" bitfld.long 0x0 0. "ERRINTVLD0,Error Interrupt Valid" "0,1" rgroup.long 0x10C++0x7 line.long 0x0 "CSCEIS3,Coherent Subsystem Correctable Error Interrupt Status" bitfld.long 0x0 1. "ERRINTVLD1,Error Interrupt Valid" "0,1" bitfld.long 0x0 0. "ERRINTVLD0,Error Interrupt Valid" "0,1" line.long 0x4 "CSCEIS4,Coherent Subsystem Correctable Error Interrupt Status" bitfld.long 0x4 0. "ERRINTVLD0,Error Interrupt Valid" "0,1" rgroup.long 0x118++0x3 line.long 0x0 "CSCEIS6,Coherent Subsystem Correctable Error Interrupt Status" bitfld.long 0x0 0. "ERRINTVLD0,Error Interrupt Valid" "0,1" rgroup.long 0x140++0x3 line.long 0x0 "CSUEIS0,Coherent Subsystem Uncorrectable Error Interrupt Status" bitfld.long 0x0 1. "ERRINTVLD1,Error Interrupt Valid" "0,1" bitfld.long 0x0 0. "ERRINTVLD0,Error Interrupt Valid" "0,1" rgroup.long 0x14C++0x7 line.long 0x0 "CSUEIS3,Coherent Subsystem Uncorrectable Error Interrupt Status" bitfld.long 0x0 1. "ERRINTVLD1,Error Interrupt Valid" "0,1" bitfld.long 0x0 0. "ERRINTVLD0,Error Interrupt Valid" "0,1" line.long 0x4 "CSUEIS4,Coherent Subsystem Uncorrectable Error Interrupt Status" bitfld.long 0x4 0. "ERRINTVLD0,Error Interrupt Valid" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "CSUEIS6,Coherent Subsystem Uncorrectable Error Interrupt Status" bitfld.long 0x0 0. "ERRINTVLD0,Error Interrupt Valid" "0,1" rgroup.long 0xF00++0x7F line.long 0x0 "CSSFIDR0,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x0 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x0 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x0 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x4 "CSSFIDR1,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x4 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x4 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x4 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x8 "CSSFIDR2,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x8 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x8 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x8 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0xC "CSSFIDR3,Coherent Subsystem Snoop Filter Identification" bitfld.long 0xC 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0xC 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0xC 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x10 "CSSFIDR4,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x10 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x10 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x10 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x14 "CSSFIDR5,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x14 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x14 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x14 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x18 "CSSFIDR6,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x18 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x18 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x18 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x1C "CSSFIDR7,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x1C 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x1C 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x1C 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x20 "CSSFIDR8,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x20 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x20 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x20 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x24 "CSSFIDR9,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x24 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x24 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x24 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x28 "CSSFIDR10,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x28 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x28 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x28 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x2C "CSSFIDR11,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x2C 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x2C 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x2C 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x30 "CSSFIDR12,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x30 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x30 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x30 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x34 "CSSFIDR13,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x34 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x34 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x34 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x38 "CSSFIDR14,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x38 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x38 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x38 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x3C "CSSFIDR15,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x3C 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x3C 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x3C 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x40 "CSSFIDR16,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x40 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x40 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x40 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x44 "CSSFIDR17,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x44 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x44 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x44 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x48 "CSSFIDR18,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x48 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x48 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x48 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x4C "CSSFIDR19,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x4C 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x4C 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x4C 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x50 "CSSFIDR20,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x50 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x50 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x50 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x54 "CSSFIDR21,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x54 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x54 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x54 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x58 "CSSFIDR22,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x58 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x58 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x58 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x5C "CSSFIDR23,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x5C 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x5C 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x5C 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x60 "CSSFIDR24,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x60 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x60 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x60 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x64 "CSSFIDR25,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x64 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x64 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x64 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x68 "CSSFIDR26,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x68 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x68 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x68 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x6C "CSSFIDR27,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x6C 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x6C 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x6C 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x70 "CSSFIDR28,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x70 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x70 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x70 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x74 "CSSFIDR29,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x74 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x74 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x74 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x78 "CSSFIDR30,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x78 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x78 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x78 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" line.long 0x7C "CSSFIDR31,Coherent Subsystem Snoop Filter Identification" bitfld.long 0x7C 26.--28. "TYPE,Snoop Filter Type" "0: Unimplemented filter,1: Null filter,2: Tag filter - presence vector,3: Tag filter - owner-sharer vector,?,?,?,?" hexmask.long.byte 0x7C 20.--25. 1. "NUMWAYS,Number of Snoop Filter Ways" hexmask.long.tbyte 0x7C 0.--19. 1. "NUMSETS,Number of Snoop Filter Sets" rgroup.long 0xFF8++0x7 line.long 0x0 "CSUID,Coherent Subsystem Unit Identification" hexmask.long.byte 0x0 24.--29. 1. "NUMCMIUS,Number of CMIUs" hexmask.long.byte 0x0 16.--21. 1. "NUMDIRUS,Number of DIRUs" hexmask.long.byte 0x0 8.--13. 1. "NUMNCBUS,Number of NCBUs" hexmask.long.byte 0x0 0.--6. 1. "NUMCAIUS,Number of CAIUs" line.long 0x4 "CSID,Coherent Subsystem Identification" hexmask.long.byte 0x4 18.--22. 1. "NUMSFS,Number of Snoop Filters (-1)" bitfld.long 0x4 8.--10. "DIRCLOFFSET,Directory Cache Line Offset (-5)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "RELVER,Release Version" tree.end tree "CTU (Cross-Triggering Unit)" base ad:0x401FC000 group.long 0x0++0x3 line.long 0x0 "TGSISR,Trigger Generator Subunit Input Selection Register" bitfld.long 0x0 31. "I15_FE,Input 15 Falling Edge Enable." "0: Disabled,1: Enabled" bitfld.long 0x0 30. "I15_RE,Input 15 Rising Edge Enable." "0: Disabled,1: Enabled" bitfld.long 0x0 13. "I6_FE,Input 6 Falling Edge Enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "I6_RE,Input 6 Rising Edge Enable." "0: Disabled,1: Enabled" bitfld.long 0x0 11. "I5_FE,Input 5 Falling Edge Enable." "0: Disabled,1: Enabled" bitfld.long 0x0 10. "I5_RE,Input 5 Rising Edge Enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "I4_FE,Input 4 Falling Edge Enable." "0: Disabled,1: Enabled" bitfld.long 0x0 8. "I4_RE,Input 4 Rising Edge Enable." "0: Disabled,1: Enabled" bitfld.long 0x0 7. "I3_FE,Input 3 Falling Edge Enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "I3_RE,Input 3 Rising edge Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 5. "I2_FE,Input 2 Falling Edge Enable." "0: Disabled,1: Enabled" bitfld.long 0x0 4. "I2_RE,Input 2 Rising Edge Enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "I1_FE,Input 1 Falling Edge Enable." "0: Disabled,1: Enabled" bitfld.long 0x0 2. "I1_RE,Input 1 Rising edge Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 1. "I0_FE,Input 0 Falling Edge Enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "I0_RE,Input 0 Rising Edge Enable." "0: Disabled,1: Enabled" group.word 0x4++0x15 line.word 0x0 "TGSCR,Trigger Generator Subunit Control Register" bitfld.word 0x0 8. "ET_TM,Enable Toggle Mode for external Trigger." "0: Pulse mode,1: Toggle mode" bitfld.word 0x0 6.--7. "PRES,Prescaler selection bits for TGS and SU. This prescaler is used by the TGS counter." "0: Value is 1,1: Value is 2,2: Value is 3,3: Value is 4" hexmask.word.byte 0x0 1.--5. 1. "MRS_SM,MRS Selection in Sequential Mode-5 bits to select one of the 2 x 16inputs shown in the Trigger generator subunit input selection (TGSISR) register" newline bitfld.word 0x0 0. "TGS_M,Trigger Generator Subunit Mode" "0: Triggered Mode,1: Sequential Mode" line.word 0x2 "T0CR,Trigger Compare Register" hexmask.word 0x2 0.--15. 1. "TCRV,Trigger Compare Register Value" line.word 0x4 "T1CR,Trigger Compare Register" hexmask.word 0x4 0.--15. 1. "TCRV,Trigger Compare Register Value" line.word 0x6 "T2CR,Trigger Compare Register" hexmask.word 0x6 0.--15. 1. "TCRV,Trigger Compare Register Value" line.word 0x8 "T3CR,Trigger Compare Register" hexmask.word 0x8 0.--15. 1. "TCRV,Trigger Compare Register Value" line.word 0xA "T4CR,Trigger Compare Register" hexmask.word 0xA 0.--15. 1. "TCRV,Trigger Compare Register Value" line.word 0xC "T5CR,Trigger Compare Register" hexmask.word 0xC 0.--15. 1. "TCRV,Trigger Compare Register Value" line.word 0xE "T6CR,Trigger Compare Register" hexmask.word 0xE 0.--15. 1. "TCRV,Trigger Compare Register Value" line.word 0x10 "T7CR,Trigger Compare Register" hexmask.word 0x10 0.--15. 1. "TCRV,Trigger Compare Register Value" line.word 0x12 "TGSCCR,TGS Counter Compare Register" hexmask.word 0x12 0.--15. 1. "TGSCCV,TGS Counter Compare Value" line.word 0x14 "TGSCRR,TGS Counter Reload Register" hexmask.word 0x14 0.--15. 1. "TGSCRV,TGSCRV" group.long 0x1C++0xF line.long 0x0 "CLCR1,Commands List Control Register 1" hexmask.long.byte 0x0 24.--28. 1. "T3_INDEX,Trigger 3 Commands List 1st command address" hexmask.long.byte 0x0 16.--20. 1. "T2_INDEX,Trigger 2 Commands List 1st command address" hexmask.long.byte 0x0 8.--12. 1. "T1_INDEX,Trigger 1 Commands List 1st command address" newline hexmask.long.byte 0x0 0.--4. 1. "T0_INDEX,Trigger 0 Commands List 1st command address" line.long 0x4 "CLCR2,Commands List Control Register 2" hexmask.long.byte 0x4 24.--28. 1. "T7_INDEX,T7_INDEX" hexmask.long.byte 0x4 16.--20. 1. "T6_INDEX,Trigger 6 Commands List 1st command address" hexmask.long.byte 0x4 8.--12. 1. "T5_INDEX,Trigger 5 Commands List 1st command address" newline hexmask.long.byte 0x4 0.--4. 1. "T4_INDEX,Trigger 4 Commands List 1st command address" line.long 0x8 "THCR1,Trigger Handler Control Register 1" bitfld.long 0x8 30. "T3_E,Trigger 3 Enable." "0: Disabled,1: Enabled" bitfld.long 0x8 24. "T3_ADCE,Trigger 3 ADC command output Enable." "0: Disabled,1: Enabled" bitfld.long 0x8 22. "T2_E,Trigger 2 Enable." "0: Disabled,1: Enabled" newline bitfld.long 0x8 16. "T2_ADCE,Trigger 2 ADC command output Enable." "0: Disabled,1: Enabled" bitfld.long 0x8 14. "T1_E,Trigger 1 Enable." "0: Disabled,1: Enabled" bitfld.long 0x8 8. "T1_ADCE,Trigger 1 ADC command output Enable." "0: Disabled,1: Enabled" newline bitfld.long 0x8 6. "T0_E,Trigger 0 Enable." "0: Disabled,1: Enabled" bitfld.long 0x8 0. "T0_ADCE,Trigger 0 ADC command output Enable." "0: Disabled,1: Enabled" line.long 0xC "THCR2,Trigger Handler Control Register 2" bitfld.long 0xC 30. "T7_E,Trigger 7 Enable." "0: Disabled,1: Enabled" bitfld.long 0xC 24. "T7_ADCE,Trigger 7 ADC command output Enable." "0: Disabled,1: Enabled" bitfld.long 0xC 22. "T6_E,Trigger 6 Enable." "0: Disabled,1: Enabled" newline bitfld.long 0xC 16. "T6_ADCE,Trigger 6 ADC command output Enable." "0: Disabled,1: Enabled" bitfld.long 0xC 14. "T5_E,Trigger 5 Enable." "0: Disabled,1: Enabled" bitfld.long 0xC 8. "T5_ADCE,Trigger 5 ADC command output Enable." "0: Disabled,1: Enabled" newline bitfld.long 0xC 6. "T4_E,Trigger 4 Enable." "0: Disabled,1: Enabled" bitfld.long 0xC 0. "T4_ADCE,Trigger 4 ADC command output Enable." "0: Disabled,1: Enabled" group.word 0x2C++0x1 line.word 0x0 "CLR_A_1,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x0 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x0 0.--3. 1. "CH,ADC Port channel number." group.word 0x2C++0x3 line.word 0x0 "CLR_B_1,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_2,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x2E++0x3 line.word 0x0 "CLR_B_2,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_3,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x30++0x3 line.word 0x0 "CLR_B_3,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_4,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x32++0x3 line.word 0x0 "CLR_B_4,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_5,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x34++0x3 line.word 0x0 "CLR_B_5,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_6,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x36++0x3 line.word 0x0 "CLR_B_6,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_7,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x38++0x3 line.word 0x0 "CLR_B_7,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_8,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x3A++0x3 line.word 0x0 "CLR_B_8,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_9,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x3C++0x3 line.word 0x0 "CLR_B_9,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_10,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x3E++0x3 line.word 0x0 "CLR_B_10,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_11,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x40++0x3 line.word 0x0 "CLR_B_11,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_12,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x42++0x3 line.word 0x0 "CLR_B_12,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_13,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x44++0x3 line.word 0x0 "CLR_B_13,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_14,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x46++0x3 line.word 0x0 "CLR_B_14,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_15,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x48++0x3 line.word 0x0 "CLR_B_15,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_16,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x4A++0x3 line.word 0x0 "CLR_B_16,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_17,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x4C++0x3 line.word 0x0 "CLR_B_17,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_18,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x4E++0x3 line.word 0x0 "CLR_B_18,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_19,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x50++0x3 line.word 0x0 "CLR_B_19,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_20,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x52++0x3 line.word 0x0 "CLR_B_20,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_21,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x54++0x3 line.word 0x0 "CLR_B_21,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_22,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x56++0x3 line.word 0x0 "CLR_B_22,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_23,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x58++0x3 line.word 0x0 "CLR_B_23,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" line.word 0x2 "CLR_A_24,Commands List Register A for ADC single-conversion mode commands" bitfld.word 0x2 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x2 14. "LC,Last Command bit" "0: Not last,1: Last" bitfld.word 0x2 13. "CMS,Conversion Mode Selection. Must be 0 in this register format." "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x2 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" bitfld.word 0x2 5. "SU,ADC Port A / Port B selection." "0: ADC Port A selected,1: ADC Port B selected" hexmask.word.byte 0x2 0.--3. 1. "CH,ADC Port channel number." group.word 0x5A++0x1 line.word 0x0 "CLR_B_24,Command List Register B for ADC dual-conversion mode commands" bitfld.word 0x0 15. "CIR,Command execution Interrupt Request enable bit." "0: Disabled,1: Enabled" bitfld.word 0x0 14. "LC,Last Command Bit" "0: Not last,1: Last" bitfld.word 0x0 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode" newline bitfld.word 0x0 10.--12. "FIFO,FIFO used for ADC Port A / Port B." "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?,?,?,?" hexmask.word.byte 0x0 5.--8. 1. "CH_B,ADC Port B Channel Number" hexmask.word.byte 0x0 0.--3. 1. "CH_A,ADC Port A Channel Number" group.word 0x6C++0x1 line.word 0x0 "FDCR,FIFO DMA Control Register" bitfld.word 0x0 3. "DE3,FIFO 3 DMA enable." "0: Disabled,1: Enabled" bitfld.word 0x0 2. "DE2,FIFO 2 DMA enable." "0: Disabled,1: Enabled" bitfld.word 0x0 1. "DE1,FIFO 1 DMA enable." "0: Disabled,1: Enabled" newline bitfld.word 0x0 0. "DE0,FIFO 0 DMA enable." "0: Disabled,1: Enabled" group.long 0x70++0x7 line.long 0x0 "FCR,FIFO Control Register" bitfld.long 0x0 15. "OR_EN3,FIFO 3 Overrun interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 14. "OF_EN3,FIFO 3 threshold Overflow interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 13. "EMPTY_EN3,FIFO 3 Empty interrupt enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "FULL_EN3,FIFO 3 Full interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 11. "OR_EN2,FIFO 2 Overrun interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 10. "OF_EN2,FIFO 2 threshold Overflow interrupt enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "EMPTY_EN2,FIFO 2 Empty interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 8. "FULL_EN2,FIFO 2 Full interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 7. "OR_EN1,FIFO 1 Overrun interrupt enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "OF_EN1,FIFO 1 threshold Overflow interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 5. "EMPTY_EN1,FIFO 1 Empty interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 4. "FULL_EN1,FIFO 1 Full interrupt enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "OR_EN0,FIFO 0 Overrun interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 2. "OF_EN0,FIFO 0 threshold Overflow interrupt enable." "0: Disabled,1: Enabled" bitfld.long 0x0 1. "EMPTY_EN0,FIFO 0 Empty interrupt enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "FULL_EN0,FIFO 0 Full interrupt enable." "0: Disabled,1: Enabled" line.long 0x4 "FTH,FIFO Threshold Register" hexmask.long.byte 0x4 24.--31. 1. "TH3,FIFO 3 Threshold." hexmask.long.byte 0x4 16.--23. 1. "TH2,FIFO 2 Threshold." hexmask.long.byte 0x4 8.--15. 1. "TH1,FIFO 1 Threshold." newline hexmask.long.byte 0x4 0.--7. 1. "TH0,FIFO 0 Threshold." group.long 0x7C++0x3 line.long 0x0 "FST,FIFO Status Register" eventfld.long 0x0 15. "OR3,FIFO 3 Overrun interrupt flag. It is cleared if 1 is written to this bit location." "0: Interrupt has not occurred,1: Interrupt has occurred" rbitfld.long 0x0 14. "OF3,FIFO 3 threshold Overflow interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" rbitfld.long 0x0 13. "EMP3,FIFO 3 Empty interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" newline rbitfld.long 0x0 12. "FULL3,FIFO 3 Full interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" eventfld.long 0x0 11. "OR2,FIFO 2 Overrun interrupt flag. It is cleared if 1 is written to this bit location." "0: Interrupt has not occurred,1: Interrupt has occurred" rbitfld.long 0x0 10. "OF2,FIFO 2 threshold Overflow interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" newline rbitfld.long 0x0 9. "EMP2,FIFO 2 Empty interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" rbitfld.long 0x0 8. "FULL2,FIFO 2 Full interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" eventfld.long 0x0 7. "OR1,FIFO 1 Overrun interrupt flag. It is cleared if 1 is written to this bit location." "0: Interrupt has not occurred,1: Interrupt has occurred" newline rbitfld.long 0x0 6. "OF1,FIFO 1 threshold Overflow interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" rbitfld.long 0x0 5. "EMP1,FIFO 1 Empty interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" rbitfld.long 0x0 4. "FULL1,FULL1" "0: Interrupt has not occurred,1: Interrupt has occurred" newline eventfld.long 0x0 3. "OR0,FIFO 0 Overrun interrupt flag. It is cleared if 1 is written to this bit location." "0: Interrupt has not occurred,1: Interrupt has occurred" rbitfld.long 0x0 2. "OF0,FIFO 0 threshold Overflow interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" rbitfld.long 0x0 1. "EMP0,FIFO 0 Empty interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" newline rbitfld.long 0x0 0. "FULL0,FIFO 0 Full interrupt flag." "0: Interrupt has not occurred,1: Interrupt has occurred" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x80)++0x3 line.long 0x0 "FR[$1],FIFO Right Aligned Data Register" bitfld.long 0x0 19. "ADC,This bit indicates from which ADC Port the value in the DATA field corresponds to." "0: Data coming from ADC Port B,1: Data coming from ADC Port A" bitfld.long 0x0 16.--18. "N_CH,Number of the channel that DATA field corresponds to." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 0.--11. 1. "DATA,Data of stored channel." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0xA0)++0x3 line.long 0x0 "FL[$1],FIFO Signed Left Aligned Data Register" bitfld.long 0x0 19. "ADC,This bit indicates from which ADC Port the value in the DATA field corresponds to." "0: Data coming from ADC Port B,1: Data coming from ADC Port A" bitfld.long 0x0 16.--18. "N_CH,Number of the channel that DATA field corresponds to." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 3.--14. 1. "LA_DATA,LA_DATA" repeat.end group.word 0xC0++0x11 line.word 0x0 "EFR,Error Flag Register" eventfld.word 0x0 13. "LIST_BE,List Busy Error" "0: No error,1: Error" eventfld.word 0x0 10. "ERRCMP,Error Compare" "0: No match,1: Match" eventfld.word 0x0 5. "ADC_OE,ADC command generation Overrun Error" "0: No Error,1: Error" newline eventfld.word 0x0 4. "TGS_OSM,The TGS Overrun in Sequential Mode" "0: No overrun,1: Overrun" eventfld.word 0x0 3. "MRS_O,Master Reload Signal Overrun" "0: No overrun,1: Overrun" eventfld.word 0x0 2. "ICE,Invalid Command Error" "0: No error,1: Error" newline eventfld.word 0x0 1. "SM_TO,Trigger Overrun (more than 8 ES) in TGS Sequential Mode" "0: No overrun,1: Overrun" eventfld.word 0x0 0. "MRS_RE,Master Reload Signal Reload Error" "0: No error,1: Error" line.word 0x2 "IFR,Interrupt Flag Register" eventfld.word 0x2 11. "SERR_B,If this bit is set it means that the time between the start of a conversion and the end of that conversion is out of the expected range which is defined by the EXPBR and CNTRNGR registers" "0,1" eventfld.word 0x2 10. "SERR_A,If this bit is set it means that the time between the start of a conversion and the end of that conversion is out of the expected range defined by the EXPAR and CNTRNGR registers" "0,1" eventfld.word 0x2 9. "ADC_I,ADC command interrupt flag is set when a new command is issued" "0,1" newline eventfld.word 0x2 8. "T7_I,Trigger 7 interrupt flag is set when the corresponding trigger is issued" "0,1" eventfld.word 0x2 7. "T6_I,Trigger 6 interrupt flag is set when the corresponding trigger is issued" "0,1" eventfld.word 0x2 6. "T5_I,Trigger 5 interrupt flag is set when the corresponding trigger is issued" "0,1" newline eventfld.word 0x2 5. "T4_I,Trigger 4 interrupt flag is set when the corresponding trigger is issued" "0,1" eventfld.word 0x2 4. "T3_I,Trigger 3 interrupt flag is set when the corresponding trigger is issued" "0,1" eventfld.word 0x2 3. "T2_I,Trigger 2 interrupt flag is set when the corresponding trigger is issued" "0,1" newline eventfld.word 0x2 2. "T1_I,Trigger 1 interrupt flag is set when the corresponding trigger is issued" "0,1" eventfld.word 0x2 1. "T0_I,Trigger 0 interrupt flag is set when the corresponding trigger is issued" "0,1" eventfld.word 0x2 0. "MRS_I,MRS Interrupt flag is set when the Master Reload Signal occurs" "0,1" line.word 0x4 "IR,Interrupt/DMA Register" bitfld.word 0x4 15. "T7_IE,Trigger 7 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x4 14. "T6_IE,Trigger 6 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x4 13. "T5_IE,Trigger 5 Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x4 12. "T4_IE,Trigger 4 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x4 11. "T3_IE,Trigger 3 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x4 10. "T2_IE,Trigger 2 Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x4 9. "T1_IE,Trigger 1 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x4 8. "T0_IE,Trigger 0 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x4 5. "SAF_CNT_B_EN,Enable the ADC Port B counter to check the conversion time." "0: Disabled,1: Enabled" newline bitfld.word 0x4 4. "SAF_CNT_A_EN,Enable the ADC Port A counter to check the conversion time." "0: Disabled,1: Enabled" bitfld.word 0x4 3. "DMA_DE,If this bit is set a dma done acts as a write '1' in the GRE bit." "0,1" bitfld.word 0x4 2. "MRS_DMAE,If GRE bit is set DMA request is issued on MRS occurrence." "0,1" newline bitfld.word 0x4 1. "MRS_IE,MRS Interrupt Enable." "0: Disabled,1: Enabled" bitfld.word 0x4 0. "IEE,Interrupt Error Enable." "0: Disabled,1: Enabled" line.word 0x6 "COTR,Control ON Time Register" hexmask.word.byte 0x6 0.--7. 1. "COTGT,COTGT" line.word 0x8 "CR,Control Register" bitfld.word 0x8 15. "T7_SG,Trigger 7 Software Generated." "0: S/W not generated,1: S/W generated" bitfld.word 0x8 14. "T6_SG,Trigger 6 Software Generated." "0: S/W not generated,1: S/W generated" bitfld.word 0x8 13. "T5_SG,Trigger 5 Software Generated." "0: S/W not generated,1: S/W generated" newline bitfld.word 0x8 12. "T4_SG,Trigger 4 Software Generated." "0: S/W not generated,1: S/W generated" bitfld.word 0x8 11. "T3_SG,Trigger 3 Software Generated." "0: S/W not generated,1: S/W generated" bitfld.word 0x8 10. "T2_SG,Trigger 2 Software Generated." "0: S/W not generated,1: S/W generated" newline bitfld.word 0x8 9. "T1_SG,Trigger 1 Software Generated." "0: S/W not generated,1: S/W generated" bitfld.word 0x8 8. "T0_SG,Trigger 0 Software Generated." "0: S/W not generated,1: S/W generated" bitfld.word 0x8 7. "CTU_ADC_R,CTU command list control state machine Reset" "0,1" newline bitfld.word 0x8 6. "CTU_ODIS,CTU Output Disable." "0: Enabled,1: Disabled" bitfld.word 0x8 5. "DFE,Writing a 1b to this bit creates a trigger in CTU timer clock domain which is used to register the value of Digital Filter in the register CTU_DFR into CTU timer clock domain" "0: Disabled,1: Enabled" bitfld.word 0x8 4. "CGRE,Clear GRE to 0." "0,1" newline rbitfld.word 0x8 3. "FGRE,Flag GRE. See for more details." "0,1" bitfld.word 0x8 2. "MRS_SG,MRS Software Generated." "0: S/W not generated,1: S/W generated" bitfld.word 0x8 1. "GRE,General Reload Enable. See for more details." "0: Disabled,1: Enabled" newline bitfld.word 0x8 0. "TGSISR_RE,TGS Input Selection Register Reload Enable" "0,1" line.word 0xA "DFR,Digital Filter Register" hexmask.word.byte 0xA 0.--7. 1. "FILTER_N,Digital Filter value" line.word 0xC "EXPAR,Expected Value A Register" hexmask.word 0xC 0.--15. 1. "EXPA,This value is the expected number of system clock cycles needed by ADC Port A to complete a conversion." line.word 0xE "EXPBR,Expected Value B Register" hexmask.word 0xE 0.--15. 1. "EXPB,This value is the expected number of system clock cycles needed by ADC Port B to complete a conversion." line.word 0x10 "CNTRNGR,Counter Range Register" hexmask.word.byte 0x10 0.--7. 1. "CNTRNG,CNTRNG" group.long 0xD4++0x3 line.long 0x0 "LISTCSR,List Control/Status Register" rbitfld.long 0x0 31. "LIST1_BLK,List 1 Blocked flag" "0,1" hexmask.long.byte 0x0 24.--28. 1. "LIST1_ADDR,List Address 1" rbitfld.long 0x0 23. "LIST0_BLK,List 0 Blocked flag" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "LIST0_ADDR,List Address 0. Indicates the command address being executed when LIST_BE flag in EFR register was set." bitfld.long 0x0 0. "PAR_LIST,Parallel mode List. This bit selects the parallel mode for the list execution." "0: List is executed in streaming mode,1: List is executed in parallel mode" tree.end tree "DDR" base ad:0x0 tree "DDR_GPR" base ad:0x4007C600 group.long 0x0++0xB line.long 0x0 "DDR_Config_0,Configuration 0" bitfld.long 0x0 31. "PERF_CNT_FULL_MASK,Monitor Counter Full Interrupt" "0: Disable,1: Enable" hexmask.long.byte 0x0 27.--30. 1. "sbrAddressRangeMask_35_32,Scrubber Address Range Mask Bits 35:32" hexmask.long.byte 0x0 23.--26. 1. "sbrAddressStartMask_35_32,Scrubber Address Start Mask Bits 35:32" newline hexmask.long.byte 0x0 16.--22. 1. "WRECC_CREDIR_CNT,WRECC Credit" bitfld.long 0x0 14. "memory_ret,Memory Data Retention" "0: Do not retain,1: Retain" line.long 0x4 "DDR_Config_1,Configuration 1" hexmask.long 0x4 0.--31. 1. "sbrAddressStartMask,Scrubber Address Start Mask Bits 31:0" line.long 0x8 "DDR_Config_2,Configuration 2" hexmask.long 0x8 0.--31. 1. "sbrAddressRangeMask,Scrubber Address Range Mask Bits 31:0" rgroup.long 0xC++0x7 line.long 0x0 "DDR_Config_3,Configuration 3" bitfld.long 0x0 21.--22. "stat_ddrc_reg_selfref_type,DDR Controller 0 Self Refresh Status And Type" "0,1,2,3" hexmask.long.byte 0x0 17.--20. 1. "raqb_wcount_2,Port 2 Read Address Channel" hexmask.long.byte 0x0 13.--16. 1. "raqb_wcount_1,AXI Port 1 Read Address Channel" newline hexmask.long.byte 0x0 9.--12. 1. "raqb_wcount_0,AXI Port 0 Read Address Channel" hexmask.long.byte 0x0 3.--8. 1. "hif_refresh_req_bank,Refresh Bank" bitfld.long 0x0 0.--2. "dbg_dfi_ie_cmd_type,Debug DFI Command Type" "0,1,2,3,4,5,6,7" line.long 0x4 "DDR_Config_4,Configuration 4" hexmask.long.byte 0x4 20.--23. 1. "waq_wcount_2,AXI Port 2 Write Address Channel" hexmask.long.byte 0x4 16.--19. 1. "waq_wcount_1,AXI Port 1 Write Address Channel" hexmask.long.byte 0x4 12.--15. 1. "waq_wcount_0,AXI Port 0 Write Address Channel" newline hexmask.long.byte 0x4 8.--11. 1. "raqr_wcount_2,AXI Port 2 Read Address Channel" hexmask.long.byte 0x4 4.--7. 1. "raqr_wcount_1,AXI Port 1 Read Address Channel" hexmask.long.byte 0x4 0.--3. 1. "raqr_wcount_0,AXI Port 0 Read Address Channel" group.long 0x14++0x3 line.long 0x0 "DDR_Config_5,Configuration 5" bitfld.long 0x0 20. "main_rccu_clr_axi2,Main RCCU Clear Alarm For AXI 2" "0: Do not clear,1: Clear" bitfld.long 0x0 19. "dummy_rccu_clr_axi2,Dummy RCCU Clear Alarm For AXI 2" "0: Do not clear,1: Clear" bitfld.long 0x0 18. "main_rccu_set_axi2,Main RCCU Set Alarm For AXI 2" "0: Do not set,1: Set" newline bitfld.long 0x0 17. "dummy_rccu_set_axi2,Dummy RCCU Set Alarm For AXI 2" "0: Do not set,1: Set" bitfld.long 0x0 16. "main_rccu_clr_axi1,Main RCCU Clear Alarm For AXI 1" "0: Do not clear,1: Clear" bitfld.long 0x0 15. "dummy_rccu_clr_axi1,Dummy RCCU Clear Alarm For AXI 1" "0: Do not clear,1: Clear" newline bitfld.long 0x0 14. "main_rccu_set_axi1,Main RCCU Set Alarm For AXI 1" "0: Do not set,1: Set" bitfld.long 0x0 13. "dummy_rccu_set_axi1,Dummy RCCU Set Alarm For AXI 1" "0: Do not set,1: Set" bitfld.long 0x0 12. "main_rccu_clr_axi0,Main RCCU Clear Alarm For AXI 0" "0: Do not clear,1: Clear" newline bitfld.long 0x0 11. "dummy_rccu_clr_axi0,Dummy RCCU Clear Alarm For AXI 0" "0: Do not clear,1: Clear" bitfld.long 0x0 10. "main_rccu_set_axi0,Main RCCU Set Alarm For AXI 0" "0: Do not set,1: Set" bitfld.long 0x0 9. "dummy_rccu_set_axi0,Dummy RCCU Set Alarm For AXI 0" "0: Do not set,1: Set" group.long 0x1C++0x3 line.long 0x0 "DDR_RET_CONTROL,LP3 IO Retention Control" bitfld.long 0x0 0. "DDR_RET_CONTROL,DDR LP3 IO Retention Control" "0: Enabled,1: Disabled" tree.end tree "DDR_SUBSYSTEM" base ad:0x403D0000 group.long 0x0++0x3 line.long 0x0 "reg_grp0,DDR SS Reg" bitfld.long 0x0 31. "ddr_ss_pub_reg_deco_int_en,Enables or disables the generated interrupt if the PUB register decoder detects a difference." "0: Disables,1: Enables" bitfld.long 0x0 30. "aclk_2_disable,Enables or disables the AXI port 2 clock." "0: Disables,1: Enables" bitfld.long 0x0 29. "aclk_1_disable,Enables or disables the AXI port 1 clock." "0: Disables,1: Enables" newline bitfld.long 0x0 28. "aclk_0_disable,Enables or disables the AXI port 0 clock." "0: Disables,1: Enables" bitfld.long 0x0 27. "core_clk_disable,Enables or disables the uMCTL2 main core clock." "0,1" hexmask.long.word 0x0 16.--24. 1. "axi_parity_type,Indicates the type of parity selection for the AXI port read address." newline hexmask.long.word 0x0 4.--12. 1. "axi_parity_en,Enables parity for the AXI port write address." bitfld.long 0x0 0. "dfi1_enabled,Enables or disables DFI interface 1 on PHY." "0: Disables,1: Enables" tree.end tree.end tree "DFS (Digital Frequency Synthesizer)" base ad:0x0 tree "CORE_DFS" base ad:0x40054000 rgroup.long 0xC++0x3 line.long 0x0 "PORTSR,Port Status Register" hexmask.long.byte 0x0 0.--5. 1. "PORTSTAT,Port status" group.long 0x10++0xB line.long 0x0 "PORTLOLSR,Port Loss of Lock Status" eventfld.long 0x0 5. "LOLF5,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." eventfld.long 0x0 4. "LOLF4,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." newline eventfld.long 0x0 3. "LOLF3,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." eventfld.long 0x0 2. "LOLF2,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." newline eventfld.long 0x0 1. "LOLF1,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." eventfld.long 0x0 0. "LOLF0,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." line.long 0x4 "PORTRESET,Port Reset" bitfld.long 0x4 5. "RESET5,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." bitfld.long 0x4 4. "RESET4,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." newline bitfld.long 0x4 3. "RESET3,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." bitfld.long 0x4 2. "RESET2,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." newline bitfld.long 0x4 1. "RESET1,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." bitfld.long 0x4 0. "RESET0,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." line.long 0x8 "CTL,Control" bitfld.long 0x8 1. "DFS_RESET,This field controls the master reset of the DFS. For sequencing with PORTRESET[RESET] bits." "0: The DFS phase generator is out of reset. You can..,1: The DFS phase generator is in reset. You cannot.." repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C)++0x3 line.long 0x0 "DVPORT[$1],Divider for Port n" hexmask.long.byte 0x0 8.--15. 1. "MFI,This field provides the integer part of division factor for port n." hexmask.long.byte 0x0 0.--5. 1. "MFN,This field provides the numerator of fractional part of division factor for port n." repeat.end tree.end tree "PERIPH_DFS" base ad:0x40058000 rgroup.long 0xC++0x3 line.long 0x0 "PORTSR,Port Status Register" hexmask.long.byte 0x0 0.--5. 1. "PORTSTAT,Port status" group.long 0x10++0xB line.long 0x0 "PORTLOLSR,Port Loss of Lock Status" eventfld.long 0x0 5. "LOLF5,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." eventfld.long 0x0 4. "LOLF4,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." newline eventfld.long 0x0 3. "LOLF3,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." eventfld.long 0x0 2. "LOLF2,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." newline eventfld.long 0x0 1. "LOLF1,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." eventfld.long 0x0 0. "LOLF0,Loss of lock flag" "0: The DFS detects no loss of lock for channel port..,1: The DFS detected a loss of lock for channel port.." line.long 0x4 "PORTRESET,Port Reset" bitfld.long 0x4 5. "RESET5,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." bitfld.long 0x4 4. "RESET4,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." newline bitfld.long 0x4 3. "RESET3,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." bitfld.long 0x4 2. "RESET2,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." newline bitfld.long 0x4 1. "RESET1,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." bitfld.long 0x4 0. "RESET0,Enable control for port n" "0: Port n is enabled.,1: Port n is disabled." line.long 0x8 "CTL,Control" bitfld.long 0x8 1. "DFS_RESET,This field controls the master reset of the DFS. For sequencing with PORTRESET[RESET] bits." "0: The DFS phase generator is out of reset. You can..,1: The DFS phase generator is in reset. You cannot.." repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C)++0x3 line.long 0x0 "DVPORT[$1],Divider for Port n" hexmask.long.byte 0x0 8.--15. 1. "MFI,This field provides the integer part of division factor for port n." hexmask.long.byte 0x0 0.--5. 1. "MFN,This field provides the numerator of fractional part of division factor for port n." repeat.end tree.end tree.end tree "DIRU (Directory Unit)" base ad:0x50480000 rgroup.long 0x4++0x3 line.long 0x0 "DIRUTA,DIRU Transaction Activity" bitfld.long 0x0 0. "TRANSACTV,Transaction Active" "0,1" group.long 0x10++0x3 line.long 0x0 "DIRUSFE,DIRU Snoop Filtering Enable" bitfld.long 0x0 0. "SFEN0,Snoop Filter Enable" "0,1" group.long 0x40++0x3 line.long 0x0 "DIRUCASE0,DIRU Caching Agent Snoop Enable" bitfld.long 0x0 1. "CASNPEN1,Caching Agent Snoop Enable" "0,1" bitfld.long 0x0 0. "CASNPEN0,Caching Agent Snoop Enable" "0,1" rgroup.long 0x50++0x3 line.long 0x0 "DIRUCASA0,DIRU Caching Agent Snoop Activity" bitfld.long 0x0 1. "CASNPACTV1,Caching Agent Snoop Activity" "0,1" bitfld.long 0x0 0. "CASNPACTV0,Caching Agent Snoop Activity" "0,1" group.long 0x80++0x3 line.long 0x0 "DIRUSFMC,DIRU Snoop Filter Maintenance Control" bitfld.long 0x0 21. "SFSECATTR,Snoop Filter Security Attribute" "0: System is not configured with security attribute.,1: System is configured with security attribute." hexmask.long.byte 0x0 16.--20. 1. "SFID,Snoop Filter Identifier" newline hexmask.long.byte 0x0 0.--3. 1. "SFMNTOP,Snoop Filter Maintenance Operation" rgroup.long 0x84++0x3 line.long 0x0 "DIRUSFMA,DIRU Snoop Filter Maintenance Activity" bitfld.long 0x0 0. "MNTOPACTV,Maintenance Operation Active" "0,1" group.long 0x88++0x7 line.long 0x0 "DIRUSFMLR0,DIRU Snoop Filter Maintenance Location Register 0" hexmask.long.byte 0x0 26.--31. 1. "MNTWORD,Maintenance Word" hexmask.long.byte 0x0 20.--25. 1. "MNTWAY,Maintenance Way" newline hexmask.long.tbyte 0x0 0.--19. 1. "MNTSET,Maintenance Set" line.long 0x4 "DIRUSFMLR1,DIRU Snoop Filter Maintenance Location Register 1" bitfld.long 0x4 0.--1. "MNTADDR,Maintenance Address" "0,1,2,3" group.long 0x100++0xF line.long 0x0 "DIRUCEC,DIRU Correctable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Correctable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Correctable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" newline bitfld.long 0x0 0. "ERRDETEN,Correctable Error Detection Enable" "0: Disable correctable error detection and logging..,1: Enable correctable error detection and logging.." line.long 0x4 "DIRUCES,DIRU Correctable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" newline hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "DIRUCELR0,DIRU Correctable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" newline hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry (or Set)" line.long 0xC "DIRUCELR1,DIRU Correctable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x124++0x3 line.long 0x0 "DIRUCESA,DIRU Correctable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" newline hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" group.long 0x140++0xF line.long 0x0 "DIRUUEC,DIRU Uncorrectable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Uncorrectable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Uncorrectable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" newline bitfld.long 0x0 0. "ERRDETEN,Uncorrectable Error Detection Enable" "0: Disable uncorrectable error detection and..,1: Enable uncorrectable error detection and logging.." line.long 0x4 "DIRUUES,DIRU Uncorrectable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" newline hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "DIRUUELR0,DIRU Uncorrectable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" newline hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry (or Set)" line.long 0xC "DIRUUELR1,DIRU Uncorrectable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x164++0x3 line.long 0x0 "DIRUUESA,DIRU Uncorrectable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" newline hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "DIRUID,DIRU Identification Register" hexmask.long.byte 0x0 0.--7. 1. "IMPLVER,Implementation Version" tree.end tree "DMA (Direct Memory Access)" base ad:0x0 tree "EDMA_0_MP" base ad:0x40144000 group.long 0x0++0x3 line.long 0x0 "CSR,Management Page Control" rbitfld.long 0x0 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel" hexmask.long.byte 0x0 24.--28. 1. "ACTIVE_ID,Active Channel ID" newline bitfld.long 0x0 9. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer" bitfld.long 0x0 8. "ECX,Cancel Transfer With Error" "0: Normal operation,1: Cancel the remaining data transfer" newline bitfld.long 0x0 7. "GMRC,Global Master ID Replication Control" "0: Master ID replication disabled for all channels,1: Master ID replication available and controlled.." bitfld.long 0x0 6. "GCLC,Global Channel Linking Control" "0: Channel linking disabled for all channels,1: Channel linking available and controlled by each.." newline bitfld.long 0x0 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels" bitfld.long 0x0 4. "HAE,Halt After Error" "0: Normal operation,1: Any error causes the HALT field to be set to 1" newline bitfld.long 0x0 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Round-robin channel arbitration disabled,1: Round-robin channel arbitration enabled" bitfld.long 0x0 1. "EDBG,Enable Debug" "0: Debug mode disabled,1: Debug mode is enabled." rgroup.long 0x4++0xB line.long 0x0 "ES,Management Page Error Status" bitfld.long 0x0 31. "VLD,Valid" "0: No CHn_ES[ERR] fields are set to 1,1: At least one CHn_ES[ERR] field is set to 1.." hexmask.long.byte 0x0 24.--28. 1. "ERRCHN,Error Channel Number or Canceled Channel Number" newline bitfld.long 0x0 9. "UCE,Uncorrectable TCD Error During Channel Execution" "0: No uncorrectable ECC error,1: Last recorded error was an uncorrectable TCD RAM.." bitfld.long 0x0 8. "ECX,Transfer Canceled" "0: No canceled transfers,1: Last recorded entry was a canceled transfer by.." newline bitfld.long 0x0 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was NBYTES equal to zero.." bitfld.long 0x0 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was a bus error on a source.." bitfld.long 0x0 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was a bus error on a.." line.long 0x4 "INT,Management Page Interrupt Request Status" hexmask.long 0x4 0.--31. 1. "INT,Interrupt Request Status" line.long 0x8 "HRS,Management Page Hardware Request Status" hexmask.long 0x8 0.--31. 1. "HRS,Hardware Request Status" repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CH_GRPRI[$1],Channel Arbitration Group" hexmask.long.byte 0x0 0.--4. 1. "GRPRI,Arbitration Group For Channel n" repeat.end tree.end tree "EDMA_1_MP" base ad:0x40244000 group.long 0x0++0x3 line.long 0x0 "CSR,Management Page Control" rbitfld.long 0x0 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel" hexmask.long.byte 0x0 24.--28. 1. "ACTIVE_ID,Active Channel ID" newline bitfld.long 0x0 9. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer" bitfld.long 0x0 8. "ECX,Cancel Transfer With Error" "0: Normal operation,1: Cancel the remaining data transfer" newline bitfld.long 0x0 7. "GMRC,Global Master ID Replication Control" "0: Master ID replication disabled for all channels,1: Master ID replication available and controlled.." bitfld.long 0x0 6. "GCLC,Global Channel Linking Control" "0: Channel linking disabled for all channels,1: Channel linking available and controlled by each.." newline bitfld.long 0x0 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels" bitfld.long 0x0 4. "HAE,Halt After Error" "0: Normal operation,1: Any error causes the HALT field to be set to 1" newline bitfld.long 0x0 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Round-robin channel arbitration disabled,1: Round-robin channel arbitration enabled" bitfld.long 0x0 1. "EDBG,Enable Debug" "0: Debug mode disabled,1: Debug mode is enabled." rgroup.long 0x4++0xB line.long 0x0 "ES,Management Page Error Status" bitfld.long 0x0 31. "VLD,Valid" "0: No CHn_ES[ERR] fields are set to 1,1: At least one CHn_ES[ERR] field is set to 1.." hexmask.long.byte 0x0 24.--28. 1. "ERRCHN,Error Channel Number or Canceled Channel Number" newline bitfld.long 0x0 9. "UCE,Uncorrectable TCD Error During Channel Execution" "0: No uncorrectable ECC error,1: Last recorded error was an uncorrectable TCD RAM.." bitfld.long 0x0 8. "ECX,Transfer Canceled" "0: No canceled transfers,1: Last recorded entry was a canceled transfer by.." newline bitfld.long 0x0 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was NBYTES equal to zero.." bitfld.long 0x0 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was a bus error on a source.." bitfld.long 0x0 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was a bus error on a.." line.long 0x4 "INT,Management Page Interrupt Request Status" hexmask.long 0x4 0.--31. 1. "INT,Interrupt Request Status" line.long 0x8 "HRS,Management Page Hardware Request Status" hexmask.long 0x8 0.--31. 1. "HRS,Hardware Request Status" repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CH_GRPRI[$1],Channel Arbitration Group" hexmask.long.byte 0x0 0.--4. 1. "GRPRI,Arbitration Group For Channel n" repeat.end tree.end tree.end tree "DMA_CRC (DMA Cyclic Redundancy Check Module)" base ad:0x0 tree "DMA_CRC_0" base ad:0x4013C000 group.long 0x0++0x3 line.long 0x0 "GEC,Global Enable CRC Register" bitfld.long 0x0 7. "SWAP_BYTE,Swap Byte" "0: Do not swap.,1: Byte-wise swap on the input data." bitfld.long 0x0 1. "SWAP_BIT,Swap Bit" "0: Do not swap.,1: Bit-wise swap on the input data." bitfld.long 0x0 0. "GBL_EN,Global Enable bit" "0: Disable CRC in all channels.,1: Enable CRC in all channels." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x4013C010 ad:0x4013C020 ad:0x4013C030 ad:0x4013C040 ad:0x4013C050 ad:0x4013C060 ad:0x4013C070 ad:0x4013C080) tree "Control_Register[$1]" base $2 group.long ($2)++0x7 line.long 0x0 "CTL,CRC Control Register" bitfld.long 0x0 31. "EN,CRC Logic" "0: Disable CRC.,1: Enable CRC." bitfld.long 0x0 16.--18. "MODE,CRC Mode" "0: Normal CRC Mode. All other combinations are..,?,?,?,?,?,?,?" newline bitfld.long 0x0 15. "INIT_SEL,Initial values of the CRC" "0: Initialize CRC with the content of the Initial..,1: Continue accumulating previous CRC values stored.." hexmask.long.byte 0x0 8.--11. 1. "POLY_SEL,Polynomial Select" newline hexmask.long.byte 0x0 0.--5. 1. "CH_SEL,Channel Select" line.long 0x4 "ICRC,Initial CRC Value Register" hexmask.long 0x4 0.--31. 1. "INI_CRC_VAL,Initial CRC Value" rgroup.long ($2+0x8)++0x3 line.long 0x0 "FCRC,Final CRC Value Register" hexmask.long 0x0 0.--31. 1. "CHKSUM_VAL,Final CRC Value" tree.end repeat.end tree.end tree "DMA_CRC_1" base ad:0x4023C000 group.long 0x0++0x3 line.long 0x0 "GEC,Global Enable CRC Register" bitfld.long 0x0 7. "SWAP_BYTE,Swap Byte" "0: Do not swap.,1: Byte-wise swap on the input data." bitfld.long 0x0 1. "SWAP_BIT,Swap Bit" "0: Do not swap.,1: Bit-wise swap on the input data." bitfld.long 0x0 0. "GBL_EN,Global Enable bit" "0: Disable CRC in all channels.,1: Enable CRC in all channels." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x4023C010 ad:0x4023C020 ad:0x4023C030 ad:0x4023C040 ad:0x4023C050 ad:0x4023C060 ad:0x4023C070 ad:0x4023C080) tree "Control_Register[$1]" base $2 group.long ($2)++0x7 line.long 0x0 "CTL,CRC Control Register" bitfld.long 0x0 31. "EN,CRC Logic" "0: Disable CRC.,1: Enable CRC." bitfld.long 0x0 16.--18. "MODE,CRC Mode" "0: Normal CRC Mode. All other combinations are..,?,?,?,?,?,?,?" newline bitfld.long 0x0 15. "INIT_SEL,Initial values of the CRC" "0: Initialize CRC with the content of the Initial..,1: Continue accumulating previous CRC values stored.." hexmask.long.byte 0x0 8.--11. 1. "POLY_SEL,Polynomial Select" newline hexmask.long.byte 0x0 0.--5. 1. "CH_SEL,Channel Select" line.long 0x4 "ICRC,Initial CRC Value Register" hexmask.long 0x4 0.--31. 1. "INI_CRC_VAL,Initial CRC Value" rgroup.long ($2+0x8)++0x3 line.long 0x0 "FCRC,Final CRC Value Register" hexmask.long 0x0 0.--31. 1. "CHKSUM_VAL,Final CRC Value" tree.end repeat.end tree.end tree.end tree "DMA_TCD (DMA Transfer Control Descriptor)" base ad:0x0 tree "EDMA_0_TCD" base ad:0x40148000 group.long 0x0++0x13 line.long 0x0 "CH0_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH0_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH0_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH0_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH0_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x0 "TCD0_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x24++0x3 line.word 0x0 "TCD0_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD0_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x28++0xB line.long 0x0 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD0_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x34++0x3 line.word 0x0 "TCD0_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x36++0x1 line.word 0x0 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x38++0x3 line.long 0x0 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x3C++0x3 line.word 0x0 "TCD0_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x3E++0x1 line.word 0x0 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1000++0x13 line.long 0x0 "CH1_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH1_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH1_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH1_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH1_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1020++0x3 line.long 0x0 "TCD1_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1024++0x3 line.word 0x0 "TCD1_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD1_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1028++0xB line.long 0x0 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD1_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1034++0x3 line.word 0x0 "TCD1_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1036++0x1 line.word 0x0 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1038++0x3 line.long 0x0 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x103C++0x3 line.word 0x0 "TCD1_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x103E++0x1 line.word 0x0 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x2000++0x13 line.long 0x0 "CH2_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH2_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH2_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH2_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH2_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x2020++0x3 line.long 0x0 "TCD2_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x2024++0x3 line.word 0x0 "TCD2_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD2_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x2028++0x3 line.long 0x0 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x2028++0xB line.long 0x0 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD2_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x2034++0x3 line.word 0x0 "TCD2_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x2036++0x1 line.word 0x0 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x2038++0x3 line.long 0x0 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x203C++0x3 line.word 0x0 "TCD2_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x203E++0x1 line.word 0x0 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x3000++0x13 line.long 0x0 "CH3_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH3_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH3_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH3_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH3_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x3020++0x3 line.long 0x0 "TCD3_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x3024++0x3 line.word 0x0 "TCD3_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD3_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x3028++0x3 line.long 0x0 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x3028++0xB line.long 0x0 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD3_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x3034++0x3 line.word 0x0 "TCD3_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x3036++0x1 line.word 0x0 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x3038++0x3 line.long 0x0 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x303C++0x3 line.word 0x0 "TCD3_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x303E++0x1 line.word 0x0 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x4000++0x13 line.long 0x0 "CH4_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH4_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH4_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH4_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH4_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x4020++0x3 line.long 0x0 "TCD4_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x4024++0x3 line.word 0x0 "TCD4_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD4_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x4028++0x3 line.long 0x0 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x4028++0xB line.long 0x0 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD4_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x4034++0x3 line.word 0x0 "TCD4_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x4036++0x1 line.word 0x0 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x4038++0x3 line.long 0x0 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x403C++0x3 line.word 0x0 "TCD4_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x403E++0x1 line.word 0x0 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x5000++0x13 line.long 0x0 "CH5_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH5_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH5_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH5_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH5_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x5020++0x3 line.long 0x0 "TCD5_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x5024++0x3 line.word 0x0 "TCD5_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD5_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x5028++0x3 line.long 0x0 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x5028++0xB line.long 0x0 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD5_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x5034++0x3 line.word 0x0 "TCD5_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x5036++0x1 line.word 0x0 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x5038++0x3 line.long 0x0 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x503C++0x3 line.word 0x0 "TCD5_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x503E++0x1 line.word 0x0 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x6000++0x13 line.long 0x0 "CH6_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH6_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH6_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH6_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH6_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x6020++0x3 line.long 0x0 "TCD6_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x6024++0x3 line.word 0x0 "TCD6_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD6_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x6028++0x3 line.long 0x0 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x6028++0xB line.long 0x0 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD6_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x6034++0x3 line.word 0x0 "TCD6_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x6036++0x1 line.word 0x0 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x6038++0x3 line.long 0x0 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x603C++0x3 line.word 0x0 "TCD6_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x603E++0x1 line.word 0x0 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x7000++0x13 line.long 0x0 "CH7_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH7_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH7_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH7_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH7_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x7020++0x3 line.long 0x0 "TCD7_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x7024++0x3 line.word 0x0 "TCD7_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD7_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x7028++0x3 line.long 0x0 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x7028++0xB line.long 0x0 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD7_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x7034++0x3 line.word 0x0 "TCD7_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x7036++0x1 line.word 0x0 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x7038++0x3 line.long 0x0 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x703C++0x3 line.word 0x0 "TCD7_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x703E++0x1 line.word 0x0 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x8000++0x13 line.long 0x0 "CH8_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH8_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH8_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH8_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH8_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x8020++0x3 line.long 0x0 "TCD8_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x8024++0x3 line.word 0x0 "TCD8_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD8_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x8028++0x3 line.long 0x0 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x8028++0xB line.long 0x0 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD8_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x8034++0x3 line.word 0x0 "TCD8_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x8036++0x1 line.word 0x0 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x8038++0x3 line.long 0x0 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x803C++0x3 line.word 0x0 "TCD8_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x803E++0x1 line.word 0x0 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x9000++0x13 line.long 0x0 "CH9_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH9_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH9_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH9_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH9_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x9020++0x3 line.long 0x0 "TCD9_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x9024++0x3 line.word 0x0 "TCD9_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD9_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x9028++0x3 line.long 0x0 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x9028++0xB line.long 0x0 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD9_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x9034++0x3 line.word 0x0 "TCD9_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x9036++0x1 line.word 0x0 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x9038++0x3 line.long 0x0 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x903C++0x3 line.word 0x0 "TCD9_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x903E++0x1 line.word 0x0 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xA000++0x13 line.long 0x0 "CH10_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH10_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH10_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH10_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH10_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xA020++0x3 line.long 0x0 "TCD10_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xA024++0x3 line.word 0x0 "TCD10_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD10_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xA028++0x3 line.long 0x0 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xA028++0xB line.long 0x0 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD10_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xA034++0x3 line.word 0x0 "TCD10_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xA036++0x1 line.word 0x0 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xA038++0x3 line.long 0x0 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xA03C++0x3 line.word 0x0 "TCD10_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xA03E++0x1 line.word 0x0 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xB000++0x13 line.long 0x0 "CH11_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH11_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH11_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH11_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH11_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xB020++0x3 line.long 0x0 "TCD11_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xB024++0x3 line.word 0x0 "TCD11_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD11_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xB028++0x3 line.long 0x0 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xB028++0xB line.long 0x0 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD11_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xB034++0x3 line.word 0x0 "TCD11_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xB036++0x1 line.word 0x0 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xB038++0x3 line.long 0x0 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xB03C++0x3 line.word 0x0 "TCD11_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xB03E++0x1 line.word 0x0 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xC000++0x13 line.long 0x0 "CH12_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH12_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH12_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH12_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH12_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xC020++0x3 line.long 0x0 "TCD12_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xC024++0x3 line.word 0x0 "TCD12_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD12_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xC028++0x3 line.long 0x0 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xC028++0xB line.long 0x0 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD12_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xC034++0x3 line.word 0x0 "TCD12_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xC036++0x1 line.word 0x0 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xC038++0x3 line.long 0x0 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xC03C++0x3 line.word 0x0 "TCD12_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xC03E++0x1 line.word 0x0 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xD000++0x13 line.long 0x0 "CH13_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH13_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH13_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH13_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH13_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xD020++0x3 line.long 0x0 "TCD13_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xD024++0x3 line.word 0x0 "TCD13_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD13_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xD028++0x3 line.long 0x0 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xD028++0xB line.long 0x0 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD13_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xD034++0x3 line.word 0x0 "TCD13_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xD036++0x1 line.word 0x0 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xD038++0x3 line.long 0x0 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xD03C++0x3 line.word 0x0 "TCD13_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xD03E++0x1 line.word 0x0 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xE000++0x13 line.long 0x0 "CH14_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH14_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH14_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH14_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH14_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xE020++0x3 line.long 0x0 "TCD14_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xE024++0x3 line.word 0x0 "TCD14_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD14_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xE028++0x3 line.long 0x0 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xE028++0xB line.long 0x0 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD14_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xE034++0x3 line.word 0x0 "TCD14_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xE036++0x1 line.word 0x0 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xE038++0x3 line.long 0x0 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xE03C++0x3 line.word 0x0 "TCD14_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xE03E++0x1 line.word 0x0 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xF000++0x13 line.long 0x0 "CH15_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH15_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH15_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH15_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH15_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xF020++0x3 line.long 0x0 "TCD15_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xF024++0x3 line.word 0x0 "TCD15_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD15_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xF028++0x3 line.long 0x0 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xF028++0xB line.long 0x0 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD15_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xF034++0x3 line.word 0x0 "TCD15_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xF036++0x1 line.word 0x0 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xF038++0x3 line.long 0x0 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xF03C++0x3 line.word 0x0 "TCD15_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xF03E++0x1 line.word 0x0 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x10000++0x13 line.long 0x0 "CH16_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH16_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH16_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH16_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH16_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x10020++0x3 line.long 0x0 "TCD16_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x10024++0x3 line.word 0x0 "TCD16_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD16_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x10028++0x3 line.long 0x0 "TCD16_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x10028++0xB line.long 0x0 "TCD16_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD16_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD16_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x10034++0x3 line.word 0x0 "TCD16_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD16_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x10036++0x1 line.word 0x0 "TCD16_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x10038++0x3 line.long 0x0 "TCD16_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1003C++0x3 line.word 0x0 "TCD16_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD16_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1003E++0x1 line.word 0x0 "TCD16_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x11000++0x13 line.long 0x0 "CH17_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH17_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH17_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH17_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH17_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x11020++0x3 line.long 0x0 "TCD17_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x11024++0x3 line.word 0x0 "TCD17_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD17_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x11028++0x3 line.long 0x0 "TCD17_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x11028++0xB line.long 0x0 "TCD17_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD17_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD17_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x11034++0x3 line.word 0x0 "TCD17_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD17_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x11036++0x1 line.word 0x0 "TCD17_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x11038++0x3 line.long 0x0 "TCD17_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1103C++0x3 line.word 0x0 "TCD17_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD17_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1103E++0x1 line.word 0x0 "TCD17_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x12000++0x13 line.long 0x0 "CH18_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH18_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH18_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH18_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH18_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x12020++0x3 line.long 0x0 "TCD18_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x12024++0x3 line.word 0x0 "TCD18_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD18_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x12028++0x3 line.long 0x0 "TCD18_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x12028++0xB line.long 0x0 "TCD18_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD18_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD18_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x12034++0x3 line.word 0x0 "TCD18_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD18_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x12036++0x1 line.word 0x0 "TCD18_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x12038++0x3 line.long 0x0 "TCD18_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1203C++0x3 line.word 0x0 "TCD18_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD18_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1203E++0x1 line.word 0x0 "TCD18_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x13000++0x13 line.long 0x0 "CH19_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH19_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH19_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH19_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH19_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x13020++0x3 line.long 0x0 "TCD19_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x13024++0x3 line.word 0x0 "TCD19_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD19_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x13028++0x3 line.long 0x0 "TCD19_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x13028++0xB line.long 0x0 "TCD19_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD19_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD19_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x13034++0x3 line.word 0x0 "TCD19_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD19_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x13036++0x1 line.word 0x0 "TCD19_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x13038++0x3 line.long 0x0 "TCD19_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1303C++0x3 line.word 0x0 "TCD19_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD19_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1303E++0x1 line.word 0x0 "TCD19_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x14000++0x13 line.long 0x0 "CH20_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH20_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH20_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH20_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH20_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x14020++0x3 line.long 0x0 "TCD20_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x14024++0x3 line.word 0x0 "TCD20_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD20_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x14028++0x3 line.long 0x0 "TCD20_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x14028++0xB line.long 0x0 "TCD20_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD20_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD20_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x14034++0x3 line.word 0x0 "TCD20_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD20_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x14036++0x1 line.word 0x0 "TCD20_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x14038++0x3 line.long 0x0 "TCD20_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1403C++0x3 line.word 0x0 "TCD20_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD20_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1403E++0x1 line.word 0x0 "TCD20_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x15000++0x13 line.long 0x0 "CH21_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH21_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH21_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH21_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH21_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x15020++0x3 line.long 0x0 "TCD21_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x15024++0x3 line.word 0x0 "TCD21_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD21_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x15028++0x3 line.long 0x0 "TCD21_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x15028++0xB line.long 0x0 "TCD21_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD21_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD21_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x15034++0x3 line.word 0x0 "TCD21_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD21_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x15036++0x1 line.word 0x0 "TCD21_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x15038++0x3 line.long 0x0 "TCD21_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1503C++0x3 line.word 0x0 "TCD21_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD21_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1503E++0x1 line.word 0x0 "TCD21_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x16000++0x13 line.long 0x0 "CH22_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH22_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH22_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH22_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH22_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x16020++0x3 line.long 0x0 "TCD22_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x16024++0x3 line.word 0x0 "TCD22_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD22_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x16028++0x3 line.long 0x0 "TCD22_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x16028++0xB line.long 0x0 "TCD22_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD22_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD22_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x16034++0x3 line.word 0x0 "TCD22_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD22_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x16036++0x1 line.word 0x0 "TCD22_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x16038++0x3 line.long 0x0 "TCD22_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1603C++0x3 line.word 0x0 "TCD22_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD22_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1603E++0x1 line.word 0x0 "TCD22_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x17000++0x13 line.long 0x0 "CH23_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH23_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH23_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH23_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH23_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x17020++0x3 line.long 0x0 "TCD23_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x17024++0x3 line.word 0x0 "TCD23_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD23_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x17028++0x3 line.long 0x0 "TCD23_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x17028++0xB line.long 0x0 "TCD23_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD23_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD23_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x17034++0x3 line.word 0x0 "TCD23_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD23_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x17036++0x1 line.word 0x0 "TCD23_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x17038++0x3 line.long 0x0 "TCD23_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1703C++0x3 line.word 0x0 "TCD23_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD23_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1703E++0x1 line.word 0x0 "TCD23_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x18000++0x13 line.long 0x0 "CH24_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH24_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH24_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH24_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH24_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x18020++0x3 line.long 0x0 "TCD24_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x18024++0x3 line.word 0x0 "TCD24_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD24_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x18028++0x3 line.long 0x0 "TCD24_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x18028++0xB line.long 0x0 "TCD24_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD24_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD24_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x18034++0x3 line.word 0x0 "TCD24_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD24_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x18036++0x1 line.word 0x0 "TCD24_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x18038++0x3 line.long 0x0 "TCD24_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1803C++0x3 line.word 0x0 "TCD24_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD24_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1803E++0x1 line.word 0x0 "TCD24_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x19000++0x13 line.long 0x0 "CH25_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH25_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH25_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH25_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH25_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x19020++0x3 line.long 0x0 "TCD25_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x19024++0x3 line.word 0x0 "TCD25_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD25_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x19028++0x3 line.long 0x0 "TCD25_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x19028++0xB line.long 0x0 "TCD25_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD25_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD25_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x19034++0x3 line.word 0x0 "TCD25_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD25_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x19036++0x1 line.word 0x0 "TCD25_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x19038++0x3 line.long 0x0 "TCD25_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1903C++0x3 line.word 0x0 "TCD25_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD25_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1903E++0x1 line.word 0x0 "TCD25_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1A000++0x13 line.long 0x0 "CH26_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH26_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH26_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH26_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH26_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1A020++0x3 line.long 0x0 "TCD26_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1A024++0x3 line.word 0x0 "TCD26_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD26_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1A028++0x3 line.long 0x0 "TCD26_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1A028++0xB line.long 0x0 "TCD26_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD26_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD26_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1A034++0x3 line.word 0x0 "TCD26_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD26_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1A036++0x1 line.word 0x0 "TCD26_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1A038++0x3 line.long 0x0 "TCD26_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1A03C++0x3 line.word 0x0 "TCD26_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD26_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1A03E++0x1 line.word 0x0 "TCD26_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1B000++0x13 line.long 0x0 "CH27_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH27_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH27_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH27_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH27_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1B020++0x3 line.long 0x0 "TCD27_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1B024++0x3 line.word 0x0 "TCD27_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD27_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1B028++0x3 line.long 0x0 "TCD27_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1B028++0xB line.long 0x0 "TCD27_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD27_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD27_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1B034++0x3 line.word 0x0 "TCD27_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD27_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1B036++0x1 line.word 0x0 "TCD27_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1B038++0x3 line.long 0x0 "TCD27_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1B03C++0x3 line.word 0x0 "TCD27_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD27_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1B03E++0x1 line.word 0x0 "TCD27_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1C000++0x13 line.long 0x0 "CH28_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH28_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH28_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH28_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH28_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1C020++0x3 line.long 0x0 "TCD28_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1C024++0x3 line.word 0x0 "TCD28_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD28_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1C028++0x3 line.long 0x0 "TCD28_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1C028++0xB line.long 0x0 "TCD28_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD28_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD28_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1C034++0x3 line.word 0x0 "TCD28_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD28_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1C036++0x1 line.word 0x0 "TCD28_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1C038++0x3 line.long 0x0 "TCD28_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1C03C++0x3 line.word 0x0 "TCD28_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD28_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1C03E++0x1 line.word 0x0 "TCD28_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1D000++0x13 line.long 0x0 "CH29_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH29_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH29_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH29_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH29_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1D020++0x3 line.long 0x0 "TCD29_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1D024++0x3 line.word 0x0 "TCD29_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD29_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1D028++0x3 line.long 0x0 "TCD29_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1D028++0xB line.long 0x0 "TCD29_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD29_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD29_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1D034++0x3 line.word 0x0 "TCD29_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD29_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1D036++0x1 line.word 0x0 "TCD29_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1D038++0x3 line.long 0x0 "TCD29_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1D03C++0x3 line.word 0x0 "TCD29_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD29_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1D03E++0x1 line.word 0x0 "TCD29_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1E000++0x13 line.long 0x0 "CH30_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH30_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH30_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH30_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH30_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1E020++0x3 line.long 0x0 "TCD30_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1E024++0x3 line.word 0x0 "TCD30_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD30_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1E028++0x3 line.long 0x0 "TCD30_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1E028++0xB line.long 0x0 "TCD30_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD30_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD30_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1E034++0x3 line.word 0x0 "TCD30_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD30_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1E036++0x1 line.word 0x0 "TCD30_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1E038++0x3 line.long 0x0 "TCD30_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1E03C++0x3 line.word 0x0 "TCD30_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD30_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1E03E++0x1 line.word 0x0 "TCD30_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1F000++0x13 line.long 0x0 "CH31_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH31_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH31_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH31_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH31_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1F020++0x3 line.long 0x0 "TCD31_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1F024++0x3 line.word 0x0 "TCD31_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD31_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1F028++0x3 line.long 0x0 "TCD31_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1F028++0xB line.long 0x0 "TCD31_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD31_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD31_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1F034++0x3 line.word 0x0 "TCD31_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD31_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1F036++0x1 line.word 0x0 "TCD31_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1F038++0x3 line.long 0x0 "TCD31_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1F03C++0x3 line.word 0x0 "TCD31_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD31_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1F03E++0x1 line.word 0x0 "TCD31_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" tree.end tree "EDMA_1_TCD" base ad:0x40248000 group.long 0x0++0x13 line.long 0x0 "CH0_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH0_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH0_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH0_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH0_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x0 "TCD0_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x24++0x3 line.word 0x0 "TCD0_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD0_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x28++0xB line.long 0x0 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD0_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x34++0x3 line.word 0x0 "TCD0_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x36++0x1 line.word 0x0 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x38++0x3 line.long 0x0 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x3C++0x3 line.word 0x0 "TCD0_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x3E++0x1 line.word 0x0 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1000++0x13 line.long 0x0 "CH1_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH1_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH1_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH1_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH1_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1020++0x3 line.long 0x0 "TCD1_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1024++0x3 line.word 0x0 "TCD1_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD1_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1028++0xB line.long 0x0 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD1_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1034++0x3 line.word 0x0 "TCD1_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1036++0x1 line.word 0x0 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1038++0x3 line.long 0x0 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x103C++0x3 line.word 0x0 "TCD1_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x103E++0x1 line.word 0x0 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x2000++0x13 line.long 0x0 "CH2_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH2_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH2_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH2_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH2_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x2020++0x3 line.long 0x0 "TCD2_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x2024++0x3 line.word 0x0 "TCD2_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD2_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x2028++0x3 line.long 0x0 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x2028++0xB line.long 0x0 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD2_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x2034++0x3 line.word 0x0 "TCD2_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x2036++0x1 line.word 0x0 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x2038++0x3 line.long 0x0 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x203C++0x3 line.word 0x0 "TCD2_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x203E++0x1 line.word 0x0 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x3000++0x13 line.long 0x0 "CH3_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH3_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH3_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH3_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH3_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x3020++0x3 line.long 0x0 "TCD3_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x3024++0x3 line.word 0x0 "TCD3_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD3_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x3028++0x3 line.long 0x0 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x3028++0xB line.long 0x0 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD3_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x3034++0x3 line.word 0x0 "TCD3_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x3036++0x1 line.word 0x0 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x3038++0x3 line.long 0x0 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x303C++0x3 line.word 0x0 "TCD3_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x303E++0x1 line.word 0x0 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x4000++0x13 line.long 0x0 "CH4_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH4_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH4_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH4_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH4_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x4020++0x3 line.long 0x0 "TCD4_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x4024++0x3 line.word 0x0 "TCD4_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD4_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x4028++0x3 line.long 0x0 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x4028++0xB line.long 0x0 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD4_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x4034++0x3 line.word 0x0 "TCD4_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x4036++0x1 line.word 0x0 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x4038++0x3 line.long 0x0 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x403C++0x3 line.word 0x0 "TCD4_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x403E++0x1 line.word 0x0 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x5000++0x13 line.long 0x0 "CH5_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH5_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH5_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH5_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH5_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x5020++0x3 line.long 0x0 "TCD5_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x5024++0x3 line.word 0x0 "TCD5_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD5_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x5028++0x3 line.long 0x0 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x5028++0xB line.long 0x0 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD5_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x5034++0x3 line.word 0x0 "TCD5_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x5036++0x1 line.word 0x0 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x5038++0x3 line.long 0x0 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x503C++0x3 line.word 0x0 "TCD5_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x503E++0x1 line.word 0x0 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x6000++0x13 line.long 0x0 "CH6_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH6_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH6_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH6_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH6_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x6020++0x3 line.long 0x0 "TCD6_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x6024++0x3 line.word 0x0 "TCD6_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD6_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x6028++0x3 line.long 0x0 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x6028++0xB line.long 0x0 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD6_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x6034++0x3 line.word 0x0 "TCD6_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x6036++0x1 line.word 0x0 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x6038++0x3 line.long 0x0 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x603C++0x3 line.word 0x0 "TCD6_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x603E++0x1 line.word 0x0 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x7000++0x13 line.long 0x0 "CH7_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH7_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH7_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH7_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH7_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x7020++0x3 line.long 0x0 "TCD7_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x7024++0x3 line.word 0x0 "TCD7_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD7_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x7028++0x3 line.long 0x0 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x7028++0xB line.long 0x0 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD7_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x7034++0x3 line.word 0x0 "TCD7_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x7036++0x1 line.word 0x0 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x7038++0x3 line.long 0x0 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x703C++0x3 line.word 0x0 "TCD7_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x703E++0x1 line.word 0x0 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x8000++0x13 line.long 0x0 "CH8_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH8_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH8_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH8_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH8_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x8020++0x3 line.long 0x0 "TCD8_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x8024++0x3 line.word 0x0 "TCD8_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD8_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x8028++0x3 line.long 0x0 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x8028++0xB line.long 0x0 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD8_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x8034++0x3 line.word 0x0 "TCD8_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x8036++0x1 line.word 0x0 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x8038++0x3 line.long 0x0 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x803C++0x3 line.word 0x0 "TCD8_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x803E++0x1 line.word 0x0 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x9000++0x13 line.long 0x0 "CH9_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH9_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH9_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH9_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH9_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x9020++0x3 line.long 0x0 "TCD9_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x9024++0x3 line.word 0x0 "TCD9_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD9_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x9028++0x3 line.long 0x0 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x9028++0xB line.long 0x0 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD9_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x9034++0x3 line.word 0x0 "TCD9_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x9036++0x1 line.word 0x0 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x9038++0x3 line.long 0x0 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x903C++0x3 line.word 0x0 "TCD9_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x903E++0x1 line.word 0x0 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xA000++0x13 line.long 0x0 "CH10_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH10_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH10_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH10_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH10_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xA020++0x3 line.long 0x0 "TCD10_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xA024++0x3 line.word 0x0 "TCD10_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD10_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xA028++0x3 line.long 0x0 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xA028++0xB line.long 0x0 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD10_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xA034++0x3 line.word 0x0 "TCD10_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xA036++0x1 line.word 0x0 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xA038++0x3 line.long 0x0 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xA03C++0x3 line.word 0x0 "TCD10_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xA03E++0x1 line.word 0x0 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xB000++0x13 line.long 0x0 "CH11_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH11_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH11_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH11_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH11_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xB020++0x3 line.long 0x0 "TCD11_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xB024++0x3 line.word 0x0 "TCD11_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD11_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xB028++0x3 line.long 0x0 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xB028++0xB line.long 0x0 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD11_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xB034++0x3 line.word 0x0 "TCD11_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xB036++0x1 line.word 0x0 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xB038++0x3 line.long 0x0 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xB03C++0x3 line.word 0x0 "TCD11_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xB03E++0x1 line.word 0x0 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xC000++0x13 line.long 0x0 "CH12_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH12_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH12_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH12_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH12_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xC020++0x3 line.long 0x0 "TCD12_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xC024++0x3 line.word 0x0 "TCD12_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD12_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xC028++0x3 line.long 0x0 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xC028++0xB line.long 0x0 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD12_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xC034++0x3 line.word 0x0 "TCD12_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xC036++0x1 line.word 0x0 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xC038++0x3 line.long 0x0 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xC03C++0x3 line.word 0x0 "TCD12_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xC03E++0x1 line.word 0x0 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xD000++0x13 line.long 0x0 "CH13_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH13_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH13_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH13_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH13_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xD020++0x3 line.long 0x0 "TCD13_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xD024++0x3 line.word 0x0 "TCD13_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD13_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xD028++0x3 line.long 0x0 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xD028++0xB line.long 0x0 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD13_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xD034++0x3 line.word 0x0 "TCD13_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xD036++0x1 line.word 0x0 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xD038++0x3 line.long 0x0 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xD03C++0x3 line.word 0x0 "TCD13_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xD03E++0x1 line.word 0x0 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xE000++0x13 line.long 0x0 "CH14_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH14_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH14_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH14_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH14_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xE020++0x3 line.long 0x0 "TCD14_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xE024++0x3 line.word 0x0 "TCD14_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD14_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xE028++0x3 line.long 0x0 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xE028++0xB line.long 0x0 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD14_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xE034++0x3 line.word 0x0 "TCD14_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xE036++0x1 line.word 0x0 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xE038++0x3 line.long 0x0 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xE03C++0x3 line.word 0x0 "TCD14_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xE03E++0x1 line.word 0x0 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xF000++0x13 line.long 0x0 "CH15_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH15_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH15_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH15_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH15_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xF020++0x3 line.long 0x0 "TCD15_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xF024++0x3 line.word 0x0 "TCD15_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD15_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xF028++0x3 line.long 0x0 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xF028++0xB line.long 0x0 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD15_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xF034++0x3 line.word 0x0 "TCD15_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xF036++0x1 line.word 0x0 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xF038++0x3 line.long 0x0 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xF03C++0x3 line.word 0x0 "TCD15_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xF03E++0x1 line.word 0x0 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x10000++0x13 line.long 0x0 "CH16_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH16_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH16_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH16_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH16_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x10020++0x3 line.long 0x0 "TCD16_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x10024++0x3 line.word 0x0 "TCD16_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD16_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x10028++0x3 line.long 0x0 "TCD16_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x10028++0xB line.long 0x0 "TCD16_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD16_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD16_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x10034++0x3 line.word 0x0 "TCD16_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD16_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x10036++0x1 line.word 0x0 "TCD16_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x10038++0x3 line.long 0x0 "TCD16_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1003C++0x3 line.word 0x0 "TCD16_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD16_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1003E++0x1 line.word 0x0 "TCD16_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x11000++0x13 line.long 0x0 "CH17_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH17_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH17_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH17_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH17_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x11020++0x3 line.long 0x0 "TCD17_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x11024++0x3 line.word 0x0 "TCD17_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD17_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x11028++0x3 line.long 0x0 "TCD17_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x11028++0xB line.long 0x0 "TCD17_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD17_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD17_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x11034++0x3 line.word 0x0 "TCD17_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD17_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x11036++0x1 line.word 0x0 "TCD17_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x11038++0x3 line.long 0x0 "TCD17_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1103C++0x3 line.word 0x0 "TCD17_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD17_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1103E++0x1 line.word 0x0 "TCD17_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x12000++0x13 line.long 0x0 "CH18_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH18_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH18_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH18_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH18_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x12020++0x3 line.long 0x0 "TCD18_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x12024++0x3 line.word 0x0 "TCD18_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD18_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x12028++0x3 line.long 0x0 "TCD18_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x12028++0xB line.long 0x0 "TCD18_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD18_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD18_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x12034++0x3 line.word 0x0 "TCD18_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD18_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x12036++0x1 line.word 0x0 "TCD18_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x12038++0x3 line.long 0x0 "TCD18_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1203C++0x3 line.word 0x0 "TCD18_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD18_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1203E++0x1 line.word 0x0 "TCD18_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x13000++0x13 line.long 0x0 "CH19_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH19_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH19_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH19_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH19_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x13020++0x3 line.long 0x0 "TCD19_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x13024++0x3 line.word 0x0 "TCD19_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD19_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x13028++0x3 line.long 0x0 "TCD19_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x13028++0xB line.long 0x0 "TCD19_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD19_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD19_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x13034++0x3 line.word 0x0 "TCD19_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD19_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x13036++0x1 line.word 0x0 "TCD19_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x13038++0x3 line.long 0x0 "TCD19_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1303C++0x3 line.word 0x0 "TCD19_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD19_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1303E++0x1 line.word 0x0 "TCD19_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x14000++0x13 line.long 0x0 "CH20_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH20_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH20_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH20_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH20_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x14020++0x3 line.long 0x0 "TCD20_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x14024++0x3 line.word 0x0 "TCD20_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD20_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x14028++0x3 line.long 0x0 "TCD20_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x14028++0xB line.long 0x0 "TCD20_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD20_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD20_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x14034++0x3 line.word 0x0 "TCD20_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD20_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x14036++0x1 line.word 0x0 "TCD20_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x14038++0x3 line.long 0x0 "TCD20_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1403C++0x3 line.word 0x0 "TCD20_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD20_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1403E++0x1 line.word 0x0 "TCD20_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x15000++0x13 line.long 0x0 "CH21_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH21_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH21_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH21_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH21_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x15020++0x3 line.long 0x0 "TCD21_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x15024++0x3 line.word 0x0 "TCD21_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD21_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x15028++0x3 line.long 0x0 "TCD21_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x15028++0xB line.long 0x0 "TCD21_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD21_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD21_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x15034++0x3 line.word 0x0 "TCD21_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD21_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x15036++0x1 line.word 0x0 "TCD21_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x15038++0x3 line.long 0x0 "TCD21_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1503C++0x3 line.word 0x0 "TCD21_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD21_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1503E++0x1 line.word 0x0 "TCD21_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x16000++0x13 line.long 0x0 "CH22_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH22_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH22_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH22_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH22_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x16020++0x3 line.long 0x0 "TCD22_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x16024++0x3 line.word 0x0 "TCD22_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD22_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x16028++0x3 line.long 0x0 "TCD22_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x16028++0xB line.long 0x0 "TCD22_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD22_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD22_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x16034++0x3 line.word 0x0 "TCD22_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD22_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x16036++0x1 line.word 0x0 "TCD22_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x16038++0x3 line.long 0x0 "TCD22_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1603C++0x3 line.word 0x0 "TCD22_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD22_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1603E++0x1 line.word 0x0 "TCD22_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x17000++0x13 line.long 0x0 "CH23_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH23_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH23_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH23_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH23_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x17020++0x3 line.long 0x0 "TCD23_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x17024++0x3 line.word 0x0 "TCD23_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD23_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x17028++0x3 line.long 0x0 "TCD23_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x17028++0xB line.long 0x0 "TCD23_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD23_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD23_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x17034++0x3 line.word 0x0 "TCD23_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD23_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x17036++0x1 line.word 0x0 "TCD23_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x17038++0x3 line.long 0x0 "TCD23_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1703C++0x3 line.word 0x0 "TCD23_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD23_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1703E++0x1 line.word 0x0 "TCD23_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x18000++0x13 line.long 0x0 "CH24_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH24_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH24_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH24_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH24_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x18020++0x3 line.long 0x0 "TCD24_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x18024++0x3 line.word 0x0 "TCD24_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD24_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x18028++0x3 line.long 0x0 "TCD24_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x18028++0xB line.long 0x0 "TCD24_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD24_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD24_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x18034++0x3 line.word 0x0 "TCD24_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD24_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x18036++0x1 line.word 0x0 "TCD24_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x18038++0x3 line.long 0x0 "TCD24_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1803C++0x3 line.word 0x0 "TCD24_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD24_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1803E++0x1 line.word 0x0 "TCD24_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x19000++0x13 line.long 0x0 "CH25_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH25_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH25_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH25_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH25_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x19020++0x3 line.long 0x0 "TCD25_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x19024++0x3 line.word 0x0 "TCD25_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD25_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x19028++0x3 line.long 0x0 "TCD25_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x19028++0xB line.long 0x0 "TCD25_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD25_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD25_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x19034++0x3 line.word 0x0 "TCD25_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD25_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x19036++0x1 line.word 0x0 "TCD25_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x19038++0x3 line.long 0x0 "TCD25_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1903C++0x3 line.word 0x0 "TCD25_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD25_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1903E++0x1 line.word 0x0 "TCD25_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1A000++0x13 line.long 0x0 "CH26_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH26_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH26_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH26_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH26_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1A020++0x3 line.long 0x0 "TCD26_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1A024++0x3 line.word 0x0 "TCD26_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD26_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1A028++0x3 line.long 0x0 "TCD26_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1A028++0xB line.long 0x0 "TCD26_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD26_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD26_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1A034++0x3 line.word 0x0 "TCD26_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD26_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1A036++0x1 line.word 0x0 "TCD26_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1A038++0x3 line.long 0x0 "TCD26_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1A03C++0x3 line.word 0x0 "TCD26_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD26_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1A03E++0x1 line.word 0x0 "TCD26_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1B000++0x13 line.long 0x0 "CH27_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH27_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH27_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH27_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH27_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1B020++0x3 line.long 0x0 "TCD27_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1B024++0x3 line.word 0x0 "TCD27_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD27_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1B028++0x3 line.long 0x0 "TCD27_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1B028++0xB line.long 0x0 "TCD27_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD27_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD27_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1B034++0x3 line.word 0x0 "TCD27_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD27_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1B036++0x1 line.word 0x0 "TCD27_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1B038++0x3 line.long 0x0 "TCD27_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1B03C++0x3 line.word 0x0 "TCD27_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD27_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1B03E++0x1 line.word 0x0 "TCD27_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1C000++0x13 line.long 0x0 "CH28_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH28_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH28_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH28_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH28_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1C020++0x3 line.long 0x0 "TCD28_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1C024++0x3 line.word 0x0 "TCD28_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD28_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1C028++0x3 line.long 0x0 "TCD28_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1C028++0xB line.long 0x0 "TCD28_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD28_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD28_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1C034++0x3 line.word 0x0 "TCD28_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD28_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1C036++0x1 line.word 0x0 "TCD28_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1C038++0x3 line.long 0x0 "TCD28_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1C03C++0x3 line.word 0x0 "TCD28_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD28_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1C03E++0x1 line.word 0x0 "TCD28_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1D000++0x13 line.long 0x0 "CH29_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH29_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH29_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH29_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH29_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1D020++0x3 line.long 0x0 "TCD29_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1D024++0x3 line.word 0x0 "TCD29_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD29_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1D028++0x3 line.long 0x0 "TCD29_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1D028++0xB line.long 0x0 "TCD29_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD29_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD29_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1D034++0x3 line.word 0x0 "TCD29_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD29_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1D036++0x1 line.word 0x0 "TCD29_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1D038++0x3 line.long 0x0 "TCD29_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1D03C++0x3 line.word 0x0 "TCD29_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD29_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1D03E++0x1 line.word 0x0 "TCD29_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1E000++0x13 line.long 0x0 "CH30_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH30_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH30_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH30_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH30_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1E020++0x3 line.long 0x0 "TCD30_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1E024++0x3 line.word 0x0 "TCD30_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD30_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1E028++0x3 line.long 0x0 "TCD30_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1E028++0xB line.long 0x0 "TCD30_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD30_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD30_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1E034++0x3 line.word 0x0 "TCD30_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD30_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1E036++0x1 line.word 0x0 "TCD30_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1E038++0x3 line.long 0x0 "TCD30_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1E03C++0x3 line.word 0x0 "TCD30_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD30_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1E03E++0x1 line.word 0x0 "TCD30_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1F000++0x13 line.long 0x0 "CH31_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH31_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH31_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH31_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH31_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1F020++0x3 line.long 0x0 "TCD31_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1F024++0x3 line.word 0x0 "TCD31_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD31_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1F028++0x3 line.long 0x0 "TCD31_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1F028++0xB line.long 0x0 "TCD31_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD31_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD31_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1F034++0x3 line.word 0x0 "TCD31_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD31_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1F036++0x1 line.word 0x0 "TCD31_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1F038++0x3 line.long 0x0 "TCD31_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1F03C++0x3 line.word 0x0 "TCD31_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD31_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1F03E++0x1 line.word 0x0 "TCD31_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" tree.end tree.end tree "DMAMUX (Direct Memory Access Multiplexer)" base ad:0x0 tree "DMAMUX_0" base ad:0x4012C000 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "CHCFG$1,Channel Configuration register" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled. If triggering is enabled.." hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" repeat.end tree.end tree "DMAMUX_1" base ad:0x40130000 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "CHCFG$1,Channel Configuration register" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled. If triggering is enabled.." hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" repeat.end tree.end tree "DMAMUX_2" base ad:0x4022C000 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "CHCFG$1,Channel Configuration register" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled. If triggering is enabled.." hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" repeat.end tree.end tree "DMAMUX_3" base ad:0x40230000 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "CHCFG$1,Channel Configuration register" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled. This mode is primarily..,1: DMA channel is enabled" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled. If triggering is..,1: Triggering is enabled. If triggering is enabled.." hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" repeat.end tree.end tree.end tree "EIM (Error Injection Module)" base ad:0x0 tree "EIM" base ad:0x40308000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 14. "EICH17EN,Error Injection Channel 17 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 13. "EICH18EN,Error Injection Channel 18 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 12. "EICH19EN,Error Injection Channel 19 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 11. "EICH20EN,Error Injection Channel 20 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 10. "EICH21EN,Error Injection Channel 21 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 9. "EICH22EN,Error Injection Channel 22 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 8. "EICH23EN,Error Injection Channel 23 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 7. "EICH24EN,Error Injection Channel 24 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 6. "EICH25EN,Error Injection Channel 25 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 5. "EICH26EN,Error Injection Channel 26 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 4. "EICH27EN,Error Injection Channel 27 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 3. "EICH28EN,Error Injection Channel 28 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 2. "EICH29EN,Error Injection Channel 29 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 1. "EICH30EN,Error Injection Channel 30 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0x23 line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD0_WORD3,Error Injection Channel Descriptor 0. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD0_WORD4,Error Injection Channel Descriptor 0. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD0_WORD5,Error Injection Channel Descriptor 0. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD0_WORD6,Error Injection Channel Descriptor 0. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD0_WORD7,Error Injection Channel Descriptor 0. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD0_WORD8,Error Injection Channel Descriptor 0. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x140++0x23 line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD1_WORD3,Error Injection Channel Descriptor 1. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD1_WORD4,Error Injection Channel Descriptor 1. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD1_WORD5,Error Injection Channel Descriptor 1. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD1_WORD6,Error Injection Channel Descriptor 1. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD1_WORD7,Error Injection Channel Descriptor 1. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD1_WORD8,Error Injection Channel Descriptor 1. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x180++0x23 line.long 0x0 "EICHD2_WORD0,Error Injection Channel Descriptor 2. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD2_WORD3,Error Injection Channel Descriptor 2. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD2_WORD4,Error Injection Channel Descriptor 2. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD2_WORD5,Error Injection Channel Descriptor 2. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD2_WORD6,Error Injection Channel Descriptor 2. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD2_WORD7,Error Injection Channel Descriptor 2. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD2_WORD8,Error Injection Channel Descriptor 2. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x1C0++0x23 line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD3_WORD3,Error Injection Channel Descriptor 3. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD3_WORD4,Error Injection Channel Descriptor 3. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD3_WORD5,Error Injection Channel Descriptor 3. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD3_WORD6,Error Injection Channel Descriptor 3. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD3_WORD7,Error Injection Channel Descriptor 3. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD3_WORD8,Error Injection Channel Descriptor 3. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x200++0x23 line.long 0x0 "EICHD4_WORD0,Error Injection Channel Descriptor 4. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD4_WORD3,Error Injection Channel Descriptor 4. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD4_WORD4,Error Injection Channel Descriptor 4. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD4_WORD5,Error Injection Channel Descriptor 4. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD4_WORD6,Error Injection Channel Descriptor 4. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD4_WORD7,Error Injection Channel Descriptor 4. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD4_WORD8,Error Injection Channel Descriptor 4. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x240++0x23 line.long 0x0 "EICHD5_WORD0,Error Injection Channel Descriptor 5. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD5_WORD2,Error Injection Channel Descriptor 5. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD5_WORD3,Error Injection Channel Descriptor 5. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD5_WORD4,Error Injection Channel Descriptor 5. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD5_WORD5,Error Injection Channel Descriptor 5. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD5_WORD6,Error Injection Channel Descriptor 5. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD5_WORD7,Error Injection Channel Descriptor 5. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD5_WORD8,Error Injection Channel Descriptor 5. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x280++0x23 line.long 0x0 "EICHD6_WORD0,Error Injection Channel Descriptor 6. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD6_WORD2,Error Injection Channel Descriptor 6. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD6_WORD3,Error Injection Channel Descriptor 6. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD6_WORD4,Error Injection Channel Descriptor 6. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD6_WORD5,Error Injection Channel Descriptor 6. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD6_WORD6,Error Injection Channel Descriptor 6. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD6_WORD7,Error Injection Channel Descriptor 6. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD6_WORD8,Error Injection Channel Descriptor 6. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x2C0++0x23 line.long 0x0 "EICHD7_WORD0,Error Injection Channel Descriptor 7. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD7_WORD2,Error Injection Channel Descriptor 7. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD7_WORD3,Error Injection Channel Descriptor 7. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD7_WORD4,Error Injection Channel Descriptor 7. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD7_WORD5,Error Injection Channel Descriptor 7. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD7_WORD6,Error Injection Channel Descriptor 7. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD7_WORD7,Error Injection Channel Descriptor 7. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD7_WORD8,Error Injection Channel Descriptor 7. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x300++0xB line.long 0x0 "EICHD8_WORD0,Error Injection Channel Descriptor 8. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x340++0xB line.long 0x0 "EICHD9_WORD0,Error Injection Channel Descriptor 9. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD9_WORD2,Error Injection Channel Descriptor 9. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x380++0xB line.long 0x0 "EICHD10_WORD0,Error Injection Channel Descriptor 10. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD10_WORD2,Error Injection Channel Descriptor 10. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x3C0++0xB line.long 0x0 "EICHD11_WORD0,Error Injection Channel Descriptor 11. Word0" hexmask.long.word 0x0 18.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long.word 0x4 0.--11. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD11_WORD2,Error Injection Channel Descriptor 11. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x400++0x13 line.long 0x0 "EICHD12_WORD0,Error Injection Channel Descriptor 12. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD12_WORD2,Error Injection Channel Descriptor 12. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD12_WORD3,Error Injection Channel Descriptor 12. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD12_WORD4,Error Injection Channel Descriptor 12. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x440++0x13 line.long 0x0 "EICHD13_WORD0,Error Injection Channel Descriptor 13. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long.byte 0x4 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD13_WORD3,Error Injection Channel Descriptor 13. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD13_WORD4,Error Injection Channel Descriptor 13. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x480++0x13 line.long 0x0 "EICHD14_WORD0,Error Injection Channel Descriptor 14. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD14_WORD2,Error Injection Channel Descriptor 14. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD14_WORD3,Error Injection Channel Descriptor 14. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD14_WORD4,Error Injection Channel Descriptor 14. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x4C0++0x13 line.long 0x0 "EICHD15_WORD0,Error Injection Channel Descriptor 15. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD15_WORD1,Error Injection Channel Descriptor 15. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD15_WORD2,Error Injection Channel Descriptor 15. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD15_WORD3,Error Injection Channel Descriptor 15. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD15_WORD4,Error Injection Channel Descriptor 15. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x500++0xB line.long 0x0 "EICHD16_WORD0,Error Injection Channel Descriptor 16. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD16_WORD1,Error Injection Channel Descriptor 16. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD16_WORD2,Error Injection Channel Descriptor 16. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x540++0xB line.long 0x0 "EICHD17_WORD0,Error Injection Channel Descriptor 17. Word0" hexmask.long.word 0x0 18.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD17_WORD1,Error Injection Channel Descriptor 17. Word1" hexmask.long.word 0x4 0.--11. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD17_WORD2,Error Injection Channel Descriptor 17. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x580++0x13 line.long 0x0 "EICHD18_WORD0,Error Injection Channel Descriptor 18. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD18_WORD1,Error Injection Channel Descriptor 18. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD18_WORD2,Error Injection Channel Descriptor 18. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD18_WORD3,Error Injection Channel Descriptor 18. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD18_WORD4,Error Injection Channel Descriptor 18. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x5C0++0x13 line.long 0x0 "EICHD19_WORD0,Error Injection Channel Descriptor 19. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD19_WORD1,Error Injection Channel Descriptor 19. Word1" hexmask.long.byte 0x4 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD19_WORD2,Error Injection Channel Descriptor 19. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD19_WORD3,Error Injection Channel Descriptor 19. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD19_WORD4,Error Injection Channel Descriptor 19. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x600++0x13 line.long 0x0 "EICHD20_WORD0,Error Injection Channel Descriptor 20. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD20_WORD1,Error Injection Channel Descriptor 20. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD20_WORD2,Error Injection Channel Descriptor 20. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD20_WORD3,Error Injection Channel Descriptor 20. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD20_WORD4,Error Injection Channel Descriptor 20. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x640++0x13 line.long 0x0 "EICHD21_WORD0,Error Injection Channel Descriptor 21. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD21_WORD1,Error Injection Channel Descriptor 21. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD21_WORD2,Error Injection Channel Descriptor 21. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD21_WORD3,Error Injection Channel Descriptor 21. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD21_WORD4,Error Injection Channel Descriptor 21. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x680++0xB line.long 0x0 "EICHD22_WORD0,Error Injection Channel Descriptor 22. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD22_WORD1,Error Injection Channel Descriptor 22. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD22_WORD2,Error Injection Channel Descriptor 22. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x6C0++0xB line.long 0x0 "EICHD23_WORD0,Error Injection Channel Descriptor 23. Word0" hexmask.long.word 0x0 18.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD23_WORD1,Error Injection Channel Descriptor 23. Word1" hexmask.long.word 0x4 0.--11. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD23_WORD2,Error Injection Channel Descriptor 23. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x700++0x13 line.long 0x0 "EICHD24_WORD0,Error Injection Channel Descriptor 24. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD24_WORD1,Error Injection Channel Descriptor 24. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD24_WORD2,Error Injection Channel Descriptor 24. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD24_WORD3,Error Injection Channel Descriptor 24. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD24_WORD4,Error Injection Channel Descriptor 24. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x740++0x13 line.long 0x0 "EICHD25_WORD0,Error Injection Channel Descriptor 25. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD25_WORD1,Error Injection Channel Descriptor 25. Word1" hexmask.long.byte 0x4 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD25_WORD2,Error Injection Channel Descriptor 25. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD25_WORD3,Error Injection Channel Descriptor 25. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD25_WORD4,Error Injection Channel Descriptor 25. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x780++0x13 line.long 0x0 "EICHD26_WORD0,Error Injection Channel Descriptor 26. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD26_WORD1,Error Injection Channel Descriptor 26. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD26_WORD2,Error Injection Channel Descriptor 26. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD26_WORD3,Error Injection Channel Descriptor 26. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD26_WORD4,Error Injection Channel Descriptor 26. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x7C0++0x13 line.long 0x0 "EICHD27_WORD0,Error Injection Channel Descriptor 27. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD27_WORD1,Error Injection Channel Descriptor 27. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD27_WORD2,Error Injection Channel Descriptor 27. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD27_WORD3,Error Injection Channel Descriptor 27. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD27_WORD4,Error Injection Channel Descriptor 27. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x804++0xB line.long 0x0 "EICHD28_WORD1,Error Injection Channel Descriptor 28. Word1" hexmask.long 0x0 0.--25. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD28_WORD2,Error Injection Channel Descriptor 28. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD28_WORD3,Error Injection Channel Descriptor 28. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x844++0x3 line.long 0x0 "EICHD29_WORD1,Error Injection Channel Descriptor 29. Word1" hexmask.long.tbyte 0x0 0.--19. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x884++0x3 line.long 0x0 "EICHD30_WORD1,Error Injection Channel Descriptor 30. Word1" hexmask.long.tbyte 0x0 0.--17. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree "EIM_0" base ad:0x40330000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x104++0x1F line.long 0x0 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD0_WORD3,Error Injection Channel Descriptor 0. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD0_WORD4,Error Injection Channel Descriptor 0. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD0_WORD5,Error Injection Channel Descriptor 0. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD0_WORD6,Error Injection Channel Descriptor 0. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD0_WORD7,Error Injection Channel Descriptor 0. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD0_WORD8,Error Injection Channel Descriptor 0. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" tree.end tree "EIM_1" base ad:0x40331000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x104++0x1F line.long 0x0 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD0_WORD3,Error Injection Channel Descriptor 0. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD0_WORD4,Error Injection Channel Descriptor 0. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD0_WORD5,Error Injection Channel Descriptor 0. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD0_WORD6,Error Injection Channel Descriptor 0. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD0_WORD7,Error Injection Channel Descriptor 0. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD0_WORD8,Error Injection Channel Descriptor 0. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x144++0x1F line.long 0x0 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD1_WORD3,Error Injection Channel Descriptor 1. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD1_WORD4,Error Injection Channel Descriptor 1. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD1_WORD5,Error Injection Channel Descriptor 1. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD1_WORD6,Error Injection Channel Descriptor 1. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD1_WORD7,Error Injection Channel Descriptor 1. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD1_WORD8,Error Injection Channel Descriptor 1. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x184++0x1F line.long 0x0 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD2_WORD3,Error Injection Channel Descriptor 2. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD2_WORD4,Error Injection Channel Descriptor 2. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD2_WORD5,Error Injection Channel Descriptor 2. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD2_WORD6,Error Injection Channel Descriptor 2. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD2_WORD7,Error Injection Channel Descriptor 2. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD2_WORD8,Error Injection Channel Descriptor 2. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x1C4++0x1F line.long 0x0 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD3_WORD3,Error Injection Channel Descriptor 3. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD3_WORD4,Error Injection Channel Descriptor 3. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD3_WORD5,Error Injection Channel Descriptor 3. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD3_WORD6,Error Injection Channel Descriptor 3. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD3_WORD7,Error Injection Channel Descriptor 3. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD3_WORD8,Error Injection Channel Descriptor 3. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x204++0x1F line.long 0x0 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD4_WORD3,Error Injection Channel Descriptor 4. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD4_WORD4,Error Injection Channel Descriptor 4. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD4_WORD5,Error Injection Channel Descriptor 4. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD4_WORD6,Error Injection Channel Descriptor 4. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD4_WORD7,Error Injection Channel Descriptor 4. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD4_WORD8,Error Injection Channel Descriptor 4. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x244++0x1F line.long 0x0 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD5_WORD2,Error Injection Channel Descriptor 5. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD5_WORD3,Error Injection Channel Descriptor 5. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD5_WORD4,Error Injection Channel Descriptor 5. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD5_WORD5,Error Injection Channel Descriptor 5. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD5_WORD6,Error Injection Channel Descriptor 5. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD5_WORD7,Error Injection Channel Descriptor 5. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD5_WORD8,Error Injection Channel Descriptor 5. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x284++0x1F line.long 0x0 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD6_WORD2,Error Injection Channel Descriptor 6. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD6_WORD3,Error Injection Channel Descriptor 6. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD6_WORD4,Error Injection Channel Descriptor 6. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD6_WORD5,Error Injection Channel Descriptor 6. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD6_WORD6,Error Injection Channel Descriptor 6. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD6_WORD7,Error Injection Channel Descriptor 6. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD6_WORD8,Error Injection Channel Descriptor 6. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x2C4++0x1F line.long 0x0 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD7_WORD2,Error Injection Channel Descriptor 7. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD7_WORD3,Error Injection Channel Descriptor 7. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD7_WORD4,Error Injection Channel Descriptor 7. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD7_WORD5,Error Injection Channel Descriptor 7. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD7_WORD6,Error Injection Channel Descriptor 7. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD7_WORD7,Error Injection Channel Descriptor 7. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD7_WORD8,Error Injection Channel Descriptor 7. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x304++0x1F line.long 0x0 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD8_WORD3,Error Injection Channel Descriptor 8. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD8_WORD4,Error Injection Channel Descriptor 8. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD8_WORD5,Error Injection Channel Descriptor 8. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD8_WORD6,Error Injection Channel Descriptor 8. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD8_WORD7,Error Injection Channel Descriptor 8. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD8_WORD8,Error Injection Channel Descriptor 8. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x344++0x1F line.long 0x0 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD9_WORD2,Error Injection Channel Descriptor 9. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD9_WORD3,Error Injection Channel Descriptor 9. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD9_WORD4,Error Injection Channel Descriptor 9. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD9_WORD5,Error Injection Channel Descriptor 9. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD9_WORD6,Error Injection Channel Descriptor 9. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD9_WORD7,Error Injection Channel Descriptor 9. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD9_WORD8,Error Injection Channel Descriptor 9. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x384++0x1F line.long 0x0 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD10_WORD2,Error Injection Channel Descriptor 10. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD10_WORD3,Error Injection Channel Descriptor 10. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD10_WORD4,Error Injection Channel Descriptor 10. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD10_WORD5,Error Injection Channel Descriptor 10. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD10_WORD6,Error Injection Channel Descriptor 10. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD10_WORD7,Error Injection Channel Descriptor 10. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD10_WORD8,Error Injection Channel Descriptor 10. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x3C4++0x1F line.long 0x0 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD11_WORD2,Error Injection Channel Descriptor 11. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD11_WORD3,Error Injection Channel Descriptor 11. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD11_WORD4,Error Injection Channel Descriptor 11. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD11_WORD5,Error Injection Channel Descriptor 11. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD11_WORD6,Error Injection Channel Descriptor 11. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD11_WORD7,Error Injection Channel Descriptor 11. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD11_WORD8,Error Injection Channel Descriptor 11. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x404++0x1F line.long 0x0 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD12_WORD2,Error Injection Channel Descriptor 12. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD12_WORD3,Error Injection Channel Descriptor 12. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD12_WORD4,Error Injection Channel Descriptor 12. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD12_WORD5,Error Injection Channel Descriptor 12. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD12_WORD6,Error Injection Channel Descriptor 12. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD12_WORD7,Error Injection Channel Descriptor 12. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD12_WORD8,Error Injection Channel Descriptor 12. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x444++0x1F line.long 0x0 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD13_WORD3,Error Injection Channel Descriptor 13. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD13_WORD4,Error Injection Channel Descriptor 13. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD13_WORD5,Error Injection Channel Descriptor 13. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD13_WORD6,Error Injection Channel Descriptor 13. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD13_WORD7,Error Injection Channel Descriptor 13. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD13_WORD8,Error Injection Channel Descriptor 13. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x484++0x1F line.long 0x0 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD14_WORD2,Error Injection Channel Descriptor 14. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD14_WORD3,Error Injection Channel Descriptor 14. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD14_WORD4,Error Injection Channel Descriptor 14. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD14_WORD5,Error Injection Channel Descriptor 14. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD14_WORD6,Error Injection Channel Descriptor 14. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD14_WORD7,Error Injection Channel Descriptor 14. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD14_WORD8,Error Injection Channel Descriptor 14. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" tree.end tree "EIM_2" base ad:0x40332000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x104++0x1F line.long 0x0 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD0_WORD3,Error Injection Channel Descriptor 0. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD0_WORD4,Error Injection Channel Descriptor 0. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD0_WORD5,Error Injection Channel Descriptor 0. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD0_WORD6,Error Injection Channel Descriptor 0. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD0_WORD7,Error Injection Channel Descriptor 0. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD0_WORD8,Error Injection Channel Descriptor 0. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x144++0x1F line.long 0x0 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD1_WORD3,Error Injection Channel Descriptor 1. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD1_WORD4,Error Injection Channel Descriptor 1. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD1_WORD5,Error Injection Channel Descriptor 1. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD1_WORD6,Error Injection Channel Descriptor 1. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD1_WORD7,Error Injection Channel Descriptor 1. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD1_WORD8,Error Injection Channel Descriptor 1. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x184++0x1F line.long 0x0 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD2_WORD3,Error Injection Channel Descriptor 2. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD2_WORD4,Error Injection Channel Descriptor 2. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD2_WORD5,Error Injection Channel Descriptor 2. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD2_WORD6,Error Injection Channel Descriptor 2. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD2_WORD7,Error Injection Channel Descriptor 2. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD2_WORD8,Error Injection Channel Descriptor 2. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x1C4++0x1F line.long 0x0 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD3_WORD3,Error Injection Channel Descriptor 3. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD3_WORD4,Error Injection Channel Descriptor 3. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD3_WORD5,Error Injection Channel Descriptor 3. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD3_WORD6,Error Injection Channel Descriptor 3. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD3_WORD7,Error Injection Channel Descriptor 3. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD3_WORD8,Error Injection Channel Descriptor 3. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x204++0x1F line.long 0x0 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD4_WORD3,Error Injection Channel Descriptor 4. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD4_WORD4,Error Injection Channel Descriptor 4. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD4_WORD5,Error Injection Channel Descriptor 4. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD4_WORD6,Error Injection Channel Descriptor 4. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD4_WORD7,Error Injection Channel Descriptor 4. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD4_WORD8,Error Injection Channel Descriptor 4. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x244++0x1F line.long 0x0 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD5_WORD2,Error Injection Channel Descriptor 5. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD5_WORD3,Error Injection Channel Descriptor 5. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD5_WORD4,Error Injection Channel Descriptor 5. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD5_WORD5,Error Injection Channel Descriptor 5. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD5_WORD6,Error Injection Channel Descriptor 5. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD5_WORD7,Error Injection Channel Descriptor 5. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD5_WORD8,Error Injection Channel Descriptor 5. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" tree.end tree "EIM_3" base ad:0x40333000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x104++0x1F line.long 0x0 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD0_WORD3,Error Injection Channel Descriptor 0. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD0_WORD4,Error Injection Channel Descriptor 0. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD0_WORD5,Error Injection Channel Descriptor 0. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD0_WORD6,Error Injection Channel Descriptor 0. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD0_WORD7,Error Injection Channel Descriptor 0. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD0_WORD8,Error Injection Channel Descriptor 0. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x144++0x1F line.long 0x0 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD1_WORD3,Error Injection Channel Descriptor 1. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD1_WORD4,Error Injection Channel Descriptor 1. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD1_WORD5,Error Injection Channel Descriptor 1. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD1_WORD6,Error Injection Channel Descriptor 1. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD1_WORD7,Error Injection Channel Descriptor 1. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD1_WORD8,Error Injection Channel Descriptor 1. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x184++0x1F line.long 0x0 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD2_WORD3,Error Injection Channel Descriptor 2. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD2_WORD4,Error Injection Channel Descriptor 2. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD2_WORD5,Error Injection Channel Descriptor 2. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD2_WORD6,Error Injection Channel Descriptor 2. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD2_WORD7,Error Injection Channel Descriptor 2. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD2_WORD8,Error Injection Channel Descriptor 2. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x1C4++0x1F line.long 0x0 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD3_WORD3,Error Injection Channel Descriptor 3. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD3_WORD4,Error Injection Channel Descriptor 3. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD3_WORD5,Error Injection Channel Descriptor 3. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD3_WORD6,Error Injection Channel Descriptor 3. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x18 "EICHD3_WORD7,Error Injection Channel Descriptor 3. Word7" hexmask.long 0x18 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x1C "EICHD3_WORD8,Error Injection Channel Descriptor 3. Word8" hexmask.long 0x1C 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" tree.end tree "EIM_LLCE (EIM)" base ad:0x44050000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0x7 line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x140++0x7 line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x1C0++0x7 line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x200++0x7 line.long 0x0 "EICHD4_WORD0,Error Injection Channel Descriptor 4. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x240++0x7 line.long 0x0 "EICHD5_WORD0,Error Injection Channel Descriptor 5. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x280++0x7 line.long 0x0 "EICHD6_WORD0,Error Injection Channel Descriptor 6. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree "EIM_MISC" base ad:0x4404C000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x104++0xB line.long 0x0 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD0_WORD3,Error Injection Channel Descriptor 0. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x144++0xB line.long 0x0 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD1_WORD3,Error Injection Channel Descriptor 1. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x184++0xF line.long 0x0 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD2_WORD3,Error Injection Channel Descriptor 2. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD2_WORD4,Error Injection Channel Descriptor 2. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x1C4++0xF line.long 0x0 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD3_WORD3,Error Injection Channel Descriptor 3. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD3_WORD4,Error Injection Channel Descriptor 3. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x204++0xF line.long 0x0 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD4_WORD3,Error Injection Channel Descriptor 4. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD4_WORD4,Error Injection Channel Descriptor 4. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x244++0x7 line.long 0x0 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long.byte 0x0 0.--6. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD5_WORD2,Error Injection Channel Descriptor 5. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x284++0xB line.long 0x0 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long.tbyte 0x0 0.--22. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD6_WORD2,Error Injection Channel Descriptor 6. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD6_WORD3,Error Injection Channel Descriptor 6. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x2C4++0xB line.long 0x0 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD7_WORD2,Error Injection Channel Descriptor 7. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD7_WORD3,Error Injection Channel Descriptor 7. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x304++0xB line.long 0x0 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x0 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD8_WORD3,Error Injection Channel Descriptor 8. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x344++0x7 line.long 0x0 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long.word 0x0 0.--13. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD9_WORD2,Error Injection Channel Descriptor 9. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x384++0xB line.long 0x0 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long.tbyte 0x0 0.--21. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD10_WORD2,Error Injection Channel Descriptor 10. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD10_WORD3,Error Injection Channel Descriptor 10. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x3C4++0xB line.long 0x0 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long.tbyte 0x0 0.--21. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD11_WORD2,Error Injection Channel Descriptor 11. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD11_WORD3,Error Injection Channel Descriptor 11. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x404++0xB line.long 0x0 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long.tbyte 0x0 0.--23. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD12_WORD2,Error Injection Channel Descriptor 12. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD12_WORD3,Error Injection Channel Descriptor 12. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x444++0xB line.long 0x0 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long.tbyte 0x0 0.--21. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD13_WORD3,Error Injection Channel Descriptor 13. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x484++0xB line.long 0x0 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long.tbyte 0x0 0.--21. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD14_WORD2,Error Injection Channel Descriptor 14. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD14_WORD3,Error Injection Channel Descriptor 14. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" group.long 0x4C4++0x7 line.long 0x0 "EICHD15_WORD1,Error Injection Channel Descriptor 15. Word1" hexmask.long.word 0x0 0.--14. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD15_WORD2,Error Injection Channel Descriptor 15. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x504++0x3 line.long 0x0 "EICHD16_WORD1,Error Injection Channel Descriptor 16. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree "EIM_PFE0" base ad:0x44054000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 14. "EICH17EN,Error Injection Channel 17 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 13. "EICH18EN,Error Injection Channel 18 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 12. "EICH19EN,Error Injection Channel 19 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 11. "EICH20EN,Error Injection Channel 20 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 10. "EICH21EN,Error Injection Channel 21 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 9. "EICH22EN,Error Injection Channel 22 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 8. "EICH23EN,Error Injection Channel 23 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 7. "EICH24EN,Error Injection Channel 24 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 6. "EICH25EN,Error Injection Channel 25 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 5. "EICH26EN,Error Injection Channel 26 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 4. "EICH27EN,Error Injection Channel 27 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 3. "EICH28EN,Error Injection Channel 28 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 2. "EICH29EN,Error Injection Channel 29 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 1. "EICH30EN,Error Injection Channel 30 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 0. "EICH31EN,Error Injection Channel 31 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0x7 line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x140++0xB line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x180++0x13 line.long 0x0 "EICHD2_WORD0,Error Injection Channel Descriptor 2. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long 0x4 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD2_WORD3,Error Injection Channel Descriptor 2. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD2_WORD4,Error Injection Channel Descriptor 2. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x1C0++0xB line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long 0x0 2.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x200++0x7 line.long 0x0 "EICHD4_WORD0,Error Injection Channel Descriptor 4. Word0" hexmask.long.word 0x0 22.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x240++0x7 line.long 0x0 "EICHD5_WORD0,Error Injection Channel Descriptor 5. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x280++0x7 line.long 0x0 "EICHD6_WORD0,Error Injection Channel Descriptor 6. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x2C0++0x7 line.long 0x0 "EICHD7_WORD0,Error Injection Channel Descriptor 7. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x300++0xB line.long 0x0 "EICHD8_WORD0,Error Injection Channel Descriptor 8. Word0" hexmask.long 0x0 2.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x340++0x7 line.long 0x0 "EICHD9_WORD0,Error Injection Channel Descriptor 9. Word0" hexmask.long.word 0x0 22.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x380++0x7 line.long 0x0 "EICHD10_WORD0,Error Injection Channel Descriptor 10. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x3C0++0x7 line.long 0x0 "EICHD11_WORD0,Error Injection Channel Descriptor 11. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x400++0x7 line.long 0x0 "EICHD12_WORD0,Error Injection Channel Descriptor 12. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x440++0xB line.long 0x0 "EICHD13_WORD0,Error Injection Channel Descriptor 13. Word0" hexmask.long 0x0 2.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x480++0x7 line.long 0x0 "EICHD14_WORD0,Error Injection Channel Descriptor 14. Word0" hexmask.long.word 0x0 22.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x4C0++0x7 line.long 0x0 "EICHD15_WORD0,Error Injection Channel Descriptor 15. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD15_WORD1,Error Injection Channel Descriptor 15. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x500++0x7 line.long 0x0 "EICHD16_WORD0,Error Injection Channel Descriptor 16. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD16_WORD1,Error Injection Channel Descriptor 16. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x540++0x7 line.long 0x0 "EICHD17_WORD0,Error Injection Channel Descriptor 17. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD17_WORD1,Error Injection Channel Descriptor 17. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x580++0xB line.long 0x0 "EICHD18_WORD0,Error Injection Channel Descriptor 18. Word0" hexmask.long 0x0 2.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD18_WORD1,Error Injection Channel Descriptor 18. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD18_WORD2,Error Injection Channel Descriptor 18. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x5C0++0x7 line.long 0x0 "EICHD19_WORD0,Error Injection Channel Descriptor 19. Word0" hexmask.long.word 0x0 22.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD19_WORD1,Error Injection Channel Descriptor 19. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x600++0x7 line.long 0x0 "EICHD20_WORD0,Error Injection Channel Descriptor 20. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD20_WORD1,Error Injection Channel Descriptor 20. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x640++0x7 line.long 0x0 "EICHD21_WORD0,Error Injection Channel Descriptor 21. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD21_WORD1,Error Injection Channel Descriptor 21. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x680++0x7 line.long 0x0 "EICHD22_WORD0,Error Injection Channel Descriptor 22. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD22_WORD1,Error Injection Channel Descriptor 22. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x6C0++0xB line.long 0x0 "EICHD23_WORD0,Error Injection Channel Descriptor 23. Word0" hexmask.long 0x0 2.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD23_WORD1,Error Injection Channel Descriptor 23. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD23_WORD2,Error Injection Channel Descriptor 23. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x700++0x7 line.long 0x0 "EICHD24_WORD0,Error Injection Channel Descriptor 24. Word0" hexmask.long.word 0x0 22.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD24_WORD1,Error Injection Channel Descriptor 24. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x740++0x7 line.long 0x0 "EICHD25_WORD0,Error Injection Channel Descriptor 25. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD25_WORD1,Error Injection Channel Descriptor 25. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x780++0x7 line.long 0x0 "EICHD26_WORD0,Error Injection Channel Descriptor 26. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD26_WORD1,Error Injection Channel Descriptor 26. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x7C0++0x7 line.long 0x0 "EICHD27_WORD0,Error Injection Channel Descriptor 27. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD27_WORD1,Error Injection Channel Descriptor 27. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x800++0xB line.long 0x0 "EICHD28_WORD0,Error Injection Channel Descriptor 28. Word0" hexmask.long 0x0 2.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD28_WORD1,Error Injection Channel Descriptor 28. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD28_WORD2,Error Injection Channel Descriptor 28. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x840++0x7 line.long 0x0 "EICHD29_WORD0,Error Injection Channel Descriptor 29. Word0" hexmask.long.word 0x0 22.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD29_WORD1,Error Injection Channel Descriptor 29. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x880++0x7 line.long 0x0 "EICHD30_WORD0,Error Injection Channel Descriptor 30. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD30_WORD1,Error Injection Channel Descriptor 30. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x8C0++0x7 line.long 0x0 "EICHD31_WORD0,Error Injection Channel Descriptor 31. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD31_WORD1,Error Injection Channel Descriptor 31. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree "EIM_PFE1" base ad:0x44055000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0x7 line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x140++0xB line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long 0x0 2.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x180++0x7 line.long 0x0 "EICHD2_WORD0,Error Injection Channel Descriptor 2. Word0" hexmask.long.word 0x0 22.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x1C0++0x7 line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x200++0x7 line.long 0x0 "EICHD4_WORD0,Error Injection Channel Descriptor 4. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x240++0x7 line.long 0x0 "EICHD5_WORD0,Error Injection Channel Descriptor 5. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x280++0xB line.long 0x0 "EICHD6_WORD0,Error Injection Channel Descriptor 6. Word0" hexmask.long 0x0 2.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD6_WORD2,Error Injection Channel Descriptor 6. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x2C0++0x7 line.long 0x0 "EICHD7_WORD0,Error Injection Channel Descriptor 7. Word0" hexmask.long.word 0x0 22.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x300++0x7 line.long 0x0 "EICHD8_WORD0,Error Injection Channel Descriptor 8. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x340++0x7 line.long 0x0 "EICHD9_WORD0,Error Injection Channel Descriptor 9. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x380++0x7 line.long 0x0 "EICHD10_WORD0,Error Injection Channel Descriptor 10. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x3C0++0x7 line.long 0x0 "EICHD11_WORD0,Error Injection Channel Descriptor 11. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x400++0xB line.long 0x0 "EICHD12_WORD0,Error Injection Channel Descriptor 12. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD12_WORD2,Error Injection Channel Descriptor 12. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x440++0x13 line.long 0x0 "EICHD13_WORD0,Error Injection Channel Descriptor 13. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD13_WORD3,Error Injection Channel Descriptor 13. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD13_WORD4,Error Injection Channel Descriptor 13. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x480++0x13 line.long 0x0 "EICHD14_WORD0,Error Injection Channel Descriptor 14. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long.byte 0x4 0.--3. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD14_WORD2,Error Injection Channel Descriptor 14. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD14_WORD3,Error Injection Channel Descriptor 14. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD14_WORD4,Error Injection Channel Descriptor 14. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" tree.end tree "EIM_PFE2" base ad:0x44056000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 14. "EICH17EN,Error Injection Channel 17 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 13. "EICH18EN,Error Injection Channel 18 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 12. "EICH19EN,Error Injection Channel 19 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 11. "EICH20EN,Error Injection Channel 20 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 10. "EICH21EN,Error Injection Channel 21 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 9. "EICH22EN,Error Injection Channel 22 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 8. "EICH23EN,Error Injection Channel 23 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 7. "EICH24EN,Error Injection Channel 24 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 6. "EICH25EN,Error Injection Channel 25 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 5. "EICH26EN,Error Injection Channel 26 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 4. "EICH27EN,Error Injection Channel 27 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 3. "EICH28EN,Error Injection Channel 28 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 2. "EICH29EN,Error Injection Channel 29 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 1. "EICH30EN,Error Injection Channel 30 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 0. "EICH31EN,Error Injection Channel 31 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x104++0x3 line.long 0x0 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x144++0x3 line.long 0x0 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x184++0x3 line.long 0x0 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x1C4++0x3 line.long 0x0 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x204++0x3 line.long 0x0 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x244++0x3 line.long 0x0 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x284++0x3 line.long 0x0 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x2C4++0x3 line.long 0x0 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x304++0x3 line.long 0x0 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x344++0x3 line.long 0x0 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x384++0x3 line.long 0x0 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x3C4++0x3 line.long 0x0 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x404++0x3 line.long 0x0 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x444++0x3 line.long 0x0 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x484++0x3 line.long 0x0 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x4C4++0x3 line.long 0x0 "EICHD15_WORD1,Error Injection Channel Descriptor 15. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x500++0xB line.long 0x0 "EICHD16_WORD0,Error Injection Channel Descriptor 16. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD16_WORD1,Error Injection Channel Descriptor 16. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD16_WORD2,Error Injection Channel Descriptor 16. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x540++0xB line.long 0x0 "EICHD17_WORD0,Error Injection Channel Descriptor 17. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD17_WORD1,Error Injection Channel Descriptor 17. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD17_WORD2,Error Injection Channel Descriptor 17. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x580++0xB line.long 0x0 "EICHD18_WORD0,Error Injection Channel Descriptor 18. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD18_WORD1,Error Injection Channel Descriptor 18. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD18_WORD2,Error Injection Channel Descriptor 18. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x5C0++0xB line.long 0x0 "EICHD19_WORD0,Error Injection Channel Descriptor 19. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD19_WORD1,Error Injection Channel Descriptor 19. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD19_WORD2,Error Injection Channel Descriptor 19. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x600++0xB line.long 0x0 "EICHD20_WORD0,Error Injection Channel Descriptor 20. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD20_WORD1,Error Injection Channel Descriptor 20. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD20_WORD2,Error Injection Channel Descriptor 20. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x640++0xB line.long 0x0 "EICHD21_WORD0,Error Injection Channel Descriptor 21. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD21_WORD1,Error Injection Channel Descriptor 21. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD21_WORD2,Error Injection Channel Descriptor 21. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x680++0x23 line.long 0x0 "EICHD22_WORD0,Error Injection Channel Descriptor 22. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD22_WORD1,Error Injection Channel Descriptor 22. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD22_WORD2,Error Injection Channel Descriptor 22. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD22_WORD3,Error Injection Channel Descriptor 22. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD22_WORD4,Error Injection Channel Descriptor 22. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD22_WORD5,Error Injection Channel Descriptor 22. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD22_WORD6,Error Injection Channel Descriptor 22. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD22_WORD7,Error Injection Channel Descriptor 22. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD22_WORD8,Error Injection Channel Descriptor 22. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x6C0++0xB line.long 0x0 "EICHD23_WORD0,Error Injection Channel Descriptor 23. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD23_WORD1,Error Injection Channel Descriptor 23. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD23_WORD2,Error Injection Channel Descriptor 23. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x700++0xB line.long 0x0 "EICHD24_WORD0,Error Injection Channel Descriptor 24. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD24_WORD1,Error Injection Channel Descriptor 24. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD24_WORD2,Error Injection Channel Descriptor 24. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x740++0xB line.long 0x0 "EICHD25_WORD0,Error Injection Channel Descriptor 25. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD25_WORD1,Error Injection Channel Descriptor 25. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD25_WORD2,Error Injection Channel Descriptor 25. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x780++0xB line.long 0x0 "EICHD26_WORD0,Error Injection Channel Descriptor 26. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD26_WORD1,Error Injection Channel Descriptor 26. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD26_WORD2,Error Injection Channel Descriptor 26. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x7C0++0xB line.long 0x0 "EICHD27_WORD0,Error Injection Channel Descriptor 27. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD27_WORD1,Error Injection Channel Descriptor 27. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD27_WORD2,Error Injection Channel Descriptor 27. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x800++0xB line.long 0x0 "EICHD28_WORD0,Error Injection Channel Descriptor 28. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD28_WORD1,Error Injection Channel Descriptor 28. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD28_WORD2,Error Injection Channel Descriptor 28. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x840++0xB line.long 0x0 "EICHD29_WORD0,Error Injection Channel Descriptor 29. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD29_WORD1,Error Injection Channel Descriptor 29. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD29_WORD2,Error Injection Channel Descriptor 29. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x880++0xB line.long 0x0 "EICHD30_WORD0,Error Injection Channel Descriptor 30. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD30_WORD1,Error Injection Channel Descriptor 30. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD30_WORD2,Error Injection Channel Descriptor 30. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x8C0++0x7 line.long 0x0 "EICHD31_WORD0,Error Injection Channel Descriptor 31. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD31_WORD1,Error Injection Channel Descriptor 31. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree "EIM_PFE3" base ad:0x44057000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 14. "EICH17EN,Error Injection Channel 17 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 13. "EICH18EN,Error Injection Channel 18 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 12. "EICH19EN,Error Injection Channel 19 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 11. "EICH20EN,Error Injection Channel 20 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 10. "EICH21EN,Error Injection Channel 21 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 9. "EICH22EN,Error Injection Channel 22 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 8. "EICH23EN,Error Injection Channel 23 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 7. "EICH24EN,Error Injection Channel 24 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 6. "EICH25EN,Error Injection Channel 25 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 5. "EICH26EN,Error Injection Channel 26 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 4. "EICH27EN,Error Injection Channel 27 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 3. "EICH28EN,Error Injection Channel 28 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 2. "EICH29EN,Error Injection Channel 29 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 1. "EICH30EN,Error Injection Channel 30 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 0. "EICH31EN,Error Injection Channel 31 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0x23 line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD0_WORD3,Error Injection Channel Descriptor 0. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD0_WORD4,Error Injection Channel Descriptor 0. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD0_WORD5,Error Injection Channel Descriptor 0. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD0_WORD6,Error Injection Channel Descriptor 0. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD0_WORD7,Error Injection Channel Descriptor 0. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD0_WORD8,Error Injection Channel Descriptor 0. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x140++0xB line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x180++0xB line.long 0x0 "EICHD2_WORD0,Error Injection Channel Descriptor 2. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x1C0++0xB line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x200++0xB line.long 0x0 "EICHD4_WORD0,Error Injection Channel Descriptor 4. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x240++0xB line.long 0x0 "EICHD5_WORD0,Error Injection Channel Descriptor 5. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD5_WORD2,Error Injection Channel Descriptor 5. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x280++0xB line.long 0x0 "EICHD6_WORD0,Error Injection Channel Descriptor 6. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD6_WORD2,Error Injection Channel Descriptor 6. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x2C0++0xB line.long 0x0 "EICHD7_WORD0,Error Injection Channel Descriptor 7. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD7_WORD2,Error Injection Channel Descriptor 7. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x300++0xB line.long 0x0 "EICHD8_WORD0,Error Injection Channel Descriptor 8. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x340++0x7 line.long 0x0 "EICHD9_WORD0,Error Injection Channel Descriptor 9. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x380++0x23 line.long 0x0 "EICHD10_WORD0,Error Injection Channel Descriptor 10. Word0" hexmask.long 0x0 0.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD10_WORD2,Error Injection Channel Descriptor 10. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD10_WORD3,Error Injection Channel Descriptor 10. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD10_WORD4,Error Injection Channel Descriptor 10. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x14 "EICHD10_WORD5,Error Injection Channel Descriptor 10. Word5" hexmask.long 0x14 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x18 "EICHD10_WORD6,Error Injection Channel Descriptor 10. Word6" hexmask.long 0x18 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" line.long 0x1C "EICHD10_WORD7,Error Injection Channel Descriptor 10. Word7" hexmask.long 0x1C 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27" line.long 0x20 "EICHD10_WORD8,Error Injection Channel Descriptor 10. Word8" hexmask.long 0x20 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31" group.long 0x3C0++0xB line.long 0x0 "EICHD11_WORD0,Error Injection Channel Descriptor 11. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD11_WORD2,Error Injection Channel Descriptor 11. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x400++0xB line.long 0x0 "EICHD12_WORD0,Error Injection Channel Descriptor 12. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD12_WORD2,Error Injection Channel Descriptor 12. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x440++0xB line.long 0x0 "EICHD13_WORD0,Error Injection Channel Descriptor 13. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x480++0xB line.long 0x0 "EICHD14_WORD0,Error Injection Channel Descriptor 14. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD14_WORD2,Error Injection Channel Descriptor 14. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x4C0++0xB line.long 0x0 "EICHD15_WORD0,Error Injection Channel Descriptor 15. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD15_WORD1,Error Injection Channel Descriptor 15. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD15_WORD2,Error Injection Channel Descriptor 15. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x500++0xB line.long 0x0 "EICHD16_WORD0,Error Injection Channel Descriptor 16. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD16_WORD1,Error Injection Channel Descriptor 16. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD16_WORD2,Error Injection Channel Descriptor 16. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x540++0xB line.long 0x0 "EICHD17_WORD0,Error Injection Channel Descriptor 17. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD17_WORD1,Error Injection Channel Descriptor 17. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD17_WORD2,Error Injection Channel Descriptor 17. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x580++0xB line.long 0x0 "EICHD18_WORD0,Error Injection Channel Descriptor 18. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD18_WORD1,Error Injection Channel Descriptor 18. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD18_WORD2,Error Injection Channel Descriptor 18. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x5C0++0x7 line.long 0x0 "EICHD19_WORD0,Error Injection Channel Descriptor 19. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD19_WORD1,Error Injection Channel Descriptor 19. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x600++0xB line.long 0x0 "EICHD20_WORD0,Error Injection Channel Descriptor 20. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD20_WORD1,Error Injection Channel Descriptor 20. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD20_WORD2,Error Injection Channel Descriptor 20. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x640++0xB line.long 0x0 "EICHD21_WORD0,Error Injection Channel Descriptor 21. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD21_WORD1,Error Injection Channel Descriptor 21. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD21_WORD2,Error Injection Channel Descriptor 21. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x680++0xB line.long 0x0 "EICHD22_WORD0,Error Injection Channel Descriptor 22. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD22_WORD1,Error Injection Channel Descriptor 22. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD22_WORD2,Error Injection Channel Descriptor 22. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x6C0++0xB line.long 0x0 "EICHD23_WORD0,Error Injection Channel Descriptor 23. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD23_WORD1,Error Injection Channel Descriptor 23. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD23_WORD2,Error Injection Channel Descriptor 23. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x700++0xB line.long 0x0 "EICHD24_WORD0,Error Injection Channel Descriptor 24. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD24_WORD1,Error Injection Channel Descriptor 24. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD24_WORD2,Error Injection Channel Descriptor 24. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x740++0xB line.long 0x0 "EICHD25_WORD0,Error Injection Channel Descriptor 25. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD25_WORD1,Error Injection Channel Descriptor 25. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD25_WORD2,Error Injection Channel Descriptor 25. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x780++0xB line.long 0x0 "EICHD26_WORD0,Error Injection Channel Descriptor 26. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD26_WORD1,Error Injection Channel Descriptor 26. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD26_WORD2,Error Injection Channel Descriptor 26. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x7C0++0xB line.long 0x0 "EICHD27_WORD0,Error Injection Channel Descriptor 27. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD27_WORD1,Error Injection Channel Descriptor 27. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD27_WORD2,Error Injection Channel Descriptor 27. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x800++0xB line.long 0x0 "EICHD28_WORD0,Error Injection Channel Descriptor 28. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD28_WORD1,Error Injection Channel Descriptor 28. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD28_WORD2,Error Injection Channel Descriptor 28. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x840++0xB line.long 0x0 "EICHD29_WORD0,Error Injection Channel Descriptor 29. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD29_WORD1,Error Injection Channel Descriptor 29. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD29_WORD2,Error Injection Channel Descriptor 29. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x880++0xB line.long 0x0 "EICHD30_WORD0,Error Injection Channel Descriptor 30. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD30_WORD1,Error Injection Channel Descriptor 30. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD30_WORD2,Error Injection Channel Descriptor 30. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x8C0++0xB line.long 0x0 "EICHD31_WORD0,Error Injection Channel Descriptor 31. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD31_WORD1,Error Injection Channel Descriptor 31. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD31_WORD2,Error Injection Channel Descriptor 31. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" tree.end tree "EIM_PFE4" base ad:0x44058000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0xB line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x140++0x7 line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x180++0xB line.long 0x0 "EICHD2_WORD0,Error Injection Channel Descriptor 2. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x1C0++0xB line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x200++0xB line.long 0x0 "EICHD4_WORD0,Error Injection Channel Descriptor 4. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x240++0xB line.long 0x0 "EICHD5_WORD0,Error Injection Channel Descriptor 5. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD5_WORD2,Error Injection Channel Descriptor 5. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x280++0xB line.long 0x0 "EICHD6_WORD0,Error Injection Channel Descriptor 6. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD6_WORD2,Error Injection Channel Descriptor 6. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x2C0++0xB line.long 0x0 "EICHD7_WORD0,Error Injection Channel Descriptor 7. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD7_WORD2,Error Injection Channel Descriptor 7. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x300++0xB line.long 0x0 "EICHD8_WORD0,Error Injection Channel Descriptor 8. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x340++0xB line.long 0x0 "EICHD9_WORD0,Error Injection Channel Descriptor 9. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD9_WORD2,Error Injection Channel Descriptor 9. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" tree.end tree "EIM_PFE5" base ad:0x44059000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 14. "EICH17EN,Error Injection Channel 17 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 13. "EICH18EN,Error Injection Channel 18 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 12. "EICH19EN,Error Injection Channel 19 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 11. "EICH20EN,Error Injection Channel 20 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 10. "EICH21EN,Error Injection Channel 21 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 9. "EICH22EN,Error Injection Channel 22 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 8. "EICH23EN,Error Injection Channel 23 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 7. "EICH24EN,Error Injection Channel 24 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 6. "EICH25EN,Error Injection Channel 25 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 5. "EICH26EN,Error Injection Channel 26 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 4. "EICH27EN,Error Injection Channel 27 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 3. "EICH28EN,Error Injection Channel 28 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 2. "EICH29EN,Error Injection Channel 29 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 1. "EICH30EN,Error Injection Channel 30 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 0. "EICH31EN,Error Injection Channel 31 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x104++0x3 line.long 0x0 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x144++0x3 line.long 0x0 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x184++0x3 line.long 0x0 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x1C4++0x3 line.long 0x0 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x204++0x3 line.long 0x0 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x244++0x3 line.long 0x0 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x284++0x3 line.long 0x0 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x2C4++0x3 line.long 0x0 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x300++0xB line.long 0x0 "EICHD8_WORD0,Error Injection Channel Descriptor 8. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x340++0xB line.long 0x0 "EICHD9_WORD0,Error Injection Channel Descriptor 9. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD9_WORD2,Error Injection Channel Descriptor 9. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x380++0xB line.long 0x0 "EICHD10_WORD0,Error Injection Channel Descriptor 10. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD10_WORD2,Error Injection Channel Descriptor 10. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x3C0++0xB line.long 0x0 "EICHD11_WORD0,Error Injection Channel Descriptor 11. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD11_WORD2,Error Injection Channel Descriptor 11. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x400++0xB line.long 0x0 "EICHD12_WORD0,Error Injection Channel Descriptor 12. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD12_WORD2,Error Injection Channel Descriptor 12. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x440++0xB line.long 0x0 "EICHD13_WORD0,Error Injection Channel Descriptor 13. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x480++0x7 line.long 0x0 "EICHD14_WORD0,Error Injection Channel Descriptor 14. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x4C0++0xB line.long 0x0 "EICHD15_WORD0,Error Injection Channel Descriptor 15. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD15_WORD1,Error Injection Channel Descriptor 15. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD15_WORD2,Error Injection Channel Descriptor 15. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x500++0x7 line.long 0x0 "EICHD16_WORD0,Error Injection Channel Descriptor 16. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD16_WORD1,Error Injection Channel Descriptor 16. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x540++0xB line.long 0x0 "EICHD17_WORD0,Error Injection Channel Descriptor 17. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD17_WORD1,Error Injection Channel Descriptor 17. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD17_WORD2,Error Injection Channel Descriptor 17. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x580++0x7 line.long 0x0 "EICHD18_WORD0,Error Injection Channel Descriptor 18. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD18_WORD1,Error Injection Channel Descriptor 18. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x5C0++0xB line.long 0x0 "EICHD19_WORD0,Error Injection Channel Descriptor 19. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD19_WORD1,Error Injection Channel Descriptor 19. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD19_WORD2,Error Injection Channel Descriptor 19. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x600++0x7 line.long 0x0 "EICHD20_WORD0,Error Injection Channel Descriptor 20. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD20_WORD1,Error Injection Channel Descriptor 20. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x640++0xB line.long 0x0 "EICHD21_WORD0,Error Injection Channel Descriptor 21. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD21_WORD1,Error Injection Channel Descriptor 21. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD21_WORD2,Error Injection Channel Descriptor 21. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x680++0x7 line.long 0x0 "EICHD22_WORD0,Error Injection Channel Descriptor 22. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD22_WORD1,Error Injection Channel Descriptor 22. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x6C0++0xB line.long 0x0 "EICHD23_WORD0,Error Injection Channel Descriptor 23. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD23_WORD1,Error Injection Channel Descriptor 23. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD23_WORD2,Error Injection Channel Descriptor 23. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x700++0x7 line.long 0x0 "EICHD24_WORD0,Error Injection Channel Descriptor 24. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD24_WORD1,Error Injection Channel Descriptor 24. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x740++0x13 line.long 0x0 "EICHD25_WORD0,Error Injection Channel Descriptor 25. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD25_WORD1,Error Injection Channel Descriptor 25. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD25_WORD2,Error Injection Channel Descriptor 25. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD25_WORD3,Error Injection Channel Descriptor 25. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD25_WORD4,Error Injection Channel Descriptor 25. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x780++0xB line.long 0x0 "EICHD26_WORD0,Error Injection Channel Descriptor 26. Word0" hexmask.long.word 0x0 18.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD26_WORD1,Error Injection Channel Descriptor 26. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD26_WORD2,Error Injection Channel Descriptor 26. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x7C0++0xB line.long 0x0 "EICHD27_WORD0,Error Injection Channel Descriptor 27. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD27_WORD1,Error Injection Channel Descriptor 27. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD27_WORD2,Error Injection Channel Descriptor 27. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x800++0xB line.long 0x0 "EICHD28_WORD0,Error Injection Channel Descriptor 28. Word0" hexmask.long 0x0 2.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD28_WORD1,Error Injection Channel Descriptor 28. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD28_WORD2,Error Injection Channel Descriptor 28. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x840++0x7 line.long 0x0 "EICHD29_WORD0,Error Injection Channel Descriptor 29. Word0" hexmask.long.word 0x0 22.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD29_WORD1,Error Injection Channel Descriptor 29. Word1" hexmask.long.word 0x4 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x880++0x7 line.long 0x0 "EICHD30_WORD0,Error Injection Channel Descriptor 30. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD30_WORD1,Error Injection Channel Descriptor 30. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x8C0++0x7 line.long 0x0 "EICHD31_WORD0,Error Injection Channel Descriptor 31. Word0" hexmask.long.tbyte 0x0 12.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD31_WORD1,Error Injection Channel Descriptor 31. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree "EIM_PFE6" base ad:0x4405A000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0x7 line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x140++0x7 line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long.byte 0x0 25.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree.end tree "ERM (Error Reporting Module)" base ad:0x0 tree "ERM_CPU0" base ad:0x40318000 group.long 0x0++0x3 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." group.long 0x10++0x3 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_CPU1" base ad:0x40318400 group.long 0x0++0x3 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." group.long 0x10++0x3 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_CPU2" base ad:0x40318800 group.long 0x0++0x3 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." group.long 0x10++0x3 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_EDMA0" base ad:0x40314400 group.long 0x0++0x3 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." group.long 0x10++0x3 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_EDMA1" base ad:0x40314800 group.long 0x0++0x3 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." group.long 0x10++0x3 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_LLCE (ERM)" base ad:0x44030000 group.long 0x0++0x7 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." group.long 0x10++0x7 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PER" base ad:0x40314000 group.long 0x0++0x7 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." group.long 0x10++0x7 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." rgroup.long 0x100++0x3 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x3 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x3 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x3 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x3 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x3 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE0" base ad:0x44034000 group.long 0x0++0x7 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." group.long 0x10++0x7 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE1" base ad:0x44035000 group.long 0x0++0x7 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." group.long 0x10++0x7 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE2" base ad:0x44036000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE3" base ad:0x44037000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE4" base ad:0x44038000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE5" base ad:0x44039000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE6" base ad:0x4403A000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE7" base ad:0x4403B000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE8" base ad:0x4403C000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE9" base ad:0x4403D000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE10" base ad:0x4403E000 group.long 0x0++0x7 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." group.long 0x10++0x7 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE11" base ad:0x4403F000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." newline bitfld.long 0x8 27. "ESCIE17,ESCIE17" "0: Interrupt notification of Memory 17 single-bit..,1: Interrupt notification of Memory 17 single-bit.." bitfld.long 0x8 26. "ENCIE17,ENCIE17" "0: Interrupt notification of Memory 17..,1: Interrupt notification of Memory 17.." newline bitfld.long 0x8 23. "ESCIE18,ESCIE18" "0: Interrupt notification of Memory 18 single-bit..,1: Interrupt notification of Memory 18 single-bit.." bitfld.long 0x8 22. "ENCIE18,ENCIE18" "0: Interrupt notification of Memory 18..,1: Interrupt notification of Memory 18.." newline bitfld.long 0x8 19. "ESCIE19,ESCIE19" "0: Interrupt notification of Memory 19 single-bit..,1: Interrupt notification of Memory 19 single-bit.." bitfld.long 0x8 18. "ENCIE19,ENCIE19" "0: Interrupt notification of Memory 19..,1: Interrupt notification of Memory 19.." newline bitfld.long 0x8 15. "ESCIE20,ESCIE20" "0: Interrupt notification of Memory 20 single-bit..,1: Interrupt notification of Memory 20 single-bit.." bitfld.long 0x8 14. "ENCIE20,ENCIE20" "0: Interrupt notification of Memory 20..,1: Interrupt notification of Memory 20.." newline bitfld.long 0x8 11. "ESCIE21,ESCIE21" "0: Interrupt notification of Memory 21 single-bit..,1: Interrupt notification of Memory 21 single-bit.." bitfld.long 0x8 10. "ENCIE21,ENCIE21" "0: Interrupt notification of Memory 21..,1: Interrupt notification of Memory 21.." newline bitfld.long 0x8 7. "ESCIE22,ESCIE22" "0: Interrupt notification of Memory 22 single-bit..,1: Interrupt notification of Memory 22 single-bit.." bitfld.long 0x8 6. "ENCIE22,ENCIE22" "0: Interrupt notification of Memory 22..,1: Interrupt notification of Memory 22.." newline bitfld.long 0x8 3. "ESCIE23,ESCIE23" "0: Interrupt notification of Memory 23 single-bit..,1: Interrupt notification of Memory 23 single-bit.." bitfld.long 0x8 2. "ENCIE23,ENCIE23" "0: Interrupt notification of Memory 23..,1: Interrupt notification of Memory 23.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." newline eventfld.long 0x8 27. "SBC17,SBC17" "0: No single-bit correction event on Memory 17..,1: Single-bit correction event on Memory 17 detected." eventfld.long 0x8 26. "NCE17,NCE17" "0: No non-correctable error event on Memory 17..,1: Non-correctable error event on Memory 17 detected." newline eventfld.long 0x8 23. "SBC18,SBC18" "0: No single-bit correction event on Memory 18..,1: Single-bit correction event on Memory 18 detected." eventfld.long 0x8 22. "NCE18,NCE18" "0: No non-correctable error event on Memory 18..,1: Non-correctable error event on Memory 18 detected." newline eventfld.long 0x8 19. "SBC19,SBC19" "0: No single-bit correction event on Memory 19..,1: Single-bit correction event on Memory 19 detected." eventfld.long 0x8 18. "NCE19,NCE19" "0: No non-correctable error event on Memory 19..,1: Non-correctable error event on Memory 19 detected." newline eventfld.long 0x8 15. "SBC20,SBC20" "0: No single-bit correction event on Memory 20..,1: Single-bit correction event on Memory 20 detected." eventfld.long 0x8 14. "NCE20,NCE20" "0: No non-correctable error event on Memory 20..,1: Non-correctable error event on Memory 20 detected." newline eventfld.long 0x8 11. "SBC21,SBC21" "0: No single-bit correction event on Memory 21..,1: Single-bit correction event on Memory 21 detected." eventfld.long 0x8 10. "NCE21,NCE21" "0: No non-correctable error event on Memory 21..,1: Non-correctable error event on Memory 21 detected." newline eventfld.long 0x8 7. "SBC22,SBC22" "0: No single-bit correction event on Memory 22..,1: Single-bit correction event on Memory 22 detected." eventfld.long 0x8 6. "NCE22,NCE22" "0: No non-correctable error event on Memory 22..,1: Non-correctable error event on Memory 22 detected." newline eventfld.long 0x8 3. "SBC23,SBC23" "0: No single-bit correction event on Memory 23..,1: Single-bit correction event on Memory 23 detected." eventfld.long 0x8 2. "NCE23,NCE23" "0: No non-correctable error event on Memory 23 has..,1: Non-correctable error event on Memory 23 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x210++0x7 line.long 0x0 "EAR17,ERM Memory 17 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN17,ERM Memory 17 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x218++0x3 line.long 0x0 "CORR_ERR_CNT17,ERM Memory 17 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x220++0x7 line.long 0x0 "EAR18,ERM Memory 18 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN18,ERM Memory 18 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x228++0x3 line.long 0x0 "CORR_ERR_CNT18,ERM Memory 18 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x230++0x7 line.long 0x0 "EAR19,ERM Memory 19 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN19,ERM Memory 19 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x238++0x3 line.long 0x0 "CORR_ERR_CNT19,ERM Memory 19 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x240++0x7 line.long 0x0 "EAR20,ERM Memory 20 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN20,ERM Memory 20 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x248++0x3 line.long 0x0 "CORR_ERR_CNT20,ERM Memory 20 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x250++0x7 line.long 0x0 "EAR21,ERM Memory 21 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN21,ERM Memory 21 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x258++0x3 line.long 0x0 "CORR_ERR_CNT21,ERM Memory 21 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x260++0x7 line.long 0x0 "EAR22,ERM Memory 22 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN22,ERM Memory 22 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x268++0x3 line.long 0x0 "CORR_ERR_CNT22,ERM Memory 22 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x270++0x7 line.long 0x0 "EAR23,ERM Memory 23 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN23,ERM Memory 23 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x278++0x3 line.long 0x0 "CORR_ERR_CNT23,ERM Memory 23 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE12" base ad:0x44040000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE13" base ad:0x44041000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." newline bitfld.long 0x8 27. "ESCIE17,ESCIE17" "0: Interrupt notification of Memory 17 single-bit..,1: Interrupt notification of Memory 17 single-bit.." bitfld.long 0x8 26. "ENCIE17,ENCIE17" "0: Interrupt notification of Memory 17..,1: Interrupt notification of Memory 17.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." newline eventfld.long 0x8 27. "SBC17,SBC17" "0: No single-bit correction event on Memory 17..,1: Single-bit correction event on Memory 17 detected." eventfld.long 0x8 26. "NCE17,NCE17" "0: No non-correctable error event on Memory 17..,1: Non-correctable error event on Memory 17 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x210++0x7 line.long 0x0 "EAR17,ERM Memory 17 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN17,ERM Memory 17 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x218++0x3 line.long 0x0 "CORR_ERR_CNT17,ERM Memory 17 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE14" base ad:0x44042000 group.long 0x0++0x7 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." group.long 0x10++0x7 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_PFE15" base ad:0x44043000 group.long 0x0++0x7 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." group.long 0x10++0x7 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x120++0x7 line.long 0x0 "EAR2,ERM Memory 2 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN2,ERM Memory 2 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x130++0x7 line.long 0x0 "EAR3,ERM Memory 3 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN3,ERM Memory 3 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x140++0x7 line.long 0x0 "EAR4,ERM Memory 4 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN4,ERM Memory 4 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x150++0x7 line.long 0x0 "EAR5,ERM Memory 5 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN5,ERM Memory 5 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x160++0x7 line.long 0x0 "EAR6,ERM Memory 6 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN6,ERM Memory 6 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x170++0x7 line.long 0x0 "EAR7,ERM Memory 7 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN7,ERM Memory 7 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x180++0x7 line.long 0x0 "EAR8,ERM Memory 8 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN8,ERM Memory 8 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x190++0x7 line.long 0x0 "EAR9,ERM Memory 9 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN9,ERM Memory 9 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_STDBY_SRAM" base ad:0x44044000 group.long 0x0++0x3 line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." group.long 0x10++0x3 line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree.end tree "FCCU (Fault Collection and Control Unit)" base ad:0x4030C000 group.long 0x0++0x3 line.long 0x0 "CTRL,Control" bitfld.long 0x0 9. "DEBUG,Debug Mode Enable" "0: Disabled,1: Enabled" newline rbitfld.long 0x0 6.--7. "OPS,Operation Status" "0: Idle,1: In progress,2: Aborted,3: Successful" newline hexmask.long.byte 0x0 0.--4. 1. "OPR,Operation Run" wgroup.long 0x4++0x3 line.long 0x0 "CTRLK,Control Key" hexmask.long 0x0 0.--31. 1. "CTRLK,Locked-Operation Control Key" group.long 0x8++0x3 line.long 0x0 "CFG,Configuration" bitfld.long 0x0 24. "FCCU_SET_AFTER_RESET,Fault-Output (EOUT) Activate" "0: Inactive (the EOUT signals are in a..,1: Active (the EOUT signals indicate FCCU's.." newline bitfld.long 0x0 22.--23. "FCCU_SET_CLEAR,Fault-Output (EOUT) Control" "0: Controlled by the FSM,1: Always low,2: Controlled by the FSM,3: High until a fault occurs on a channel.." newline bitfld.long 0x0 9. "PS,Fault-Output (EOUT) Polarity Selection" "0: For the faulty indication EOUT1 is high and..,1: For the faulty indication EOUT1 is low and EOUT0.." newline bitfld.long 0x0 6.--8. "FOM,Fault-Output (EOUT) Mode" "?,?,2: Bi-Stable,?,?,5: Test 0 (controlled by the EINOUT register; EOUT1..,6: Test 1 (controlled by the EINOUT register; EOUT1..,7: Test 2 (controlled by the EINOUT register; EOUT1.." group.long 0x1C++0xF line.long 0x0 "NCF_CFG0,Non-critical Fault Configuration" bitfld.long 0x0 31. "NCFC31,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 30. "NCFC30,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 29. "NCFC29,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 28. "NCFC28,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 27. "NCFC27,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 26. "NCFC26,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 25. "NCFC25,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 24. "NCFC24,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 23. "NCFC23,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 22. "NCFC22,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 21. "NCFC21,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 20. "NCFC20,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 19. "NCFC19,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 18. "NCFC18,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 17. "NCFC17,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 16. "NCFC16,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 15. "NCFC15,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 14. "NCFC14,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 13. "NCFC13,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 12. "NCFC12,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 11. "NCFC11,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 10. "NCFC10,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 9. "NCFC9,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 8. "NCFC8,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 7. "NCFC7,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 6. "NCFC6,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 5. "NCFC5,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 4. "NCFC4,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 3. "NCFC3,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 2. "NCFC2,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 1. "NCFC1,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 0. "NCFC0,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" line.long 0x4 "NCF_CFG1,Non-critical Fault Configuration" bitfld.long 0x4 31. "NCFC31,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 30. "NCFC30,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 29. "NCFC29,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 28. "NCFC28,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 27. "NCFC27,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 26. "NCFC26,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 25. "NCFC25,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 24. "NCFC24,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 23. "NCFC23,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 22. "NCFC22,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 21. "NCFC21,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 20. "NCFC20,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 19. "NCFC19,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 18. "NCFC18,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 17. "NCFC17,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 16. "NCFC16,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 15. "NCFC15,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 14. "NCFC14,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 13. "NCFC13,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 12. "NCFC12,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 11. "NCFC11,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 10. "NCFC10,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 9. "NCFC9,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 8. "NCFC8,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 7. "NCFC7,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 6. "NCFC6,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 5. "NCFC5,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 4. "NCFC4,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 3. "NCFC3,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 2. "NCFC2,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 1. "NCFC1,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x4 0. "NCFC0,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" line.long 0x8 "NCF_CFG2,Non-critical Fault Configuration" bitfld.long 0x8 31. "NCFC31,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 30. "NCFC30,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 29. "NCFC29,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 28. "NCFC28,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 27. "NCFC27,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 26. "NCFC26,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 25. "NCFC25,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 24. "NCFC24,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 23. "NCFC23,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 22. "NCFC22,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 21. "NCFC21,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 20. "NCFC20,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 19. "NCFC19,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 18. "NCFC18,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 17. "NCFC17,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 16. "NCFC16,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 15. "NCFC15,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 14. "NCFC14,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 13. "NCFC13,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 12. "NCFC12,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 11. "NCFC11,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 10. "NCFC10,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 9. "NCFC9,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 8. "NCFC8,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 7. "NCFC7,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 6. "NCFC6,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 5. "NCFC5,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 4. "NCFC4,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 3. "NCFC3,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 2. "NCFC2,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 1. "NCFC1,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x8 0. "NCFC0,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" line.long 0xC "NCF_CFG3,Non-critical Fault Configuration" bitfld.long 0xC 31. "NCFC31,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 30. "NCFC30,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 29. "NCFC29,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 28. "NCFC28,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 27. "NCFC27,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 26. "NCFC26,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 25. "NCFC25,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 24. "NCFC24,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 23. "NCFC23,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 22. "NCFC22,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 21. "NCFC21,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 20. "NCFC20,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 19. "NCFC19,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 18. "NCFC18,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 17. "NCFC17,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 16. "NCFC16,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 15. "NCFC15,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 14. "NCFC14,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 13. "NCFC13,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 12. "NCFC12,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 11. "NCFC11,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 10. "NCFC10,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 9. "NCFC9,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 8. "NCFC8,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 7. "NCFC7,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 6. "NCFC6,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 5. "NCFC5,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 4. "NCFC4,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 3. "NCFC3,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 2. "NCFC2,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 1. "NCFC1,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0xC 0. "NCFC0,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" group.long 0x4C++0x1F line.long 0x0 "NCFS_CFG0,Non-critical Fault-State Configuration" bitfld.long 0x0 30.--31. "NCFSC15,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 28.--29. "NCFSC14,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 26.--27. "NCFSC13,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 24.--25. "NCFSC12,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 22.--23. "NCFSC11,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 20.--21. "NCFSC10,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 18.--19. "NCFSC9,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 16.--17. "NCFSC8,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" line.long 0x4 "NCFS_CFG1,Non-critical Fault-State Configuration" bitfld.long 0x4 30.--31. "NCFSC15,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 28.--29. "NCFSC14,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 26.--27. "NCFSC13,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 24.--25. "NCFSC12,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 22.--23. "NCFSC11,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 20.--21. "NCFSC10,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 18.--19. "NCFSC9,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 16.--17. "NCFSC8,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x4 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" line.long 0x8 "NCFS_CFG2,Non-critical Fault-State Configuration" bitfld.long 0x8 30.--31. "NCFSC15,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 28.--29. "NCFSC14,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 26.--27. "NCFSC13,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 24.--25. "NCFSC12,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 22.--23. "NCFSC11,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 20.--21. "NCFSC10,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 18.--19. "NCFSC9,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 16.--17. "NCFSC8,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x8 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" line.long 0xC "NCFS_CFG3,Non-critical Fault-State Configuration" bitfld.long 0xC 30.--31. "NCFSC15,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 28.--29. "NCFSC14,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 26.--27. "NCFSC13,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 24.--25. "NCFSC12,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 22.--23. "NCFSC11,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 20.--21. "NCFSC10,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 18.--19. "NCFSC9,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 16.--17. "NCFSC8,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0xC 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" line.long 0x10 "NCFS_CFG4,Non-critical Fault-State Configuration" bitfld.long 0x10 30.--31. "NCFSC15,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 28.--29. "NCFSC14,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 26.--27. "NCFSC13,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 24.--25. "NCFSC12,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 22.--23. "NCFSC11,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 20.--21. "NCFSC10,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 18.--19. "NCFSC9,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 16.--17. "NCFSC8,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x10 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" line.long 0x14 "NCFS_CFG5,Non-critical Fault-State Configuration" bitfld.long 0x14 30.--31. "NCFSC15,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 28.--29. "NCFSC14,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 26.--27. "NCFSC13,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 24.--25. "NCFSC12,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 22.--23. "NCFSC11,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 20.--21. "NCFSC10,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 18.--19. "NCFSC9,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 16.--17. "NCFSC8,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x14 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" line.long 0x18 "NCFS_CFG6,Non-critical Fault-State Configuration" bitfld.long 0x18 30.--31. "NCFSC15,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 28.--29. "NCFSC14,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 26.--27. "NCFSC13,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 24.--25. "NCFSC12,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 22.--23. "NCFSC11,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 20.--21. "NCFSC10,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 18.--19. "NCFSC9,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 16.--17. "NCFSC8,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x18 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" line.long 0x1C "NCFS_CFG7,Non-critical Fault-State Configuration" bitfld.long 0x1C 30.--31. "NCFSC15,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 28.--29. "NCFSC14,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 26.--27. "NCFSC13,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 24.--25. "NCFSC12,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 22.--23. "NCFSC11,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 20.--21. "NCFSC10,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 18.--19. "NCFSC9,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 16.--17. "NCFSC8,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x1C 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "NCF_S[$1],Non-critical Fault Status" eventfld.long 0x0 31. "NCFS31,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 30. "NCFS30,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 29. "NCFS29,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 28. "NCFS28,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 27. "NCFS27,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 26. "NCFS26,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 25. "NCFS25,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 24. "NCFS24,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 23. "NCFS23,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 22. "NCFS22,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 21. "NCFS21,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 20. "NCFS20,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 19. "NCFS19,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 18. "NCFS18,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 17. "NCFS17,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 16. "NCFS16,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 15. "NCFS15,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 14. "NCFS14,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 13. "NCFS13,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 12. "NCFS12,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 11. "NCFS11,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 10. "NCFS10,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 9. "NCFS9,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 8. "NCFS8,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 7. "NCFS7,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 6. "NCFS6,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 5. "NCFS5,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 4. "NCFS4,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 3. "NCFS3,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 2. "NCFS2,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 1. "NCFS1,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 0. "NCFS0,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" repeat.end group.long 0x90++0x2F line.long 0x0 "NCFK,Non-critical Fault Key" hexmask.long 0x0 0.--31. 1. "NCFK,Non-critical Fault Key" line.long 0x4 "NCF_E0,Non-critical Fault Enable" bitfld.long 0x4 31. "NCFE31,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 30. "NCFE30,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 29. "NCFE29,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 28. "NCFE28,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 27. "NCFE27,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 26. "NCFE26,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 25. "NCFE25,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 24. "NCFE24,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "NCFE23,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 22. "NCFE22,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "NCFE21,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 20. "NCFE20,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "NCFE19,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 18. "NCFE18,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "NCFE17,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 16. "NCFE16,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 15. "NCFE15,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 14. "NCFE14,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 13. "NCFE13,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 12. "NCFE12,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 11. "NCFE11,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "NCFE10,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 9. "NCFE9,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 8. "NCFE8,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 7. "NCFE7,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 6. "NCFE6,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 5. "NCFE5,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 4. "NCFE4,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 3. "NCFE3,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 2. "NCFE2,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 1. "NCFE1,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 0. "NCFE0,Non-critical Fault Enable n" "0: Disabled,1: Enabled" line.long 0x8 "NCF_E1,Non-critical Fault Enable" bitfld.long 0x8 31. "NCFE31,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 30. "NCFE30,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 29. "NCFE29,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 28. "NCFE28,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 27. "NCFE27,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 26. "NCFE26,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 25. "NCFE25,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 24. "NCFE24,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 23. "NCFE23,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 22. "NCFE22,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 21. "NCFE21,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 20. "NCFE20,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 19. "NCFE19,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 18. "NCFE18,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "NCFE17,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 16. "NCFE16,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 15. "NCFE15,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 14. "NCFE14,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 13. "NCFE13,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 12. "NCFE12,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 11. "NCFE11,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 10. "NCFE10,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 9. "NCFE9,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 8. "NCFE8,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 7. "NCFE7,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 6. "NCFE6,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 5. "NCFE5,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 4. "NCFE4,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 3. "NCFE3,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 2. "NCFE2,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 1. "NCFE1,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x8 0. "NCFE0,Non-critical Fault Enable n" "0: Disabled,1: Enabled" line.long 0xC "NCF_E2,Non-critical Fault Enable" bitfld.long 0xC 31. "NCFE31,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 30. "NCFE30,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 29. "NCFE29,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 28. "NCFE28,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 27. "NCFE27,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 26. "NCFE26,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 25. "NCFE25,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 24. "NCFE24,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 23. "NCFE23,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 22. "NCFE22,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 21. "NCFE21,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 20. "NCFE20,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 19. "NCFE19,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 18. "NCFE18,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 17. "NCFE17,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 16. "NCFE16,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 15. "NCFE15,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 14. "NCFE14,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 13. "NCFE13,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 12. "NCFE12,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 11. "NCFE11,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 10. "NCFE10,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 9. "NCFE9,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 8. "NCFE8,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 7. "NCFE7,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 6. "NCFE6,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 5. "NCFE5,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 4. "NCFE4,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 3. "NCFE3,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 2. "NCFE2,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 1. "NCFE1,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0xC 0. "NCFE0,Non-critical Fault Enable n" "0: Disabled,1: Enabled" line.long 0x10 "NCF_E3,Non-critical Fault Enable" bitfld.long 0x10 31. "NCFE31,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 30. "NCFE30,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 29. "NCFE29,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 28. "NCFE28,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 27. "NCFE27,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 26. "NCFE26,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 25. "NCFE25,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 24. "NCFE24,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 23. "NCFE23,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 22. "NCFE22,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 21. "NCFE21,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 20. "NCFE20,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 19. "NCFE19,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 18. "NCFE18,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 17. "NCFE17,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 16. "NCFE16,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 15. "NCFE15,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 14. "NCFE14,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 13. "NCFE13,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 12. "NCFE12,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 11. "NCFE11,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 10. "NCFE10,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 9. "NCFE9,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 8. "NCFE8,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 7. "NCFE7,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 6. "NCFE6,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 5. "NCFE5,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 4. "NCFE4,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 3. "NCFE3,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 2. "NCFE2,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 1. "NCFE1,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x10 0. "NCFE0,Non-critical Fault Enable n" "0: Disabled,1: Enabled" line.long 0x14 "NCF_TOE0,Non-critical-Fault Alarm-State Timeout Enable" bitfld.long 0x14 31. "NCFTOE31,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 30. "NCFTOE30,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 29. "NCFTOE29,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 28. "NCFTOE28,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 27. "NCFTOE27,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 26. "NCFTOE26,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 25. "NCFTOE25,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 24. "NCFTOE24,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 23. "NCFTOE23,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 22. "NCFTOE22,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 21. "NCFTOE21,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 20. "NCFTOE20,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 19. "NCFTOE19,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 18. "NCFTOE18,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 17. "NCFTOE17,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 16. "NCFTOE16,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 15. "NCFTOE15,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 14. "NCFTOE14,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 13. "NCFTOE13,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 12. "NCFTOE12,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 11. "NCFTOE11,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 10. "NCFTOE10,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 9. "NCFTOE9,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 8. "NCFTOE8,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 7. "NCFTOE7,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 6. "NCFTOE6,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 5. "NCFTOE5,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 4. "NCFTOE4,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 3. "NCFTOE3,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 2. "NCFTOE2,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 1. "NCFTOE1,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x14 0. "NCFTOE0,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" line.long 0x18 "NCF_TOE1,Non-critical-Fault Alarm-State Timeout Enable" bitfld.long 0x18 31. "NCFTOE31,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 30. "NCFTOE30,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 29. "NCFTOE29,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 28. "NCFTOE28,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 27. "NCFTOE27,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 26. "NCFTOE26,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 25. "NCFTOE25,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 24. "NCFTOE24,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 23. "NCFTOE23,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 22. "NCFTOE22,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 21. "NCFTOE21,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 20. "NCFTOE20,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 19. "NCFTOE19,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 18. "NCFTOE18,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 17. "NCFTOE17,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 16. "NCFTOE16,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 15. "NCFTOE15,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 14. "NCFTOE14,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 13. "NCFTOE13,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 12. "NCFTOE12,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 11. "NCFTOE11,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 10. "NCFTOE10,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 9. "NCFTOE9,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 8. "NCFTOE8,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 7. "NCFTOE7,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 6. "NCFTOE6,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 5. "NCFTOE5,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 4. "NCFTOE4,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 3. "NCFTOE3,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 2. "NCFTOE2,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 1. "NCFTOE1,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x18 0. "NCFTOE0,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" line.long 0x1C "NCF_TOE2,Non-critical-Fault Alarm-State Timeout Enable" bitfld.long 0x1C 31. "NCFTOE31,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 30. "NCFTOE30,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 29. "NCFTOE29,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 28. "NCFTOE28,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 27. "NCFTOE27,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 26. "NCFTOE26,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 25. "NCFTOE25,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 24. "NCFTOE24,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 23. "NCFTOE23,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 22. "NCFTOE22,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 21. "NCFTOE21,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 20. "NCFTOE20,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 19. "NCFTOE19,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 18. "NCFTOE18,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 17. "NCFTOE17,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 16. "NCFTOE16,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 15. "NCFTOE15,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 14. "NCFTOE14,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 13. "NCFTOE13,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 12. "NCFTOE12,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 11. "NCFTOE11,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 10. "NCFTOE10,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 9. "NCFTOE9,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 8. "NCFTOE8,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 7. "NCFTOE7,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 6. "NCFTOE6,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 5. "NCFTOE5,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 4. "NCFTOE4,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 3. "NCFTOE3,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 2. "NCFTOE2,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 1. "NCFTOE1,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 0. "NCFTOE0,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" line.long 0x20 "NCF_TOE3,Non-critical-Fault Alarm-State Timeout Enable" bitfld.long 0x20 31. "NCFTOE31,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 30. "NCFTOE30,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 29. "NCFTOE29,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 28. "NCFTOE28,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 27. "NCFTOE27,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 26. "NCFTOE26,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 25. "NCFTOE25,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 24. "NCFTOE24,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 23. "NCFTOE23,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 22. "NCFTOE22,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 21. "NCFTOE21,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 20. "NCFTOE20,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 19. "NCFTOE19,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 18. "NCFTOE18,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 17. "NCFTOE17,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 16. "NCFTOE16,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 15. "NCFTOE15,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 14. "NCFTOE14,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 13. "NCFTOE13,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 12. "NCFTOE12,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 11. "NCFTOE11,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 10. "NCFTOE10,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 9. "NCFTOE9,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 8. "NCFTOE8,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 7. "NCFTOE7,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 6. "NCFTOE6,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 5. "NCFTOE5,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 4. "NCFTOE4,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 3. "NCFTOE3,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 2. "NCFTOE2,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 1. "NCFTOE1,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x20 0. "NCFTOE0,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" line.long 0x24 "NCF_TO,Non-critical-Fault Alarm-State Timeout Interval" hexmask.long 0x24 0.--31. 1. "TO,Non-critical-Fault Alarm-State Timeout Interval" line.long 0x28 "CFG_TO,Configuration-State Timeout Interval" bitfld.long 0x28 0.--2. "TO,Configuration-State Timeout Interval" "0,1,2,3,4,5,6,7" line.long 0x2C "EINOUT,IO Control" rbitfld.long 0x2C 5. "EIN1,Error Input 1" "0: Low,1: High" newline rbitfld.long 0x2C 4. "EIN0,Error Input 0" "0: Low,1: High" newline bitfld.long 0x2C 1. "EOUT1,EOUT1" "0: force EOUT[1] = 0,1: force EOUT[1] = 1" newline bitfld.long 0x2C 0. "EOUT0,EOUT0" "0: force EOUT[0] = 0,1: force EOUT[0] = 1" rgroup.long 0xC0++0x13 line.long 0x0 "STAT,Status" bitfld.long 0x0 4.--5. "PhysicErrorPin,EOUT Signal States" "0: EOUT1 is low; EOUT0 is low.,1: EOUT1 is low; EOUT0 is high.,2: EOUT1 is high; EOUT0 is low.,3: EOUT1 is high; EOUT0 is high." newline bitfld.long 0x0 3. "ESTAT,FCCU Faulty Condition" "0: Not in faulty condition (in non-faulty or..,1: In faulty condition" newline bitfld.long 0x0 0.--2. "STATUS,FCCU State" "0: NORMAL,1: CONFIG,2: ALARM,3: FAULT,?,?,?,?" line.long 0x4 "N2AF_STATUS,Normal-to-Alarm Freeze Status" hexmask.long.byte 0x4 0.--7. 1. "NAFS,Normal-to-Alarm Freeze Status" line.long 0x8 "A2FF_STATUS,Alarm-to-Fault Freeze Status" bitfld.long 0x8 8.--9. "AF_SRC,Alarm-to-Fault Source" "0: No Alarm-to-Fault-state fault,?,2: Non-critical fault,3: Multiple Alarm-to-Fault-state faults" newline hexmask.long.byte 0x8 0.--7. 1. "AFFS,Alarm-to-Fault Freeze Status" line.long 0xC "N2FF_STATUS,Normal-to-Fault Freeze Status" bitfld.long 0xC 8.--9. "NF_SRC,Normal-to-Fault Source" "0: No Normal-to-Fault-state fault,?,2: Non-critical fault,3: Multiple Normal-to-Fault-state faults" newline hexmask.long.byte 0xC 0.--7. 1. "NFFS,Normal-to-Fault Freeze Status" line.long 0x10 "F2AF_STATUS,Fault-to-Alarm Freeze Status" hexmask.long.word 0x10 0.--8. 1. "FAFS,Fault-to-Alarm Freeze Status" wgroup.long 0xDC++0x3 line.long 0x0 "NCFF,Non-critical Fault Fake" hexmask.long.byte 0x0 0.--6. 1. "FNCFC,FNCFC" group.long 0xE0++0x7 line.long 0x0 "IRQ_STAT,IRQ Status" rbitfld.long 0x0 2. "NMI_STAT,NMI Interrupt Status" "0: NMI interrupt is OFF,1: NMI interrupt is ON" newline rbitfld.long 0x0 1. "ALRM_STAT,Alarm Interrupt Status" "0: Alarm interrupt is OFF,1: Alarm interrupt is ON" newline eventfld.long 0x0 0. "CFG_TO_STAT,Configuration-State Timeout Status" "0: No configuration-stat timeout error,1: Configuration-state timeout error" line.long 0x4 "IRQ_EN,IRQ Enable" bitfld.long 0x4 0. "CFG_TO_IEN,Configuration-State Timeout Interrupt Enable" "0: Configuration-state timeout interrupt disabled,1: Configuration-state timeout interrupt enabled" wgroup.long 0xF0++0x7 line.long 0x0 "TRANS_LOCK,Transient Configuration Lock" hexmask.long.word 0x0 0.--8. 1. "TRANSKEY,Transient Configuration Lock" line.long 0x4 "PERMNT_LOCK,Permanent Configuration Lock" hexmask.long.word 0x4 0.--8. 1. "PERMNTKEY,Permanent Configuration Lock" group.long 0xF8++0x3 line.long 0x0 "DELTA_T,Delta T" hexmask.long.word 0x0 0.--13. 1. "DELTA_T,Minimum Fault-Output (EOUT) Timer Interval" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xFC)++0x3 line.long 0x0 "IRQ_ALARM_EN[$1],Non-critical Alarm-State Interrupt-Request Enable" bitfld.long 0x0 31. "IRQEN31,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "IRQEN30,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "IRQEN29,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "IRQEN28,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "IRQEN27,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "IRQEN26,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "IRQEN25,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "IRQEN24,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "IRQEN23,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "IRQEN22,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "IRQEN21,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "IRQEN20,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "IRQEN19,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "IRQEN18,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "IRQEN17,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "IRQEN16,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "IRQEN15,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "IRQEN14,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "IRQEN13,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "IRQEN12,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "IRQEN11,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "IRQEN10,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IRQEN9,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "IRQEN8,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IRQEN7,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IRQEN6,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IRQEN5,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "IRQEN4,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IRQEN3,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IRQEN2,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IRQEN1,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "IRQEN0,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10C)++0x3 line.long 0x0 "NMI_EN[$1],Non-critical Fault-State Non-maskable-Interrupt-Request Enable" bitfld.long 0x0 31. "NMIEN31,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "NMIEN30,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "NMIEN29,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "NMIEN28,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "NMIEN27,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "NMIEN26,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "NMIEN25,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "NMIEN24,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "NMIEN23,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "NMIEN22,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "NMIEN21,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "NMIEN20,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "NMIEN19,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "NMIEN18,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "NMIEN17,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "NMIEN16,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "NMIEN15,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "NMIEN14,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "NMIEN13,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "NMIEN12,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "NMIEN11,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "NMIEN10,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "NMIEN9,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "NMIEN8,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "NMIEN7,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "NMIEN6,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "NMIEN5,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "NMIEN4,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "NMIEN3,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "NMIEN2,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "NMIEN1,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "NMIEN0,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x11C)++0x3 line.long 0x0 "EOUT_SIG_EN[$1],Non-critical Fault-State EOUT Signaling Enable" bitfld.long 0x0 31. "EOUTEN31,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 30. "EOUTEN30,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 29. "EOUTEN29,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 28. "EOUTEN28,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 27. "EOUTEN27,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 26. "EOUTEN26,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 25. "EOUTEN25,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 24. "EOUTEN24,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 23. "EOUTEN23,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 22. "EOUTEN22,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 21. "EOUTEN21,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 20. "EOUTEN20,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 19. "EOUTEN19,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 18. "EOUTEN18,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 17. "EOUTEN17,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 16. "EOUTEN16,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 15. "EOUTEN15,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 14. "EOUTEN14,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 13. "EOUTEN13,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 12. "EOUTEN12,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 11. "EOUTEN11,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 10. "EOUTEN10,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 9. "EOUTEN9,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 8. "EOUTEN8,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 7. "EOUTEN7,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 6. "EOUTEN6,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 5. "EOUTEN5,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 4. "EOUTEN4,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 3. "EOUTEN3,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 2. "EOUTEN2,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 1. "EOUTEN1,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 0. "EOUTEN0,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." repeat.end rgroup.long 0x12C++0x3 line.long 0x0 "TMR_ALARM,Alarm-State Timer" hexmask.long 0x0 0.--31. 1. "COUNT,Alarm-State Timer Count" rgroup.long 0x134++0x7 line.long 0x0 "TMR_CFG,Configuration-State Timer" hexmask.long 0x0 0.--31. 1. "COUNT,Configuration-State Timer Count" line.long 0x4 "TMR_ETMR,Fault-Output Timer" hexmask.long 0x4 0.--31. 1. "COUNT,Fault-Output Timer Count" tree.end tree "FLEXCAN (Flexible Controller Area Network)" base ad:0x0 tree "CAN_0" base ad:0x401B4000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode.,1: Enabled to enter Freeze mode." newline bitfld.long 0x0 29. "RFEN,Legacy RX FIFO Enable" "0: Legacy RX FIFO not enabled.,1: Legacy RX FIFO enabled." bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if the FRZ field is 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset request.,1: Resets the registers affected by soft reset." newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running.,1: FlexCAN in Freeze mode prescaler stopped." bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" newline rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" bitfld.long 0x0 17. "SRXDIS,Self Reception Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x0 16. "IRMQ,Individual RX Masking And Queue Enable" "0: Individual RX masking and queue feature are..,1: Individual RX masking and queue feature are.." bitfld.long 0x0 15. "DMA,DMA Enable" "0: DMA feature for Legacy RX FIFO or Enhanced RX..,1: DMA feature for Legacy RX FIFO or Enhanced RX.." newline bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled.,1: Local Priority enabled." bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0: Disabled. FlexCAN is able to receive and..,1: Enabled. FlexCAN is able to receive and transmit.." bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." newline hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number Of The Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled.,1: Bus Off interrupt enabled." bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled.,1: Error interrupt enabled." newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Timer sync feature disabled,1: Timer sync feature enabled" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun" "0: Overrun has not occurred.,1: Overrun has occurred." newline eventfld.long 0x10 20. "ERRINT_FAST,Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set" "0: No such occurrence.,1: Indicates setting of any error bit detected in.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence.,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus.,1: FlexCAN is synchronized to the CAN bus." eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence.,1: The TX error counter transitioned from less than.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence.,1: The RX error counter transitioned from less than.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning" "0: No such occurrence.,1: TXERRCNT is greater than or equal to 96." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,IDLE" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN In Reception" "0: Not receiving.,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt" "0: No such occurrence.,1: Indicates setting of any error bit in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt Or Legacy RX FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt Or Legacy RX FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Legacy RX FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt Or Clear Legacy FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames" "0: ERRINT_FAST error interrupt disabled.,1: ERRINT_FAST error interrupt enabled." bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus off done interrupt disabled.,1: Bus off done interrupt enabled." newline bitfld.long 0x24 29. "ECRWRE,Error-correction Configuration Register Write Enable" "0: Disable update.,1: Enable update." bitfld.long 0x24 28. "WRMFRZ,Write-Access To Memory In Freeze Mode" "0: Maintain the write access restrictions.,1: Enable unrestricted write access to FlexCAN.." newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Legacy RX FIFO or Enhanced..,1: Matching starts from mailboxes and continues on.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Remote response frame is generated.,1: Remote request frame is stored." newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For RX Mailboxes" "0: IDE field of RX mailbox filter is always..,1: Enables the comparison of IDE and RTR fields of.." bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: The free running timer is clocked by the CAN bit..,1: The free running timer is clocked by an external.." newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Protocol exception is disabled.,1: Protocol exception is enabled." bitfld.long 0x24 13. "BTE,Bit Timing Expansion enable" "0: CAN Bit timing expansion is disabled.,1: CAN bit timing expansion is enabled." newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD protocol.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high resolution timer,2: Upper 16 bits of high resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Mailbox" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid.,1: Contents of IMB and LPTM are valid." newline bitfld.long 0x0 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is not..,1: If ESR2[VPS] is asserted there is at least one.." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,CRC" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Mailbox" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,Legacy RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,Legacy RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,Legacy RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled.,1: Extended bit time definitions enabled." hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" group.long 0x68++0xF line.long 0x0 "IMASK4,Interrupt Masks 4" hexmask.long 0x0 0.--31. 1. "BUF127TO96M,Buffer MBi Mask" line.long 0x4 "IMASK3,Interrupt Masks 3" hexmask.long 0x4 0.--31. 1. "BUF95TO64M,Buffer MBi Mask" line.long 0x8 "IFLAG4,Interrupt Flags 4" hexmask.long 0x8 0.--31. 1. "BUF127TO96,Buffer MBi Interrupt" line.long 0xC "IFLAG3,Interrupt Flags 3" hexmask.long 0xC 0.--31. 1. "BUF95TO64,Buffer MBi Interrupt" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Write is enabled.,1: Write is disabled." bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Injection is disabled.,1: Injection is enabled." newline bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Injection is disabled.,1: Injection is enabled." bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Error injection is applied only to the 32-bit..,1: Error injection is applied to the 64-bit word." newline bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable updates of the error report registers.,1: Disable updates of the error report registers." bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable memory error correction.,1: Disable memory error correction." newline bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data flip pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern For Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern For Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw data word read from memory with error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled For Byte 3 (most significant)" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome For Byte 3 (most significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled For Byte 2" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome For Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled For Byte 1" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled For Byte 0 (least significant)" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome For Byte 0 (least significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in host..,1: A non-correctable error was detected in a host.." eventfld.long 0x0 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in..,1: A non-correctable error was detected in a.." newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No correctable errors were detected so far.,1: A correctable error was detected." eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in host..,1: Overrun on non-correctable errors in host access" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in FlexCAN..,1: Overrun on non-correctable errors in FlexCAN.." eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No overrun on correctable errors,1: Overrun on correctable errors" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate. The BRS bit in..,1: Transmit a frame with bit rate switching if the.." bitfld.long 0x10 25.--26. "MBDSR3,Message Buffer Data Size for Region 3" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." newline bitfld.long 0x10 22.--23. "MBDSR2,Message Buffer Data Size for Region 2" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." newline bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled" newline eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" newline hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" group.long 0xC0C++0xB line.long 0x0 "ERFCR,Enhanced RX FIFO Control" bitfld.long 0x0 31. "ERFEN,Enhanced RX FIFO enable" "0: Enhanced RX FIFO is disabled,1: Enhanced RX FIFO is enabled" hexmask.long.byte 0x0 26.--30. 1. "DMALW,DMA Last Word" newline hexmask.long.byte 0x0 16.--22. 1. "NEXIF,Number of Extended ID Filter Elements" hexmask.long.byte 0x0 8.--13. 1. "NFE,Number of Enhanced RX FIFO Filter Elements" newline hexmask.long.byte 0x0 0.--4. 1. "ERFWM,Enhanced RX FIFO Watermark" line.long 0x4 "ERFIER,Enhanced RX FIFO Interrupt Enable" bitfld.long 0x4 31. "ERFUFWIE,Enhanced RX FIFO Underflow Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 30. "ERFOVFIE,Enhanced RX FIFO Overflow Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 29. "ERFWMIIE,Enhanced RX FIFO Watermark Indication Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 28. "ERFDAIE,Enhanced RX FIFO Data Available Interrupt Enable" "0: Disabled,1: Enabled" line.long 0x8 "ERFSR,Enhanced RX FIFO Status" eventfld.long 0x8 31. "ERFUFW,Enhanced RX FIFO Underflow" "0: No such occurrence,1: Underflow" eventfld.long 0x8 30. "ERFOVF,Enhanced RX FIFO Overflow" "0: No such occurrence,1: Overflow" newline eventfld.long 0x8 29. "ERFWMI,Enhanced RX FIFO Watermark Indication" "0: No such occurrence,1: The number of messages in FIFO is greater than.." eventfld.long 0x8 28. "ERFDA,Enhanced Rx FIFO Data Available" "0: No such occurrence,1: At least one message stored in Enhanced RX FIFO" newline bitfld.long 0x8 27. "ERFCLR,Enhanced RX FIFO Clear" "0: No effect,1: Clear Enhanced RX FIFO content" rbitfld.long 0x8 17. "ERFE,Enhanced RX FIFO empty" "0: Not empty,1: Empty" newline rbitfld.long 0x8 16. "ERFF,Enhanced RX FIFO full" "0: Not full,1: Full" hexmask.long.byte 0x8 0.--5. 1. "ERFEL,Enhanced RX FIFO Elements" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High Resolution Timestamp" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3000)++0x3 line.long 0x0 "ERFFEL[$1],Enhanced RX FIFO Filter Element" hexmask.long 0x0 0.--31. 1. "FEL,Filter Element Bits" repeat.end tree.end tree "CAN_1" base ad:0x401BE000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode.,1: Enabled to enter Freeze mode." newline bitfld.long 0x0 29. "RFEN,Legacy RX FIFO Enable" "0: Legacy RX FIFO not enabled.,1: Legacy RX FIFO enabled." bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if the FRZ field is 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset request.,1: Resets the registers affected by soft reset." newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running.,1: FlexCAN in Freeze mode prescaler stopped." bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" newline rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" bitfld.long 0x0 17. "SRXDIS,Self Reception Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x0 16. "IRMQ,Individual RX Masking And Queue Enable" "0: Individual RX masking and queue feature are..,1: Individual RX masking and queue feature are.." bitfld.long 0x0 15. "DMA,DMA Enable" "0: DMA feature for Legacy RX FIFO or Enhanced RX..,1: DMA feature for Legacy RX FIFO or Enhanced RX.." newline bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled.,1: Local Priority enabled." bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0: Disabled. FlexCAN is able to receive and..,1: Enabled. FlexCAN is able to receive and transmit.." bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." newline hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number Of The Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled.,1: Bus Off interrupt enabled." bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled.,1: Error interrupt enabled." newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Timer sync feature disabled,1: Timer sync feature enabled" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun" "0: Overrun has not occurred.,1: Overrun has occurred." newline eventfld.long 0x10 20. "ERRINT_FAST,Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set" "0: No such occurrence.,1: Indicates setting of any error bit detected in.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence.,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus.,1: FlexCAN is synchronized to the CAN bus." eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence.,1: The TX error counter transitioned from less than.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence.,1: The RX error counter transitioned from less than.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning" "0: No such occurrence.,1: TXERRCNT is greater than or equal to 96." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,IDLE" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN In Reception" "0: Not receiving.,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt" "0: No such occurrence.,1: Indicates setting of any error bit in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt Or Legacy RX FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt Or Legacy RX FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Legacy RX FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt Or Clear Legacy FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames" "0: ERRINT_FAST error interrupt disabled.,1: ERRINT_FAST error interrupt enabled." bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus off done interrupt disabled.,1: Bus off done interrupt enabled." newline bitfld.long 0x24 29. "ECRWRE,Error-correction Configuration Register Write Enable" "0: Disable update.,1: Enable update." bitfld.long 0x24 28. "WRMFRZ,Write-Access To Memory In Freeze Mode" "0: Maintain the write access restrictions.,1: Enable unrestricted write access to FlexCAN.." newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Legacy RX FIFO or Enhanced..,1: Matching starts from mailboxes and continues on.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Remote response frame is generated.,1: Remote request frame is stored." newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For RX Mailboxes" "0: IDE field of RX mailbox filter is always..,1: Enables the comparison of IDE and RTR fields of.." bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: The free running timer is clocked by the CAN bit..,1: The free running timer is clocked by an external.." newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Protocol exception is disabled.,1: Protocol exception is enabled." bitfld.long 0x24 13. "BTE,Bit Timing Expansion enable" "0: CAN Bit timing expansion is disabled.,1: CAN bit timing expansion is enabled." newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD protocol.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high resolution timer,2: Upper 16 bits of high resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Mailbox" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid.,1: Contents of IMB and LPTM are valid." newline bitfld.long 0x0 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is not..,1: If ESR2[VPS] is asserted there is at least one.." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,CRC" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Mailbox" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,Legacy RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,Legacy RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,Legacy RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled.,1: Extended bit time definitions enabled." hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" group.long 0x68++0xF line.long 0x0 "IMASK4,Interrupt Masks 4" hexmask.long 0x0 0.--31. 1. "BUF127TO96M,Buffer MBi Mask" line.long 0x4 "IMASK3,Interrupt Masks 3" hexmask.long 0x4 0.--31. 1. "BUF95TO64M,Buffer MBi Mask" line.long 0x8 "IFLAG4,Interrupt Flags 4" hexmask.long 0x8 0.--31. 1. "BUF127TO96,Buffer MBi Interrupt" line.long 0xC "IFLAG3,Interrupt Flags 3" hexmask.long 0xC 0.--31. 1. "BUF95TO64,Buffer MBi Interrupt" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Write is enabled.,1: Write is disabled." bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Injection is disabled.,1: Injection is enabled." newline bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Injection is disabled.,1: Injection is enabled." bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Error injection is applied only to the 32-bit..,1: Error injection is applied to the 64-bit word." newline bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable updates of the error report registers.,1: Disable updates of the error report registers." bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable memory error correction.,1: Disable memory error correction." newline bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data flip pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern For Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern For Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw data word read from memory with error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled For Byte 3 (most significant)" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome For Byte 3 (most significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled For Byte 2" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome For Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled For Byte 1" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled For Byte 0 (least significant)" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome For Byte 0 (least significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in host..,1: A non-correctable error was detected in a host.." eventfld.long 0x0 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in..,1: A non-correctable error was detected in a.." newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No correctable errors were detected so far.,1: A correctable error was detected." eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in host..,1: Overrun on non-correctable errors in host access" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in FlexCAN..,1: Overrun on non-correctable errors in FlexCAN.." eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No overrun on correctable errors,1: Overrun on correctable errors" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate. The BRS bit in..,1: Transmit a frame with bit rate switching if the.." bitfld.long 0x10 25.--26. "MBDSR3,Message Buffer Data Size for Region 3" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." newline bitfld.long 0x10 22.--23. "MBDSR2,Message Buffer Data Size for Region 2" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." newline bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled" newline eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" newline hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" group.long 0xC0C++0xB line.long 0x0 "ERFCR,Enhanced RX FIFO Control" bitfld.long 0x0 31. "ERFEN,Enhanced RX FIFO enable" "0: Enhanced RX FIFO is disabled,1: Enhanced RX FIFO is enabled" hexmask.long.byte 0x0 26.--30. 1. "DMALW,DMA Last Word" newline hexmask.long.byte 0x0 16.--22. 1. "NEXIF,Number of Extended ID Filter Elements" hexmask.long.byte 0x0 8.--13. 1. "NFE,Number of Enhanced RX FIFO Filter Elements" newline hexmask.long.byte 0x0 0.--4. 1. "ERFWM,Enhanced RX FIFO Watermark" line.long 0x4 "ERFIER,Enhanced RX FIFO Interrupt Enable" bitfld.long 0x4 31. "ERFUFWIE,Enhanced RX FIFO Underflow Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 30. "ERFOVFIE,Enhanced RX FIFO Overflow Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 29. "ERFWMIIE,Enhanced RX FIFO Watermark Indication Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 28. "ERFDAIE,Enhanced RX FIFO Data Available Interrupt Enable" "0: Disabled,1: Enabled" line.long 0x8 "ERFSR,Enhanced RX FIFO Status" eventfld.long 0x8 31. "ERFUFW,Enhanced RX FIFO Underflow" "0: No such occurrence,1: Underflow" eventfld.long 0x8 30. "ERFOVF,Enhanced RX FIFO Overflow" "0: No such occurrence,1: Overflow" newline eventfld.long 0x8 29. "ERFWMI,Enhanced RX FIFO Watermark Indication" "0: No such occurrence,1: The number of messages in FIFO is greater than.." eventfld.long 0x8 28. "ERFDA,Enhanced Rx FIFO Data Available" "0: No such occurrence,1: At least one message stored in Enhanced RX FIFO" newline bitfld.long 0x8 27. "ERFCLR,Enhanced RX FIFO Clear" "0: No effect,1: Clear Enhanced RX FIFO content" rbitfld.long 0x8 17. "ERFE,Enhanced RX FIFO empty" "0: Not empty,1: Empty" newline rbitfld.long 0x8 16. "ERFF,Enhanced RX FIFO full" "0: Not full,1: Full" hexmask.long.byte 0x8 0.--5. 1. "ERFEL,Enhanced RX FIFO Elements" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High Resolution Timestamp" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3000)++0x3 line.long 0x0 "ERFFEL[$1],Enhanced RX FIFO Filter Element" hexmask.long 0x0 0.--31. 1. "FEL,Filter Element Bits" repeat.end tree.end tree "CAN_2" base ad:0x402A8000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode.,1: Enabled to enter Freeze mode." newline bitfld.long 0x0 29. "RFEN,Legacy RX FIFO Enable" "0: Legacy RX FIFO not enabled.,1: Legacy RX FIFO enabled." bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if the FRZ field is 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset request.,1: Resets the registers affected by soft reset." newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running.,1: FlexCAN in Freeze mode prescaler stopped." bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" newline rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" bitfld.long 0x0 17. "SRXDIS,Self Reception Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x0 16. "IRMQ,Individual RX Masking And Queue Enable" "0: Individual RX masking and queue feature are..,1: Individual RX masking and queue feature are.." bitfld.long 0x0 15. "DMA,DMA Enable" "0: DMA feature for Legacy RX FIFO or Enhanced RX..,1: DMA feature for Legacy RX FIFO or Enhanced RX.." newline bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled.,1: Local Priority enabled." bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0: Disabled. FlexCAN is able to receive and..,1: Enabled. FlexCAN is able to receive and transmit.." bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." newline hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number Of The Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled.,1: Bus Off interrupt enabled." bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled.,1: Error interrupt enabled." newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Timer sync feature disabled,1: Timer sync feature enabled" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun" "0: Overrun has not occurred.,1: Overrun has occurred." newline eventfld.long 0x10 20. "ERRINT_FAST,Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set" "0: No such occurrence.,1: Indicates setting of any error bit detected in.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence.,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus.,1: FlexCAN is synchronized to the CAN bus." eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence.,1: The TX error counter transitioned from less than.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence.,1: The RX error counter transitioned from less than.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning" "0: No such occurrence.,1: TXERRCNT is greater than or equal to 96." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,IDLE" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN In Reception" "0: Not receiving.,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt" "0: No such occurrence.,1: Indicates setting of any error bit in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt Or Legacy RX FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt Or Legacy RX FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Legacy RX FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt Or Clear Legacy FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames" "0: ERRINT_FAST error interrupt disabled.,1: ERRINT_FAST error interrupt enabled." bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus off done interrupt disabled.,1: Bus off done interrupt enabled." newline bitfld.long 0x24 29. "ECRWRE,Error-correction Configuration Register Write Enable" "0: Disable update.,1: Enable update." bitfld.long 0x24 28. "WRMFRZ,Write-Access To Memory In Freeze Mode" "0: Maintain the write access restrictions.,1: Enable unrestricted write access to FlexCAN.." newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Legacy RX FIFO or Enhanced..,1: Matching starts from mailboxes and continues on.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Remote response frame is generated.,1: Remote request frame is stored." newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For RX Mailboxes" "0: IDE field of RX mailbox filter is always..,1: Enables the comparison of IDE and RTR fields of.." bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: The free running timer is clocked by the CAN bit..,1: The free running timer is clocked by an external.." newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Protocol exception is disabled.,1: Protocol exception is enabled." bitfld.long 0x24 13. "BTE,Bit Timing Expansion enable" "0: CAN Bit timing expansion is disabled.,1: CAN bit timing expansion is enabled." newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD protocol.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high resolution timer,2: Upper 16 bits of high resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Mailbox" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid.,1: Contents of IMB and LPTM are valid." newline bitfld.long 0x0 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is not..,1: If ESR2[VPS] is asserted there is at least one.." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,CRC" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Mailbox" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,Legacy RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,Legacy RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,Legacy RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled.,1: Extended bit time definitions enabled." hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" group.long 0x68++0xF line.long 0x0 "IMASK4,Interrupt Masks 4" hexmask.long 0x0 0.--31. 1. "BUF127TO96M,Buffer MBi Mask" line.long 0x4 "IMASK3,Interrupt Masks 3" hexmask.long 0x4 0.--31. 1. "BUF95TO64M,Buffer MBi Mask" line.long 0x8 "IFLAG4,Interrupt Flags 4" hexmask.long 0x8 0.--31. 1. "BUF127TO96,Buffer MBi Interrupt" line.long 0xC "IFLAG3,Interrupt Flags 3" hexmask.long 0xC 0.--31. 1. "BUF95TO64,Buffer MBi Interrupt" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Write is enabled.,1: Write is disabled." bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Injection is disabled.,1: Injection is enabled." newline bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Injection is disabled.,1: Injection is enabled." bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Error injection is applied only to the 32-bit..,1: Error injection is applied to the 64-bit word." newline bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable updates of the error report registers.,1: Disable updates of the error report registers." bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable memory error correction.,1: Disable memory error correction." newline bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data flip pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern For Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern For Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw data word read from memory with error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled For Byte 3 (most significant)" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome For Byte 3 (most significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled For Byte 2" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome For Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled For Byte 1" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled For Byte 0 (least significant)" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome For Byte 0 (least significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in host..,1: A non-correctable error was detected in a host.." eventfld.long 0x0 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in..,1: A non-correctable error was detected in a.." newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No correctable errors were detected so far.,1: A correctable error was detected." eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in host..,1: Overrun on non-correctable errors in host access" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in FlexCAN..,1: Overrun on non-correctable errors in FlexCAN.." eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No overrun on correctable errors,1: Overrun on correctable errors" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate. The BRS bit in..,1: Transmit a frame with bit rate switching if the.." bitfld.long 0x10 25.--26. "MBDSR3,Message Buffer Data Size for Region 3" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." newline bitfld.long 0x10 22.--23. "MBDSR2,Message Buffer Data Size for Region 2" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." newline bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled" newline eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" newline hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" group.long 0xC0C++0xB line.long 0x0 "ERFCR,Enhanced RX FIFO Control" bitfld.long 0x0 31. "ERFEN,Enhanced RX FIFO enable" "0: Enhanced RX FIFO is disabled,1: Enhanced RX FIFO is enabled" hexmask.long.byte 0x0 26.--30. 1. "DMALW,DMA Last Word" newline hexmask.long.byte 0x0 16.--22. 1. "NEXIF,Number of Extended ID Filter Elements" hexmask.long.byte 0x0 8.--13. 1. "NFE,Number of Enhanced RX FIFO Filter Elements" newline hexmask.long.byte 0x0 0.--4. 1. "ERFWM,Enhanced RX FIFO Watermark" line.long 0x4 "ERFIER,Enhanced RX FIFO Interrupt Enable" bitfld.long 0x4 31. "ERFUFWIE,Enhanced RX FIFO Underflow Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 30. "ERFOVFIE,Enhanced RX FIFO Overflow Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 29. "ERFWMIIE,Enhanced RX FIFO Watermark Indication Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 28. "ERFDAIE,Enhanced RX FIFO Data Available Interrupt Enable" "0: Disabled,1: Enabled" line.long 0x8 "ERFSR,Enhanced RX FIFO Status" eventfld.long 0x8 31. "ERFUFW,Enhanced RX FIFO Underflow" "0: No such occurrence,1: Underflow" eventfld.long 0x8 30. "ERFOVF,Enhanced RX FIFO Overflow" "0: No such occurrence,1: Overflow" newline eventfld.long 0x8 29. "ERFWMI,Enhanced RX FIFO Watermark Indication" "0: No such occurrence,1: The number of messages in FIFO is greater than.." eventfld.long 0x8 28. "ERFDA,Enhanced Rx FIFO Data Available" "0: No such occurrence,1: At least one message stored in Enhanced RX FIFO" newline bitfld.long 0x8 27. "ERFCLR,Enhanced RX FIFO Clear" "0: No effect,1: Clear Enhanced RX FIFO content" rbitfld.long 0x8 17. "ERFE,Enhanced RX FIFO empty" "0: Not empty,1: Empty" newline rbitfld.long 0x8 16. "ERFF,Enhanced RX FIFO full" "0: Not full,1: Full" hexmask.long.byte 0x8 0.--5. 1. "ERFEL,Enhanced RX FIFO Elements" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High Resolution Timestamp" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3000)++0x3 line.long 0x0 "ERFFEL[$1],Enhanced RX FIFO Filter Element" hexmask.long 0x0 0.--31. 1. "FEL,Filter Element Bits" repeat.end tree.end tree "CAN_3" base ad:0x402B2000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode.,1: Enabled to enter Freeze mode." newline bitfld.long 0x0 29. "RFEN,Legacy RX FIFO Enable" "0: Legacy RX FIFO not enabled.,1: Legacy RX FIFO enabled." bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if the FRZ field is 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset request.,1: Resets the registers affected by soft reset." newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running.,1: FlexCAN in Freeze mode prescaler stopped." bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" newline rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" bitfld.long 0x0 17. "SRXDIS,Self Reception Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x0 16. "IRMQ,Individual RX Masking And Queue Enable" "0: Individual RX masking and queue feature are..,1: Individual RX masking and queue feature are.." bitfld.long 0x0 15. "DMA,DMA Enable" "0: DMA feature for Legacy RX FIFO or Enhanced RX..,1: DMA feature for Legacy RX FIFO or Enhanced RX.." newline bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled.,1: Local Priority enabled." bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "FDEN,CAN FD operation enable" "0: Disabled. FlexCAN is able to receive and..,1: Enabled. FlexCAN is able to receive and transmit.." bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." newline hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number Of The Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled.,1: Bus Off interrupt enabled." bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled.,1: Error interrupt enabled." newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Timer sync feature disabled,1: Timer sync feature enabled" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun" "0: Overrun has not occurred.,1: Overrun has occurred." newline eventfld.long 0x10 20. "ERRINT_FAST,Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set" "0: No such occurrence.,1: Indicates setting of any error bit detected in.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence.,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus.,1: FlexCAN is synchronized to the CAN bus." eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence.,1: The TX error counter transitioned from less than.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence.,1: The RX error counter transitioned from less than.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning" "0: No such occurrence.,1: TXERRCNT is greater than or equal to 96." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,IDLE" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN In Reception" "0: Not receiving.,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt" "0: No such occurrence.,1: Indicates setting of any error bit in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt Or Legacy RX FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt Or Legacy RX FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Legacy RX FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt Or Clear Legacy FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames" "0: ERRINT_FAST error interrupt disabled.,1: ERRINT_FAST error interrupt enabled." bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus off done interrupt disabled.,1: Bus off done interrupt enabled." newline bitfld.long 0x24 29. "ECRWRE,Error-correction Configuration Register Write Enable" "0: Disable update.,1: Enable update." bitfld.long 0x24 28. "WRMFRZ,Write-Access To Memory In Freeze Mode" "0: Maintain the write access restrictions.,1: Enable unrestricted write access to FlexCAN.." newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Legacy RX FIFO or Enhanced..,1: Matching starts from mailboxes and continues on.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Remote response frame is generated.,1: Remote request frame is stored." newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For RX Mailboxes" "0: IDE field of RX mailbox filter is always..,1: Enables the comparison of IDE and RTR fields of.." bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: The free running timer is clocked by the CAN bit..,1: The free running timer is clocked by an external.." newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Protocol exception is disabled.,1: Protocol exception is enabled." bitfld.long 0x24 13. "BTE,Bit Timing Expansion enable" "0: CAN Bit timing expansion is disabled.,1: CAN bit timing expansion is enabled." newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD protocol.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high resolution timer,2: Upper 16 bits of high resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Mailbox" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid.,1: Contents of IMB and LPTM are valid." newline bitfld.long 0x0 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is not..,1: If ESR2[VPS] is asserted there is at least one.." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,CRC" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Mailbox" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,Legacy RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,Legacy RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,Legacy RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled.,1: Extended bit time definitions enabled." hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" group.long 0x68++0xF line.long 0x0 "IMASK4,Interrupt Masks 4" hexmask.long 0x0 0.--31. 1. "BUF127TO96M,Buffer MBi Mask" line.long 0x4 "IMASK3,Interrupt Masks 3" hexmask.long 0x4 0.--31. 1. "BUF95TO64M,Buffer MBi Mask" line.long 0x8 "IFLAG4,Interrupt Flags 4" hexmask.long 0x8 0.--31. 1. "BUF127TO96,Buffer MBi Interrupt" line.long 0xC "IFLAG3,Interrupt Flags 3" hexmask.long 0xC 0.--31. 1. "BUF95TO64,Buffer MBi Interrupt" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Write is enabled.,1: Write is disabled." bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Injection is disabled.,1: Injection is enabled." newline bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Injection is disabled.,1: Injection is enabled." bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Error injection is applied only to the 32-bit..,1: Error injection is applied to the 64-bit word." newline bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable updates of the error report registers.,1: Disable updates of the error report registers." bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable memory error correction.,1: Disable memory error correction." newline bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data flip pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern For Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern For Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw data word read from memory with error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled For Byte 3 (most significant)" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome For Byte 3 (most significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled For Byte 2" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome For Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled For Byte 1" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled For Byte 0 (least significant)" "0: The byte was not read.,1: The byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome For Byte 0 (least significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in host..,1: A non-correctable error was detected in a host.." eventfld.long 0x0 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in..,1: A non-correctable error was detected in a.." newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No correctable errors were detected so far.,1: A correctable error was detected." eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in host..,1: Overrun on non-correctable errors in host access" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in FlexCAN..,1: Overrun on non-correctable errors in FlexCAN.." eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No overrun on correctable errors,1: Overrun on correctable errors" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate. The BRS bit in..,1: Transmit a frame with bit rate switching if the.." bitfld.long 0x10 25.--26. "MBDSR3,Message Buffer Data Size for Region 3" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." newline bitfld.long 0x10 22.--23. "MBDSR2,Message Buffer Data Size for Region 2" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." newline bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per message buffer.,1: Selects 16 bytes per message buffer.,2: Selects 32 bytes per message buffer.,3: Selects 64 bytes per message buffer." bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled" newline eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" newline hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" group.long 0xC0C++0xB line.long 0x0 "ERFCR,Enhanced RX FIFO Control" bitfld.long 0x0 31. "ERFEN,Enhanced RX FIFO enable" "0: Enhanced RX FIFO is disabled,1: Enhanced RX FIFO is enabled" hexmask.long.byte 0x0 26.--30. 1. "DMALW,DMA Last Word" newline hexmask.long.byte 0x0 16.--22. 1. "NEXIF,Number of Extended ID Filter Elements" hexmask.long.byte 0x0 8.--13. 1. "NFE,Number of Enhanced RX FIFO Filter Elements" newline hexmask.long.byte 0x0 0.--4. 1. "ERFWM,Enhanced RX FIFO Watermark" line.long 0x4 "ERFIER,Enhanced RX FIFO Interrupt Enable" bitfld.long 0x4 31. "ERFUFWIE,Enhanced RX FIFO Underflow Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 30. "ERFOVFIE,Enhanced RX FIFO Overflow Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 29. "ERFWMIIE,Enhanced RX FIFO Watermark Indication Interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 28. "ERFDAIE,Enhanced RX FIFO Data Available Interrupt Enable" "0: Disabled,1: Enabled" line.long 0x8 "ERFSR,Enhanced RX FIFO Status" eventfld.long 0x8 31. "ERFUFW,Enhanced RX FIFO Underflow" "0: No such occurrence,1: Underflow" eventfld.long 0x8 30. "ERFOVF,Enhanced RX FIFO Overflow" "0: No such occurrence,1: Overflow" newline eventfld.long 0x8 29. "ERFWMI,Enhanced RX FIFO Watermark Indication" "0: No such occurrence,1: The number of messages in FIFO is greater than.." eventfld.long 0x8 28. "ERFDA,Enhanced Rx FIFO Data Available" "0: No such occurrence,1: At least one message stored in Enhanced RX FIFO" newline bitfld.long 0x8 27. "ERFCLR,Enhanced RX FIFO Clear" "0: No effect,1: Clear Enhanced RX FIFO content" rbitfld.long 0x8 17. "ERFE,Enhanced RX FIFO empty" "0: Not empty,1: Empty" newline rbitfld.long 0x8 16. "ERFF,Enhanced RX FIFO full" "0: Not full,1: Full" hexmask.long.byte 0x8 0.--5. 1. "ERFEL,Enhanced RX FIFO Elements" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High Resolution Timestamp" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3000)++0x3 line.long 0x0 "ERFFEL[$1],Enhanced RX FIFO Filter Element" hexmask.long 0x0 0.--31. 1. "FEL,Filter Element Bits" repeat.end tree.end tree.end tree "FLEXRAY (FlexRay Communication Controller)" base ad:0x402F8000 rgroup.word 0x0++0x1 line.word 0x0 "MVR,Module Version" hexmask.word.byte 0x0 8.--15. 1. "CHIVER,CHI Version Number" newline hexmask.word.byte 0x0 0.--7. 1. "PEVER,PE Version Number" group.word 0x2++0x7 line.word 0x0 "MCR,Module Configuration" bitfld.word 0x0 15. "MEN,Module Enable" "0: Write: only during POC:default config CC disable..,1: Write: enable CC Read: CC enabled" newline bitfld.word 0x0 14. "SBFF,System Bus Failure Freeze" "0: Continue normal operation,1: Transition to freeze mode" newline bitfld.word 0x0 13. "SCM,Single Channel Device Mode" "0: Dual channel,1: Single channel" newline bitfld.word 0x0 12. "CHB,Channel B Enable" "0,1" newline bitfld.word 0x0 11. "CHA,Channel A Enable" "0,1" newline bitfld.word 0x0 10. "SFFE,Synchronization Frame Filter Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 9. "ECCE,ECC Functionality Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 7. "FUM,FIFO Update Mode" "0: Updated,1: Not updated" newline bitfld.word 0x0 6. "FAM,FIFO Address Mode" "0: SYMBADHR,1: RFSYMBADHR" newline bitfld.word 0x0 1.--3. "BITRATE,FlexRay Bus Bit Rate" "0: 10.0 Mbit/s,1: 5.0 Mbit/s,2: 2.5 Mbit/s,3: 8.0 Mbit/s,?,?,?,?" line.word 0x2 "SYMBADHR,System Memory Base Address High" hexmask.word 0x2 0.--15. 1. "SMBA,System Memory Base Address High" line.word 0x4 "SYMBADLR,System Memory Base Address Low" hexmask.word 0x4 4.--15. 1. "SMBA,System Memory Base Address Low" line.word 0x6 "STBSCR,Strobe Signal Control" bitfld.word 0x6 15. "WMD,Write Mode" "0: Write to all fields in this register on a write..,1: Write only to the SEL field on write access" newline hexmask.word.byte 0x6 8.--11. 1. "SEL,Strobe Signal Select" newline bitfld.word 0x6 4. "ENB,Strobe Signal Enable" "0: Disabled and not assigned to any strobe port,1: Enabled and assigned to the strobe port selected.." newline bitfld.word 0x6 0.--1. "STBPSEL,Strobe Port Select" "0: FR_DBG[0],1: FR_DBG[1],2: FR_DBG[2],3: FR_DBG[3]" group.word 0xC++0x15 line.word 0x0 "MBDSR,MB Data Size" hexmask.word.byte 0x0 8.--14. 1. "MBSEG2DS,MB Segment 2 Data Size" newline hexmask.word.byte 0x0 0.--6. 1. "MBSEG1DS,MB Segment 1 Data Size" line.word 0x2 "MBSSUTR,MB Segment Size and Utilization" hexmask.word.byte 0x2 8.--15. 1. "LAST_MB_SEG1,Last MB In Segment 1" newline hexmask.word.byte 0x2 0.--7. 1. "LAST_MB_UTIL,Last MB Utilized" line.word 0x4 "PEDRAR,PE DRAM Access" hexmask.word.byte 0x4 12.--15. 1. "INST,PE DRAM Access Instruction" newline hexmask.word 0x4 1.--11. 1. "ADDR,PE DRAM Access Address" newline rbitfld.word 0x4 0. "DAD,PE DRAM Access Done" "0: Access running,1: Access done" line.word 0x6 "PEDRDR,PE DRAM Data" hexmask.word 0x6 0.--15. 1. "DATA,Data To Or From PE DRAM" line.word 0x8 "POCR,Protocol Operation Control" bitfld.word 0x8 15. "WME,Write Mode External Correction" "0: Write to EOC_AP and ERC_AP fields on register..,1: No write to EOC_AP and ERC_AP fields on register.." newline bitfld.word 0x8 10.--11. "EOC_AP,External Offset Correction Application" "0: Do not apply external offset correction value,?,2: Subtract external offset correction value,3: Add external offset correction value" newline bitfld.word 0x8 8.--9. "ERC_AP,External Rate Correction Application" "0: Do not apply external rate correction value,?,2: Subtract external rate correction value,3: Add external rate correction value" newline bitfld.word 0x8 7. "BSY_WMC,Protocol Control Command Busy Or Command Write" "0: Read operation: Command write idle; command..,1: Read operation: Command write busy; command not.." newline hexmask.word.byte 0x8 0.--3. 1. "POCCMD,Protocol Control Command" line.word 0xA "GIFER,Global Interrupt Flag And Enable" rbitfld.word 0xA 15. "MIF,Module Interrupt Flag" "0: No interrupt flag and related interrupt enable..,1: At least one of the other interrupt flags in.." newline rbitfld.word 0xA 14. "PRIF,Protocol Interrupt Flag" "0: No individual protocol interrupt flag and..,1: At least one of the individual protocol.." newline rbitfld.word 0xA 13. "CHIF,CHI Interrupt Flag" "0: All CHI error flags are 0 or the CHI error..,1: At least one CHI error flag and the CHI error.." newline eventfld.word 0xA 12. "WUPIF,Wakeup Interrupt Flag" "0: Not received,1: Received" newline eventfld.word 0xA 11. "FAFBIF,Receive FIFO Channel B Almost Full Interrupt Flag" "0: No such event,1: FIFO B almost-full event has occurred" newline eventfld.word 0xA 10. "FAFAIF,Receive FIFO Channel A Almost Full Interrupt Flag" "0: No such event,1: FIFO A almost-full event has occurred" newline rbitfld.word 0xA 9. "RBIF,Receive MB Interrupt Flag" "0: None of the individual transmit MBs has MBIF =..,1: At least one individual transmit MB has MBIF =.." newline rbitfld.word 0xA 8. "TBIF,Transmit MB Interrupt Flag" "0: None of the individual transmit MBs has MBIF =..,1: At least one individual transmit MB has MBIF =.." newline bitfld.word 0xA 7. "MIE,Module Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 6. "PRIE,Protocol Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 5. "CHIE,CHI Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 4. "WUPIE,Wakeup Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 3. "FAFBIE,Receive FIFO Channel B Almost Full Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 2. "FAFAIE,Receive FIFO Channel A Almost Full Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 1. "RBIE,Receive MB Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 0. "TBIE,Transmit MB Interrupt Enable" "0: Disable,1: Enable" line.word 0xC "PIFR0,Protocol Interrupt Flag 0" eventfld.word 0xC 15. "FATL_IF,Fatal Protocol Error Interrupt Flag" "0: No such event,1: Fatal protocol error detected" newline eventfld.word 0xC 14. "INTL_IF,Internal Protocol Error Interrupt Flag" "0: No such event,1: Internal protocol error detected" newline eventfld.word 0xC 13. "ILCF_IF,Illegal Protocol Configuration Interrupt Flag" "0: No such event,1: Illegal protocol configuration detected" newline eventfld.word 0xC 12. "CSA_IF,Cold Start Abort Interrupt Flag" "0: No such event,1: Cold start aborted and no more coldstart.." newline eventfld.word 0xC 11. "MRC_IF,Missing Rate Correction Interrupt Flag" "0: No such event,1: Insufficient number of measurements for rate.." newline eventfld.word 0xC 10. "MOC_IF,Missing Offset Correction Interrupt Flag" "0: No such event,1: Insufficient number of measurements for offset.." newline eventfld.word 0xC 9. "CCL_IF,Clock Correction Limit Reached Interrupt Flag" "0: No such event,1: Offset or rate correction limit reached" newline eventfld.word 0xC 8. "MXS_IF,Max Sync Frames Detected Interrupt Flag" "0: No such event,1: More than node_sync_max sync frames detected" newline eventfld.word 0xC 7. "MTX_IF,Media Access Test Symbol Received Interrupt Flag" "0: No such event,1: MTS symbol received" newline eventfld.word 0xC 6. "LTXB_IF,pLatestTx Violation on Channel B Interrupt Flag" "0: No such event,1: pLatestTx violation occurred on channel B" newline eventfld.word 0xC 5. "LTXA_IF,pLatestTx Violation on Channel A Interrupt Flag" "0: No such event,1: pLatestTx violation occurred on channel A" newline eventfld.word 0xC 4. "TBVB_IF,Transmission Across Boundary On Channel B Interrupt Flag" "0: No such event,1: Transmission across boundary violation occurred.." newline eventfld.word 0xC 3. "TBVA_IF,Transmission Across Boundary On Channel A Interrupt Flag" "0: No such event,1: Transmission across boundary violation occurred.." newline eventfld.word 0xC 2. "TI2_IF,Timer 2 Expired Interrupt Flag" "0: No such event,1: Timer 2 has reached its time limit" newline eventfld.word 0xC 1. "TI1_IF,Timer 1 Expired Interrupt Flag" "0: No such event,1: Timer 1 has reached its time limit" newline eventfld.word 0xC 0. "CYS_IF,Cycle Start Interrupt Flag" "0: No such event,1: Communication cycle started" line.word 0xE "PIFR1,Protocol Interrupt Flag 1" eventfld.word 0xE 15. "EMC_IF,Error Mode Changed Interrupt Flag" "0: No such event,1: ERRMODE field changed" newline eventfld.word 0xE 14. "IPC_IF,Illegal Protocol Control Command Interrupt Flag" "0: No such event,1: Illegal protocol control command detected" newline eventfld.word 0xE 13. "PECF_IF,PE Communication Failure Interrupt Flag" "0: No such event,1: Failure detected" newline eventfld.word 0xE 12. "PSC_IF,Protocol State Changed Interrupt Flag" "0: No such event,1: Protocol state changed" newline eventfld.word 0xE 11. "SSI3_IF,Slot Status Counter Incremented Interrupt Flag 3" "0: No such event,1: The corresponding slot status counter has.." newline eventfld.word 0xE 10. "SSI2_IF,Slot Status Counter Incremented Interrupt Flag 2" "0: No such event,1: The corresponding slot status counter has.." newline eventfld.word 0xE 9. "SSI1_IF,Slot Status Counter Incremented Interrupt Flag 1" "0: No such event,1: The corresponding slot status counter has.." newline eventfld.word 0xE 8. "SSI0_IF,Slot Status Counter Incremented Interrupt Flag 0" "0: No such event,1: The corresponding slot status counter has.." newline eventfld.word 0xE 5. "EVT_IF,Even Cycle Table Written Interrupt Flag" "0: No such event,1: Sync frame measurement table written" newline eventfld.word 0xE 4. "ODT_IF,Odd Cycle Table Written Interrupt Flag" "0: No such event,1: Sync frame measurement table written" line.word 0x10 "PIER0,Protocol Interrupt Enable 0" bitfld.word 0x10 15. "FATL_IE,Fatal Protocol Error Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 14. "INTL_IE,Internal Protocol Error Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 13. "ILCF_IE,Illegal Protocol Configuration Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 12. "CSA_IE,Cold Start Abort Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 11. "MRC_IE,Missing Rate Correction Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 10. "MOC_IE,Missing Offset Correction Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 9. "CCL_IE,Clock Correction Limit Reached Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 8. "MXS_IE,Max Sync Frames Detected Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 7. "MTX_IE,Media Access Test Symbol Received Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 6. "LTXB_IE,pLatestTx Violation on Channel B Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 5. "LTXA_IE,pLatestTx Violation On Channel A Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 4. "TBVB_IE,Transmission Across Boundary On Channel B Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 3. "TBVA_IE,Transmission Across Boundary On Channel A Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 2. "TI2_IE,Timer 2 Expired Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 1. "TI1_IE,Timer 1 Expired Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x10 0. "CYS_IE,Cycle Start Interrupt Enable" "0: Disabled,1: Enabled" line.word 0x12 "PIER1,Protocol Interrupt Enable 1" bitfld.word 0x12 15. "EMC_IE,Error Mode Changed Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x12 14. "IPC_IE,Illegal Protocol Control Command Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x12 13. "PECF_IE,PE Communication Failure Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x12 12. "PSC_IE,Protocol State Changed Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x12 11. "SSI3_IE,Slot Status Counter Incremented Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x12 10. "SSI2_IE,Slot Status Counter Incremented Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x12 9. "SSI1_IE,Slot Status Counter Incremented Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x12 8. "SSI0_IE,Slot Status Counter Incremented Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x12 5. "EVT_IE,Even Cycle Table Written Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x12 4. "ODT_IE,Odd Cycle Table Written Interrupt Enable" "0: Disabled,1: Enabled" line.word 0x14 "CHIERFR,CHI Error Flag" eventfld.word 0x14 15. "FRLB_EF,Frame Lost Channel B Error Flag" "0: No such event,1: Frame lost on channel B detected" newline eventfld.word 0x14 14. "FRLA_EF,Frame Lost Channel A Error Flag" "0: No such error,1: Frame lost on channel A detected" newline eventfld.word 0x14 13. "PCMI_EF,Protocol Command Ignored Error Flag" "0: No such error,1: POC command is ignored" newline eventfld.word 0x14 12. "FOVB_EF,Receive FIFO Overrun Channel B Error Flag" "0: No such error,1: FIFO overrun on channel B is detected" newline eventfld.word 0x14 11. "FOVA_EF,Receive FIFO Overrun Channel A Error Flag" "0: No such error,1: FIFO overrun on channel B is detected" newline eventfld.word 0x14 10. "MBS_EF,MB Search Error Flag" "0: No such event,1: Search engine is active while search start.." newline eventfld.word 0x14 9. "MBU_EF,MB Usage Error Flag" "0: No such event,1: Unused MB enabled" newline eventfld.word 0x14 8. "LCK_EF,Lock Error Flag" "0: No such error,1: Lock error detected" newline eventfld.word 0x14 6. "SBCF_EF,System Bus Communication Failure Error Flag" "0: No such event,1: System bus access not finished in time" newline eventfld.word 0x14 5. "FID_EF,FID Error Flag" "0: No such error occurred,1: FID error occurred" newline eventfld.word 0x14 4. "DPL_EF,Dynamic Payload Length Error Flag" "0: No such error occurred,1: Dynamic payload length error occurred" newline eventfld.word 0x14 3. "SPL_EF,Static Payload Length Error Flag" "0: No such error occurred,1: Static payload length error occurred" newline eventfld.word 0x14 2. "NML_EF,Network Management Length Error Flag" "0: No such error occurred,1: Network management length error occurred" newline eventfld.word 0x14 1. "NMF_EF,Network Management Frame Error Flag" "0: No such error occurred,1: Network management frame error occurred" newline eventfld.word 0x14 0. "ILSA_EF,Illegal System Bus Address Error Flag" "0: No such event,1: Illegal system bus address accessed" rgroup.word 0x22++0x7 line.word 0x0 "MBIVEC,MB Interrupt Vector" hexmask.word.byte 0x0 8.--15. 1. "TBIVEC,Transmit Buffer Interrupt Vector" newline hexmask.word.byte 0x0 0.--7. 1. "RBIVEC,Receive Buffer Interrupt Vector" line.word 0x2 "CASERCR,Channel A Status Error Counter Register" hexmask.word 0x2 0.--15. 1. "CHAERSCNT,Channel A Status Error Counter" line.word 0x4 "CBSERCR,Channel B Status Error Counter" hexmask.word 0x4 0.--15. 1. "CHBERSCNT,Channel B Status Error Counter" line.word 0x6 "PSR0,Protocol Status 0" bitfld.word 0x6 14.--15. "ERRMODE,Error Mode" "0: ACTIVE,1: PASSIVE,2: COMM_HALT,?" newline bitfld.word 0x6 12.--13. "SLOTMODE,Slot Mode" "0: SINGLE,1: ALL_PENDING,2: ALL,?" newline bitfld.word 0x6 8.--10. "PROTSTATE,Protocol State" "0: POC:default config,1: POC:config,2: POC:wakeup,3: POC:ready,4: POC:normal passive,5: POC:normal active,6: POC:halt,7: POC:startup" newline hexmask.word.byte 0x6 4.--7. 1. "STARTUPSTATE,Startup State" newline bitfld.word 0x6 0.--2. "WAKEUPSTATUS,Wakeup Status" "0: UNDEFINED,1: RECEIVED_HEADER,2: RECEIVED_WUP,3: COLLISION_HEADER,4: COLLISION_WUP,5: COLLISION_UNKNOWN,6: TRANSMITTED,?" group.word 0x2A++0x1 line.word 0x0 "PSR1,Protocol Status 1" eventfld.word 0x0 15. "CSAA,Cold Start Attempt Aborted Flag" "0: No such event,1: Cold start attempt aborted" newline rbitfld.word 0x0 14. "CSP,Leading Cold Start Path" "0: No such event,1: POC:normal active reached from POC:startup state.." newline hexmask.word.byte 0x0 8.--12. 1. "REMCSAT,Remaining Coldstart Attempts" newline rbitfld.word 0x0 7. "CPN,Leading Cold Start Path Noise" "0: No such event,1: POC:normal active state was reached from.." newline rbitfld.word 0x0 6. "HHR,Host Halt Request Pending" "0: No such event,1: HALT command received" newline rbitfld.word 0x0 5. "FRZ,Freeze Occurred" "0: No such event,1: Immediate halt because of FREEZE or internal.." newline hexmask.word.byte 0x0 0.--4. 1. "APTAC,Allow Passive To Active Counter" rgroup.word 0x2C++0x1 line.word 0x0 "PSR2,Protocol Status 2" bitfld.word 0x0 15. "NBVB,NIT Boundary Violation On Channel B" "0: No such event,1: Media activity detected at boundaries" newline bitfld.word 0x0 14. "NSEB,NIT Syntax Error On Channel B" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 13. "STCB,Symbol Window Transmit Conflict On Channel B" "0: No such event,1: Transmission conflict detected" newline bitfld.word 0x0 12. "SBVB,Symbol Window Boundary Violation On Channel B" "0: No such event,1: Media activity detected at boundaries" newline bitfld.word 0x0 11. "SSEB,Symbol Window Syntax Error On Channel B" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 10. "MTB,MTS Received On Channel B" "0: No such event,1: MTS received" newline bitfld.word 0x0 9. "NBVA,NIT Boundary Violation On Channel A" "0: No such event,1: Media activity detected at boundaries" newline bitfld.word 0x0 8. "NSEA,NIT Syntax Error On Channel A" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 7. "STCA,Symbol Window Transmit Conflict On Channel A" "0: No such event,1: Transmission conflict detected" newline bitfld.word 0x0 6. "SBVA,Symbol Window Boundary Violation On Channel A" "0: No such event,1: Media activity detected at boundaries" newline bitfld.word 0x0 5. "SSEA,Symbol Window Syntax Error On Channel A" "0: No such event,1: Syntax error detected" newline bitfld.word 0x0 4. "MTA,MTS Received On Channel A" "0: No such event,1: MTS received" newline hexmask.word.byte 0x0 0.--3. 1. "CKCORFCNT,Clock Correction Failed Counter" group.word 0x2E++0x1 line.word 0x0 "PSR3,Protocol Status 3" eventfld.word 0x0 13. "WUB,Wakeup Symbol Received On Channel B" "0: Not received,1: Received" newline eventfld.word 0x0 12. "ABVB,Aggregated Boundary Violation On Channel B" "0: No violation detected,1: Violation detected" newline eventfld.word 0x0 11. "AACB,Aggregated Additional Communication On Channel B" "0: No additional communication detected,1: Additional communication detected" newline eventfld.word 0x0 10. "ACEB,Aggregated Content Error On Channel B" "0: No error detected,1: Errors detected" newline eventfld.word 0x0 9. "ASEB,Aggregated Syntax Error On Channel B" "0: No error detected,1: Errors detected" newline eventfld.word 0x0 8. "AVFB,Aggregated Valid Frame On Channel B" "0: No syntactically valid frames received,1: At least one syntactically valid frame received" newline eventfld.word 0x0 5. "WUA,Wakeup Symbol Received On Channel A" "0: Not received,1: Received" newline eventfld.word 0x0 4. "ABVA,Aggregated Boundary Violation On Channel A" "0: No violation detected,1: Violation detected" newline eventfld.word 0x0 3. "AACA,Aggregated Additional Communication On Channel A" "0: No additional communication detected,1: Additional communication detected" newline eventfld.word 0x0 2. "ACEA,Aggregated Content Error On Channel A" "0: No error detected,1: Errors detected" newline eventfld.word 0x0 1. "ASEA,Aggregated Syntax Error On Channel A" "0: No error detected,1: Errors detected" newline eventfld.word 0x0 0. "AVFA,Aggregated Valid Frame On Channel A" "0: No syntactically valid frames received,1: At least one syntactically valid frame received" rgroup.word 0x30++0xD line.word 0x0 "MTCTR,MT Counter" hexmask.word 0x0 0.--13. 1. "MTCT,MT Counter" line.word 0x2 "CYCTR,Cycle Counter" hexmask.word.byte 0x2 0.--5. 1. "CYCCNT,Cycle Counter" line.word 0x4 "SLTCTAR,Slot Counter Channel A" hexmask.word 0x4 0.--10. 1. "SLOTCNTA,Slot Counter Value For Channel A" line.word 0x6 "SLTCTBR,Slot Counter Channel B" hexmask.word 0x6 0.--10. 1. "SLOTCNTB,Slot Counter Value For Channel B" line.word 0x8 "RTCORVR,Rate Correction Value" hexmask.word 0x8 0.--15. 1. "RATECORR,Rate Correction Value" line.word 0xA "OFCORVR,Offset Correction Value" hexmask.word 0xA 0.--15. 1. "OFFSETCORR,Offset Correction Value" line.word 0xC "CIFR,Combined Interrupt Flag" bitfld.word 0xC 7. "MIF,Module Interrupt Flag" "0: No interrupt source has its interrupt flag equal..,1: At least one interrupt source has its interrupt.." newline bitfld.word 0xC 6. "PRIF,Protocol Interrupt Flag" "0: All individual protocol interrupt flags are 0.,1: At least one of the individual protocol.." newline bitfld.word 0xC 5. "CHIF,CHI Interrupt Flag" "0: All CHI error flags are 0.,1: At least one CHI error flag is 1." newline bitfld.word 0xC 4. "WUPIF,Wakeup Interrupt Flag" "0,1" newline bitfld.word 0xC 3. "FAFBIF,Receive FIFO Channel B Almost Full Interrupt Flag" "0,1" newline bitfld.word 0xC 2. "FAFAIF,Receive FIFO Channel A Almost Full Interrupt Flag" "0,1" newline bitfld.word 0xC 1. "RBIF,Receive MB Interrupt Flag" "0: None of the individual receive MBs have have..,1: At least one individual receive MB has MBIF = 1." newline bitfld.word 0xC 0. "TBIF,Transmit MB Interrupt Flag" "0: None of the individual transmit MBs have MBIF = 1.,1: At least one individual transmit MB has MBIF = 1." group.word 0x3E++0x1 line.word 0x0 "SYMATOR,System Memory Access Timeout" hexmask.word.byte 0x0 0.--7. 1. "TIMEOUT,System Memory Access Timeout" rgroup.word 0x40++0x1 line.word 0x0 "SFCNTR,Sync Frame Counter" hexmask.word.byte 0x0 12.--15. 1. "SFEVB,Sync Frames Channel B Even Cycle" newline hexmask.word.byte 0x0 8.--11. 1. "SFEVA,Sync Frames Channel A Even Cycle" newline hexmask.word.byte 0x0 4.--7. 1. "SFODB,Sync Frames Channel B Odd cycle" newline hexmask.word.byte 0x0 0.--3. 1. "SFODA,Sync Frames Channel A Odd Cycle" group.word 0x42++0x9 line.word 0x0 "SFTOR,Sync Frame Table Offset" hexmask.word 0x0 1.--15. 1. "SFT_OFFSET,Sync Frame Table Offset" line.word 0x2 "SFTCCSR,Sync Frame Table Configuration Control Status" bitfld.word 0x2 15. "ELKT,Even Cycle Tables Lock/Unlock Trigger" "0: No effect,1: Trigger lock and unlock" newline bitfld.word 0x2 14. "OLKT,Odd Cycle Tables Lock And Unlock Trigger" "0: No effect,1: Trigger lock and unlock" newline hexmask.word.byte 0x2 8.--13. 1. "CYCNUM,Cycle Number" newline rbitfld.word 0x2 7. "ELKS,Even Cycle Tables Lock Status" "0: Not locked,1: Locked" newline rbitfld.word 0x2 6. "OLKS,Odd Cycle Tables Lock Status" "0: Not locked,1: Locked" newline rbitfld.word 0x2 5. "EVAL,Even Cycle Tables Valid" "0: Invalid,1: Valid" newline rbitfld.word 0x2 4. "OVAL,Odd Cycle Tables Valid" "0: Invalid,1: Valid" newline bitfld.word 0x2 2. "OPT,One Pair Trigger" "0: Write continuously,1: Write only one pair" newline bitfld.word 0x2 1. "SDVEN,Sync Frame Deviation Table Enable" "0: Do not write sync frame deviation tables,1: Write sync frame deviation tables" newline bitfld.word 0x2 0. "SIDEN,Sync Frame ID Table Enable" "0: Do not write sync frame ID tables,1: Write sync frame ID tables" line.word 0x4 "SFIDRFR,Sync Frame ID Rejection Filter" hexmask.word 0x4 0.--9. 1. "SYNFRID,Sync Frame Rejection ID" line.word 0x6 "SFIDAFVR,Sync Frame ID Acceptance Filter Value" hexmask.word 0x6 0.--9. 1. "FVAL,Filter Value" line.word 0x8 "SFIDAFMR,Sync Frame ID Acceptance Filter Mask" hexmask.word 0x8 0.--9. 1. "FMSK,Filter Mask" repeat 6. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x4C)++0x1 line.word 0x0 "NMVR[$1],NMV n" hexmask.word 0x0 0.--15. 1. "NMVP,NMV Part" repeat.end group.word 0x58++0x9 line.word 0x0 "NMVLR,Network Management Vector Length Register" hexmask.word.byte 0x0 0.--3. 1. "NMVL,Network Management Vector Length" line.word 0x2 "TICCR,Timer Configuration And Control" bitfld.word 0x2 13. "T2_CFG,Timer T2 Configuration" "0: Absolute,1: Relative" newline bitfld.word 0x2 12. "T2_REP,Timer T2 Repetitive Mode" "0: Non-repetitive,1: Repetitive" newline bitfld.word 0x2 10. "T2SP,Timer T2 Stop" "0: No effect,1: Stop" newline bitfld.word 0x2 9. "T2TR,Timer T2 Trigger" "0: No effect,1: Start" newline rbitfld.word 0x2 8. "T2ST,Timer T2 State" "0: Idle,1: Running" newline bitfld.word 0x2 4. "T1_REP,Timer T1 Repetitive Mode" "0: Non-repetitive,1: Repetitive" newline bitfld.word 0x2 2. "T1SP,Timer T1 Stop" "0: No effect,1: Stop" newline bitfld.word 0x2 1. "T1TR,Timer T1 Trigger" "0: No effect,1: Start" newline rbitfld.word 0x2 0. "T1ST,Timer T1 State" "0: Idle,1: Running" line.word 0x4 "TI1CYSR,Timer 1 Cycle Set" hexmask.word.byte 0x4 8.--13. 1. "T1_CYC_VAL,Timer T1 Cycle Filter Value" newline hexmask.word.byte 0x4 0.--5. 1. "T1_CYC_MSK,Timer T1 Cycle Filter Mask" line.word 0x6 "TI1MTOR,Timer 1 MT Offset" hexmask.word 0x6 0.--13. 1. "T1_MTOFFSET,Timer 1 MT Offset" line.word 0x8 "TI2CR0_ABS,Timer 2 Configuration 0 (Absolute Timer Configuration)" hexmask.word.byte 0x8 8.--13. 1. "T2CYCVAL,Timer T2 Cycle Filter Mask" newline hexmask.word.byte 0x8 0.--5. 1. "T2CYCMSK,Timer T2 Cycle Filter Mask" group.word 0x60++0x3 line.word 0x0 "TI2CR0_REL,Timer 2 Configuration 0 (Relative Timer Configuration)" hexmask.word 0x0 0.--15. 1. "T2MTCNT,Timer T2 MT High Word" line.word 0x2 "TI2CR1_ABS,Timer 2 Configuration 1 (Absolute Timer Configuration)" hexmask.word 0x2 0.--13. 1. "T2MOFF,Timer T2 MT Offset" group.word 0x62++0x5 line.word 0x0 "TI2CR1_REL,Timer 2 Configuration 1 (Relative Timer Configuration)" hexmask.word 0x0 0.--15. 1. "T2MTCNT,Timer T2 Macrotick Low Word" line.word 0x2 "SSSR,Slot Status Selection" bitfld.word 0x2 15. "WMD,Write Mode" "0: All fields,1: Only the SEL field" newline bitfld.word 0x2 12.--13. "SEL,Selector" "0: SSSR0,1: SSSR1,2: SSSR2,3: SSSR3" newline hexmask.word 0x2 0.--10. 1. "SLOTNUMBER,Slot Number" line.word 0x4 "SSCCR,Slot Status Counter Condition" bitfld.word 0x4 15. "WMD,Write Mode" "0: All fields,1: Only the SEL field" newline bitfld.word 0x4 12.--13. "SEL,Selector" "0: SSCCR0,1: SSCCR1,2: SSCCR2,3: SSCCR3" newline bitfld.word 0x4 9.--10. "CNTCFG,Counter Configuration" "0: Increment by 1 if condition is fulfilled on..,1: Increment by 1 if condition is fulfilled on..,2: Increment by 1 if condition is fulfilled on at..,3: Increment by 2 if condition is fulfilled on both.." newline bitfld.word 0x4 8. "MCY,Multi Cycle Selection" "0: Only for the previous communication cycle,1: Over multiple communication cycles" newline bitfld.word 0x4 7. "VFR,Valid Frame Restriction" "0: Not restricted,1: Restricted" newline bitfld.word 0x4 6. "SYF,Sync Frame Restriction" "0: Not restricted,1: Restricted" newline bitfld.word 0x4 5. "NUF,Null Frame Restriction" "0: Not restricted,1: Restricted" newline bitfld.word 0x4 4. "SUF,Startup Frame Restriction" "0: Not restricted,1: Restricted" newline hexmask.word.byte 0x4 0.--3. 1. "STATUSMASK,Slot Status Mask" repeat 8. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x68)++0x1 line.word 0x0 "SSR[$1],Slot Status" bitfld.word 0x0 15. "VFB,Valid Frame On Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x0 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x0 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x0 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x0 11. "SEB,Syntax Error On Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x0 10. "CEB,Content Error On Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x0 9. "BVB,Boundary Violation On Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x0 8. "TCB,Transmission Conflict On Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" newline bitfld.word 0x0 7. "VFA,Valid Frame On Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1" newline bitfld.word 0x0 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1" newline bitfld.word 0x0 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1" newline bitfld.word 0x0 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1" newline bitfld.word 0x0 3. "SEA,Syntax Error On Channel A" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1" newline bitfld.word 0x0 2. "CEA,Content Error On Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1" newline bitfld.word 0x0 1. "BVA,Boundary Violation On Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1" newline bitfld.word 0x0 0. "TCA,Transmission Conflict On Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x78)++0x1 line.word 0x0 "SSCR[$1],Slot Status Counter" hexmask.word 0x0 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter" repeat.end group.word 0x80++0xB line.word 0x0 "MTSACFR,MTS A Configuration" bitfld.word 0x0 15. "MTE,MTS Transmission Enable" "0: Disable,1: Enable" newline hexmask.word.byte 0x0 8.--13. 1. "CYCCNTMSK,Cycle Counter Mask" newline hexmask.word.byte 0x0 0.--5. 1. "CYCCNTVAL,Cycle Counter Value" line.word 0x2 "MTSBCFR,MTS B Configuration" bitfld.word 0x2 15. "MTE,MTS Transmission Enable" "0: Disable,1: Enable" newline hexmask.word.byte 0x2 8.--13. 1. "CYCCNTMSK,Cycle Counter Mask" newline hexmask.word.byte 0x2 0.--5. 1. "CYCCNTVAL,Cycle Counter Value" line.word 0x4 "RSBIR,Receive Shadow Buffer Index" bitfld.word 0x4 15. "WMD,Write Mode" "0: Update SEL and RSBIDX field on register write,1: Update only SEL field on register write" newline bitfld.word 0x4 12.--13. "SEL,Selector" "0: RSBIR_A1-receive shadow buffer index register..,1: RSBIR_A2-receive shadow buffer index register..,2: RSBIR_B1-receive shadow buffer index register..,3: RSBIR_B2-receive shadow buffer index register.." newline hexmask.word 0x4 0.--8. 1. "RSBIDX,RSBIDXA1/RSBIDXA2/RSBIDXB1/RSBIDXB2- Receive Shadow Buffer Index" line.word 0x6 "RFWMSR,Receive FIFO Watermark And Selection" hexmask.word.byte 0x6 8.--15. 1. "WM,WMA/WMB - Watermark" newline bitfld.word 0x6 0. "SEL,Select" "0: Channel A,1: Channel B" line.word 0x8 "RFSIR,Receive FIFO Start Index" hexmask.word 0x8 0.--9. 1. "SIDX,SIDXA Or SIDXB Start Index" line.word 0xA "RFDSR,Receive FIFO Depth And Size" hexmask.word.byte 0xA 8.--15. 1. "FIFO_DEPTH,FIFO_DEPTHA And FIFO_DEPTHB FIFO Depth" newline hexmask.word.byte 0xA 0.--6. 1. "ENTRY_SIZE,ENTRY_SIZEA Or ENTRY_SIZEB Entry Size" rgroup.word 0x8C++0x3 line.word 0x0 "RFARIR,Receive FIFO A Read Index" hexmask.word 0x0 0.--9. 1. "RDIDX,Read Index" line.word 0x2 "RFBRIR,Receive FIFO B Read Index" hexmask.word 0x2 0.--9. 1. "RDIDX,Read Index" group.word 0x90++0xB line.word 0x0 "RFMIDAFVR,Receive FIFO Message ID Acceptance Filter Value" hexmask.word 0x0 0.--15. 1. "MIDAFVAL,MIDAFVALA Or MIDAFVALB Message ID Acceptance Filter Value" line.word 0x2 "RFMIDAFMR,Receive FIFO Message ID Acceptance Filter Mask" hexmask.word 0x2 0.--15. 1. "MIDAFMSK,MIDAFMSKA Or MIDAFMSKB Message ID Acceptance Filter Mask" line.word 0x4 "RFFIDRFVR,Receive FIFO Frame ID Rejection Filter Value" hexmask.word 0x4 0.--10. 1. "FIDRFVAL,FIDRFVALA Or FIDRFVALB Frame ID Rejection Filter Value" line.word 0x6 "RFFIDRFMR,Receive FIFO Frame ID Rejection Filter Mask" hexmask.word 0x6 0.--10. 1. "FIDRFMSK,Frame ID Rejection Filter Mask" line.word 0x8 "RFRFCFR,Receive FIFO Range Filter Configuration" bitfld.word 0x8 15. "WMD,Write Mode" "0: Write to all fields in this register on a write..,1: Write only to the SEL and IBD fields on write.." newline bitfld.word 0x8 14. "IBD,Interval Boundary" "0: Lower,1: Upper" newline bitfld.word 0x8 12.--13. "SEL,Filter Selector" "0: Filter 0,1: Filter 1,2: Filter 2,3: Filter 3" newline hexmask.word 0x8 0.--10. 1. "SID,Slot ID" line.word 0xA "RFRFCTR,Receive FIFO Range Filter Control" bitfld.word 0xA 11. "F3MD,Range Filter 3 Mode" "0: Acceptance,1: Rejection" newline bitfld.word 0xA 10. "F2MD,Range Filter 2 Mode" "0: Acceptance,1: Rejection" newline bitfld.word 0xA 9. "F1MD,Range Filter 1 Mode" "0: Acceptance,1: Rejection" newline bitfld.word 0xA 8. "F0MD,Range Filter 0 Mode" "0: Acceptance,1: Rejection" newline bitfld.word 0xA 3. "F3EN,Range Filter 3 Enable" "0: Disabled,1: Enabled" newline bitfld.word 0xA 2. "F2EN,Range Filter 2 Enable" "0: Disabled,1: Enabled" newline bitfld.word 0xA 1. "F1EN,Range Filter 1 Enable" "0: Disabled,1: Enabled" newline bitfld.word 0xA 0. "F0EN,Range Filter 0 Enable" "0: Disabled,1: Enabled" rgroup.word 0x9C++0x3 line.word 0x0 "LDTXSLAR,Last Dynamic Transmit Slot Channel A" hexmask.word 0x0 0.--10. 1. "LDYNTXSLOTA,Last Dynamic Transmission Slot Channel A" line.word 0x2 "LDTXSLBR,Last Dynamic Transmit Slot Channel B" hexmask.word 0x2 0.--10. 1. "LDYNTXSLOTB,Last Dynamic Transmission Slot Channel B" group.word 0xA0++0x43 line.word 0x0 "PCR0,Protocol Configuration 0" hexmask.word.byte 0x0 10.--15. 1. "action_point_offset,action_point_offset" newline hexmask.word 0x0 0.--9. 1. "static_slot_length,static_slot_length" line.word 0x2 "PCR1,Protocol Configuration 1" hexmask.word 0x2 0.--13. 1. "macro_after_first_static_slot,macro_after_first_static_slot" line.word 0x4 "PCR2,Protocol Configuration 2" hexmask.word.byte 0x4 10.--15. 1. "minislot_after_action_point,minislot_after_action_point" newline hexmask.word 0x4 0.--9. 1. "number_of_static_slots,gNumberOfStaticSlots" line.word 0x6 "PCR3,Protocol Configuration 3" hexmask.word.byte 0x6 10.--15. 1. "wakeup_symbol_rx_low,wakeup_symbol_rx_low" newline hexmask.word.byte 0x6 5.--9. 1. "minislot_action_point_offset,minislot_action_point_offset" newline hexmask.word.byte 0x6 0.--4. 1. "coldstart_attempts,coldstart_attempts" line.word 0x8 "PCR4,Protocol Configuration 4" hexmask.word.byte 0x8 9.--15. 1. "cas_rx_low_max,cas_rx_low_max" newline hexmask.word 0x8 0.--8. 1. "wakeup_symbol_rx_window,wakeup_symbol_rx_window" line.word 0xA "PCR5,Protocol Configuration 5" hexmask.word.byte 0xA 12.--15. 1. "tss_transmitter,tss_transmitter" newline hexmask.word.byte 0xA 6.--11. 1. "wakeup_symbol_tx_low,wakeup_symbol_tx_low" newline hexmask.word.byte 0xA 0.--5. 1. "wakeup_symbol_rx_idle,wakeup_symbol_rx_idle" line.word 0xC "PCR6,Protocol Configuration 6" hexmask.word.byte 0xC 7.--14. 1. "symbol_window_after_action_point,symbol_window_after_action_point" newline hexmask.word.byte 0xC 0.--6. 1. "macro_initial_offset_a,macro_initial_offset_a" line.word 0xE "PCR7,Protocol Configuration 7" hexmask.word 0xE 7.--15. 1. "decoding_correction_b,decoding_correction_b" newline hexmask.word.byte 0xE 0.--6. 1. "micro_per_macro_nom_half,micro_per_macro_nom_half" line.word 0x10 "PCR8,Protocol Configuration 8" hexmask.word.byte 0x10 12.--15. 1. "max_without_clock_correction_fatal,max_without_clock_correction_fatal" newline hexmask.word.byte 0x10 8.--11. 1. "max_without_clock_correction_passive,max_without_clock_correction_passive" newline hexmask.word.byte 0x10 0.--7. 1. "wakeup_symbol_tx_idle,wakeup_symbol_tx_idle" line.word 0x12 "PCR9,Protocol Configuration 9" bitfld.word 0x12 15. "minislot_exists,minislot_exists" "0,1" newline bitfld.word 0x12 14. "symbol_window_exists,symbol_window_exists" "0,1" newline hexmask.word 0x12 0.--13. 1. "offset_correction_out,offset_correction_out" line.word 0x14 "PCR10,Protocol Configuration 10" bitfld.word 0x14 15. "single_slot_enabled,single_slot_enabled" "0,1" newline bitfld.word 0x14 14. "wakeup_channel,wakeup_channel" "0,1" newline hexmask.word 0x14 0.--13. 1. "macro_per_cycle,macro_per_cycle" line.word 0x16 "PCR11,Protocol Configuration 11" bitfld.word 0x16 15. "key_slot_used_for_startup,key_slot_used_for_startup" "0,1" newline bitfld.word 0x16 14. "key_slot_used_for_sync,key_slot_used_for_sync" "0,1" newline hexmask.word 0x16 0.--13. 1. "offset_correction_start,offset_correction_start" line.word 0x18 "PCR12,Protocol Configuration 12" hexmask.word.byte 0x18 11.--15. 1. "allow_passive_to_active,allow_passive_to_active" newline hexmask.word 0x18 0.--10. 1. "key_slot_header_crc,key_slot_header_crc" line.word 0x1A "PCR13,Protocol Configuration 13" hexmask.word.byte 0x1A 10.--15. 1. "first_minislot_action_point_offset,first_minislot_action_point_offset" newline hexmask.word 0x1A 0.--9. 1. "static_slot_after_action_point,static_slot_after_action_point" line.word 0x1C "PCR14,Protocol Configuration 14" hexmask.word 0x1C 5.--15. 1. "rate_correction_out,rate_correction_out" newline hexmask.word.byte 0x1C 0.--4. 1. "listen_timeout,listen_timeout" line.word 0x1E "PCR15,Protocol Configuration 15" hexmask.word 0x1E 0.--15. 1. "listen_timeout,listen_timeout" line.word 0x20 "PCR16,Protocol Configuration 16" hexmask.word.byte 0x20 9.--15. 1. "macro_initial_offset_b,macro_initial_offset_b" newline hexmask.word 0x20 0.--8. 1. "noise_listen_timeout,noise_listen_timeout" line.word 0x22 "PCR17,Protocol Configuration 17" hexmask.word 0x22 0.--15. 1. "noise_listen_timeout,noise_listen_timeout" line.word 0x24 "PCR18,Protocol Configuration 18" hexmask.word.byte 0x24 10.--15. 1. "wakeup_pattern,wakeup_pattern" newline hexmask.word 0x24 0.--9. 1. "key_slot_id,key_slot_id" line.word 0x26 "PCR19,Protocol Configuration 19" hexmask.word 0x26 7.--15. 1. "decoding_correction_a,decoding_correction_a" newline hexmask.word.byte 0x26 0.--6. 1. "payload_length_static,payload_length_static" line.word 0x28 "PCR20,Protocol Configuration 20" hexmask.word.byte 0x28 8.--15. 1. "micro_initial_offset_b,micro_initial_offset_b" newline hexmask.word.byte 0x28 0.--7. 1. "micro_initial_offset_a,micro_initial_offset_a" line.word 0x2A "PCR21,Protocol Configuration 21" bitfld.word 0x2A 13.--15. "extern_rate_correction,extern_rate_correction" "0,1,2,3,4,5,6,7" newline hexmask.word 0x2A 0.--12. 1. "latest_tx,latest_tx" line.word 0x2C "PCR22,Protocol Configuration 22" hexmask.word 0x2C 4.--14. 1. "comp_accepted_startup_range_a,comp_accepted_startup_range_a" newline hexmask.word.byte 0x2C 0.--3. 1. "micro_per_cycle,micro_per_cycle" line.word 0x2E "PCR23,Protocol Configuration 23" hexmask.word 0x2E 0.--15. 1. "micro_per_cycle,micro_per_cycle" line.word 0x30 "PCR24,Protocol Configuration 24" hexmask.word.byte 0x30 11.--15. 1. "cluster_drift_damping,cluster_drift_damping" newline hexmask.word.byte 0x30 4.--10. 1. "max_payload_length_dynamic,max_payload_length_dynamic" newline hexmask.word.byte 0x30 0.--3. 1. "micro_per_cycle_min,micro_per_cycle_min" line.word 0x32 "PCR25,Protocol Configuration 25" hexmask.word 0x32 0.--15. 1. "micro_per_cycle_min,micro_per_cycle_min" line.word 0x34 "PCR26,Protocol Configuration 26" bitfld.word 0x34 15. "allow_halt_due_to_clock,allow_halt_due_to_clock" "0,1" newline hexmask.word 0x34 4.--14. 1. "comp_accepted_startup_range_b,comp_accepted_startup_range_b" newline hexmask.word.byte 0x34 0.--3. 1. "micro_per_cycle_max,micro_per_cycle_max" line.word 0x36 "PCR27,Protocol Configuration 27" hexmask.word 0x36 0.--15. 1. "micro_per_cycle_max,micro_per_cycle_max" line.word 0x38 "PCR28,Protocol Configuration 28" bitfld.word 0x38 14.--15. "dynamic_slot_idle_phase,dynamic_slot_idle_phase" "0,1,2,3" newline hexmask.word 0x38 0.--13. 1. "macro_after_offset_correction,macro_after_offset_correction" line.word 0x3A "PCR29,Protocol Configuration 29" bitfld.word 0x3A 13.--15. "extern_offset_correction,extern_offset_correction" "0,1,2,3,4,5,6,7" newline hexmask.word 0x3A 0.--12. 1. "minislots_max,minislots_max" line.word 0x3C "PCR30,Protocol Configuration 30" hexmask.word.byte 0x3C 0.--3. 1. "sync_node_max,sync_node_max" line.word 0x3E "STPWHR,Stopwatch Count High" hexmask.word 0x3E 0.--15. 1. "STPW_S_H,Stopwatch Count High" line.word 0x40 "STPWLR,Stopwatch Count Low" hexmask.word 0x40 0.--15. 1. "STPW_S_L,Stopwatch Count Low" line.word 0x42 "PEOER,Protocol Event Output Enable And Stopwatch Control" bitfld.word 0x42 8. "STPW_EN,Stopwatch Count Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x42 2. "TIM2_EE,Timer 2 Expired Event Output Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x42 1. "TIM1_EE,Timer 1 Expired Event Output Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x42 0. "CYC_EE,Cycle Start Event Output Enable" "0: Disabled,1: Enabled" group.word 0xE6++0xD line.word 0x0 "RFSDOR,Receive FIFO Start Data Offset" hexmask.word 0x0 0.--15. 1. "SDO,SDOA And SDOB Start Data Field Offset" line.word 0x2 "RFSYMBADHR,Receive FIFO System Memory Base Address High" hexmask.word 0x2 0.--15. 1. "SMBA,System Memory Base Address" line.word 0x4 "RFSYMBADLR,Receive FIFO System Memory Base Address Low" hexmask.word 0x4 4.--15. 1. "SMBA,System Memory Base Address" line.word 0x6 "RFPTR,Receive FIFO Periodic Timer" hexmask.word 0x6 0.--13. 1. "PTD,Periodic Timer Duration" line.word 0x8 "RFFLPCR,Receive FIFO Fill Level and Pop Count" hexmask.word.byte 0x8 8.--15. 1. "FLB_or_PCB,FLB Or PCB" newline hexmask.word.byte 0x8 0.--7. 1. "FLA_or_PCA,FLA Or PCA" line.word 0xA "EEIFER,ECC Error Interrupt Flag And Enable" eventfld.word 0xA 15. "LRNE_OF,LRAM Non-Corrected Error Overflow Flag" "0: No such event,1: Non-corrected error overflow detected on CHI LRAM" newline eventfld.word 0xA 14. "LRCE_OF,LRAM Corrected Error Overflow Flag" "0: No such event,1: Corrected error overflow detected on CHI LRAM" newline eventfld.word 0xA 13. "DRNE_OF,DRAM Non-Corrected Error Overflow Flag" "0: No such event,1: Non-corrected error overflow detected on PE DRAM" newline eventfld.word 0xA 12. "DRCE_OF,DRAM Corrected Error Overflow Flag" "0: No such event,1: Corrected error overflow detected on PE DRAM" newline eventfld.word 0xA 11. "LRNE_IF,LRAM Non-Corrected Error Interrupt Flag" "0: No such event,1: Non-corrected error detected on CHI LRAM" newline eventfld.word 0xA 10. "LRCE_IF,LRAM Corrected Error Interrupt Flag" "0: No such event,1: Corrected error detected on CHI LRAM" newline eventfld.word 0xA 9. "DRNE_IF,DRAM Non-Corrected Error Interrupt Flag" "0: No such event,1: Non-corrected error detected on PE DRAM" newline eventfld.word 0xA 8. "DRCE_IF,DRAM Corrected Error Interrupt Flag" "0: No such event,1: Corrected error detected on PE DRAM" newline bitfld.word 0xA 3. "LRNE_IE,LRAM Non-Corrected Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 2. "LRCE_IE,LRAM Corrected Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 1. "DRNE_IE,DRAM Non-Corrected Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.word 0xA 0. "DRCE_IE,DRAM Corrected Error Interrupt Enable" "0: Disable,1: Enable" line.word 0xC "EERICR,ECC Error Report And Injection Control" rbitfld.word 0xC 15. "BSY,Register Update Busy" "0: Idle,1: Running" newline bitfld.word 0xC 8.--9. "ERS,Error Report Select" "0: Show PE DRAM noncorrected error information.,1: Show PE DRAM corrected error information.,2: Show CHI LRAM noncorrected error information.,3: Show CHI LRAM corrected error information." newline bitfld.word 0xC 4. "ERM,Error Report Mode" "0: Store data and code as delivered by ECC decoding..,1: Store data and code as read from the memory." newline bitfld.word 0xC 1. "EIM,Error Injection Mode" "0: Use EEIDR[DATA] and EEICR[CODE] as XOR..,1: Use EEIDR[DATA] and EEICR[CODE] as write value.." newline bitfld.word 0xC 0. "EIE,Error Injection Enable" "0: Disabled,1: Enabled" rgroup.word 0xF4++0x5 line.word 0x0 "EERAR,ECC Error Report Address" bitfld.word 0x0 15. "MID,Memory Identifier" "0: PE DRAM,1: CHI LRAM" newline bitfld.word 0x0 12.--14. "BANK,Memory Bank" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--11. 1. "ADDR,Memory Address" line.word 0x2 "EERDR,ECC Error Report Data" hexmask.word 0x2 0.--15. 1. "DATA,Data" line.word 0x4 "EERCR,ECC Error Report Code" hexmask.word.byte 0x4 0.--4. 1. "CODE,Code" group.word 0xFA++0x5 line.word 0x0 "EEIAR,ECC Error Injection Address" bitfld.word 0x0 15. "MID,Memory Identifier" "0: PE DRAM,1: CHI LRAM" newline bitfld.word 0x0 12.--14. "BANK,Memory Bank" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--11. 1. "ADDR,Memory Address" line.word 0x2 "EEIDR,ECC Error Injection Data" hexmask.word 0x2 0.--15. 1. "DATA,Data" line.word 0x4 "EEICR,ECC Error Injection Code" hexmask.word.byte 0x4 0.--4. 1. "CODE,Code" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x402F8800 ad:0x402F8808 ad:0x402F8810 ad:0x402F8818 ad:0x402F8820 ad:0x402F8828 ad:0x402F8830 ad:0x402F8838 ad:0x402F8840 ad:0x402F8848 ad:0x402F8850 ad:0x402F8858 ad:0x402F8860 ad:0x402F8868 ad:0x402F8870 ad:0x402F8878) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x402F8880 ad:0x402F8888 ad:0x402F8890 ad:0x402F8898 ad:0x402F88A0 ad:0x402F88A8 ad:0x402F88B0 ad:0x402F88B8 ad:0x402F88C0 ad:0x402F88C8 ad:0x402F88D0 ad:0x402F88D8 ad:0x402F88E0 ad:0x402F88E8 ad:0x402F88F0 ad:0x402F88F8) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x402F8900 ad:0x402F8908 ad:0x402F8910 ad:0x402F8918 ad:0x402F8920 ad:0x402F8928 ad:0x402F8930 ad:0x402F8938 ad:0x402F8940 ad:0x402F8948 ad:0x402F8950 ad:0x402F8958 ad:0x402F8960 ad:0x402F8968 ad:0x402F8970 ad:0x402F8978) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x402F8980 ad:0x402F8988 ad:0x402F8990 ad:0x402F8998 ad:0x402F89A0 ad:0x402F89A8 ad:0x402F89B0 ad:0x402F89B8 ad:0x402F89C0 ad:0x402F89C8 ad:0x402F89D0 ad:0x402F89D8 ad:0x402F89E0 ad:0x402F89E8 ad:0x402F89F0 ad:0x402F89F8) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x402F8A00 ad:0x402F8A08 ad:0x402F8A10 ad:0x402F8A18 ad:0x402F8A20 ad:0x402F8A28 ad:0x402F8A30 ad:0x402F8A38 ad:0x402F8A40 ad:0x402F8A48 ad:0x402F8A50 ad:0x402F8A58 ad:0x402F8A60 ad:0x402F8A68 ad:0x402F8A70 ad:0x402F8A78) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list ad:0x402F8A80 ad:0x402F8A88 ad:0x402F8A90 ad:0x402F8A98 ad:0x402F8AA0 ad:0x402F8AA8 ad:0x402F8AB0 ad:0x402F8AB8 ad:0x402F8AC0 ad:0x402F8AC8 ad:0x402F8AD0 ad:0x402F8AD8 ad:0x402F8AE0 ad:0x402F8AE8 ad:0x402F8AF0 ad:0x402F8AF8) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list ad:0x402F8B00 ad:0x402F8B08 ad:0x402F8B10 ad:0x402F8B18 ad:0x402F8B20 ad:0x402F8B28 ad:0x402F8B30 ad:0x402F8B38 ad:0x402F8B40 ad:0x402F8B48 ad:0x402F8B50 ad:0x402F8B58 ad:0x402F8B60 ad:0x402F8B68 ad:0x402F8B70 ad:0x402F8B78) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list ad:0x402F8B80 ad:0x402F8B88 ad:0x402F8B90 ad:0x402F8B98 ad:0x402F8BA0 ad:0x402F8BA8 ad:0x402F8BB0 ad:0x402F8BB8 ad:0x402F8BC0 ad:0x402F8BC8 ad:0x402F8BD0 ad:0x402F8BD8 ad:0x402F8BE0 ad:0x402F8BE8 ad:0x402F8BF0 ad:0x402F8BF8) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F)(list ad:0x402F8C00 ad:0x402F8C08 ad:0x402F8C10 ad:0x402F8C18 ad:0x402F8C20 ad:0x402F8C28 ad:0x402F8C30 ad:0x402F8C38 ad:0x402F8C40 ad:0x402F8C48 ad:0x402F8C50 ad:0x402F8C58 ad:0x402F8C60 ad:0x402F8C68 ad:0x402F8C70 ad:0x402F8C78) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F)(list ad:0x402F8C80 ad:0x402F8C88 ad:0x402F8C90 ad:0x402F8C98 ad:0x402F8CA0 ad:0x402F8CA8 ad:0x402F8CB0 ad:0x402F8CB8 ad:0x402F8CC0 ad:0x402F8CC8 ad:0x402F8CD0 ad:0x402F8CD8 ad:0x402F8CE0 ad:0x402F8CE8 ad:0x402F8CF0 ad:0x402F8CF8) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF)(list ad:0x402F8D00 ad:0x402F8D08 ad:0x402F8D10 ad:0x402F8D18 ad:0x402F8D20 ad:0x402F8D28 ad:0x402F8D30 ad:0x402F8D38 ad:0x402F8D40 ad:0x402F8D48 ad:0x402F8D50 ad:0x402F8D58 ad:0x402F8D60 ad:0x402F8D68 ad:0x402F8D70 ad:0x402F8D78) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF)(list ad:0x402F8D80 ad:0x402F8D88 ad:0x402F8D90 ad:0x402F8D98 ad:0x402F8DA0 ad:0x402F8DA8 ad:0x402F8DB0 ad:0x402F8DB8 ad:0x402F8DC0 ad:0x402F8DC8 ad:0x402F8DD0 ad:0x402F8DD8 ad:0x402F8DE0 ad:0x402F8DE8 ad:0x402F8DF0 ad:0x402F8DF8) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF)(list ad:0x402F8E00 ad:0x402F8E08 ad:0x402F8E10 ad:0x402F8E18 ad:0x402F8E20 ad:0x402F8E28 ad:0x402F8E30 ad:0x402F8E38 ad:0x402F8E40 ad:0x402F8E48 ad:0x402F8E50 ad:0x402F8E58 ad:0x402F8E60 ad:0x402F8E68 ad:0x402F8E70 ad:0x402F8E78) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF)(list ad:0x402F8E80 ad:0x402F8E88 ad:0x402F8E90 ad:0x402F8E98 ad:0x402F8EA0 ad:0x402F8EA8 ad:0x402F8EB0 ad:0x402F8EB8 ad:0x402F8EC0 ad:0x402F8EC8 ad:0x402F8ED0 ad:0x402F8ED8 ad:0x402F8EE0 ad:0x402F8EE8 ad:0x402F8EF0 ad:0x402F8EF8) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF)(list ad:0x402F8F00 ad:0x402F8F08 ad:0x402F8F10 ad:0x402F8F18 ad:0x402F8F20 ad:0x402F8F28 ad:0x402F8F30 ad:0x402F8F38 ad:0x402F8F40 ad:0x402F8F48 ad:0x402F8F50 ad:0x402F8F58 ad:0x402F8F60 ad:0x402F8F68 ad:0x402F8F70 ad:0x402F8F78) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF)(list ad:0x402F8F80 ad:0x402F8F88 ad:0x402F8F90 ad:0x402F8F98 ad:0x402F8FA0 ad:0x402F8FA8 ad:0x402F8FB0 ad:0x402F8FB8 ad:0x402F8FC0 ad:0x402F8FC8 ad:0x402F8FD0 ad:0x402F8FD8 ad:0x402F8FE0 ad:0x402F8FE8 ad:0x402F8FF0 ad:0x402F8FF8) tree "MB[$1]" base $2 group.word ($2)++0x7 line.word 0x0 "MBCCSR,MB Configuration Control Status" bitfld.word 0x0 12. "MTD,MB Transfer Direction" "0: Receive MB,1: Transmit MB" bitfld.word 0x0 11. "CMT,Commit To Transmission" "0: Not ready,1: Ready" newline bitfld.word 0x0 10. "EDT,Enable And Disable Trigger" "0: No effect,1: MB enable or disable is triggered" bitfld.word 0x0 9. "LCKT,Lock And Unlock Trigger" "0: No effect,1: MB lock or unlock is triggered" newline bitfld.word 0x0 8. "MBIE,MB Interrupt Enable" "0: Disabled,1: Enabled" rbitfld.word 0x0 4. "DUP,Data Updated" "0: Not updated,1: Updated" newline rbitfld.word 0x0 3. "DVAL,Data Valid" "0: Receive MB contains no valid frame data or..,1: Receive MB contains valid frame data or message.." rbitfld.word 0x0 2. "EDS,Enable And Disable Status" "0: Disabled,1: Enabled" newline rbitfld.word 0x0 1. "LCKS,Lock Status" "0: You have not locked the MB,1: You have locked the MB" eventfld.word 0x0 0. "MBIF,MB Interrupt Flag" "0: No such event,1: Slot status field updated or transmit MB just.." line.word 0x2 "MBCCFR,MB Cycle Counter Filter" bitfld.word 0x2 15. "MTM,MB Transmission Mode" "0: Event,1: State" bitfld.word 0x2 14. "CHA,Channel Assignment A" "0,1" newline bitfld.word 0x2 13. "CHB,Channel Assignment B" "0,1" bitfld.word 0x2 12. "CCFE,Cycle Counter Filtering Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x2 6.--11. 1. "CCFMSK,Cycle Counter Filtering Mask" hexmask.word.byte 0x2 0.--5. 1. "CCFVAL,Cycle Counter Filtering Value" line.word 0x4 "MBFIDR,MB FID" hexmask.word 0x4 0.--10. 1. "FID,FID" line.word 0x6 "MBIDXR,MB Index" hexmask.word 0x6 0.--8. 1. "MBIDX,MB Index" tree.end repeat.end base ad:0x402F8000 repeat 260. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x1000)++0x1 line.word 0x0 "MBDOR[$1],MB Data Field Offset" hexmask.word 0x0 0.--15. 1. "MBDO,MB Data Field Offset" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x1210)++0x1 line.word 0x0 "LEETR[$1],LRAM ECC Error Test Register" hexmask.word 0x0 0.--15. 1. "LEETD,LRAM ECC Error Test Data" repeat.end tree.end tree "FLEXTIMER" base ad:0x0 tree "FTM_0" base ad:0x401F4000 group.long 0x0++0xB line.long 0x0 "SC,Status And Control" hexmask.long.byte 0x0 24.--27. 1. "FLTPS,Filter Prescaler" bitfld.long 0x0 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." newline bitfld.long 0x0 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." bitfld.long 0x0 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." newline bitfld.long 0x0 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." bitfld.long 0x0 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." newline bitfld.long 0x0 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." bitfld.long 0x0 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed.,1: FTM counter has overflowed." newline bitfld.long 0x0 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts. Use software polling.,1: Enable TOF interrupts. An interrupt is generated.." bitfld.long 0x0 7. "RF,Reload Flag" "0: A selected reload point did not happen.,1: A selected reload point happened." newline bitfld.long 0x0 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled.,1: Reload point interrupt is enabled." bitfld.long 0x0 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode.,1: FTM counter operates in Up-Down Counting mode." newline bitfld.long 0x0 3.--4. "CLKS,Clock Source Selection" "0: No clock selected. This in effect disables the..,1: FTM input clock,2: Fixed frequency clock,3: External clock" bitfld.long 0x0 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" line.long 0x4 "CNT,Counter" hexmask.long.word 0x4 0.--15. 1. "COUNT,Counter Value" line.long 0x8 "MOD,Modulo" hexmask.long.word 0x8 0.--15. 1. "MOD,MOD" repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x401F400C ad:0x401F4014 ad:0x401F401C ad:0x401F4024 ad:0x401F402C ad:0x401F4034) tree "CONTROLS[$1]" base $2 group.long ($2)++0x7 line.long 0x0 "CSC,Channel (n) Status And Control" rbitfld.long 0x0 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero.,1: The channel (n) output is one." rbitfld.long 0x0 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero.,1: The channel (n) input is one." newline bitfld.long 0x0 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.." bitfld.long 0x0 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred.,1: A channel (n) event has occurred." newline bitfld.long 0x0 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt. Use software..,1: Enable channel (n) interrupt." bitfld.long 0x0 5. "MSB,Channel (n) Mode Select" "0,1" newline bitfld.long 0x0 4. "MSA,Channel (n) Mode Select" "0,1" bitfld.long 0x0 3. "ELSB,Channel (n) Edge or Level Select" "0,1" newline bitfld.long 0x0 2. "ELSA,Channel (n) Edge or Level Select" "0,1" bitfld.long 0x0 1. "ICRST,FTM counter reset by the selected input capture event." "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected channel.." newline bitfld.long 0x0 0. "DMA,DMA Enable" "0: Disable DMA transfers.,1: Enable DMA transfers." line.long 0x4 "CV,Channel (n) Value" hexmask.long.word 0x4 0.--15. 1. "VAL,Channel Value" tree.end repeat.end base ad:0x401F4000 group.long 0x4C++0x2F line.long 0x0 "CNTIN,Counter Initial Value" hexmask.long.word 0x0 0.--15. 1. "INIT,INIT" line.long 0x4 "STATUS,Capture And Compare Status" bitfld.long 0x4 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred.,1: A channel event has occurred." bitfld.long 0x4 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred.,1: A channel event has occurred." newline bitfld.long 0x4 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred.,1: A channel event has occurred." bitfld.long 0x4 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred.,1: A channel event has occurred." newline bitfld.long 0x4 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred.,1: A channel event has occurred." bitfld.long 0x4 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred.,1: A channel event has occurred." line.long 0x8 "MODE,Features Mode Selection" bitfld.long 0x8 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled.,1: Capture test mode is enabled." bitfld.long 0x8 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions. Software and hardware triggers..,1: Software trigger can only be used by MOD and CnV.." newline bitfld.long 0x8 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled.,1: Write protection is disabled." bitfld.long 0x8 1. "INIT,Initialize The Channels Output" "0,1" newline bitfld.long 0x8 0. "FTMEN,FTM Enable" "0: TPM compatibility. Free running counter and..,1: Free running counter and synchronization are.." line.long 0xC "SYNC,Synchronization" bitfld.long 0xC 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected.,1: Software trigger is selected." bitfld.long 0xC 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled.,1: Trigger is enabled." newline bitfld.long 0xC 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled.,1: Trigger is enabled." bitfld.long 0xC 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled.,1: Trigger is enabled." newline bitfld.long 0xC 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.." bitfld.long 0xC 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally.,1: FTM counter is updated with its initial value.." newline bitfld.long 0xC 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled.,1: The maximum loading point is enabled." bitfld.long 0xC 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled.,1: The minimum loading point is enabled." line.long 0x10 "OUTINIT,Initial State For Channels Output" bitfld.long 0x10 5. "CH5OI,Channel 5 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." bitfld.long 0x10 4. "CH4OI,Channel 4 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." newline bitfld.long 0x10 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." bitfld.long 0x10 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." newline bitfld.long 0x10 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." bitfld.long 0x10 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." line.long 0x14 "OUTMASK,Output Mask" bitfld.long 0x14 5. "CH5OM,Channel 5 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." bitfld.long 0x14 4. "CH4OM,Channel 4 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." newline bitfld.long 0x14 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." bitfld.long 0x14 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." newline bitfld.long 0x14 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." bitfld.long 0x14 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." line.long 0x18 "COMBINE,Function For Linked Channels" bitfld.long 0x18 23. "MCOMBINE2,Modified Combine Mode For n = 4" "0,1" bitfld.long 0x18 21. "SYNCEN2,Synchronization Enable For n = 4" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.." newline bitfld.long 0x18 20. "DTEN2,Deadtime Enable For n = 4" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.." bitfld.long 0x18 19. "DECAP2,Dual Edge Capture Mode Captures For n = 4" "0: The dual edge captures are inactive.,1: The dual edge captures are active." newline bitfld.long 0x18 18. "DECAPEN2,Dual Edge Capture Mode Enable For n = 4" "0,1" bitfld.long 0x18 17. "COMP2,Complement Of Channel (n) For n = 4" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.." newline bitfld.long 0x18 16. "COMBINE2,Combine Channels For n = 4" "0,1" bitfld.long 0x18 15. "MCOMBINE1,Modified Combine Mode For n = 2" "0,1" newline bitfld.long 0x18 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.." bitfld.long 0x18 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.." newline bitfld.long 0x18 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive.,1: The dual edge captures are active." bitfld.long 0x18 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1" newline bitfld.long 0x18 9. "COMP1,Complement Of Channel (n) For n = 2" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.." bitfld.long 0x18 8. "COMBINE1,Combine Channels For n = 2" "0,1" newline bitfld.long 0x18 7. "MCOMBINE0,Modified Combine Mode For n = 0" "0,1" bitfld.long 0x18 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.." newline bitfld.long 0x18 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.." bitfld.long 0x18 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive.,1: The dual edge captures are active." newline bitfld.long 0x18 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1" bitfld.long 0x18 1. "COMP0,Complement Of Channel (n) For n = 0" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.." newline bitfld.long 0x18 0. "COMBINE0,Combine Channels For n = 0" "0,1" line.long 0x1C "DEADTIME,Deadtime Configuration" hexmask.long.byte 0x1C 16.--19. 1. "DTVALEX,Extended Deadtime Value" bitfld.long 0x1C 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1.,1: Divide the FTM input clock by 1.,2: Divide the FTM input clock by 4.,3: Divide the FTM input clock by 16." newline hexmask.long.byte 0x1C 0.--5. 1. "DTVAL,Deadtime Value" line.long 0x20 "EXTTRIG,FTM External Trigger" bitfld.long 0x20 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated.,1: A channel trigger was generated." bitfld.long 0x20 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.." newline bitfld.long 0x20 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." bitfld.long 0x20 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." newline bitfld.long 0x20 3. "CH5TRIG,Channel 5 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." bitfld.long 0x20 2. "CH4TRIG,Channel 4 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." newline bitfld.long 0x20 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." bitfld.long 0x20 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." line.long 0x24 "POL,Channels Polarity" bitfld.long 0x24 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." bitfld.long 0x24 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." newline bitfld.long 0x24 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." bitfld.long 0x24 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." newline bitfld.long 0x24 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." bitfld.long 0x24 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." line.long 0x28 "FMS,Fault Mode Status" bitfld.long 0x28 6. "WPEN,Write Protection Enable" "0: Write protection is disabled. Write protected..,1: Write protection is enabled. Write protected.." line.long 0x2C "FILTER,Input Capture Filter Control" hexmask.long.byte 0x2C 12.--15. 1. "CH3FVAL,Channel 3 Input Filter" hexmask.long.byte 0x2C 8.--11. 1. "CH2FVAL,Channel 2 Input Filter" newline hexmask.long.byte 0x2C 4.--7. 1. "CH1FVAL,Channel 1 Input Filter" hexmask.long.byte 0x2C 0.--3. 1. "CH0FVAL,Channel 0 Input Filter" group.long 0x80++0x7 line.long 0x0 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x0 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled.,1: Phase A input filter is enabled." bitfld.long 0x0 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled.,1: Phase B input filter is enabled." newline bitfld.long 0x0 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity. Phase A input signal is not..,1: Inverted polarity. Phase A input signal is.." bitfld.long 0x0 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity. Phase B input signal is not..,1: Inverted polarity. Phase B input signal is.." newline bitfld.long 0x0 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode.,1: Count and direction encoding mode." rbitfld.long 0x0 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.." newline rbitfld.long 0x0 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting. There..,1: TOF bit was set on the top of counting. There.." bitfld.long 0x0 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled.,1: Quadrature Decoder mode is enabled." line.long 0x4 "CONF,Configuration" bitfld.long 0x4 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on counter..,1: Initialization trigger is generated when a.." bitfld.long 0x4 10. "GTBEOUT,Global Time Base Output" "0: A global time base signal generation is disabled.,1: A global time base signal generation is enabled." newline bitfld.long 0x4 9. "GTBEEN,Global Time Base Enable" "0: Use of an external global time base is disabled.,1: Use of an external global time base is enabled." bitfld.long 0x4 6.--7. "BDMMODE,Debug Mode" "0,1,2,3" newline hexmask.long.byte 0x4 0.--4. 1. "LDFQ,Frequency of the Reload Opportunities" group.long 0x8C++0x13 line.long 0x0 "SYNCONF,Synchronization Configuration" bitfld.long 0x0 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the SWOCTRL..,1: A hardware trigger activates the SWOCTRL.." bitfld.long 0x0 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the INVCTRL..,1: A hardware trigger activates the INVCTRL.." newline bitfld.long 0x0 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the OUTMASK..,1: A hardware trigger activates the OUTMASK.." bitfld.long 0x0 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN and.." newline bitfld.long 0x0 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.." bitfld.long 0x0 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.." newline bitfld.long 0x0 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.." bitfld.long 0x0 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.." newline bitfld.long 0x0 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD HCR..,1: The software trigger activates MOD HCR CNTIN and.." bitfld.long 0x0 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the FTM..,1: The software trigger activates the FTM counter.." newline bitfld.long 0x0 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected.,1: Enhanced PWM synchronization is selected." bitfld.long 0x0 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.." newline bitfld.long 0x0 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.." bitfld.long 0x0 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer value..,1: CNTIN register is updated with its buffer value.." newline bitfld.long 0x0 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.." line.long 0x4 "INVCTRL,FTM Inverting Control" bitfld.long 0x4 2. "INV2EN,Pair Channels 2 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled." bitfld.long 0x4 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled." newline bitfld.long 0x4 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled." line.long 0x8 "SWOCTRL,FTM Software Output Control" bitfld.long 0x8 13. "CH5OCV,Channel 5 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." bitfld.long 0x8 12. "CH4OCV,Channel 4 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." newline bitfld.long 0x8 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." bitfld.long 0x8 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." newline bitfld.long 0x8 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." bitfld.long 0x8 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." newline bitfld.long 0x8 5. "CH5OC,Channel 5 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." bitfld.long 0x8 4. "CH4OC,Channel 4 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." newline bitfld.long 0x8 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." bitfld.long 0x8 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." newline bitfld.long 0x8 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." bitfld.long 0x8 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." line.long 0xC "PWMLOAD,FTM PWM Load" bitfld.long 0xC 11. "GLDOK,Global Load OK" "0: No action.,1: LDOK bit is set." bitfld.long 0xC 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled.,1: Global Load OK enabled. A pulse event on the.." newline bitfld.long 0xC 9. "LDOK,Load Enable" "0: Loading updated values is disabled.,1: Loading updated values is enabled." bitfld.long 0xC 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.." newline bitfld.long 0xC 5. "CH5SEL,Channel 5 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." bitfld.long 0xC 4. "CH4SEL,Channel 4 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." newline bitfld.long 0xC 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." bitfld.long 0xC 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." newline bitfld.long 0xC 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." bitfld.long 0xC 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." line.long 0x10 "HCR,Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. "HCVAL,Half Cycle Value" group.long 0x200++0x3 line.long 0x0 "MOD_MIRROR,Mirror of Modulo Value" hexmask.long.word 0x0 16.--31. 1. "MOD,Mirror of the Modulo Integer Value" hexmask.long.byte 0x0 11.--15. 1. "FRACMOD,Modulo Fractional Value" repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x204)++0x3 line.long 0x0 "CV_MIRROR[$1],Mirror of Channel (n) Match Value" hexmask.long.word 0x0 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value" hexmask.long.byte 0x0 11.--15. 1. "FRACVAL,Channel (n) Match Fractional Value" repeat.end tree.end tree "FTM_1" base ad:0x402E4000 group.long 0x0++0xB line.long 0x0 "SC,Status And Control" hexmask.long.byte 0x0 24.--27. 1. "FLTPS,Filter Prescaler" bitfld.long 0x0 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." newline bitfld.long 0x0 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." bitfld.long 0x0 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." newline bitfld.long 0x0 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." bitfld.long 0x0 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." newline bitfld.long 0x0 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled.,1: Channel output port is enabled." bitfld.long 0x0 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed.,1: FTM counter has overflowed." newline bitfld.long 0x0 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts. Use software polling.,1: Enable TOF interrupts. An interrupt is generated.." bitfld.long 0x0 7. "RF,Reload Flag" "0: A selected reload point did not happen.,1: A selected reload point happened." newline bitfld.long 0x0 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled.,1: Reload point interrupt is enabled." bitfld.long 0x0 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode.,1: FTM counter operates in Up-Down Counting mode." newline bitfld.long 0x0 3.--4. "CLKS,Clock Source Selection" "0: No clock selected. This in effect disables the..,1: FTM input clock,2: Fixed frequency clock,3: External clock" bitfld.long 0x0 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" line.long 0x4 "CNT,Counter" hexmask.long.word 0x4 0.--15. 1. "COUNT,Counter Value" line.long 0x8 "MOD,Modulo" hexmask.long.word 0x8 0.--15. 1. "MOD,MOD" repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x402E400C ad:0x402E4014 ad:0x402E401C ad:0x402E4024 ad:0x402E402C ad:0x402E4034) tree "CONTROLS[$1]" base $2 group.long ($2)++0x7 line.long 0x0 "CSC,Channel (n) Status And Control" rbitfld.long 0x0 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero.,1: The channel (n) output is one." rbitfld.long 0x0 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero.,1: The channel (n) input is one." newline bitfld.long 0x0 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.." bitfld.long 0x0 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred.,1: A channel (n) event has occurred." newline bitfld.long 0x0 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt. Use software..,1: Enable channel (n) interrupt." bitfld.long 0x0 5. "MSB,Channel (n) Mode Select" "0,1" newline bitfld.long 0x0 4. "MSA,Channel (n) Mode Select" "0,1" bitfld.long 0x0 3. "ELSB,Channel (n) Edge or Level Select" "0,1" newline bitfld.long 0x0 2. "ELSA,Channel (n) Edge or Level Select" "0,1" bitfld.long 0x0 1. "ICRST,FTM counter reset by the selected input capture event." "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected channel.." newline bitfld.long 0x0 0. "DMA,DMA Enable" "0: Disable DMA transfers.,1: Enable DMA transfers." line.long 0x4 "CV,Channel (n) Value" hexmask.long.word 0x4 0.--15. 1. "VAL,Channel Value" tree.end repeat.end base ad:0x402E4000 group.long 0x4C++0x2F line.long 0x0 "CNTIN,Counter Initial Value" hexmask.long.word 0x0 0.--15. 1. "INIT,INIT" line.long 0x4 "STATUS,Capture And Compare Status" bitfld.long 0x4 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred.,1: A channel event has occurred." bitfld.long 0x4 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred.,1: A channel event has occurred." newline bitfld.long 0x4 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred.,1: A channel event has occurred." bitfld.long 0x4 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred.,1: A channel event has occurred." newline bitfld.long 0x4 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred.,1: A channel event has occurred." bitfld.long 0x4 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred.,1: A channel event has occurred." line.long 0x8 "MODE,Features Mode Selection" bitfld.long 0x8 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled.,1: Capture test mode is enabled." bitfld.long 0x8 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions. Software and hardware triggers..,1: Software trigger can only be used by MOD and CnV.." newline bitfld.long 0x8 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled.,1: Write protection is disabled." bitfld.long 0x8 1. "INIT,Initialize The Channels Output" "0,1" newline bitfld.long 0x8 0. "FTMEN,FTM Enable" "0: TPM compatibility. Free running counter and..,1: Free running counter and synchronization are.." line.long 0xC "SYNC,Synchronization" bitfld.long 0xC 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected.,1: Software trigger is selected." bitfld.long 0xC 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled.,1: Trigger is enabled." newline bitfld.long 0xC 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled.,1: Trigger is enabled." bitfld.long 0xC 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled.,1: Trigger is enabled." newline bitfld.long 0xC 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.." bitfld.long 0xC 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally.,1: FTM counter is updated with its initial value.." newline bitfld.long 0xC 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled.,1: The maximum loading point is enabled." bitfld.long 0xC 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled.,1: The minimum loading point is enabled." line.long 0x10 "OUTINIT,Initial State For Channels Output" bitfld.long 0x10 5. "CH5OI,Channel 5 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." bitfld.long 0x10 4. "CH4OI,Channel 4 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." newline bitfld.long 0x10 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." bitfld.long 0x10 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." newline bitfld.long 0x10 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." bitfld.long 0x10 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0.,1: The initialization value is 1." line.long 0x14 "OUTMASK,Output Mask" bitfld.long 0x14 5. "CH5OM,Channel 5 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." bitfld.long 0x14 4. "CH4OM,Channel 4 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." newline bitfld.long 0x14 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." bitfld.long 0x14 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." newline bitfld.long 0x14 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." bitfld.long 0x14 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked. It continues to..,1: Channel output is masked. It is forced to its.." line.long 0x18 "COMBINE,Function For Linked Channels" bitfld.long 0x18 23. "MCOMBINE2,Modified Combine Mode For n = 4" "0,1" bitfld.long 0x18 21. "SYNCEN2,Synchronization Enable For n = 4" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.." newline bitfld.long 0x18 20. "DTEN2,Deadtime Enable For n = 4" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.." bitfld.long 0x18 19. "DECAP2,Dual Edge Capture Mode Captures For n = 4" "0: The dual edge captures are inactive.,1: The dual edge captures are active." newline bitfld.long 0x18 18. "DECAPEN2,Dual Edge Capture Mode Enable For n = 4" "0,1" bitfld.long 0x18 17. "COMP2,Complement Of Channel (n) For n = 4" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.." newline bitfld.long 0x18 16. "COMBINE2,Combine Channels For n = 4" "0,1" bitfld.long 0x18 15. "MCOMBINE1,Modified Combine Mode For n = 2" "0,1" newline bitfld.long 0x18 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.." bitfld.long 0x18 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.." newline bitfld.long 0x18 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive.,1: The dual edge captures are active." bitfld.long 0x18 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1" newline bitfld.long 0x18 9. "COMP1,Complement Of Channel (n) For n = 2" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.." bitfld.long 0x18 8. "COMBINE1,Combine Channels For n = 2" "0,1" newline bitfld.long 0x18 7. "MCOMBINE0,Modified Combine Mode For n = 0" "0,1" bitfld.long 0x18 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of channels..,1: The PWM synchronization in this pair of channels.." newline bitfld.long 0x18 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of channels..,1: The deadtime insertion in this pair of channels.." bitfld.long 0x18 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive.,1: The dual edge captures are active." newline bitfld.long 0x18 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1" bitfld.long 0x18 1. "COMP0,Complement Of Channel (n) For n = 0" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.." newline bitfld.long 0x18 0. "COMBINE0,Combine Channels For n = 0" "0,1" line.long 0x1C "DEADTIME,Deadtime Configuration" hexmask.long.byte 0x1C 16.--19. 1. "DTVALEX,Extended Deadtime Value" bitfld.long 0x1C 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1.,1: Divide the FTM input clock by 1.,2: Divide the FTM input clock by 4.,3: Divide the FTM input clock by 16." newline hexmask.long.byte 0x1C 0.--5. 1. "DTVAL,Deadtime Value" line.long 0x20 "EXTTRIG,FTM External Trigger" bitfld.long 0x20 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated.,1: A channel trigger was generated." bitfld.long 0x20 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.." newline bitfld.long 0x20 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." bitfld.long 0x20 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." newline bitfld.long 0x20 3. "CH5TRIG,Channel 5 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." bitfld.long 0x20 2. "CH4TRIG,Channel 4 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." newline bitfld.long 0x20 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." bitfld.long 0x20 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.." line.long 0x24 "POL,Channels Polarity" bitfld.long 0x24 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." bitfld.long 0x24 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." newline bitfld.long 0x24 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." bitfld.long 0x24 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." newline bitfld.long 0x24 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." bitfld.long 0x24 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high.,1: The channel polarity is active low." line.long 0x28 "FMS,Fault Mode Status" bitfld.long 0x28 6. "WPEN,Write Protection Enable" "0: Write protection is disabled. Write protected..,1: Write protection is enabled. Write protected.." line.long 0x2C "FILTER,Input Capture Filter Control" hexmask.long.byte 0x2C 12.--15. 1. "CH3FVAL,Channel 3 Input Filter" hexmask.long.byte 0x2C 8.--11. 1. "CH2FVAL,Channel 2 Input Filter" newline hexmask.long.byte 0x2C 4.--7. 1. "CH1FVAL,Channel 1 Input Filter" hexmask.long.byte 0x2C 0.--3. 1. "CH0FVAL,Channel 0 Input Filter" group.long 0x80++0x7 line.long 0x0 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x0 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled.,1: Phase A input filter is enabled." bitfld.long 0x0 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled.,1: Phase B input filter is enabled." newline bitfld.long 0x0 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity. Phase A input signal is not..,1: Inverted polarity. Phase A input signal is.." bitfld.long 0x0 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity. Phase B input signal is not..,1: Inverted polarity. Phase B input signal is.." newline bitfld.long 0x0 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode.,1: Count and direction encoding mode." rbitfld.long 0x0 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.." newline rbitfld.long 0x0 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting. There..,1: TOF bit was set on the top of counting. There.." bitfld.long 0x0 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled.,1: Quadrature Decoder mode is enabled." line.long 0x4 "CONF,Configuration" bitfld.long 0x4 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on counter..,1: Initialization trigger is generated when a.." bitfld.long 0x4 10. "GTBEOUT,Global Time Base Output" "0: A global time base signal generation is disabled.,1: A global time base signal generation is enabled." newline bitfld.long 0x4 9. "GTBEEN,Global Time Base Enable" "0: Use of an external global time base is disabled.,1: Use of an external global time base is enabled." bitfld.long 0x4 6.--7. "BDMMODE,Debug Mode" "0,1,2,3" newline hexmask.long.byte 0x4 0.--4. 1. "LDFQ,Frequency of the Reload Opportunities" group.long 0x8C++0x13 line.long 0x0 "SYNCONF,Synchronization Configuration" bitfld.long 0x0 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the SWOCTRL..,1: A hardware trigger activates the SWOCTRL.." bitfld.long 0x0 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the INVCTRL..,1: A hardware trigger activates the INVCTRL.." newline bitfld.long 0x0 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the OUTMASK..,1: A hardware trigger activates the OUTMASK.." bitfld.long 0x0 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN and.." newline bitfld.long 0x0 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.." bitfld.long 0x0 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.." newline bitfld.long 0x0 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.." bitfld.long 0x0 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.." newline bitfld.long 0x0 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD HCR..,1: The software trigger activates MOD HCR CNTIN and.." bitfld.long 0x0 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the FTM..,1: The software trigger activates the FTM counter.." newline bitfld.long 0x0 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected.,1: Enhanced PWM synchronization is selected." bitfld.long 0x0 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.." newline bitfld.long 0x0 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.." bitfld.long 0x0 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer value..,1: CNTIN register is updated with its buffer value.." newline bitfld.long 0x0 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.." line.long 0x4 "INVCTRL,FTM Inverting Control" bitfld.long 0x4 2. "INV2EN,Pair Channels 2 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled." bitfld.long 0x4 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled." newline bitfld.long 0x4 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled.,1: Inverting is enabled." line.long 0x8 "SWOCTRL,FTM Software Output Control" bitfld.long 0x8 13. "CH5OCV,Channel 5 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." bitfld.long 0x8 12. "CH4OCV,Channel 4 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." newline bitfld.long 0x8 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." bitfld.long 0x8 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." newline bitfld.long 0x8 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." bitfld.long 0x8 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.." newline bitfld.long 0x8 5. "CH5OC,Channel 5 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." bitfld.long 0x8 4. "CH4OC,Channel 4 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." newline bitfld.long 0x8 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." bitfld.long 0x8 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." newline bitfld.long 0x8 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." bitfld.long 0x8 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by software..,1: The channel output is affected by software.." line.long 0xC "PWMLOAD,FTM PWM Load" bitfld.long 0xC 11. "GLDOK,Global Load OK" "0: No action.,1: LDOK bit is set." bitfld.long 0xC 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled.,1: Global Load OK enabled. A pulse event on the.." newline bitfld.long 0xC 9. "LDOK,Load Enable" "0: Loading updated values is disabled.,1: Loading updated values is enabled." bitfld.long 0xC 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.." newline bitfld.long 0xC 5. "CH5SEL,Channel 5 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." bitfld.long 0xC 4. "CH4SEL,Channel 4 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." newline bitfld.long 0xC 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." bitfld.long 0xC 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." newline bitfld.long 0xC 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." bitfld.long 0xC 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload opportunity." line.long 0x10 "HCR,Half Cycle Register" hexmask.long.word 0x10 0.--15. 1. "HCVAL,Half Cycle Value" group.long 0x200++0x3 line.long 0x0 "MOD_MIRROR,Mirror of Modulo Value" hexmask.long.word 0x0 16.--31. 1. "MOD,Mirror of the Modulo Integer Value" hexmask.long.byte 0x0 11.--15. 1. "FRACMOD,Modulo Fractional Value" repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x204)++0x3 line.long 0x0 "CV_MIRROR[$1],Mirror of Channel (n) Match Value" hexmask.long.word 0x0 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value" hexmask.long.byte 0x0 11.--15. 1. "FRACVAL,Channel (n) Match Fractional Value" repeat.end tree.end tree.end tree "FSC (Functional Safety Controller)" base ad:0x50600000 group.long 0x0++0x3 line.long 0x0 "SCBISTC,FSC BIST Control" bitfld.long 0x0 1. "BISTSTEP,BIST Step" "0,1" bitfld.long 0x0 0. "BISTSTART,BIST Start" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SCBISTA,FSC BIST Activity" hexmask.long.byte 0x0 5.--9. 1. "BISTERR,BIST Error" hexmask.long.byte 0x0 0.--4. 1. "BISTDONE,BIST Done" group.long 0x8++0x3 line.long 0x0 "SCCETH,FSC Correctable Errors Threshold" hexmask.long.byte 0x0 0.--7. 1. "CERRTHRES,Correctable Errors Threshold" rgroup.long 0x10++0x3 line.long 0x0 "SCLF0,FSC Latent Fault" hexmask.long.byte 0x0 0.--5. 1. "LATENTFAULT,Latent Fault" rgroup.long 0x20++0x3 line.long 0x0 "SCMF0,FSC Mission Fault" hexmask.long.byte 0x0 0.--5. 1. "MISSIONFAULT,Mission Faults" rgroup.long 0x30++0x3 line.long 0x0 "SCCETHF0,FSC Correctable Error Threshold Fault" hexmask.long.byte 0x0 0.--5. 1. "CERRTHFAULT,Correctable Error Threshold Fault" tree.end tree "FXOSC (Fast External Crystal Oscillator)" base ad:0x40050000 group.long 0x0++0x3 line.long 0x0 "CTRL,FXOSC Control Register" bitfld.long 0x0 31. "OSC_BYP,Oscillator bypass" "0: Internal oscillator not bypassed,1: Internal oscillator bypassed" bitfld.long 0x0 24. "COMP_EN,Comparator enable" "0: Comparator disabled,1: Comparator enabled" hexmask.long.byte 0x0 16.--23. 1. "EOCV,End of count value" newline hexmask.long.byte 0x0 4.--7. 1. "GM_SEL,Crystal overdrive protection" bitfld.long 0x0 2. "ALC_D,Automatic level controller enable" "0: Enables automatic level controller,1: Disables automatic level controller" bitfld.long 0x0 0. "OSCON,Crystal oscillator power-down control" "0: Disables FXOSC,1: Enables FXOSC" rgroup.long 0x4++0x3 line.long 0x0 "STAT,Oscillator Status Register" bitfld.long 0x0 31. "OSC_STAT,Crystal oscillator status" "0: Crystal oscillator is off or on but not stable.,1: Crystal oscillator is on and providing a stable.." tree.end tree "GMAC (Gigabit Ethernet Media Access Controller)" base ad:0x4033C000 group.long 0x0++0x2F line.long 0x0 "MAC_Configuration,The MAC Configuration Register establishes the operating mode of the MAC." bitfld.long 0x0 31. "ARPEN,ARP Offload Enable When this bit is set the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission" "0: ARP Offload is disabled,1: ARP Offload is enabled" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets" "0: mti_sa_ctrl_i and ati_sa_ctrl_i input signals..,?,2: Contents of MAC Addr-0 inserted in SA field,3: Contents of MAC Addr-0 replaces SA field,?,?,6: Contents of MAC Addr-1 inserted in SA field,7: Contents of MAC Addr-1 replaces SA field" newline bitfld.long 0x0 27. "IPC,Checksum Offload When set this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP UDP or ICMP payload checksum checking" "0: IP header/payload checksum checking is disabled,1: IP header/payload checksum checking is enabled" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission" "0: 96 bit times IPG,1: 88 bit times IPG,2: 80 bit times IPG,3: 72 bit times IPG,4: 64 bit times IPG,5: 56 bit times IPG,6: 48 bit times IPG,7: 40 bit times IPG" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet" "0: Giant Packet Size Limit Control is disabled,1: Giant Packet Size Limit Control is enabled" newline bitfld.long 0x0 22. "S2KP,IEEE 802" "0: Support upto 2K packet is disabled,1: Support upto 2K packet is Enabled" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application" "0: CRC stripping for Type packets is disabled,1: CRC stripping for Type packets is enabled" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes" "0: Automatic Pad or CRC Stripping is disabled,1: Automatic Pad or CRC Stripping is enabled" newline bitfld.long 0x0 19. "WD,Watchdog Disable When this bit is set the MAC disables the watchdog timer on the receiver" "0: Watchdog is enabled,1: Watchdog is disabled" newline bitfld.long 0x0 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode" "0: Packet Burst is disabled,1: Packet Burst is enabled" newline bitfld.long 0x0 17. "JD,Jabber Disable When this bit is set the MAC disables the jabber timer on the transmitter" "0: Jabber is enabled,1: Jabber is disabled" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status" "0: Jumbo packet is disabled,1: Jumbo packet is enabled" newline bitfld.long 0x0 15. "PS,Port Select This bit selects the Ethernet line speed" "0: For 1000 or 2500 Mbps operations,1: For 10 or 100 Mbps operations" newline bitfld.long 0x0 14. "FES,Speed This bit selects the speed mode. The mac_speed_o[0] signal reflects the value of this bit." "0: 10 Mbps when PS bit is 1 and 1 Gbps when PS bit..,1: 100 Mbps when PS bit is 1 and 2.5 Gbps when PS.." newline bitfld.long 0x0 13. "DM,Duplex Mode When this bit is set the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously" "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 12. "LM,Loopback Mode When this bit is set the MAC operates in the loopback mode at GMII or MII" "0: Loopback is disabled,1: Loopback is enabled" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode" "0: ECRSFD is disabled,1: ECRSFD is enabled" newline bitfld.long 0x0 10. "DO,Disable Receive Own When this bit is set the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode" "0: Enable Receive Own,1: Disable Receive Own" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode" "0: Enable Carrier Sense During Transmission,1: Disable Carrier Sense During Transmission" newline bitfld.long 0x0 8. "DR,Disable Retry When this bit is set the MAC attempts only one transmission" "0: Enable Retry,1: Disable Retry" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000/2500 Mbps; 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after.." "0: k = min(n 10),1: k = min(n 8),2: k = min(n 4),3: k = min(n 1)" newline bitfld.long 0x0 4. "DC,Deferral Check When this bit is set the deferral check function is enabled in the MAC" "0: Deferral check function is disabled,1: Deferral check function is enabled" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?" newline bitfld.long 0x0 1. "TE,Transmitter Enable When this bit is set the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface" "0: Transmitter is disabled,1: Transmitter is enabled" newline bitfld.long 0x0 0. "RE,Receiver Enable When this bit is set the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface" "0: Receiver is disabled,1: Receiver is enabled" line.long 0x4 "MAC_Ext_Configuration,The MAC Extended Configuration Register establishes the operating mode of the MAC." hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable When this bit is set the MAC interprets EIPG field and IPG field in MAC_Configuration register together as minimum IPG greater than 96 bit times in steps of 8 bit times" "0: Extended Inter-Packet Gap is disabled,1: Extended Inter-Packet Gap is enabled" newline bitfld.long 0x4 20.--22. "HDSMS,Maximum Size for Splitting the Header Data These bits indicate the maximum header size allowed for splitting the header data in the received packet" "0: Maximum Size for Splitting the Header Data is 64..,1: Maximum Size for Splitting the Header Data is..,2: Maximum Size for Splitting the Header Data is..,3: Maximum Size for Splitting the Header Data is..,4: Maximum Size for Splitting the Header Data is..,?,?,?" newline bitfld.long 0x4 19. "PDC,Packet Duplication Control When this bit is set the received packet with Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels" "0: Packet Duplication Control is disabled,1: Packet Duplication Control is enabled" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers" "0: Unicast Slow Protocol Packet Detection is disabled,1: Unicast Slow Protocol Packet Detection is enabled" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable When this bit is set MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Slow Protocol Sub-Type and Code fields in Rx status" "0: Slow Protocol Detection is disabled,1: Slow Protocol Detection is enabled" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set the MAC receiver does not check the CRC field in the received packets" "0: CRC Checking is enabled,1: CRC Checking is disabled" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes the MAC declares the received packet as Giant packet" line.long 0x8 "MAC_Packet_Filter,The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of.." bitfld.long 0x8 31. "RA,Receive All When this bit is set the MAC Receiver module passes all received packets to the application irrespective of whether they pass the address filter or not" "0: Receive All is disabled,1: Receive All is enabled" newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets When this bit is set the MAC drops the non-TCP or UDP over IP packets" "0: Forward Non-TCP/UDP over IP Packets,1: Drop Non-TCP/UDP over IP Packets" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable When this bit is set the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters" "0: Layer 3 and Layer 4 Filters are disabled,1: Layer 3 and Layer 4 Filters are enabled" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable When this bit is set the MAC drops the VLAN tagged packets that do not match the VLAN Tag" "0: VLAN Tag Filter is disabled,1: VLAN Tag Filter is enabled" newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter When this bit is set the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit" "0: Hash or Perfect Filter is disabled,1: Hash or Perfect Filter is enabled" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable When this bit is set the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers" "0: SA Filtering is disabled,1: SA Filtering is enabled" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering When this bit is set the Address Check block operates in the inverse filtering mode for SA address comparison" "0: SA Inverse Filtering is disabled,1: SA Inverse Filtering is enabled" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets)" "0: MAC filters all control packets from reaching..,1: MAC forwards all control packets except Pause..,2: MAC forwards all control packets to the..,3: MAC forwards the control packets that pass the.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets When this bit is set the AFM module blocks all incoming broadcast packets" "0: Enable Broadcast Packets,1: Disable Broadcast Packets" newline bitfld.long 0x8 4. "PM,Pass All Multicast When this bit is set it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed" "0: Pass All Multicast is disabled,1: Pass All Multicast is enabled" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets" "0: DA Inverse Filtering is disabled,1: DA Inverse Filtering is enabled" newline bitfld.long 0x8 2. "HMC,Hash Multicast When this bit is set the MAC performs the destination address filtering of received multicast packets according to the hash table" "0: Hash Multicast is disabled,1: Hash Multicast is enabled" newline bitfld.long 0x8 1. "HUC,Hash Unicast When this bit is set the MAC performs the destination address filtering of unicast packets according to the hash table" "0: Hash Unicast is disabled,1: Hash Unicast is enabled" newline bitfld.long 0x8 0. "PR,Promiscuous Mode When this bit is set the Address Filtering module passes all incoming packets irrespective of the destination or source address" "0: Promiscuous Mode is disabled,1: Promiscuous Mode is enabled" line.long 0xC "MAC_Watchdog_Timeout,The Watchdog Timeout register controls the watchdog timeout for received packets." bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_Configuration register is reset the WTO field is used as watchdog timeout for a received packet" "0: Programmable Watchdog is disabled,1: Programmable Watchdog is enabled" newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_Configuration register is reset this field is used as watchdog timeout for a received packet" line.long 0x10 "MAC_Hash_Table_Reg0,The Hash Table Register 0 contains the first 32 bits of the hash table. when the width of the hash table is 128 or 256 bits. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash.." hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table." line.long 0x14 "MAC_Hash_Table_Reg1,The Hash Table Register 1 contains the second 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table." line.long 0x18 "MAC_Hash_Table_Reg2,The Hash Table Register 2 contains the third 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x18 0.--31. 1. "HT95T64,MAC Hash Table Third 32 Bits This field contains the third 32 Bits [95:64] of the Hash table." line.long 0x1C "MAC_Hash_Table_Reg3,The Hash Table Register 3 contains the fourth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x1C 0.--31. 1. "HT127T96,MAC Hash Table Fourth 32 Bits This field contains the fourth 32 Bits [127:96] of the Hash table." line.long 0x20 "MAC_Hash_Table_Reg4,The Hash Table Register 4 contains the fifth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x20 0.--31. 1. "HT159T128,MAC Hash Table Fifth 32 Bits This field contains the fifth 32 Bits [159:128] of the Hash table." line.long 0x24 "MAC_Hash_Table_Reg5,The Hash Table Register 5 contains the sixth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x24 0.--31. 1. "HT191T160,MAC Hash Table Sixth 32 Bits This field contains the sixth 32 Bits [191:160] of the Hash table." line.long 0x28 "MAC_Hash_Table_Reg6,The Hash Table Register 6 contains the seventh 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x28 0.--31. 1. "HT223T192,MAC Hash Table Seventh 32 Bits This field contains the seventh 32 Bits [223:192] of the Hash table." line.long 0x2C "MAC_Hash_Table_Reg7,The Hash Table Register 7 contains the eighth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x2C 0.--31. 1. "HT255T224,MAC Hash Table Eighth 32 Bits This field contains the eighth 32 Bits [255:224] of the Hash table." group.long 0x50++0xB line.long 0x0 "MAC_VLAN_Tag_Ctrl,This register is the redefined format of the MAC VLAN Tag Register. It is used for indirect addressing. It contains the address offset. command type and Busy Bit for CSR access of the Per VLAN Tag registers." bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status When this bit is set the MAC provides the inner VLAN Tag in the Rx status" "0: Inner VLAN Tag in Rx status is disabled,1: Inner VLAN Tag in Rx status is enabled" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag Comparison" "0: Inner VLAN tag is disabled,1: Inner VLAN tag is enabled" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing When this bit is set the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present)" "0: Double VLAN Processing is disabled,1: Double VLAN Processing is enabled" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable When this bit is set the most significant four bits of CRC of VLAN Tag are used to index the content of the MAC_VLAN_Hash_Table register" "0: VLAN Tag Hash Table Match is disabled,1: VLAN Tag Hash Table Match is enabled" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status When this bit is set MAC provides the outer VLAN Tag in the Rx status" "0: VLAN Tag in Rx status is disabled,1: VLAN Tag in Rx status is enabled" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check for VLAN Hash Filtering When this bit is set the MAC VLAN Hash Filter does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN" "0: VLAN Type Check is enabled,1: VLAN Type Check is disabled" newline bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match for VLAN Hash Filtering When this bit is set the MAC receiver enables VLAN Hash filtering or matching for S-VLAN (Type = 0x88A8) packets" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets" "0: S-VLAN is disabled,1: S-VLAN is enabled" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable When this bit is set this bit enables the VLAN Tag inverse matching" "0: VLAN Tag Inverse Match is disabled,1: VLAN Tag Inverse Match is enabled" newline bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison for VLAN Hash Filtering When this bit is set a 12-bit VLAN identifier is used for VLAN Hash filtering instead of the complete 16-bit VLAN tag" "0: 12-Bit VLAN Tag Comparison is disabled,1: 12-Bit VLAN Tag Comparison is enabled" newline hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset This field holds the address offset of the MAC VLAN Tag Filter Register which the application is trying to access" newline bitfld.long 0x0 1. "CT,Command Type This bit indicates if the current register access is a read or a write" "0: Write operation,1: Read operation" newline bitfld.long 0x0 0. "OB,Operation Busy This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register" "0: Operation Busy is disabled,1: Operation Busy is enabled" line.long 0x4 "MAC_VLAN_Tag_Data,This register holds the read/write data for Indirect Access of the Per VLAN Tag registers. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field should be valid.." bitfld.long 0x4 25.--27. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x4 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x4 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x4 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" line.long 0x8 "MAC_VLAN_Hash_Table,When VTHM bit of the MAC_VLAN_Tag register is set. the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the.." hexmask.long.word 0x8 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table." group.long 0x60++0x7 line.long 0x0 "MAC_VLAN_Incl,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls." rbitfld.long 0x0 31. "BUSY,Busy This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register" "0: Busy status not detected,1: Busy status detected" newline bitfld.long 0x0 30. "RDWR,Read write control This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register" "0: Read operation of indirect access,1: Write operation of indirect access" newline bitfld.long 0x0 24.--26. "ADDR,Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion When this bit is set outer VLAN tag is inserted for every packets transmitted by the MAC" "0: Channel based tag insertion is disabled,1: Channel based tag insertion is enabled" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted or replaced,1: S-VLAN type (0x88A8) is inserted or replaced" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control When this bit is set the control bits[17:16] are used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags" "0: No VLAN tag deletion,1: VLAN tag deletion The MAC removes the VLAN type,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced" line.long 0x4 "MAC_Inner_VLAN_Incl,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls." bitfld.long 0x4 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN Controls the type insertion or replacement in the 17th and 18th bytes of transmitted packets" "0: C-VLAN type (8100h),1: S-VLAN type (88A8h)" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control When this bit is set the VLC field is used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags" "0: No VLAN tag deletion,1: VLAN tag deletion The MAC removes the VLAN type,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced" group.long 0x70++0x13 line.long 0x0 "MAC_Q0_Tx_Flow_Ctrl,The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate.." hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode when this bit is set the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." line.long 0x4 "MAC_Q1_Tx_Flow_Ctrl,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x4 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline bitfld.long 0x4 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x4 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline bitfld.long 0x4 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x4 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." line.long 0x8 "MAC_Q2_Tx_Flow_Ctrl,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x8 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline bitfld.long 0x8 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x8 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline bitfld.long 0x8 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x8 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." line.long 0xC "MAC_Q3_Tx_Flow_Ctrl,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0xC 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline bitfld.long 0xC 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0xC 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline bitfld.long 0xC 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0xC 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." line.long 0x10 "MAC_Q4_Tx_Flow_Ctrl,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x10 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline bitfld.long 0x10 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x10 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline bitfld.long 0x10 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x10 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." group.long 0x90++0x1F line.long 0x0 "MAC_Rx_Flow_Ctrl,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet." bitfld.long 0x0 8. "PFCE,Priority Based Flow Control Enable When this bit is set it enables generation and reception of priority-based flow control (PFC) packets" "0: Priority Based Flow Control is disabled,1: Priority Based Flow Control is enabled" newline bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802" "0: Unicast Pause Packet Detect disabled,1: Unicast Pause Packet Detect enabled" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time" "0: Receive Flow Control is disabled,1: Receive Flow Control is enabled" line.long 0x4 "MAC_RxQ_Ctrl4,The Receive Queue Control 4 register controls the routing of unicast and multicast packets that fail the Destination or Source address filter to the Rx queues." bitfld.long 0x4 17.--19. "VFFQ,VLAN Tag Filter Fail Packets Queue This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable When this bit is set the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed to the Rx Queue Number programmed in the VFFQ" "0: VLAN tag Filter Fail Packets Queuing is disabled,1: VLAN tag Filter Fail Packets Queuing is enabled" newline bitfld.long 0x4 9.--11. "MFFQ,Multicast Address Filter Fail Packets Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable" "0: Multicast Address Filter Fail Packets Queuing is..,1: Multicast Address Filter Fail Packets Queuing is.." newline bitfld.long 0x4 1.--3. "UFFQ,Unicast Address Filter Fail Packets Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable" "0: Unicast Address Filter Fail Packets Queuing is..,1: Unicast Address Filter Fail Packets Queuing is.." line.long 0x8 "MAC_TxQ_Prty_Map0,The Transmit Queue Priority Mapping 0 register contains the priority values assigned to Tx Queue 0 through Tx Queue 3." hexmask.long.byte 0x8 24.--31. 1. "PSTQ3,Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 16.--23. 1. "PSTQ2,Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software" line.long 0xC "MAC_TxQ_Prty_Map1,The Transmit Queue Priority Mapping 1 register contains the priority values assigned to Tx Queue 4 through Tx Queue 7." hexmask.long.byte 0xC 0.--7. 1. "PSTQ4,Priorities Selected in Transmit Queue 4 This field holds the priorities assigned to Tx Queue 4 by the software" line.long 0x10 "MAC_RxQ_Ctrl0,The Receive Queue Control 0 register controls the queue management in the MAC Receiver. Note: In multiple Rx queues configuration. all the queues are disabled by default. Enable the Rx queue by programming the corresponding field in this.." bitfld.long 0x10 8.--9. "RXQ4EN,Receive Queue 4 Enable This field is similar to the RXQ0EN field." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" newline bitfld.long 0x10 6.--7. "RXQ3EN,Receive Queue 3 Enable This field is similar to the RXQ0EN field." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" newline bitfld.long 0x10 4.--5. "RXQ2EN,Receive Queue 2 Enable This field is similar to the RXQ0EN field." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" newline bitfld.long 0x10 2.--3. "RXQ1EN,Receive Queue 1 Enable This field is similar to the RXQ0EN field." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" newline bitfld.long 0x10 0.--1. "RXQ0EN,Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" line.long 0x14 "MAC_RxQ_Ctrl1,The Receive Queue Control 1 register controls the routing of multicast. broadcast. AV. DCB. and untagged packets to the Rx queues." bitfld.long 0x14 24.--26. "FPRQ,Frame Preemption Residue Queue This field holds the Rx queue number to which the residual preemption frames must be forwarded" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0,1,2,3" newline bitfld.long 0x14 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0: Tagged AV Control Packets Queuing is disabled,1: Tagged AV Control Packets Queuing is enabled" newline bitfld.long 0x14 20. "MCBCQEN,Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field" "0: Multicast and Broadcast Queue is disabled,1: Multicast and Broadcast Queue is enabled" newline bitfld.long 0x14 16.--18. "MCBCQ,Multicast and Broadcast Queue This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline bitfld.long 0x14 12.--14. "UPQ,Untagged Packet Queue This field indicates the Rx Queue to which Untagged Packets are to be routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline bitfld.long 0x14 8.--10. "DCBCPQ,DCB Control Packets Queue This field specifies the Rx queue on which the received DCB control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline bitfld.long 0x14 4.--6. "PTPQ,PTP Packets Queue This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline bitfld.long 0x14 0.--2. "AVCPQ,AV Untagged Control Packets Queue This field specifies the Receive queue on which the received AV tagged and untagged control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" line.long 0x18 "MAC_RxQ_Ctrl2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 0 to 3." hexmask.long.byte 0x18 24.--31. 1. "PSRQ3,Priorities Selected in the Receive Queue 3 This field decides the priorities assigned to Rx Queue 3" newline hexmask.long.byte 0x18 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2 This field decides the priorities assigned to Rx Queue 2" newline hexmask.long.byte 0x18 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1 This field decides the priorities assigned to Rx Queue 1" newline hexmask.long.byte 0x18 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0 This field decides the priorities assigned to Rx Queue 0" line.long 0x1C "MAC_RxQ_Ctrl3,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 4 to 7." hexmask.long.byte 0x1C 0.--7. 1. "PSRQ4,Priorities Selected in the Receive Queue 4 This field decides the priorities assigned to Rx Queue 4" rgroup.long 0xB0++0x3 line.long 0x0 "MAC_Interrupt_Status,The Interrupt Status register contains the status of interrupts." bitfld.long 0x0 20. "MFRIS,MMC FPE Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Receive Interrupt Register" "0: MMC FPE Receive Interrupt status not active,1: MMC FPE Receive Interrupt status active" newline bitfld.long 0x0 19. "MFTIS,MMC FPE Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Transmit Interrupt Register" "0: MMC FPE Transmit Interrupt status not active,1: MMC FPE Transmit Interrupt status active" newline bitfld.long 0x0 18. "MDIOIS,MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation" "0: MDIO Interrupt status not active,1: MDIO Interrupt status active" newline bitfld.long 0x0 17. "FPEIS,Frame Preemption Interrupt Status This bit indicates an interrupt event during the operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set)" "0: Frame Preemption Interrupt status not active,1: Frame Preemption Interrupt status active" newline bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt This bit indicates the status of received packets" "0: Receive Interrupt status not active,1: Receive Interrupt status active" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt This bit indicates the status of transmitted packets" "0: Transmit Interrupt status not active,1: Transmit Interrupt status active" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status If the Timestamp feature is enabled this bit is set when any of the following conditions is true: - The system time value is equal to or exceeds the value specified in the Target Time High and Low registers" "0: Timestamp Interrupt status not active,1: Timestamp Interrupt status active" newline bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register" "0: MMC Transmit Interrupt status not active,1: MMC Transmit Interrupt status active" newline bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register" "0: MMC Receive Interrupt status not active,1: MMC Receive Interrupt status active" newline bitfld.long 0x0 8. "MMCIS,MMC Interrupt Status This bit is set high when Bit 11 Bit 10 or Bit 9 is set high" "0: MMC Interrupt status not active,1: MMC Interrupt status active" newline bitfld.long 0x0 4. "PMTIS,PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_Control_Status register)" "0: PMT Interrupt status not active,1: PMT Interrupt status active" newline bitfld.long 0x0 3. "PHYIS,PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input" "0: PHY Interrupt not detected,1: PHY Interrupt detected" newline bitfld.long 0x0 0. "RGSMIIIS,RGMII or SMII Interrupt Status This bit is set because of any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_Control_Status register)" "0: RGMII or SMII Interrupt Status is not active,1: RGMII or SMII Interrupt Status is active" group.long 0xB4++0x3 line.long 0x0 "MAC_Interrupt_Enable,The Interrupt Enable register contains the masks for generating the interrupts." bitfld.long 0x0 18. "MDIOIE,MDIO Interrupt Enable When this bit is set it enables the assertion of the interrupt when MDIOIS field is set in the MAC_Interrupt_Status register" "0: MDIO Interrupt is disabled,1: MDIO Interrupt is enabled" newline bitfld.long 0x0 17. "FPEIE,Frame Preemption Interrupt Enable When this bit is set it enables the assertion of the interrupt when FPEIS field is set in the MAC_Interrupt_Status register" "0: Frame Preemption Interrupt is disabled,1: Frame Preemption Interrupt is enabled" newline bitfld.long 0x0 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register" "0: Receive Status Interrupt is disabled,1: Receive Status Interrupt is enabled" newline bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register" "0: Timestamp Status Interrupt is disabled,1: Timestamp Status Interrupt is enabled" newline bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register" "0: Timestamp Interrupt is disabled,1: Timestamp Interrupt is enabled" newline bitfld.long 0x0 4. "PMTIE,PMT Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PMTIS bit in MAC_Interrupt_Status register" "0: PMT Interrupt is disabled,1: PMT Interrupt is enabled" newline bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register" "0: PHY Interrupt is disabled,1: PHY Interrupt is enabled" newline bitfld.long 0x0 0. "RGSMIIIE,RGMII or SMII Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_Interrupt_Status register" "0: RGMII or SMII Interrupt is disabled,1: RGMII or SMII Interrupt is enabled" rgroup.long 0xB8++0x3 line.long 0x0 "MAC_Rx_Tx_Status,The Receive Transmit Status register contains the Receive and Transmit Error status." bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register" "0: No receive watchdog timeout,1: Receive watchdog timed out" newline bitfld.long 0x0 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet" "0: No collision,1: Excessive collision is sensed" newline bitfld.long 0x0 4. "LCOL,Late Collision When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes.." "0: No collision,1: Late collision is sensed" newline bitfld.long 0x0 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "0: No Excessive deferral,1: Excessive deferral" newline bitfld.long 0x0 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "0: Carrier is present,1: Loss of carrier" newline bitfld.long 0x0 1. "NCARR,No Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission" "0: Carrier is present,1: No carrier" newline bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register" "0: No Transmit Jabber Timeout,1: Transmit Jabber Timeout occurred" group.long 0xC0++0x7 line.long 0x0 "MAC_PMT_Control_Status,The PMT Control and Status Register." bitfld.long 0x0 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set the remote wake-up packet filter register pointer is reset to 3'b000" "0: Remote Wake-Up Packet Filter Register Pointer is..,1: Remote Wake-Up Packet Filter Register Pointer is.." newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote Wake-up FIFO Pointer This field gives the current value (0 to 7 15 or 31 when 4 8 or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer" newline bitfld.long 0x0 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN the MAC receiver drops all received frames until it receives the expected Wake-up frame" "0: Remote Wake-up Packet Forwarding is disabled,1: Remote Wake-up Packet Forwarding is enabled" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast When this bit set any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet" "0: Global unicast is disabled,1: Global unicast is enabled" newline rbitfld.long 0x0 6. "RWKPRCVD,Remote Wake-Up Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a remote wake-up packet" "0: Remote wake-up packet is received,1: Remote wake-up packet is received" newline rbitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a magic packet" "0: No Magic packet is received,1: Magic packet is received" newline bitfld.long 0x0 2. "RWKPKTEN,Remote Wake-Up Packet Enable When this bit is set a power management event is generated when the MAC receives a remote wake-up packet" "0: Remote wake-up packet is disabled,1: Remote wake-up packet is enabled" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable When this bit is set a power management event is generated when the MAC receives a magic packet" "0: Magic Packet is disabled,1: Magic Packet is enabled" newline bitfld.long 0x0 0. "PWRDWN,Power Down When this bit is set the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet" "0: Power down is disabled,1: Power down is enabled" line.long 0x4 "MAC_RWK_Packet_Filter,The Remote Wakeup Filter registers are implemented as 8. 16. or 32 indirect access registers (wkuppktfilter_reg#i) based on whether 4. 8. or 16 Remote Wakeup Filters are selected in the configuration and accessed by application.." hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,RWK Packet Filter This field contains the various controls of RWK Packet filter." group.long 0xF8++0x3 line.long 0x0 "MAC_PHYIF_Control_Status,The PHY Interface Control and Status register indicates the status signals received by the SGMII. RGMII. or SMII interface (selected at reset) from the PHY. This register is optional." rbitfld.long 0x0 19. "LNKSTS,Link Status This bit indicates whether the link is up (1'b1) or down (1'b0)." "0: Link down,1: Link up" newline rbitfld.long 0x0 17.--18. "LNKSPEED,Link Speed This bit indicates the current speed of the link." "0: 2.5 MHz,1: 25 MHz,2: 125 MHz,?" newline rbitfld.long 0x0 16. "LNKMOD,Link Mode This bit indicates the current mode of operation of the link." "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 1. "LUD,Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII SGMII or SMII interface" "0: Link down,1: Link up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII SGMII or SMII When set this bit enables the transmission of duplex mode link speed and link up or down information to the PHY in the RGMII SMII or SGMII port" "0: Disable Transmit Configuration in RGMII SGMII or..,1: Enable Transmit Configuration in RGMII SGMII or.." rgroup.long 0x110++0x7 line.long 0x0 "MAC_Version,The version register identifies the version of the module." hexmask.long.byte 0x0 8.--15. 1. "CFGVER,IP configuration version" newline hexmask.long.byte 0x0 0.--7. 1. "IPVER,IP version" line.long 0x4 "MAC_Debug,The Debug register provides the debug status of various MAC blocks." bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module" "0: Idle state,1: Waiting for one of the following: Status of the..,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state" "0: MAC GMII or MII Transmit Protocol Engine Status..,1: MAC GMII or MII Transmit Protocol Engine Status.." newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state" "0: MAC GMII or MII Receive Protocol Engine Status..,1: MAC GMII or MII Receive Protocol Engine Status.." rgroup.long 0x11C++0xF line.long 0x0 "MAC_HW_Feature0,This register indicates the presence of first set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,7: RevMII" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected" "0: Source Address or VLAN Insertion Enable option..,1: Source Address or VLAN Insertion Enable option.." newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: Internal,1: External,2: Both,?" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected" "0: MAC Addresses 64-127 Select option is not selected,1: MAC Addresses 64-127 Select option is selected" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected" "0: MAC Addresses 32-63 Select option is not selected,1: MAC Addresses 32-63 Select option is selected" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected" "0: Receive Checksum Offload Enable option is not..,1: Receive Checksum Offload Enable option is selected" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected" "0: Transmit Checksum Offload Enable option is not..,1: Transmit Checksum Offload Enable option is.." newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected" "0: Energy Efficient Ethernet Enable option is not..,1: Energy Efficient Ethernet Enable option is.." newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: IEEE 1588-2008 Timestamp Enable option is not..,1: IEEE 1588-2008 Timestamp Enable option is selected" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected" "0: ARP Offload Enable option is not selected,1: ARP Offload Enable option is selected" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected" "0: RMON Module Enable option is not selected,1: RMON Module Enable option is selected" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected" "0: PMT Magic Packet Enable option is not selected,1: PMT Magic Packet Enable option is selected" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected" "0: PMT Remote Wake-up Packet Enable option is not..,1: PMT Remote Wake-up Packet Enable option is.." newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected" "0: SMA (MDIO) Interface not selected,1: SMA (MDIO) Interface selected" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected" "0: VLAN Hash Filter not selected,1: VLAN Hash Filter selected" newline bitfld.long 0x0 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface) This bit is set to 1 when the TBI SGMII or RTBI PHY interface option is selected" "0: No PCS Registers (TBI SGMII or RTBI PHY interface),1: PCS Registers (TBI SGMII or RTBI PHY interface)" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is selected" "0: No Half-duplex support,1: Half-duplex support" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation" "0: No 1000 Mbps support,1: 1000 Mbps support" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation" "0: No 10 or 100 Mbps support,1: 10 or 100 Mbps support" line.long 0x4 "MAC_HW_Feature1,This register indicates the presence of second set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters:" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table:" "0: No hash table,1: 64,2: 128,3: 256" newline bitfld.long 0x4 23. "POUOST,One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected" "0: One Step for PTP over UDP/IP Feature is not..,1: One Step for PTP over UDP/IP Feature is selected" newline bitfld.long 0x4 21. "RAVSEL,Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected" "0: Rx Side Only AV Feature is not selected,1: Rx Side Only AV Feature is selected" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected." "0: AV Feature is not selected,1: AV Feature is selected" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected" "0: DMA Debug Registers option is not selected,1: DMA Debug Registers option is selected" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected" "0: TCP Segmentation Offload Feature is not selected,1: TCP Segmentation Offload Feature is selected" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected" "0: Split Header Feature is not selected,1: Split Header Feature is selected" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected" "0: DCB Feature is not selected,1: DCB Feature is selected" newline bitfld.long 0x4 14.--15. "ADDR64,Address Width. This field indicates the configured address width:" "0: 32,1: 40,2: 48,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected" "0: IEEE 1588 High Word Register option is not..,1: IEEE 1588 High Word Register option is selected" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected." "0: PTP Offload feature is not selected,1: PTP Offload feature is selected" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected" "0: One-Step Timestamping feature is not selected,1: One-Step Timestamping feature is selected" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE) -7:" newline bitfld.long 0x4 5. "SPRAM,Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected." "0: Single Port RAM feature is not selected,1: Single Port RAM feature is selected" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE) -7:" line.long 0x8 "MAC_HW_Feature2,This register indicates the presence of third set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs:" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary input,3: 3 auxiliary input,4: 4 auxiliary input,?,?,?" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs:" "0: No PPS output,1: 1 PPS output,2: 2 PPS output,3: 3 PPS output,4: 4 PPS output,?,?,?" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels:" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels:" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues:" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues:" line.long 0xC "MAC_HW_Feature3,This register indicates the presence of fourth set the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0xC 28.--29. "ASP,Automotive Safety Package Following are the encoding for the different Safety features" "0: No Safety features selected,1: Only 'ECC protection for external memory'..,2: All the Automotive Safety features are selected..,3: All the Automotive Safety features are selected.." newline bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected" "0: Time Based Scheduling Enable feature is not..,1: Time Based Scheduling Enable feature is selected" newline bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected." "0: Frame Preemption Enable feature is not selected,1: Frame Preemption Enable feature is selected" newline bitfld.long 0xC 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field" "0: Width not configured,1: 16,2: 20,3: 24" newline bitfld.long 0xC 17.--19. "ESTDEP,Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5" "0: No Depth configured,1: 64,2: 128,3: 256,4: 512,5: 1024,?,?" newline bitfld.long 0xC 16. "ESTSEL,Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected" "0: Enable Enhancements to Scheduling Traffic..,1: Enable Enhancements to Scheduling Traffic.." newline bitfld.long 0xC 13.--14. "FRPES,Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser" "0: 64 Entries,1: 128 Entries,2: 256 Entries,?" newline bitfld.long 0xC 11.--12. "FRPBS,Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser" "0: 64 Bytes,1: 128 Bytes,2: 256 Bytes,?" newline bitfld.long 0xC 10. "FRPSEL,Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected" "0: Flexible Receive Parser feature is not selected,1: Flexible Receive Parser feature is selected" newline bitfld.long 0xC 9. "PDUPSEL,Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected" "0: Broadcast/Multicast Packet Duplication feature..,1: Broadcast/Multicast Packet Duplication feature.." newline bitfld.long 0xC 5. "DVLAN,Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected" "0: Double VLAN option is not selected,1: Double VLAN option is selected" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected" "0: Enable Queue/Channel based VLAN tag insertion on..,1: Enable Queue/Channel based VLAN tag insertion on.." newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected:" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?,?" group.long 0x140++0x3 line.long 0x0 "MAC_DPP_FSM_Interrupt_Status,This register contains the status of Automotive Safety related Data Path Parity Errors. Interface Timeout Errors. FSM State Parity Errors and FSM State Timeout Errors. All the non-Reserved bits are cleared on read." bitfld.long 0x0 24. "FSMPES,FSM State Parity Error Status This field when set indicates one of the FSMs State registers has a parity error detected" "0: FSM State Parity Error Status not detected,1: FSM State Parity Error Status detected" newline bitfld.long 0x0 16. "MSTTES,Master Read/Write Timeout Error Status This field when set indicates that an Application/CSR Timeout has occurred on the master (AXI/AHB/ARI/ATI) interface" "0: Master Read/Write Timeout Error Status not..,1: Master Read/Write Timeout Error Status detected" newline bitfld.long 0x0 12. "PTES,PTP FSM Timeout Error Status This field when set indicates that one of the PTP FSM Timeout has occurred" "0: PTP FSM Timeout Error Status not detected,1: PTP FSM Timeout Error Status detected" newline bitfld.long 0x0 11. "ATES,APP FSM Timeout Error Status This field when set indicates that one of the APP FSM Timeout has occurred" "0: APP FSM Timeout Error Status not detected,1: APP FSM Timeout Error Status detected" newline bitfld.long 0x0 9. "RTES,Rx FSM Timeout Error Status This field when set indicates that one of the Rx FSM Timeout has occurred" "0: Rx FSM Timeout Error Status not detected,1: Rx FSM Timeout Error Status detected" newline bitfld.long 0x0 8. "TTES,Tx FSM Timeout Error Status This field when set indicates that one of the Tx FSM Timeout has occurred" "0: Tx FSM Timeout Error Status not detected,1: Tx FSM Timeout Error Status detected" newline bitfld.long 0x0 5. "ARPES,This bit when set indicates that a parity error is detected at checker" "0: Application Receive interface data path Parity..,1: Application Receive interface data path Parity.." newline bitfld.long 0x0 4. "MTSPES,MTL TX Status data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL TX Status data on ati interface (or at PC5 as shown in Transmit data path parity protection diagram)" "0: MTL TX Status data path Parity checker Error..,1: MTL TX Status data path Parity checker Error.." newline bitfld.long 0x0 3. "MPES,MTL data path Parity checker Error Status This bit when set indicates that a parity error is detected at the MTL transmit write controller parity checker (or at PC4 as shown in Transmit data path parity protection diagram)" "0: MTL data path Parity checker Error Status not..,1: MTL data path Parity checker Error Status detected" newline bitfld.long 0x0 2. "RDPES,Read Descriptor Parity checker Error Status This bit when set indicates that a parity error is detected at the DMA Read descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram)" "0: Read Descriptor Parity checker Error Status not..,1: Read Descriptor Parity checker Error Status.." group.long 0x148++0xB line.long 0x0 "MAC_FSM_Control,This register is used to control the FSM State parity and timeout error injection in Debug mode." bitfld.long 0x0 28. "PLGRNML,PTP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for PTP domain else normal mode tic generation is used" "0: normal mode tic generation is used for PTP domain,1: large mode tic generation is used for PTP domain" newline bitfld.long 0x0 27. "ALGRNML,APP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for APP domain else normal mode tic generation is used" "0: normal mode tic generation is used for APP domain,1: large mode tic generation is used for APP domain" newline bitfld.long 0x0 25. "RLGRNML,Rx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Rx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Rx domain,1: large mode tic generation is used for Rx domain" newline bitfld.long 0x0 24. "TLGRNML,Tx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Tx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Tx domain,1: large mode tic generation is used for Tx domain" newline bitfld.long 0x0 20. "PPEIN,PTP FSM Parity Error Injection This field when set indicates that Error Injection for PTP FSM Parity is enabled" "0: PTP FSM Parity Error Injection is disabled,1: PTP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 19. "APEIN,APP FSM Parity Error Injection This field when set indicates that Error Injection for APP FSM Parity is enabled" "0: APP FSM Parity Error Injection is disabled,1: APP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 17. "RPEIN,Rx FSM Parity Error Injection This field when set indicates that Error Injection for RX FSM Parity is enabled" "0: Rx FSM Parity Error Injection is disabled,1: Rx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 16. "TPEIN,Tx FSM Parity Error Injection This field when set indicates that Error Injection for TX FSM Parity is enabled" "0: Tx FSM Parity Error Injection is disabled,1: Tx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 12. "PTEIN,PTP FSM Timeout Error Injection This field when set indicates that Error Injection for PTP FSM timeout is enabled" "0: PTP FSM Timeout Error Injection is disabled,1: PTP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 11. "ATEIN,APP FSM Timeout Error Injection This field when set indicates that Error Injection for APP FSM timeout is enabled" "0: APP FSM Timeout Error Injection is disabled,1: APP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 9. "RTEIN,Rx FSM Timeout Error Injection This field when set indicates that Error Injection for RX FSM timeout is enabled" "0: Rx FSM Timeout Error Injection is disabled,1: Rx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 8. "TTEIN,Tx FSM Timeout Error Injection This field when set indicates that Error Injection for TX FSM timeout is enabled" "0: Tx FSM Timeout Error Injection is disabled,1: Tx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 1. "PRTYEN,. This bit when set indicates that the FSM parity feature is enabled." "0: FSM Parity feature is disabled,1: FSM Parity feature is enabled" newline bitfld.long 0x0 0. "TMOUTEN,. This bit when set indicates that the FSM timeout feature is enabled." "0: FSM timeout feature is disabled,1: FSM timeout feature is enabled" line.long 0x4 "MAC_FSM_ACT_Timer,This register is used to select the FSM and Interface Timeout values." hexmask.long.byte 0x4 20.--23. 1. "LTMRMD,no description available" newline hexmask.long.byte 0x4 16.--19. 1. "NTMRMD,no description available" newline hexmask.long.word 0x4 0.--9. 1. "TMR,. This field indicates the number of CSR clocks required to generate 1us tic." line.long 0x8 "SCS_REG1,NXP Reserved Register" hexmask.long 0x8 0.--31. 1. "MAC_SCS1,NXP Reserved All the bits must be set to '0'" group.long 0x200++0x7 line.long 0x0 "MAC_MDIO_Address,The MDIO Address register controls the management cycles to external PHY through a management interface." bitfld.long 0x0 27. "PSE,Preamble Suppression Enable When this bit is set the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit" "0: Preamble Suppression disabled,1: Preamble Suppression enabled" newline bitfld.long 0x0 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0 then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted)" "0: Back to Back transactions disabled,1: Back to Back transactions enabled" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address These bits select the PHY register in selected Clause 22 PHY device" newline bitfld.long 0x0 12.--14. "NTC,Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR.." newline bitfld.long 0x0 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets" "0: Skip Address Packet is disabled,1: Skip Address Packet is enabled" newline bitfld.long 0x0 3. "GOC_1,GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or RevMII GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or.." "0: Reserved,1: Write" newline bitfld.long 0x0 2. "GOC_0,GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII" "0: GMII Operation Command 0 is disabled,1: GMII Operation Command 0 is enabled" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO" "0: Clause 45 PHY is disabled,1: Clause 45 PHY is enabled" newline bitfld.long 0x0 0. "GB,GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave" "0: GMII Busy is disabled,1: GMII Busy is enabled" line.long 0x4 "MAC_MDIO_Data,The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address. This register also stores the Read data from the PHY register located at the address specified by MDIO.." hexmask.long.word 0x4 16.--31. 1. "RA,Register Address This field is valid only when C45E is set" newline hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation" group.long 0x210++0x3 line.long 0x0 "MAC_ARP_Address,The ARP Address register contains the IPv4 Destination Address of the MAC." hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address This field contains the IPv4 Destination Address of the MAC" group.long 0x230++0xB line.long 0x0 "MAC_CSR_SW_Ctrl,This register contains SW programmable controls for changing the CSR access response and status bits clearing." bitfld.long 0x0 8. "SEEN,Slave Error Response Enable When this bit is set the MAC responds with Slave Error for accesses to reserved registers in CSR space" "0: Slave Error Response is disabled,1: Slave Error Response is enabled" newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable When this bit is set the access mode of some register fields changes to Clear on Write 1 the application needs to set that respective bit to 1 to clear it" "0: Register Clear on Write 1 is disabled,1: Register Clear on Write 1 is enabled" line.long 0x4 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption." bitfld.long 0x4 19. "TRSP,Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field)" "0: Not transmitted Respond Frame,1: transmitted Respond Frame" newline bitfld.long 0x4 18. "TVER,Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field)" "0: Not transmitted Verify Frame,1: transmitted Verify Frame" newline bitfld.long 0x4 17. "RRSP,Received Respond Frame Set when a Respond mPacket is received" "0: Not received Respond Frame,1: Received Respond Frame" newline bitfld.long 0x4 16. "RVER,Received Verify Frame Set when a Verify mPacket is received" "0: Not received Verify Frame,1: Received Verify Frame" newline bitfld.long 0x4 3. "S1_SET_0,NXP Reserved Must be set to '0'" "0,1" newline bitfld.long 0x4 2. "SRSP,Send Respond mPacket When set indicates hardware to send a Respond mPacket" "0: Send Respond mPacket is disabled,1: Send Respond mPacket is enabled" newline bitfld.long 0x4 1. "SVER,Send Verify mPacket When set indicates hardware to send a verify mPacket" "0: Send Verify mPacket is disabled,1: Send Verify mPacket is enabled" newline bitfld.long 0x4 0. "EFPE,Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled." "0: Tx Frame Preemption is disabled,1: Tx Frame Preemption is enabled" line.long 0x8 "MAC_Ext_Cfg1,This register contains Split mode control field and offset field for Split Header feature." bitfld.long 0x8 8.--9. "SPLM,Split Mode These bits indicate the mode of splitting the incoming Rx packets. They are" "0: Split at L3/L4 header,1: Split at L2 header with an offset. Always Split..,2: Combination mode: Split similar to SPLM=00 for..,?" newline hexmask.long.byte 0x8 0.--6. 1. "SPLOFST,Split Offset These bits indicate the value of offset from the beginning of Length/Type field at which header split should take place when the appropriate SPLM is selected" rgroup.long 0x240++0x3 line.long 0x0 "MAC_Presn_Time_ns,This register contains the 32-bit binary rollover equivalent time of the PTP System Time in ns Exists when DWC_EQOS_FLEXI_PPS_OUT_EN is configured" hexmask.long 0x0 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns" group.long 0x244++0x3 line.long 0x0 "MAC_Presn_Time_Updt,This field holds the 32-bit value of MAC 1722 Presentation Time in ns. that should be added to the Current Presentation Time Counter value. Init happens when TSINIT is set. and update happens when the TSUPDT bit is set (TSINIT and.." hexmask.long 0x0 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time" group.long 0x300++0xF line.long 0x0 "MAC_Address0_High,The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register." rbitfld.long 0x0 31. "AE,Address Enable This bit is always set to 1." "0: INVALID : This bit must be always set to 1,1: This bit is always set to 1" newline hexmask.long.byte 0x0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address" line.long 0x4 "MAC_Address0_Low,The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station." hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address" line.long 0x8 "MAC_Address1_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled" newline bitfld.long 0x8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" newline hexmask.long.byte 0x8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xC "MAC_Address1_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address" group.long 0x700++0x3 line.long 0x0 "MMC_Control,This register establishes the operating mode of MMC." bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit" "0: Update MMC Counters for Dropped Broadcast..,1: Update MMC Counters for Dropped Broadcast.." newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value" "0: Full-Half Preset is disabled,1: Full-Half Preset is enabled" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit" "0: Counters Preset is disabled,1: Counters Preset is enabled" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value" "0: MMC Counter Freeze is disabled,1: MMC Counter Freeze is enabled" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset)" "0: Reset on Read is disabled,1: Reset on Read is enabled" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value" "0: Counter Stop Rollover is disabled,1: Counter Stop Rollover is enabled" newline bitfld.long 0x0 0. "CNTRST,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset" rgroup.long 0x704++0x7 line.long 0x0 "MMC_Rx_Interrupt,This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: - Receive statistic counters reach half of.." bitfld.long 0x0 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.." newline bitfld.long 0x0 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.." newline bitfld.long 0x0 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt Status..,1: MMC Receive Runt Packet Counter Interrupt Status.." newline bitfld.long 0x0 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter Interrupt..,1: MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Status..,1: MMC Receive Good Octet Counter Interrupt Status.." newline bitfld.long 0x0 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_Tx_Interrupt,This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000.." bitfld.long 0x4 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter Interrupt..,1: MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.." newline bitfld.long 0x4 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet Counter..,1: MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.." newline bitfld.long 0x4 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt Status..,1: MMC Transmit Good Octet Counter Interrupt Status.." newline bitfld.long 0x4 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet Counter..,1: MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter Interrupt..,1: MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet Counter..,1: MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet Counter..,1: MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad Packet..,1: MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter Interrupt..,1: MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.." group.long 0x70C++0x7 line.long 0x0 "MMC_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of.." bitfld.long 0x0 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt Mask..,1: MMC Receive Error Packet Counter Interrupt Mask.." newline bitfld.long 0x0 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt Mask..,1: MMC Receive Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x0 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt Mask..,1: MMC Receive Runt Packet Counter Interrupt Mask.." newline bitfld.long 0x0 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter Interrupt..,1: MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Mask is..,1: MMC Receive Good Octet Counter Interrupt Mask is.." newline bitfld.long 0x0 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach.." bitfld.long 0x4 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter Interrupt..,1: MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt Mask..,1: MMC Transmit Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x4 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet Counter..,1: MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt Mask..,1: MMC Transmit Good Packet Counter Interrupt Mask.." newline bitfld.long 0x4 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt Mask..,1: MMC Transmit Good Octet Counter Interrupt Mask.." newline bitfld.long 0x4 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet Counter..,1: MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter Interrupt..,1: MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet Counter..,1: MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet Counter..,1: MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad Packet..,1: MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter Interrupt..,1: MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.." rgroup.long 0x714++0x67 line.long 0x0 "Tx_Octet_Count_Good_Bad,This register provides the number of bytes transmitted by the DWC_ether_qos. exclusive of preamble and retried bytes. in good and bad packets." hexmask.long 0x0 0.--31. 1. "TXOCTGB,Tx Octet Count Good Bad This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets" line.long 0x4 "Tx_Packet_Count_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos. exclusive of retried packets." hexmask.long 0x4 0.--31. 1. "TXPKTGB,Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted exclusive of retried packets" line.long 0x8 "Tx_Broadcast_Packets_Good,This register provides the number of good broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x8 0.--31. 1. "TXBCASTG,Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted." line.long 0xC "Tx_Multicast_Packets_Good,This register provides the number of good multicast packets transmitted by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "TXMCASTG,Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted." line.long 0x10 "Tx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 64 bytes. exclusive of preamble and retried packets." hexmask.long 0x10 0.--31. 1. "TX64OCTGB,Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets" line.long 0x14 "Tx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x14 0.--31. 1. "TX65_127OCTGB,Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x18 "Tx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 128 to 255 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x18 0.--31. 1. "TX128_255OCTGB,Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x1C "Tx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 256 to 511 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x1C 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x20 "Tx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 512 to 1023 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x20 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x24 "Tx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 1024 to maxsize (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x24 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes exclusive of preamble and retried packets" line.long 0x28 "Tx_Unicast_Packets_Good_Bad,This register provides the number of good and bad unicast packets transmitted by DWC_ether_qos." hexmask.long 0x28 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted" line.long 0x2C "Tx_Multicast_Packets_Good_Bad,This register provides the number of good and bad multicast packets transmitted by DWC_ether_qos." hexmask.long 0x2C 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted" line.long 0x30 "Tx_Broadcast_Packets_Good_Bad,This register provides the number of good and bad broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x30 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted" line.long 0x34 "Tx_Underflow_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of packets underflow error." hexmask.long 0x34 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error" line.long 0x38 "Tx_Single_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after a single collision in the half-duplex mode." hexmask.long 0x38 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode" line.long 0x3C "Tx_Multiple_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after multiple collisions in the half-duplex mode." hexmask.long 0x3C 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode" line.long 0x40 "Tx_Deferred_Packets,This register provides the number of successfully transmitted by DWC_ether_qos after a deferral in the half-duplex mode." hexmask.long 0x40 0.--31. 1. "TXDEFRD,Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode" line.long 0x44 "Tx_Late_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of late collision error." hexmask.long 0x44 0.--31. 1. "TXLATECOL,Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error" line.long 0x48 "Tx_Excessive_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of excessive (16) collision errors." hexmask.long 0x48 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors" line.long 0x4C "Tx_Carrier_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of carrier sense error (no carrier or loss of carrier)." hexmask.long 0x4C 0.--31. 1. "TXCARR,Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier)" line.long 0x50 "Tx_Octet_Count_Good,This register provides the number of bytes transmitted by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x50 0.--31. 1. "TXOCTG,Tx Octet Count Good This field indicates the number of bytes transmitted exclusive of preamble only in good packets" line.long 0x54 "Tx_Packet_Count_Good,This register provides the number of good packets transmitted by DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "TXPKTG,Tx Packet Count Good This field indicates the number of good packets transmitted." line.long 0x58 "Tx_Excessive_Deferral_Error,This register provides the number of packets aborted by DWC_ether_qos because of excessive deferral error (deferred for more than two max-sized packet times)." hexmask.long 0x58 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times)" line.long 0x5C "Tx_Pause_Packets,This register provides the number of good Pause packets transmitted by DWC_ether_qos." hexmask.long 0x5C 0.--31. 1. "TXPAUSE,Tx Pause Packets This field indicates the number of good Pause packets transmitted." line.long 0x60 "Tx_VLAN_Packets_Good,This register provides the number of good VLAN packets transmitted by DWC_ether_qos." hexmask.long 0x60 0.--31. 1. "TXVLANG,Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted." line.long 0x64 "Tx_OSize_Packets_Good,This register provides the number of packets transmitted by DWC_ether_qos without errors and with length greater than the maxsize (1.518 or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the.." hexmask.long 0x64 0.--31. 1. "TXOSIZG,Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the MAC_Configuration register)" rgroup.long 0x780++0x67 line.long 0x0 "Rx_Packets_Count_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos." hexmask.long 0x0 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad This field indicates the number of good and bad packets received." line.long 0x4 "Rx_Octet_Count_Good_Bad,This register provides the number of bytes received by DWC_ther_qos. exclusive of preamble. in good and bad packets." hexmask.long 0x4 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad This field indicates the number of bytes received exclusive of preamble in good and bad packets" line.long 0x8 "Rx_Octet_Count_Good,This register provides the number of bytes received by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x8 0.--31. 1. "RXOCTG,Rx Octet Count Good This field indicates the number of bytes received exclusive of preamble only in good packets" line.long 0xC "Rx_Broadcast_Packets_Good,This register provides the number of good broadcast packets received by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good This field indicates the number of good broadcast packets received." line.long 0x10 "Rx_Multicast_Packets_Good,This register provides the number of good multicast packets received by DWC_ether_qos." hexmask.long 0x10 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good This field indicates the number of good multicast packets received." line.long 0x14 "Rx_CRC_Error_Packets,This register provides the number of packets received by DWC_ether_qos with CRC error." hexmask.long 0x14 0.--31. 1. "RXCRCERR,Rx CRC Error Packets This field indicates the number of packets received with CRC error." line.long 0x18 "Rx_Alignment_Error_Packets,This register provides the number of packets received by DWC_ether_qos with alignment (dribble) error. It is valid only in 10/100 mode." hexmask.long 0x18 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error" line.long 0x1C "Rx_Runt_Error_Packets,This register provides the number of packets received by DWC_ether_qos with runt (length less than 64 bytes and CRC error) error." hexmask.long 0x1C 0.--31. 1. "RXRUNTERR,Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error" line.long 0x20 "Rx_Jabber_Error_Packets,This register provides the number of giant packets received by DWC_ether_qos with length (including CRC) greater than 1.518 bytes (1.522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled. packets of length.." hexmask.long 0x20 0.--31. 1. "RXJABERR,Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error" line.long 0x24 "Rx_Undersize_Packets_Good,This register provides the number of packets received by DWC_ether_qos with length less than 64 bytes. without any errors." hexmask.long 0x24 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes without any errors" line.long 0x28 "Rx_Oversize_Packets_Good,This register provides the number of packets received by DWC_ether_qos without errors. with length greater than the maxsize (1.518 bytes or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." hexmask.long 0x28 0.--31. 1. "RXOVERSZG,Rx Oversize Packets Good This field indicates the number of packets received without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." line.long 0x2C "Rx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length 64 bytes. exclusive of the preamble." hexmask.long 0x2C 0.--31. 1. "RX64OCTGB,Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble" line.long 0x30 "Rx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x30 0.--31. 1. "RX65_127OCTGB,Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble" line.long 0x34 "Rx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 128 and 255 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x34 0.--31. 1. "RX128_255OCTGB,Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble" line.long 0x38 "Rx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 256 and 511 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x38 0.--31. 1. "RX256_511OCTGB,Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble" line.long 0x3C "Rx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 512 and 1023 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x3C 0.--31. 1. "RX512_1023OCTGB,RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble" line.long 0x40 "Rx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 1024 and maxsize (inclusive) bytes. exclusive of the preamble." hexmask.long 0x40 0.--31. 1. "RX1024_MAXOCTGB,Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble" line.long 0x44 "Rx_Unicast_Packets_Good,This register provides the number of good unicast packets received by DWC_ether_qos." hexmask.long 0x44 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good This field indicates the number of good unicast packets received." line.long 0x48 "Rx_Length_Error_Packets,This register provides the number of packets received by DWC_ether_qos with length error (Length Type field not equal to packet size). for all packets with valid length field." hexmask.long 0x48 0.--31. 1. "RXLENERR,Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field" line.long 0x4C "Rx_Out_Of_Range_Type_Packets,This register provides the number of packets received by DWC_ether_qos with length field not equal to the valid packet size (greater than 1.500 but less than 1.536)." hexmask.long 0x4C 0.--31. 1. "RXOUTOFRNG,Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)" line.long 0x50 "Rx_Pause_Packets,This register provides the number of good and valid Pause packets received by DWC_ether_qos." hexmask.long 0x50 0.--31. 1. "RXPAUSEPKT,Rx Pause Packets This field indicates the number of good and valid Pause packets received." line.long 0x54 "Rx_FIFO_Overflow_Packets,This register provides the number of missed received packets because of FIFO overflow in DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "RXFIFOOVFL,Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow" line.long 0x58 "Rx_VLAN_Packets_Good_Bad,This register provides the number of good and bad VLAN packets received by DWC_ether_qos." hexmask.long 0x58 0.--31. 1. "RXVLANPKTGB,Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received." line.long 0x5C "Rx_Watchdog_Error_Packets,This register provides the number of packets received by DWC_ether_qos with error because of watchdog timeout error (packets with a data load larger than 2.048 bytes (when JE and WD bits are reset in MAC_Configuration register)..." hexmask.long 0x5C 0.--31. 1. "RXWDGERR,Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_Configuration register) 10 240.." line.long 0x60 "Rx_Receive_Error_Packets,This register provides the number of packets received by DWC_ether_qos with Receive error or Packet Extension error on the GMII or MII interface." hexmask.long 0x60 0.--31. 1. "RXRCVERR,Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface" line.long 0x64 "Rx_Control_Packets_Good,This register provides the number of good control packets received by DWC_ether_qos." hexmask.long 0x64 0.--31. 1. "RXCTRLG,Rx Control Packets Good This field indicates the number of good control packets received." rgroup.long 0x8A0++0x3 line.long 0x0 "MMC_FPE_Tx_Interrupt,This register maintains the interrupts generated from all FPE related Transmit statistics counters. The MMC FPE Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx Hold Request Counter Interrupt Status not..,1: MMC Tx Hold Request Counter Interrupt Status.." newline bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx FPE Fragment Counter Interrupt status not..,1: MMC Tx FPE Fragment Counter Interrupt status.." group.long 0x8A4++0x3 line.long 0x0 "MMC_FPE_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Hold Request Counter Interrupt Mask..,1: MMC Transmit Hold Request Counter Interrupt Mask.." newline bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Fragment Counter Interrupt Mask is..,1: MMC Transmit Fragment Counter Interrupt Mask is.." rgroup.long 0x8A8++0x7 line.long 0x0 "MMC_Tx_FPE_Fragment_Cntr,This register provides the number of additional mPackets transmitted due to preemption." hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration" line.long 0x4 "MMC_Tx_Hold_Req_Cntr,This register provides the count of number of times a hold request is given to MAC" hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC" rgroup.long 0x8C0++0x3 line.long 0x0 "MMC_FPE_Rx_Interrupt,This register maintains the interrupts generated from all FPE related Receive statistics counters. The MMC FPE Receive Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Status not..,1: MMC Rx FPE Fragment Counter Interrupt Status.." newline bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.." newline bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt Status..,1: MMC Rx Packet SMD Error Counter Interrupt Status.." newline bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter Interrupt..,1: MMC Rx Packet Assembly Error Counter Interrupt.." group.long 0x8C4++0x3 line.long 0x0 "MMC_FPE_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Mask is..,1: MMC Rx FPE Fragment Counter Interrupt Mask is.." newline bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt Mask..,1: MMC Rx Packet Assembly OK Counter Interrupt Mask.." newline bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt Mask..,1: MMC Rx Packet SMD Error Counter Interrupt Mask.." newline bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter Interrupt..,1: MMC Rx Packet Assembly Error Counter Interrupt.." rgroup.long 0x8C8++0xF line.long 0x0 "MMC_Rx_Packet_Assembly_Err_Cntr,This register provides the number of MAC frames with reassembly errors on the Receiver. due to mismatch in the Fragment Count value." hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value" line.long 0x4 "MMC_Rx_Packet_SMD_Err_Cntr,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame." hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame" line.long 0x8 "MMC_Rx_Packet_Assembly_OK_Cntr,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC." hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC" line.long 0xC "MMC_Rx_FPE_Fragment_Cntr,This register provides the number of additional mPackets received due to preemption." hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration" group.long 0x900++0x7 line.long 0x0 "MAC_L3_L4_Control0,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." bitfld.long 0x0 28. "DMCHEN0,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline bitfld.long 0x0 24.--26. "DMCHN0,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address0,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x910++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg0,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg0,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg0,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg0,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x930++0x7 line.long 0x0 "MAC_L3_L4_Control1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." bitfld.long 0x0 28. "DMCHEN1,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline bitfld.long 0x0 24.--26. "DMCHN1,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address1,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x940++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg1,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg1,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A11,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg1,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A21,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg1,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A31,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x960++0x7 line.long 0x0 "MAC_L3_L4_Control2,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." bitfld.long 0x0 28. "DMCHEN2,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline bitfld.long 0x0 24.--26. "DMCHN2,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM2,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM2,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline bitfld.long 0x0 16. "L4PEN2,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM2,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM2,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM2,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM2,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline bitfld.long 0x0 0. "L3PEN2,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address2,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x970++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg2,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A02,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg2,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A12,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg2,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A22,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg2,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A32,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x990++0x7 line.long 0x0 "MAC_L3_L4_Control3,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." bitfld.long 0x0 28. "DMCHEN3,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline bitfld.long 0x0 24.--26. "DMCHN3,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM3,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM3,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline bitfld.long 0x0 16. "L4PEN3,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM3,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM3,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM3,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM3,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline bitfld.long 0x0 0. "L3PEN3,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address3,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x9A0++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg3,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A03,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg3,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A13,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg3,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A23,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg3,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A33,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x9C0++0x7 line.long 0x0 "MAC_L3_L4_Control4,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." bitfld.long 0x0 28. "DMCHEN4,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline bitfld.long 0x0 24.--26. "DMCHN4,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "L4DPIM4,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM4,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM4,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM4,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline bitfld.long 0x0 16. "L4PEN4,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM4,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM4,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM4,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM4,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM4,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM4,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline bitfld.long 0x0 0. "L3PEN4,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address4,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP4,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP4,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x9D0++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg4,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A04,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg4,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A14,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg4,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A24,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg4,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A34,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x9F0++0x7 line.long 0x0 "MAC_L3_L4_Control5,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." bitfld.long 0x0 28. "DMCHEN5,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline bitfld.long 0x0 24.--26. "DMCHN5,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "L4DPIM5,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM5,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM5,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM5,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline bitfld.long 0x0 16. "L4PEN5,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM5,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM5,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM5,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM5,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM5,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM5,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline bitfld.long 0x0 0. "L3PEN5,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address5,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP5,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP5,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0xA00++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg5,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A05,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg5,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A15,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg5,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A25,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg5,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A35,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0xA20++0x7 line.long 0x0 "MAC_L3_L4_Control6,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." bitfld.long 0x0 28. "DMCHEN6,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline bitfld.long 0x0 24.--26. "DMCHN6,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "L4DPIM6,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM6,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM6,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM6,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline bitfld.long 0x0 16. "L4PEN6,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM6,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM6,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM6,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM6,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM6,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM6,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline bitfld.long 0x0 0. "L3PEN6,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address6,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP6,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP6,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0xA30++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg6,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A06,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg6,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A16,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg6,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A26,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg6,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A36,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0xA50++0x7 line.long 0x0 "MAC_L3_L4_Control7,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." bitfld.long 0x0 28. "DMCHEN7,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline bitfld.long 0x0 24.--26. "DMCHN7,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "L4DPIM7,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM7,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM7,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM7,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline bitfld.long 0x0 16. "L4PEN7,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM7,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM7,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM7,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM7,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM7,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM7,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline bitfld.long 0x0 0. "L3PEN7,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address7,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP7,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP7,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0xA60++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg7,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A07,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg7,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A17,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg7,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A27,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg7,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A37,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0xB00++0x7 line.long 0x0 "MAC_Timestamp_Control,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver." bitfld.long 0x0 28. "AV8021ASMEN,AV 802" "0: AV 802.1AS Mode is disabled,1: AV 802.1AS Mode is enabled" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software" "0: Transmit Timestamp Status Mode is disabled,1: Transmit Timestamp Status Mode is enabled" newline bitfld.long 0x0 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "0: External System Time Input is disabled,1: External System Time Input is enabled" newline bitfld.long 0x0 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum correct for changes made to origin timestamp and/or correction field.." "0: checksum correction during OST for PTP over..,1: checksum correction during OST for PTP over.." newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet" "0: MAC Address for PTP Packet Filtering is disabled,1: MAC Address for PTP Packet Filtering is enabled" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node" "0: Snapshot for Messages Relevant to Master is..,1: Snapshot for Messages Relevant to Master is.." newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp)" "0: Timestamp Snapshot for Event Messages is disabled,1: Timestamp Snapshot for Event Messages is enabled" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets" "0: Processing of PTP Packets Sent over IPv4-UDP is..,1: Processing of PTP Packets Sent over IPv4-UDP is.." newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets" "0: Processing of PTP Packets Sent over IPv6-UDP is..,1: Processing of PTP Packets Sent over IPv6-UDP is.." newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets" "0: Processing of PTP over Ethernet Packets is..,1: Processing of PTP over Ethernet Packets is enabled" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets" "0: PTP Packet Processing for Version 2 Format is..,1: PTP Packet Processing for Version 2 Format is.." newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds" "0: Timestamp Digital or Binary Rollover Control is..,1: Timestamp Digital or Binary Rollover Control is.." newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC" "0: Timestamp for All Packets disabled,1: Timestamp for All Packets enabled" newline bitfld.long 0x0 6. "PTGE,Presentation Time Generation Enable When this bit is set the Presentation Time generation is enabled" "0: Presentation Time Generation is disabled,1: Presentation Time Generation is enabled" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction" "0: Addend Register is not updated,1: Addend Register is updated" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not updated,1: Timestamp is updated" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not initialized,1: Timestamp is initialized" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp" "0: Coarse method is used to update system timestamp,1: Fine method is used to update system timestamp" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp When this bit is set the timestamp is added for Transmit and Receive packets" "0: Timestamp is disabled,1: Timestamp is enabled" line.long 0x4 "MAC_Sub_Second_Increment,This register specifies the value to be added to the internal system time register every cycle of clk_ptp_ref_i clock." hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register" newline hexmask.long.byte 0x4 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value represented in nanoseconds multiplied by 2^8" rgroup.long 0xB08++0x7 line.long 0x0 "MAC_System_Time_Seconds,The System Time Seconds register. along with System Time Nanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the actual.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC" line.long 0x4 "MAC_System_Time_Nanoseconds,The System Time Nanoseconds register. along with System Time Seconds register. indicates the current value of the system time maintained by the MAC." hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0" group.long 0xB10++0xF line.long 0x0 "MAC_System_Time_Seconds_Update,The System Time Seconds Update register. along with the System Time Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds The value in this field is the seconds part of the update" line.long 0x4 "MAC_System_Time_Nanoseconds_Update,MAC System Time Nanoseconds Update register." bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register" "0: Add time,1: Subtract time" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field is the sub-seconds part of the update" line.long 0x8 "MAC_Timestamp_Addend,Timestamp Addend register. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the MAC_Timestamp_Control register). The content of this register is added to a 32-bit accumulator.." hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization" line.long 0xC "MAC_System_Time_Higher_Word_Seconds,System Time - Higher Word Seconds register." hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value" rgroup.long 0xB20++0x3 line.long 0x0 "MAC_Timestamp_Status,Timestamp Status register. All bits except Bits[27:25] gets cleared when the application reads this register." hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO" newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set" "0: Auxiliary Timestamp Snapshot Trigger Missed..,1: Auxiliary Timestamp Snapshot Trigger Missed.." newline hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable" newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and.." "0: Tx Timestamp Status Interrupt status not detected,1: Tx Timestamp Status Interrupt status detected" newline bitfld.long 0x0 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers" "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers" "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers" "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO" "0: Auxiliary Timestamp Trigger Snapshot status not..,1: Auxiliary Timestamp Trigger Snapshot status.." newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers" "0: Timestamp Target Time Reached status not detected,1: Timestamp Target Time Reached status detected" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF" "0: Timestamp Seconds Overflow status not detected,1: Timestamp Seconds Overflow status detected" rgroup.long 0xB30++0x7 line.long 0x0 "MAC_Tx_Timestamp_Status_Nanoseconds,This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled. The MAC_Tx_Timestamp_Status_Nanoseconds register. along with MAC_Tx_Timestamp_Status_Seconds. gives the.." bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the MAC_Timestamp_Control register is reset - The timestamp of the previous packet is.." "0: Transmit Timestamp Status Missed status not..,1: Transmit Timestamp Status Missed status detected" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp" line.long 0x4 "MAC_Tx_Timestamp_Status_Seconds,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted." hexmask.long 0x4 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp" group.long 0xB40++0x3 line.long 0x0 "MAC_Auxiliary_Control,The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot." bitfld.long 0x0 7. "ATSEN3,Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 6. "ATSEN2,Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear When set this bit resets the pointers of the Auxiliary Snapshot FIFO" "0: Auxiliary Snapshot FIFO Clear is disabled,1: Auxiliary Snapshot FIFO Clear is enabled" rgroup.long 0xB48++0x7 line.long 0x0 "MAC_Auxiliary_Timestamp_Nanoseconds,The Auxiliary Timestamp Nanoseconds register. along with MAC_Auxiliary_Timestamp_Seconds. gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a.." hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp." line.long 0x4 "MAC_Auxiliary_Timestamp_Seconds,The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register." hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp." group.long 0xB50++0x17 line.long 0x0 "MAC_Timestamp_Ingress_Asym_Corr,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages." hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet" line.long 0x4 "MAC_Timestamp_Egress_Asym_Corr,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages." hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet" line.long 0x8 "MAC_Timestamp_Ingress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path." hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression" line.long 0xC "MAC_Timestamp_Egress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path." hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression" line.long 0x10 "MAC_Timestamp_Ingress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for ingress direction." hexmask.long.byte 0x10 8.--15. 1. "TSICSNS,Timestamp Ingress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the 'Ingress Correction' expression" line.long 0x14 "MAC_Timestamp_Egress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for egress direction." hexmask.long.byte 0x14 8.--15. 1. "TSECSNS,Timestamp Egress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the 'Egress Correction' expression" rgroup.long 0xB68++0x7 line.long 0x0 "MAC_Timestamp_Ingress_Latency,This register holds the Ingress MAC latency." hexmask.long.word 0x0 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken" newline hexmask.long.byte 0x0 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken" line.long 0x4 "MAC_Timestamp_Egress_Latency,This register holds the Egress MAC latency." hexmask.long.word 0x4 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC" newline hexmask.long.byte 0x4 8.--15. 1. "ETLSNS,Egress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC" group.long 0xB70++0x3 line.long 0x0 "MAC_PPS_Control,PPS Control register. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more.." bitfld.long 0x0 31. "MCGREN3,MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode" "0,1" newline bitfld.long 0x0 29.--30. "TRGTMODSEL3,Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds) mode for PPS3 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline hexmask.long.byte 0x0 24.--27. 1. "PPSCMD3,Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal" newline bitfld.long 0x0 23. "MCGREN2,MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode" "0: 2nd PPS instance is disabled to operate in PPS..,1: 2nd PPS instance is enabled to operate in PPS or.." newline bitfld.long 0x0 21.--22. "TRGTMODSEL2,Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds) mode for PPS2 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline hexmask.long.byte 0x0 16.--19. 1. "PPSCMD2,Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal" newline bitfld.long 0x0 15. "MCGREN1,MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode" "0: 1st PPS instance is disabled to operate in PPS..,1: 1st PPS instance is enabled to operate in PPS or.." newline bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds) mode for PPS1 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline hexmask.long.byte 0x0 8.--11. 1. "PPSCMD1,Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal" newline bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode" "0: 0th PPS instance is enabled to operate in PPS mode,1: 0th PPS instance is enabled to operate in MCGR.." newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds) mode for PPS0 output signal:" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable When this bit is set Bits[3:0] function as PPSCMD" "0: Flexible PPS Output Mode is disabled,1: Flexible PPS Output Mode is enabled" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL_PPSCMD,PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal" group.long 0xB80++0x53 line.long 0x0 "MAC_PPS0_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x4 "MAC_PPS0_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x8 "MAC_PPS0_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0xC "MAC_PPS0_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x10 "MAC_PPS1_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x10 0.--31. 1. "TSTRH1,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x14 "MAC_PPS1_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x14 31. "TRGTBUSY1,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x14 0.--30. 1. "TTSL1,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x18 "MAC_PPS1_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x18 0.--31. 1. "PPSINT1,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0x1C "MAC_PPS1_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x1C 0.--31. 1. "PPSWIDTH1,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x20 "MAC_PPS2_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x20 0.--31. 1. "TSTRH2,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x24 "MAC_PPS2_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x24 31. "TRGTBUSY2,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x24 0.--30. 1. "TTSL2,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x28 "MAC_PPS2_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x28 0.--31. 1. "PPSINT2,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0x2C "MAC_PPS2_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x2C 0.--31. 1. "PPSWIDTH2,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x30 "MAC_PPS3_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x30 0.--31. 1. "TSTRH3,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x34 "MAC_PPS3_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x34 31. "TRGTBUSY3,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x34 0.--30. 1. "TTSL3,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x38 "MAC_PPS3_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x38 0.--31. 1. "PPSINT3,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0x3C "MAC_PPS3_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x3C 0.--31. 1. "PPSWIDTH3,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x40 "MAC_PTO_Control,This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long.byte 0x40 8.--15. 1. "DN,Domain Number This field indicates the domain Number in which the PTP node is operating." newline bitfld.long 0x40 7. "PDRDIS,Disable Peer Delay Response response generation When this bit is set the Peer Delay Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) request packet as required by the programmed mode" "0: Peer Delay Response response generation is enabled,1: Peer Delay Response response generation is.." newline bitfld.long 0x40 6. "DRRDIS,Disable PTO Delay Request/Response response generation When this bit is set the Delay Request and Delay response is not generated for received SYNC and Delay request packet respectively as required by the programmed mode" "0: PTO Delay Request/Response response generation..,1: PTO Delay Request/Response response generation.." newline bitfld.long 0x40 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger When this bit is set one PTP Pdelay_Req message is transmitted" "0: Automatic PTP Pdelay_Req message Trigger is..,1: Automatic PTP Pdelay_Req message Trigger is.." newline bitfld.long 0x40 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger When this bit is set one PTP SYNC message is transmitted" "0: Automatic PTP SYNC message Trigger is disabled,1: Automatic PTP SYNC message Trigger is enabled" newline bitfld.long 0x40 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable When this bit is set PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Peer-to-Peer Transparent mode" "0: Automatic PTP Pdelay_Req message is disabled,1: Automatic PTP Pdelay_Req message is enabled" newline bitfld.long 0x40 1. "ASYNCEN,Automatic PTP SYNC message Enable When this bit is set PTP SYNC message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Clock Master mode" "0: Automatic PTP SYNC message is disabled,1: Automatic PTP SYNC message is enabled" newline bitfld.long 0x40 0. "PTOEN,PTP Offload Enable When this bit is set the PTP Offload feature is enabled." "0: PTP Offload feature is disabled,1: PTP Offload feature is enabled" line.long 0x44 "MAC_Source_Port_Identity0,This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long 0x44 0.--31. 1. "SPI0,Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node." line.long 0x48 "MAC_Source_Port_Identity1,This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long 0x48 0.--31. 1. "SPI1,Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node." line.long 0x4C "MAC_Source_Port_Identity2,This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long.word 0x4C 0.--15. 1. "SPI2,Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node." line.long 0x50 "MAC_Log_Message_Interval,. This register contains the periodic intervals for automatic PTP packet generation. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long.byte 0x50 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node" newline bitfld.long 0x50 8.--10. "DRSYNCR,no description available" "0: DelayReq generated for every received SYNC,1: DelayReq generated every alternate reception of..,2: for every 4 SYNC messages,3: for every 8 SYNC messages,4: for every 16 SYNC messages,5: for every 32 SYNC messages,?,?" newline hexmask.long.byte 0x50 0.--7. 1. "LSI,no description available" group.long 0xC00++0x3 line.long 0x0 "MTL_Operation_Mode,The Operation Mode register establishes the Transmit and Receive operating modes and commands." bitfld.long 0x0 15. "FRPE,Flexible Rx parser Enable When this bit is set to 1 the Programmable Rx Parser functionality is enabled" "0: Flexible Rx parser is disabled,1: Flexible Rx parser is enabled" newline bitfld.long 0x0 9. "CNTCLR,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset When this bit is set - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0" "0: Counters Preset is disabled,1: Counters Preset is enabled" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling:" "0: WRR algorithm,1: WFQ algorithm when DCB feature is..,2: DWRR algorithm when DCB feature is..,3: Strict priority algorithm" newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status When this bit is set the Tx packet status received from the MAC is dropped in the MTL" "0: Drop Transmit Status is disabled,1: Drop Transmit Status is enabled" group.long 0xC08++0xB line.long 0x0 "MTL_DBG_CTL,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access." bitfld.long 0x0 17.--18. "EIEC,ECC Inject Error Control for Tx Rx and TSO memories When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field" newline bitfld.long 0x0 16. "EIEE,ECC Inject Error Enable for Tx Rx and TSO memories When set enables the ECC error injection feature" "0: ECC Inject Error for Tx Rx and TSO memories is..,1: ECC Inject Error for Tx Rx and TSO memories is.." newline bitfld.long 0x0 15. "STSIE,Transmit Status Available Interrupt Status Enable When this bit is set an interrupt is generated when Transmit status is available in slave mode" "0: Transmit Packet Available Interrupt Status is..,1: Transmit Packet Available Interrupt Status is.." newline bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable When this bit is set an interrupt is generated when EOP of received packet is written to the Rx FIFO" "0: Receive Packet Available Interrupt Status is..,1: Receive Packet Available Interrupt Status is.." newline bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access This field indicates the FIFO selected for debug access:" "0: Tx FIFO,1: Tx Status FIFO (only read access when SLVMOD is..,2: TSO FIFO (cannot be accessed when SLVMOD is set),3: Rx FIFO" newline bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable When this bit is set it enables the Write operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Write is disabled,1: FIFO Write is enabled" newline bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable When this bit is set it enables the Read operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Read is disabled,1: FIFO Read is enabled" newline bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO When this bit is set the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled" "0: Reset Pointers of Selected FIFO is disabled,1: Reset Pointers of Selected FIFO is enabled" newline bitfld.long 0x0 8. "RSTALL,Reset All Pointers When this bit is set the pointers of all FIFOs are reset when FIFO Debug Access is enabled" "0: Reset All Pointers is disabled,1: Reset All Pointers is enabled" newline bitfld.long 0x0 5.--6. "PKTSTATE,Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP" newline bitfld.long 0x0 2.--3. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Write operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO When this bit is set it indicates that the current access to the FIFO is read write and debug access" "0: Debug Mode Access to FIFO is disabled,1: Debug Mode Access to FIFO is enabled" newline bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable When this bit is set it indicates that the debug mode access to the FIFO is enabled" "0: FIFO Debug Access is disabled,1: FIFO Debug Access is enabled" line.long 0x4 "MTL_DBG_STS,The FIFO Debug Status register contains the status of FIFO debug access." hexmask.long.tbyte 0x4 15.--31. 1. "LOCR,Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO" newline bitfld.long 0x4 9. "STSI,Transmit Status Available Interrupt Status When set this bit indicates that the Slave mode Tx packet is transmitted and the status is available in Tx Status FIFO" "0: Transmit Status Available Interrupt Status not..,1: Transmit Status Available Interrupt Status.." newline bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status When set this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO" "0: Receive Packet Available Interrupt Status not..,1: Receive Packet Available Interrupt Status detected" newline rbitfld.long 0x4 3.--4. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Read operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline rbitfld.long 0x4 1.--2. "PKTSTATE,Encoded Packet State This field is used to get the control or status information of the selected FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP" newline rbitfld.long 0x4 0. "FIFOBUSY,FIFO Busy When set this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_Debug_Data register" "0: FIFO Busy not detected,1: FIFO Busy detected" line.long 0x8 "MTL_FIFO_Debug_Data,The FIFO Debug Data register contains the data to be written to or read from the FIFOs." hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data During debug or slave access write operation this field contains the data to be written to the Tx FIFO Rx FIFO or TSO FIFO" rgroup.long 0xC20++0x3 line.long 0x0 "MTL_Interrupt_Status,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC." bitfld.long 0x0 23. "MTLPIS,MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block" "0: MTL Rx Parser Interrupt status not detected,1: MTL Rx Parser Interrupt status detected" newline bitfld.long 0x0 18. "ESTIS,EST (TAS- 802" "0: EST (TAS- 802.1Qbv) Interrupt status not detected,1: EST (TAS- 802.1Qbv) Interrupt status detected" newline bitfld.long 0x0 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access" "0: Debug Interrupt status not detected,1: Debug Interrupt status detected" newline bitfld.long 0x0 4. "Q4IS,Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4" "0: Queue 4 Interrupt status not detected,1: Queue 4 Interrupt status detected" newline bitfld.long 0x0 3. "Q3IS,Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3" "0: Queue 3 Interrupt status not detected,1: Queue 3 Interrupt status detected" newline bitfld.long 0x0 2. "Q2IS,Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2" "0: Queue 2 Interrupt status not detected,1: Queue 2 Interrupt status detected" newline bitfld.long 0x0 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1" "0: Queue 1 Interrupt status not detected,1: Queue 1 Interrupt status detected" newline bitfld.long 0x0 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0" "0: Queue 0 Interrupt status not detected,1: Queue 0 Interrupt status detected" group.long 0xC30++0x7 line.long 0x0 "MTL_RxQ_DMA_Map0,The Receive Queue and DMA Channel Mapping 0 register is reserved in EQOS-CORE and EQOS-MTL configurations." bitfld.long 0x0 28. "Q3DDMACH,Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set this bit indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in.." "0: Queue 3 disabled for DA-based DMA Channel..,1: Queue 3 enabled for DA-based DMA Channel Selection" newline bitfld.long 0x0 24.--26. "Q3MDMACH,Queue 3 Mapped to DMA Channel This field controls the routing of the received packet in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?,?,?,?,?" newline bitfld.long 0x0 20. "Q2DDMACH,Queue 2 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 2 disabled for DA-based DMA Channel..,1: Queue 2 enabled for DA-based DMA Channel Selection" newline bitfld.long 0x0 16.--18. "Q2MDMACH,Queue 2 Mapped to DMA Channel This field controls the routing of the received packet in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?,?,?,?,?" newline bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 1 disabled for DA-based DMA Channel..,1: Queue 1 enabled for DA-based DMA Channel Selection" newline bitfld.long 0x0 8.--10. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?,?,?,?,?" newline bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 0 disabled for DA-based DMA Channel..,1: Queue 0 enabled for DA-based DMA Channel Selection" newline bitfld.long 0x0 0.--2. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?,?,?,?,?" line.long 0x4 "MTL_RxQ_DMA_Map1,The Receive Queue and DMA Channel Mapping 1 register is reserved in EQOS-CORE and EQOS-MTL configurations." bitfld.long 0x4 4. "Q4DDMACH,Queue 4 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 4 disabled for DA-based DMA Channel..,1: Queue 4 enabled for DA-based DMA Channel Selection" newline bitfld.long 0x4 0.--2. "Q4MDMACH,Queue 4 Mapped to DMA Channel This field controls the routing of the packet received in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?,?,?,?,?" group.long 0xC40++0x3 line.long 0x0 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling." hexmask.long.tbyte 0x0 8.--31. 1. "LEOS,Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time" newline bitfld.long 0x0 4.--6. "LEGOS,Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "LEOV,Launch Expiry Offset Valid When set indicates the LEOS field is valid" "0: LEOS field is invalid,1: LEOS field is valid" newline bitfld.long 0x0 0. "ESTM,EST offset Mode When this bit is set the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list" "0: EST offset Mode is disabled,1: EST offset Mode is enabled" group.long 0xC50++0x3 line.long 0x0 "MTL_EST_Control,This register controls the operation of Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.byte 0x0 24.--31. 1. "PTOV,PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds" newline hexmask.long.word 0x0 12.--23. 1. "CTOV,Current Time Offset Value Provides a 12 bit time offset value in nano second that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay buffering delays data path delays etc" newline bitfld.long 0x0 8.--10. "TILS,Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "LCSE,Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_Status register" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations" newline bitfld.long 0x0 5. "DFBS,Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_Status register) after 4 8 16 32 (based on LCSE field of this register) GCL iterations are dropped" "0: Do not Drop Frames causing Scheduling Error,1: Drop Frames causing Scheduling Error" newline bitfld.long 0x0 4. "DDBF,Do not Drop frames during Frame Size Error When set frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of EST_Status register)" "0: Drop frames during Frame Size Error,1: Do not Drop frames during Frame Size Error" newline bitfld.long 0x0 1. "SSWL,Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR" "0: Switch to S/W owned list is disabled,1: Switch to S/W owned list is enabled" newline bitfld.long 0x0 0. "EEST,Enable EST When reset the gate control list processing is halted and all gates are assumed to be in Open state" "0: EST is disabled,1: EST is enabled" group.long 0xC58++0x3 line.long 0x0 "MTL_EST_Status,This register provides Status related to Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.byte 0x0 16.--19. 1. "CGSN,Current GCL Slot Number Indicates the slot number of the GCL list" newline hexmask.long.byte 0x0 8.--11. 1. "BTRL,BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true" newline rbitfld.long 0x0 7. "SWOL,S/W owned list When '0' indicates Gate control list number '0' is owned by software and when '1' indicates the Gate Control list '1' is owned by the software" "0: Gate control list number '0' is owned by software,1: Gate control list number '1' is owned by software" newline bitfld.long 0x0 4. "CGCE,Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting" "0: Constant Gate Control Error not detected,1: Constant Gate Control Error detected" newline rbitfld.long 0x0 3. "HLBS,Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL" "0: Head-Of-Line Blocking due to Scheduling not..,1: Head-Of-Line Blocking due to Scheduling detected" newline rbitfld.long 0x0 2. "HLBF,Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment.." "0: Head-Of-Line Blocking due to Frame Size not..,1: Head-Of-Line Blocking due to Frame Size detected" newline bitfld.long 0x0 1. "BTRE,BTR Error When '1' indicates a programming error in the BTR of SWOL where the programmed value is less than current time" "0: BTR Error not detected,1: BTR Error detected" newline bitfld.long 0x0 0. "SWLC,Switch to S/W owned list Complete When '1' indicates the hardware has successfully switched to the SWOL and the SWOL bit has been updated to that effect" "0: Switch to S/W owned list Complete not detected,1: Switch to S/W owned list Complete detected" group.long 0xC60++0x7 line.long 0x0 "MTL_EST_Sch_Error,This register provides the One Hot encoded Queue Numbers that are having the Scheduling related error (timeout)." hexmask.long.byte 0x0 0.--4. 1. "SEQN,Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register" line.long 0x4 "MTL_EST_Frm_Size_Error,This register provides the One Hot encoded Queue Numbers that are having the Frame Size related error." hexmask.long.byte 0x4 0.--4. 1. "FEQN,Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register" rgroup.long 0xC68++0x3 line.long 0x0 "MTL_EST_Frm_Size_Capture,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error. Up on clearing it captures the data of immediate next occurrence of a similar error." bitfld.long 0x0 16.--18. "HBFQ,Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register)" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register" group.long 0xC70++0x3 line.long 0x0 "MTL_EST_Intr_Enable,This register implements the Interrupt Enable bits for the various events that generate an interrupt. Bit positions have a 1 to 1 correlation with the status bit positions in MTL_ETS_Status register." bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE When set generates interrupt when the Constant Gate Control Error occurs and is indicated in the status" "0: Interrupt for CGCE is disabled,1: Interrupt for CGCE is enabled" newline bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS When set generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status" "0: Interrupt for HLBS is disabled,1: Interrupt for HLBS is enabled" newline bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF When set generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status" "0: Interrupt for HLBF is disabled,1: Interrupt for HLBF is enabled" newline bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error When set generates interrupt when the BTR Error occurs and is indicated in the status" "0: Interrupt for BTR Error is disabled,1: Interrupt for BTR Error is enabled" newline bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List When set generates interrupt when the configuration change is successful and the hardware has switched to the new list" "0: Interrupt for Switch List is disabled,1: Interrupt for Switch List is enabled" group.long 0xC80++0x7 line.long 0x0 "MTL_EST_GCL_Control,This register provides the control information for reading/writing to the Gate Control lists." bitfld.long 0x0 22.--23. "ESTEIEC,ECC Inject Error Control for EST Memory When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field" newline bitfld.long 0x0 21. "ESTEIEE,EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC error injection feature" "0: EST ECC Inject Error is disabled,1: EST ECC Inject Error is enabled" newline bitfld.long 0x0 20. "ERR0,When set indicates the last write operation was aborted as software writes to GCL and GCL registers is prohibited when SSWL bit of MTL_EST_Control Register is set" "0: ERR0 is disabled,1: ERR1 is enabled" newline hexmask.long.byte 0x0 8.--15. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is '0')" newline bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select When set to '0' indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers)" "0: R/W in debug mode should be directed to Bank 0,1: R/W in debug mode should be directed to Bank 1" newline bitfld.long 0x0 4. "DBGM,Debug Mode When set to '1' indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value when set to '0' SWOL bit is used to determine which bank to use" "0: Debug Mode is disabled,1: Debug Mode is enabled" newline bitfld.long 0x0 2. "GCRR,Gate Control Related Registers When set to '1' indicates the R/W access is for the GCL related registers (BTR CTR TER LLR) whose address is provided by GCRA" "0: Gate Control Related Registers are disabled,1: Gate Control Related Registers are enabled" newline bitfld.long 0x0 1. "R1W0,Read '1' Write '0': When set to '1': Read Operation When set to '0': Write Operation." "0: Write Operation,1: Read Operation When set to" newline bitfld.long 0x0 0. "SRWO,Start Read/Write Op When set indicates a Read/Write Op has started and is in progress" "0: Start Read/Write Op disabled,1: Start Read/Write Op enabled" line.long 0x4 "MTL_EST_GCL_Data,This register holds the read data or write data in case of reads and writes respectively." hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data The data corresponding to the address selected in the GCL_Control register" group.long 0xC90++0x7 line.long 0x0 "MTL_FPE_CTRL_STS,This register controls the operation of. and provides status for Frame Preemption (IEEE802.1Qbu/802.3br)." rbitfld.long 0x0 28. "HRS,Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.." newline hexmask.long.byte 0x0 8.--12. 1. "PEC,Preemption Classification When set indicates the corresponding Queue must be classified as preemptable when '0' Queue is classified as express" newline bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size used to indicate in units of 64 bytes the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames" "0,1,2,3" line.long 0x4 "MTL_FPE_Advance,This register holds the Hold and Release Advance time." hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames in the absence of there being any express frames available for transmission" newline hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission" group.long 0xCA0++0x7 line.long 0x0 "MTL_RXP_Control_Status,The MTL_RXP_Control_Status register establishes the operating mode of Rx Parser and provides some status." rbitfld.long 0x0 31. "RXPI,RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing" "0: RX Parser not in Idle state,1: RX Parser in Idle state" newline hexmask.long.byte 0x0 16.--23. 1. "NPE,Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory" newline bitfld.long 0x0 15. "MTL_SCS1,NXP Reserved All the bits must be set to '0'" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "NVE,Number of valid entry address/index in the Instruction table This control indicates the number of valid entries address/index in the Instruction Memory (i" line.long 0x4 "MTL_RXP_Interrupt_Control_Status,The MTL_RXP_Interrupt_Control_Status registers provides enable control for the interrupts and provides interrupt status." bitfld.long 0x4 19. "PDRFIE,Packet Drop due to RF Interrupt Enable When this bit is set the PDRFIS interrupt is enabled" "0: Packet Drop due to RF Interrupt is disabled,1: Packet Drop due to RF Interrupt is enabled" newline bitfld.long 0x4 18. "FOOVIE,Frame Offset Overflow Interrupt Enable When this bit is set the FOOVIS interrupt is enabled" "0: Frame Offset Overflow Interrupt is disabled,1: Frame Offset Overflow Interrupt is enabled" newline bitfld.long 0x4 17. "NPEOVIE,Number of Parsable Entries Overflow Interrupt Enable When this bit is set the NPEOVIS interrupt is enabled" "0: Number of Parsable Entries Overflow Interrupt is..,1: Number of Parsable Entries Overflow Interrupt is.." newline bitfld.long 0x4 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable When this bit is set the NVEOVIS interrupt is enabled" "0: Number of Valid Entries Overflow Interrupt is..,1: Number of Valid Entries Overflow Interrupt is.." newline bitfld.long 0x4 3. "PDRFIS,Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory then this bit is set to 1" "0: Packet Dropped due to RF Interrupt Status not..,1: Packet Dropped due to RF Interrupt Status detected" newline bitfld.long 0x4 2. "FOOVIS,Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset then then this bit is set" "0: Frame Offset Overflow Interrupt Status not..,1: Frame Offset Overflow Interrupt Status detected" newline bitfld.long 0x4 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.." newline bitfld.long 0x4 0. "NVEOVIS,Number of Valid Entry Address/Index Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entry Address/index in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Valid Entries Overflow Interrupt..,1: Number of Valid Entries Overflow Interrupt.." rgroup.long 0xCA8++0x7 line.long 0x0 "MTL_RXP_Drop_Cnt,The MTL_RXP_Drop_Cnt register provides the drop count of Rx Parser initiated drops." bitfld.long 0x0 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit When set this bit indicates that the MTL_RXP_Drop_cnt (RXPDC) Counter field crossed the maximum limit" "0: Rx Parser Drop count overflow not occurred,1: Rx Parser Drop count overflow occurred" newline hexmask.long 0x0 0.--30. 1. "RXPDC,Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1" line.long 0x4 "MTL_RXP_Error_Cnt,The MTL_RXP_Error_Cnt register provides the Rx Parser related error occurrence count." bitfld.long 0x4 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit When set this bit indicates that the MTL_RXP_Error_cnt (RXPEC) Counter field crossed the maximum limit" "0: Rx Parser Error count overflow not occurred,1: Rx Parser Error count overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPEC,Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the.." group.long 0xCB0++0x3 line.long 0x0 "MTL_RXP_Indirect_Acc_Control_Status,The MTL_RXP_Indirect_Acc_Control_Status register provides the Indirect Access control and status for Rx Parser memory." bitfld.long 0x0 31. "STARTBUSY,FRP Instruction Table Access Busy When this bit is set to 1 by the software then it indicates to start the Read/Write operation from/to the Rx Parser Memory" "0: hardware not busy,1: hardware is busy (Read/Write operation from/to.." newline bitfld.long 0x0 21.--22. "RXPEIEC,ECC Inject Error Control for Rx Parser Memory When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field" newline bitfld.long 0x0 20. "RXPEIEE,ECC Inject Error Enable for Rx Parser Memory When set enables the ECC error injection feature" "0: ECC Inject Error for Rx Parser Memory is disabled,1: ECC Inject Error for Rx Parser Memory is enabled" newline bitfld.long 0x0 16. "WRRDN,Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory" "0: Read operation to the Rx Parser Memory,1: Write operation to the Rx Parser Memory" newline hexmask.long.word 0x0 0.--9. 1. "ADDR,FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table" rgroup.long 0xCB4++0x3 line.long 0x0 "MTL_RXP_Indirect_Acc_Data,The MTL_RXP_Indirect_Acc_Data registers holds the data associated to Indirect Access to Rx Parser memory." hexmask.long 0x0 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data Software should write this register before issuing any write command" group.long 0xCC0++0x3 line.long 0x0 "MTL_ECC_Control,The MTL_ECC_Control register establishes the operating mode of ECC related to MTL memories." bitfld.long 0x0 8. "MEEAO,MTL ECC Error Address Status Over-ride When set the following error address fields hold the last valid address where the error is detected" "0: MTL ECC Error Address Status Over-ride is disabled,1: MTL ECC Error Address Status Over-ride is enabled" newline bitfld.long 0x0 3. "MRXPEE,MTL Rx Parser ECC Enable When set to 1 enables the ECC feature for Rx Parser memory" "0: MTL Rx Parser ECC is disabled,1: MTL Rx Parser ECC is enabled" newline bitfld.long 0x0 2. "MESTEE,MTL EST ECC Enable When set to 1 enables the ECC feature for EST memory" "0: MTL EST ECC is disabled,1: MTL EST ECC is enabled" newline bitfld.long 0x0 1. "MRXEE,MTL Rx FIFO ECC Enable When set to 1 enables the ECC feature for MTL Rx FIFO memory" "0: MTL Rx FIFO ECC is disabled,1: MTL Rx FIFO ECC is enabled" newline bitfld.long 0x0 0. "MTXEE,MTL Tx FIFO ECC Enable When set to 1 enables the ECC feature for MTL Tx FIFO memory" "0: MTL Tx FIFO ECC is disabled,1: MTL Tx FIFO ECC is enabled" rgroup.long 0xCC4++0x3 line.long 0x0 "MTL_Safety_Interrupt_Status,The MTL_Safety_Interrupt_Status registers provides Safety interrupt status." bitfld.long 0x0 1. "MEUIS,MTL ECC Uncorrectable error Interrupt Status This bit indicates that an uncorrectable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Uncorrectable error Interrupt Status not..,1: MTL ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "MECIS,MTL ECC Correctable error Interrupt Status This bit indicates that a correctable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Correctable error Interrupt Status not..,1: MTL ECC Correctable error Interrupt Status.." group.long 0xCC8++0xB line.long 0x0 "MTL_ECC_Interrupt_Enable,The MTL_ECC_Interrupt_Enable register provides enable bits for the ECC interrupts." bitfld.long 0x0 12. "RPCEIE,Rx Parser memory Correctable Error Interrupt Enable When set generates an interrupt when an uncorrectable error is detected at the Rx Parser memory interface" "0: Rx Parser memory Correctable Error Interrupt is..,1: Rx Parser memory Correctable Error Interrupt is.." newline bitfld.long 0x0 8. "ECEIE,EST memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL EST memory interface" "0: EST memory Correctable Error Interrupt is disabled,1: EST memory Correctable Error Interrupt is enabled" newline bitfld.long 0x0 4. "RXCEIE,Rx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Rx memory interface" "0: Rx memory Correctable Error Interrupt is disabled,1: Rx memory Correctable Error Interrupt is enabled" newline bitfld.long 0x0 0. "TXCEIE,Tx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Tx memory interface" "0: Tx memory Correctable Error Interrupt is disabled,1: Tx memory Correctable Error Interrupt is enabled" line.long 0x4 "MTL_ECC_Interrupt_Status,The MTL_ECC_Interrupt_Status register provides MTL ECC Interrupt Status." bitfld.long 0x4 14. "RPUES,Rx Parser memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at Rx Parser memory interface" "0: Rx Parser memory Uncorrectable Error Status not..,1: Rx Parser memory Uncorrectable Error Status.." newline bitfld.long 0x4 13. "RPAMS,MTL Rx Parser memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of Rx Parser memory" "0: MTL Rx Parser memory Address Mismatch Status not..,1: MTL Rx Parser memory Address Mismatch Status.." newline bitfld.long 0x4 12. "RPCES,MTL Rx Parser memory Correctable Error Status This bit when set indicates that correctable error is detected at RX Parser memory interface" "0: MTL Rx Parser memory Correctable Error Status..,1: MTL Rx Parser memory Correctable Error Status.." newline bitfld.long 0x4 10. "EUES,MTL EST memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at MTL EST memory interface" "0: MTL EST memory Uncorrectable Error Status not..,1: MTL EST memory Uncorrectable Error Status detected" newline bitfld.long 0x4 9. "EAMS,MTL EST memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of MTL EST memory" "0: MTL EST memory Address Mismatch Status not..,1: MTL EST memory Address Mismatch Status detected" newline bitfld.long 0x4 8. "ECES,MTL EST memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL EST memory" "0: MTL EST memory Correctable Error Status not..,1: MTL EST memory Correctable Error Status detected" newline bitfld.long 0x4 6. "RXUES,MTL Rx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL Rx memory interface" "0: MTL Rx memory Uncorrectable Error Status not..,1: MTL Rx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 5. "RXAMS,MTL Rx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Rx memory" "0: MTL Rx memory Address Mismatch Status not detected,1: MTL Rx memory Address Mismatch Status detected" newline bitfld.long 0x4 4. "RXCES,MTL Rx memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL Rx memory" "0: MTL Rx memory correctable Error Status not..,1: MTL Rx memory correctable Error Status detected" newline bitfld.long 0x4 2. "TXUES,MTL Tx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL TX memory interface" "0: MTL Tx memory Uncorrectable Error Status not..,1: MTL Tx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 1. "TXAMS,MTL Tx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Tx memory" "0: MTL Tx memory Address Mismatch Status not detected,1: MTL Tx memory Address Mismatch Status detected" newline bitfld.long 0x4 0. "TXCES,MTL Tx memory Correctable Error Status This bit when set indicates that a correctable error is detected at the MTL Tx memory" "0: MTL Tx memory Correctable Error Status not..,1: MTL Tx memory Correctable Error Status detected" line.long 0x8 "MTL_ECC_Err_Sts_Rctl,The MTL_ECC_Err_Sts_Rctl register establishes the control for ECC Error status capture." bitfld.long 0x8 5. "CUES,Clear Uncorrectable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's uncorrectable error address and uncorrectable error count values are cleared upon reading" "0: Clear Uncorrectable Error Status not detected,1: Clear Uncorrectable Error Status detected" newline bitfld.long 0x8 4. "CCES,Clear Correctable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's correctable error address and correctable error count values are cleared upon reading" "0: Clear Correctable Error Status not detected,1: Clear Correctable Error Status detected" newline bitfld.long 0x8 1.--3. "EMS,MTL ECC Memory Selection When EESRE bit of this register is set this field indicates which memory's error status value to be read" "0: MTL Tx memory,1: MTL Rx memory,2: MTL EST memory,3: MTL Rx Parser memory,4: DMA TSO memory,?,?,?" newline bitfld.long 0x8 0. "EESRE,MTL ECC Error Status Read Enable When this bit is set based on the EMS field of this register the respective memory's error status values are captured as described: - The correctable and uncorrectable error count values are captured into.." "0: MTL ECC Error Status Read is disabled,1: MTL ECC Error Status Read is enabled" rgroup.long 0xCD4++0x7 line.long 0x0 "MTL_ECC_Err_Addr_Status,The MTL_ECC_Err_Addr_Status register provides the memory addresses for the correctable and uncorrectable errors." hexmask.long.word 0x0 16.--31. 1. "EUEAS,MTL ECC Uncorrectable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which an uncorrectable error or address mismatch is detected" newline hexmask.long.word 0x0 0.--15. 1. "ECEAS,MTL ECC Correctable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which a correctable error is detected" line.long 0x4 "MTL_ECC_Err_Cntr_Status,The MTL_ECC_Err_Cntr_Status register provides ECC Error count for Correctable and uncorrectable errors." hexmask.long.byte 0x4 16.--19. 1. "EUECS,MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's uncorrectable error count value" newline hexmask.long.byte 0x4 0.--7. 1. "ECECS,MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's correctable error count value" group.long 0xCE0++0x3 line.long 0x0 "MTL_DPP_Control,The MTL_DPP_Control establishes the operating mode of Data Parity protection and error injection." bitfld.long 0x0 11. "IPERD,Insert Parity error in Rx write-back Descriptor parity generator When set to 1 parity bit of first valid data generated by the DMA Rx write-back descriptor parity generator(or at PG8 as shown in Receive data path parity protection diagram) is.." "0: Insert Parity error in Rx write-back Descriptor..,1: Insert Parity error in Rx write-back Descriptor.." newline bitfld.long 0x0 10. "IPETD,Insert Parity error in Tx write-back Descriptor parity generator When set to 1 parity bit of first valid data generated by the DMA Tx write-back descriptor parity generator(or at PG4 as shown in Transmit data path parity protection diagram) is.." "0: Insert Parity error in Tx write-back Descriptor..,1: Insert Parity error in Tx write-back Descriptor.." newline bitfld.long 0x0 8. "IPEDDC,Insert Parity Error in DMA DTX Control word parity generator When set to 1 parity bit of first valid data generated by the DMA DTX Control word parity generator (or at PG2 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in DMA DTX Control word..,1: Insert Parity Error in DMA DTX Control word.." newline bitfld.long 0x0 7. "IPEMRF,Insert Parity Error in MTL Rx FIFO read control parity generator When set to 1 parity bit of first valid data generated by the MTL Rx FIFO read control parity generator (or at PG7 as shown in Receive data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL Rx FIFO read control..,1: Insert Parity Error in MTL Rx FIFO read control.." newline bitfld.long 0x0 6. "IPEMTS,Insert Parity Error in MTL Tx Status parity generator When set to 1 parity bit of first valid data generated by the MTL Tx Status parity generator (or at PG6 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL Tx Status parity..,1: Insert Parity Error in MTL Tx Status parity.." newline bitfld.long 0x0 5. "IPEMC,Insert Parity Error in MTL checksum parity generator When set to 1 parity bit of first valid data generated by the MTL checksum parity generator (or at PG5 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL checksum parity..,1: Insert Parity Error in MTL checksum parity.." newline bitfld.long 0x0 4. "IPEID,Insert Parity Error in Interface Data parity generator When set to 1 parity bit of first valid input data generated by the Interface data parity generator (or at PG1 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in Interface Data parity..,1: Insert Parity Error in Interface Data parity.." newline rbitfld.long 0x0 1. "OPE,Odd Parity Enable When set to 1 enables odd parity protection on all the external interfaces and when set to 0 enables even parity protection on all the external interfaces" "0: Odd Parity is disabled,1: Odd Parity is enabled" newline bitfld.long 0x0 0. "EDPP,Enable Data path Parity Protection When set to 1 enables the parity protection for EQOS datapath by generating and checking the parity on EQOS datapath" "0: Data path Parity Protection is disabled,1: Data path Parity Protection is enabled" group.long 0xD00++0x3 line.long 0x0 "MTL_TxQ0_Operation_Mode,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xD04++0x7 line.long 0x0 "MTL_TxQ0_Underflow,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ0_Debug,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" rgroup.long 0xD14++0x3 line.long 0x0 "MTL_TxQ0_ETS_Status,The Queue 0 ETS Status register provides the average traffic transmitted in Queue 0." hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xD18++0x3 line.long 0x0 "MTL_TxQ0_Quantum_Weight,The Queue 0 Quantum or Weights register contains the quantum value for Deficit Weighted Round Robin (DWRR). weights for the Weighted Round Robin (WRR). and Weighted Fair Queuing (WFQ) for Queue 0." hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic this field contains the quantum value in bytes to be added to credit during every queue scanning cycle" group.long 0xD2C++0x7 line.long 0x0 "MTL_Q0_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 0 interrupts." bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ0_Operation_Mode,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 20.--26. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline hexmask.long.byte 0x4 14.--19. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline hexmask.long.byte 0x4 8.--13. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD34++0x7 line.long 0x0 "MTL_RxQ0_Missed_Packet_Overflow_Cnt,The Queue 0 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ0_Debug,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue." hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xD3C++0x7 line.long 0x0 "MTL_RxQ0_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TxQ1_Operation_Mode,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.byte 0x4 16.--22. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xD44++0x7 line.long 0x0 "MTL_TxQ1_Underflow,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ1_Debug,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" group.long 0xD50++0x3 line.long 0x0 "MTL_TxQ1_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation." bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: 1 slot,1: 2 slots,2: 4 slots,3: 8 slots,4: 16 slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled" rgroup.long 0xD54++0x3 line.long 0x0 "MTL_TxQ1_ETS_Status,The Queue 1 ETS Status register provides the average traffic transmitted in Queue 1." hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xD58++0xF line.long 0x0 "MTL_TxQ1_Quantum_Weight,The Queue 1 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 1." hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1" line.long 0x4 "MTL_TxQ1_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1" line.long 0x8 "MTL_TxQ1_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm" line.long 0xC "MTL_TxQ1_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm" group.long 0xD6C++0x7 line.long 0x0 "MTL_Q1_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 1 interrupts." bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ1_Operation_Mode,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 20.--26. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline hexmask.long.byte 0x4 14.--19. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline hexmask.long.byte 0x4 8.--13. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD74++0x7 line.long 0x0 "MTL_RxQ1_Missed_Packet_Overflow_Cnt,The Queue 1 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ1_Debug,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue." hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xD7C++0x7 line.long 0x0 "MTL_RxQ1_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TxQ2_Operation_Mode,The Queue 2 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.byte 0x4 16.--22. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xD84++0x7 line.long 0x0 "MTL_TxQ2_Underflow,The Queue 2 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ2_Debug,The Queue 2 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" group.long 0xD90++0x3 line.long 0x0 "MTL_TxQ2_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation." bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: 1 slot,1: 2 slots,2: 4 slots,3: 8 slots,4: 16 slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled" rgroup.long 0xD94++0x3 line.long 0x0 "MTL_TxQ2_ETS_Status,The Queue 2 ETS Status register provides the average traffic transmitted in Queue 2." hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xD98++0xF line.long 0x0 "MTL_TxQ2_Quantum_Weight,The Queue 2 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 2." hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1" line.long 0x4 "MTL_TxQ2_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1" line.long 0x8 "MTL_TxQ2_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm" line.long 0xC "MTL_TxQ2_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm" group.long 0xDAC++0x7 line.long 0x0 "MTL_Q2_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 2 interrupts." bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ2_Operation_Mode,The Queue 2 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 20.--26. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline hexmask.long.byte 0x4 14.--19. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline hexmask.long.byte 0x4 8.--13. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xDB4++0x7 line.long 0x0 "MTL_RxQ2_Missed_Packet_Overflow_Cnt,The Queue 2 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ2_Debug,The Queue 2 Receive Debug register gives the debug status of various blocks related to the Receive queue." hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xDBC++0x7 line.long 0x0 "MTL_RxQ2_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TxQ3_Operation_Mode,The Queue 3 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.byte 0x4 16.--22. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xDC4++0x7 line.long 0x0 "MTL_TxQ3_Underflow,The Queue 3 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ3_Debug,The Queue 3 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" group.long 0xDD0++0x3 line.long 0x0 "MTL_TxQ3_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation." bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: 1 slot,1: 2 slots,2: 4 slots,3: 8 slots,4: 16 slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled" rgroup.long 0xDD4++0x3 line.long 0x0 "MTL_TxQ3_ETS_Status,The Queue 3 ETS Status register provides the average traffic transmitted in Queue 3." hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xDD8++0xF line.long 0x0 "MTL_TxQ3_Quantum_Weight,The Queue 3 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 3." hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1" line.long 0x4 "MTL_TxQ3_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1" line.long 0x8 "MTL_TxQ3_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm" line.long 0xC "MTL_TxQ3_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm" group.long 0xDEC++0x7 line.long 0x0 "MTL_Q3_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 3 interrupts." bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ3_Operation_Mode,The Queue 3 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 20.--26. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline hexmask.long.byte 0x4 14.--19. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline hexmask.long.byte 0x4 8.--13. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xDF4++0x7 line.long 0x0 "MTL_RxQ3_Missed_Packet_Overflow_Cnt,The Queue 3 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ3_Debug,The Queue 3 Receive Debug register gives the debug status of various blocks related to the Receive queue." hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xDFC++0x7 line.long 0x0 "MTL_RxQ3_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TxQ4_Operation_Mode,The Queue 4 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.byte 0x4 16.--22. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xE04++0x7 line.long 0x0 "MTL_TxQ4_Underflow,The Queue 4 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ4_Debug,The Queue 4 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" group.long 0xE10++0x3 line.long 0x0 "MTL_TxQ4_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation." bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: 1 slot,1: 2 slots,2: 4 slots,3: 8 slots,4: 16 slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled" rgroup.long 0xE14++0x3 line.long 0x0 "MTL_TxQ4_ETS_Status,The Queue 4 ETS Status register provides the average traffic transmitted in Queue 4." hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xE18++0xF line.long 0x0 "MTL_TxQ4_Quantum_Weight,The Queue 4 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 4." hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1" line.long 0x4 "MTL_TxQ4_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1" line.long 0x8 "MTL_TxQ4_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm" line.long 0xC "MTL_TxQ4_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm" group.long 0xE2C++0x7 line.long 0x0 "MTL_Q4_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 4 interrupts." bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ4_Operation_Mode,The Queue 4 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 20.--26. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline hexmask.long.byte 0x4 14.--19. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline hexmask.long.byte 0x4 8.--13. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xE34++0x7 line.long 0x0 "MTL_RxQ4_Missed_Packet_Overflow_Cnt,The Queue 4 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ4_Debug,The Queue 4 Receive Debug register gives the debug status of various blocks related to the Receive queue." hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xE3C++0x3 line.long 0x0 "MTL_RxQ4_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7 line.long 0x0 "DMA_Mode,The Bus Mode register establishes the bus operating modes for the DMA." bitfld.long 0x0 16.--17. "INTM,Interrupt Mode This field defines the interrupt mode of DWC_ether_qos" "0: See above description,1: See above description,2: See above description,?" newline bitfld.long 0x0 8. "DSPW,Descriptor Posted Write When this bit is set to 0 the descriptor writes are always non-posted" "0: Descriptor Posted Write is disabled,1: Descriptor Posted Write is enabled" newline bitfld.long 0x0 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC" "0: Software Reset is disabled,1: Software Reset is enabled" line.long 0x4 "DMA_SysBus_Mode,The System Bus mode register controls the behavior of the AHB or AXI master. It mainly controls burst splitting and number of outstanding requests." bitfld.long 0x4 31. "EN_LPI,Enable Low Power Interface (LPI) When set to 1 this bit enables the LPI mode supported by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock controller" "0: Low Power Interface (LPI) is disabled,1: Low Power Interface (LPI) is enabled" newline bitfld.long 0x4 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet When set to 1 this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received" "0: Unlock on Magic Packet or Remote Wake-Up Packet..,1: Unlock on Magic Packet or Remote Wake-Up Packet.." newline hexmask.long.byte 0x4 24.--27. 1. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface" newline hexmask.long.byte 0x4 16.--19. 1. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface" newline bitfld.long 0x4 13. "ONEKBBE,1 KB Boundary Crossing Enable for the EQOS-AXI Master When set the burst transfers performed by the EQOS-AXI master do not cross 1 KB boundary" "0: 1 KB Boundary Crossing for the EQOS-AXI Master..,1: 1 KB Boundary Crossing for the EQOS-AXI Master.." newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels" "0: Address-Aligned Beats is disabled,1: Address-Aligned Beats is enabled" newline bitfld.long 0x4 10. "AALE,Automatic AXI LPI enable When set to 1 enables the AXI master to enter into LPI state when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in the LPIEI field of AXI_LPI_Entry_Interval register" "0: Automatic AXI LPI is disabled,1: Automatic AXI LPI is enabled" newline bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256 When this bit is set to 1 the EQOS-AXI master can select a burst length of 256 on the AXI interface" "0: No effect,1: AXI Burst Length 256" newline bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128 When this bit is set to 1 the EQOS-AXI master can select a burst length of 128 on the AXI interface" "0: No effect,1: AXI Burst Length 128" newline bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64 When this bit is set to 1 the EQOS-AXI master can select a burst length of 64 on the AXI interface" "0: No effect,1: AXI Burst Length 64" newline bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32 When this bit is set to 1 the EQOS-AXI master can select a burst length of 32 on the AXI interface" "0: No effect,1: AXI Burst Length 32" newline bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 16 on the AXI interface" "0: No effect,1: AXI Burst Length 16" newline bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 8 on the AXI interface" "0: No effect,1: AXI Burst Length 8" newline bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 4 on the AXI interface" "0: No effect,1: AXI Burst Length 4" newline bitfld.long 0x4 0. "FB,Fixed Burst Length When this bit is set to 1 the EQOS-AXI master initiates burst transfers of specified lengths as given below" "0: Fixed Burst Length is disabled,1: Fixed Burst Length is enabled" rgroup.long 0x1008++0xB line.long 0x0 "DMA_Interrupt_Status,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels. MTL queues. and the MAC." bitfld.long 0x0 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC" "0: MAC Interrupt Status not detected,1: MAC Interrupt Status detected" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL" "0: MTL Interrupt Status not detected,1: MTL Interrupt Status detected" newline bitfld.long 0x0 4. "DC4IS,DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4" "0: DMA Channel 4 Interrupt Status not detected,1: DMA Channel 4 Interrupt Status detected" newline bitfld.long 0x0 3. "DC3IS,DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3" "0: DMA Channel 3 Interrupt Status not detected,1: DMA Channel 3 Interrupt Status detected" newline bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2" "0: DMA Channel 2 Interrupt Status not detected,1: DMA Channel 2 Interrupt Status detected" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1" "0: DMA Channel 1 Interrupt Status not detected,1: DMA Channel 1 Interrupt Status detected" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0" "0: DMA Channel 0 Interrupt Status not detected,1: DMA Channel 0 Interrupt Status detected" line.long 0x4 "DMA_Debug_Status0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose." hexmask.long.byte 0x4 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2" newline hexmask.long.byte 0x4 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2" newline hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1" newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1" newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0" newline bitfld.long 0x4 1. "AXRHSTS,AXI Master Read Channel Status When high this bit indicates that the read channel of the AXI master is active and it is transferring the data" "0: AXI Master Read Channel Status not detected,1: AXI Master Read Channel Status detected" newline bitfld.long 0x4 0. "AXWHSTS,AXI Master Write Channel When high this bit indicates that the write channel of the AXI master is active and it is transferring data" "0: AXI Master Write Channel or AHB Master Status..,1: AXI Master Write Channel or AHB Master Status.." line.long 0x8 "DMA_Debug_Status1,The Debug Status1 register gives the Receive and Transmit process status for DMA Channel 3-Channel 6." hexmask.long.byte 0x8 12.--15. 1. "TPS4,DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4" newline hexmask.long.byte 0x8 8.--11. 1. "RPS4,DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4" newline hexmask.long.byte 0x8 4.--7. 1. "TPS3,DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3" newline hexmask.long.byte 0x8 0.--3. 1. "RPS3,DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3" group.long 0x1020++0xB line.long 0x0 "AXI4_Tx_AR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for read transactions by all the Transmit DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding.." bitfld.long 0x0 20.--21. "THD,Transmit DMA First Packet Buffer This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor)" "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor)" newline bitfld.long 0x0 12.--13. "TED,Transmit DMA Extended Packet Buffer This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers)" "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers)" newline bitfld.long 0x0 4.--5. "TDRD,Transmit DMA Read Descriptor Domain Control This field is used to drive ardomain_o[1:0] signal when Transmit DMA engines access the Descriptor" "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control This field is used to drive arcache_o[3:0] signal when Transmit DMA engines access the Descriptor" line.long 0x4 "AXI4_Rx_AW_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for write transactions by all the Receive DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding.." bitfld.long 0x4 28.--29. "RDD,Receive DMA Buffer Domain Control This field is used to drive the awdomain_o[1:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated" "0,1,2,3" newline hexmask.long.byte 0x4 24.--27. 1. "RDC,Receive DMA Buffer Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated" newline bitfld.long 0x4 20.--21. "RHD,Receive DMA Header Domain Control This field is used to drive awdomain_o[1:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated" "0,1,2,3" newline hexmask.long.byte 0x4 16.--19. 1. "RHC,Receive DMA Header Cache Control This field is used to drive awcache_o[3:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated" newline bitfld.long 0x4 12.--13. "RPD,Receive DMA Payload Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated" "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RPC,Receive DMA Payload Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated" newline bitfld.long 0x4 4.--5. "RDWD,Receive DMA Write Descriptor Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA accesses the Descriptor" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA accesses the Descriptor" line.long 0x8 "AXI4_TxRx_AWAR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels. It also controls the values to be driven.." bitfld.long 0x8 20.--22. "WRP,DMA Write Protection control This field is used to drive awprot_m_o[2:0] signal on the AXI Write Channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16.--18. "RDP,DMA Read Protection control This field is used to drive arprot_m_o[2:0] signal during all read requests" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--13. "RDRD,Receive DMA Read Descriptor Domain control This field is used to drive ardomain_o[1:0] signal when Receive DMA engines read the Descriptor" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control This field is used to drive arcache_o[3:0] signal when Receive DMA engines read the Descriptor" newline bitfld.long 0x8 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control This field is used to drive awdomain_o[1:0] signal when Transmit DMA write to the Descriptor" "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control This field is used to drive awcache_o[3:0] signal when Transmit DMA writes to the Descriptor" group.long 0x1040++0x3 line.long 0x0 "AXI_LPI_Entry_Interval,This register is used to control the AXI LPI entry interval." hexmask.long.byte 0x0 0.--3. 1. "LPIEI,LPI Entry Interval Contains the number of system clock cycles multiplied by 64 to wait for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 clock cycles" group.long 0x1050++0x3 line.long 0x0 "DMA_TBS_CTRL,This register is used to control the TBS attributes." hexmask.long.tbyte 0x0 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time" newline bitfld.long 0x0 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid" rgroup.long 0x1080++0x3 line.long 0x0 "DMA_Safety_Interrupt_Status,This register indicates summary (whether error occured in DMA/MTL/MAC and correctable/uncorrectable) of the Automotive Safety related error interrupts." bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status Indicates a uncorrectable Safety related Interrupt is set in the MAC module" "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status detected" newline bitfld.long 0x0 29. "MSUIS,MTL Safety Uncorrectable error Interrupt Status This bit indicates an uncorrectable error interrupt event in MTL" "0: MTL Safety Uncorrectable error Interrupt Status..,1: MTL Safety Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 28. "MSCIS,MTL Safety Correctable error Interrupt Status This bit indicates a correctable error interrupt event in MTL" "0: MTL Safety Correctable error Interrupt Status..,1: MTL Safety Correctable error Interrupt Status.." newline bitfld.long 0x0 1. "DEUIS,DMA ECC Uncorrectable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Uncorrectable error Interrupt Status not..,1: DMA ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "DECIS,DMA ECC Correctable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Correctable error Interrupt Status not..,1: DMA ECC Correctable error Interrupt Status.." group.long 0x1100++0xB line.long 0x0 "DMA_CH0_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" line.long 0x4 "DMA_CH0_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH0_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1114++0x3 line.long 0x0 "DMA_CH0_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" group.long 0x111C++0x7 line.long 0x0 "DMA_CH0_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" line.long 0x4 "DMA_CH0_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" group.long 0x1128++0x17 line.long 0x0 "DMA_CH0_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" line.long 0x4 "DMA_CH0_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring" line.long 0x8 "DMA_CH0_RxDesc_Ring_Length,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH0_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH0_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH0_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x1144++0x3 line.long 0x0 "DMA_CH0_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x114C++0x3 line.long 0x0 "DMA_CH0_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x1154++0x3 line.long 0x0 "DMA_CH0_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x115C++0x3 line.long 0x0 "DMA_CH0_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x1160++0x3 line.long 0x0 "DMA_CH0_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x1164++0xB line.long 0x0 "DMA_CH0_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH0_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH0_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" group.long 0x1180++0xB line.long 0x0 "DMA_CH1_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" line.long 0x4 "DMA_CH1_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH1_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1194++0x3 line.long 0x0 "DMA_CH1_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" group.long 0x119C++0x7 line.long 0x0 "DMA_CH1_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" line.long 0x4 "DMA_CH1_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" group.long 0x11A8++0x17 line.long 0x0 "DMA_CH1_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" line.long 0x4 "DMA_CH1_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring" line.long 0x8 "DMA_CH1_RxDesc_Ring_Length,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH1_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH1_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH1_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x11C4++0x3 line.long 0x0 "DMA_CH1_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x11CC++0x3 line.long 0x0 "DMA_CH1_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x11D4++0x3 line.long 0x0 "DMA_CH1_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x11DC++0x3 line.long 0x0 "DMA_CH1_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x11E0++0x3 line.long 0x0 "DMA_CH1_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x11E4++0xB line.long 0x0 "DMA_CH1_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH1_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH1_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" group.long 0x1200++0xB line.long 0x0 "DMA_CH2_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" line.long 0x4 "DMA_CH2_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH2_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1214++0x3 line.long 0x0 "DMA_CH2_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" group.long 0x121C++0x7 line.long 0x0 "DMA_CH2_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" line.long 0x4 "DMA_CH2_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" group.long 0x1228++0x17 line.long 0x0 "DMA_CH2_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" line.long 0x4 "DMA_CH2_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring" line.long 0x8 "DMA_CH2_RxDesc_Ring_Length,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH2_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH2_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH2_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x1244++0x3 line.long 0x0 "DMA_CH2_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x124C++0x3 line.long 0x0 "DMA_CH2_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x1254++0x3 line.long 0x0 "DMA_CH2_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x125C++0x3 line.long 0x0 "DMA_CH2_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x1260++0x3 line.long 0x0 "DMA_CH2_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x1264++0xB line.long 0x0 "DMA_CH2_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH2_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH2_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" group.long 0x1280++0xB line.long 0x0 "DMA_CH3_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" line.long 0x4 "DMA_CH3_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH3_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1294++0x3 line.long 0x0 "DMA_CH3_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" group.long 0x129C++0x7 line.long 0x0 "DMA_CH3_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" line.long 0x4 "DMA_CH3_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" group.long 0x12A8++0x17 line.long 0x0 "DMA_CH3_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" line.long 0x4 "DMA_CH3_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring" line.long 0x8 "DMA_CH3_RxDesc_Ring_Length,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH3_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH3_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH3_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x12C4++0x3 line.long 0x0 "DMA_CH3_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x12CC++0x3 line.long 0x0 "DMA_CH3_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x12D4++0x3 line.long 0x0 "DMA_CH3_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x12DC++0x3 line.long 0x0 "DMA_CH3_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x12E0++0x3 line.long 0x0 "DMA_CH3_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x12E4++0xB line.long 0x0 "DMA_CH3_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH3_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH3_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" group.long 0x1300++0xB line.long 0x0 "DMA_CH4_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" line.long 0x4 "DMA_CH4_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH4_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1314++0x3 line.long 0x0 "DMA_CH4_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" group.long 0x131C++0x7 line.long 0x0 "DMA_CH4_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" line.long 0x4 "DMA_CH4_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" group.long 0x1328++0x17 line.long 0x0 "DMA_CH4_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" line.long 0x4 "DMA_CH4_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring" line.long 0x8 "DMA_CH4_RxDesc_Ring_Length,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH4_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH4_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH4_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x1344++0x3 line.long 0x0 "DMA_CH4_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x134C++0x3 line.long 0x0 "DMA_CH4_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x1354++0x3 line.long 0x0 "DMA_CH4_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x135C++0x3 line.long 0x0 "DMA_CH4_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x1360++0x3 line.long 0x0 "DMA_CH4_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x1364++0xB line.long 0x0 "DMA_CH4_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH4_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH4_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" tree.end tree "I2C (Inter-Integrated Circuit)" base ad:0x0 tree "I2C_0" base ad:0x401E4000 group.byte 0x0++0x6 line.byte 0x0 "IBAD,I2C Bus Address" hexmask.byte 0x0 1.--7. 1. "ADR,Slave Address" line.byte 0x1 "IBFD,I2C Bus Frequency Divider" hexmask.byte 0x1 0.--7. 1. "IBC,I-Bus Clock Rate" line.byte 0x2 "IBCR,I2C Bus Control" bitfld.byte 0x2 7. "MDIS,Module Disable" "0: The module is enabled. You must clear this field..,1: The module is reset and disabled. This is the.." bitfld.byte 0x2 6. "IBIE,Bus Interrupt Enable" "0: Interrupts from I2C are disabled. This does not..,1: Interrupts from I2C are enabled. An I2C.." newline bitfld.byte 0x2 5. "MSSL,Master/Slave Mode Select" "0: Slave,1: Master" bitfld.byte 0x2 4. "TXRX,Transmit/Receive Mode Select" "0: Receive,1: Transmit" newline bitfld.byte 0x2 3. "NOACK,Data Acknowledge Disable" "0: Send an acknowledge signal to the bus at the 9th..,1: Do not send an acknowledge-signal response (that.." bitfld.byte 0x2 2. "RSTA,Repeat START" "0: No effect,1: Generate repeated START condition" newline bitfld.byte 0x2 1. "DMAEN,DMA Enable" "0: Disable the DMA TX/RX request signals,1: Enable the DMA TX/RX request signals" line.byte 0x3 "IBSR,I2C Bus Status" rbitfld.byte 0x3 7. "TCF,Transfer Complete" "0: In progress,1: Complete" rbitfld.byte 0x3 6. "IAAS,Addressed As A Slave" "0: Not addressed,1: Addressed as a slave" newline rbitfld.byte 0x3 5. "IBB,Bus Busy" "0: Idle,1: Busy" eventfld.byte 0x3 4. "IBAL,Arbitration Lost" "0,1" newline rbitfld.byte 0x3 2. "SRW,Slave Read/Write" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave" eventfld.byte 0x3 1. "IBIF,Bus Interrupt Flag" "0,1" newline rbitfld.byte 0x3 0. "RXAK,Received Acknowledge" "0: Acknowledge received,1: No acknowledge received" line.byte 0x4 "IBDR,I2C Bus Data I/O" hexmask.byte 0x4 0.--7. 1. "DATA,Data transmitted or received" line.byte 0x5 "IBIC,I2C Bus Interrupt Configuration" bitfld.byte 0x5 7. "BIIE,Bus Idle Interrupt Enable" "0: Disable,1: Enable" bitfld.byte 0x5 6. "BYTERXIE,Byte Receive Interrupt Enable" "0,1" line.byte 0x6 "IBDBG,I2C Bus Debug" bitfld.byte 0x6 3. "GLFLT_EN,Glitch Filter Enable" "0: The I2C module allows all pulses on the SCL or..,1: The I2C module filters out any pulse (rising or.." eventfld.byte 0x6 2. "BYTE_RX,Byte Receive" "0,1" newline rbitfld.byte 0x6 1. "IPG_DEBUG_HALTED,Debug Halted" "0: Still executing a transaction,1: Entered DEBUG mode" bitfld.byte 0x6 0. "IPG_DEBUG_EN,Debug Enable" "0: Normal operation; the bus idle interrupts are..,1: In DEBUG mode" tree.end tree "I2C_1" base ad:0x401E8000 group.byte 0x0++0x6 line.byte 0x0 "IBAD,I2C Bus Address" hexmask.byte 0x0 1.--7. 1. "ADR,Slave Address" line.byte 0x1 "IBFD,I2C Bus Frequency Divider" hexmask.byte 0x1 0.--7. 1. "IBC,I-Bus Clock Rate" line.byte 0x2 "IBCR,I2C Bus Control" bitfld.byte 0x2 7. "MDIS,Module Disable" "0: The module is enabled. You must clear this field..,1: The module is reset and disabled. This is the.." bitfld.byte 0x2 6. "IBIE,Bus Interrupt Enable" "0: Interrupts from I2C are disabled. This does not..,1: Interrupts from I2C are enabled. An I2C.." newline bitfld.byte 0x2 5. "MSSL,Master/Slave Mode Select" "0: Slave,1: Master" bitfld.byte 0x2 4. "TXRX,Transmit/Receive Mode Select" "0: Receive,1: Transmit" newline bitfld.byte 0x2 3. "NOACK,Data Acknowledge Disable" "0: Send an acknowledge signal to the bus at the 9th..,1: Do not send an acknowledge-signal response (that.." bitfld.byte 0x2 2. "RSTA,Repeat START" "0: No effect,1: Generate repeated START condition" newline bitfld.byte 0x2 1. "DMAEN,DMA Enable" "0: Disable the DMA TX/RX request signals,1: Enable the DMA TX/RX request signals" line.byte 0x3 "IBSR,I2C Bus Status" rbitfld.byte 0x3 7. "TCF,Transfer Complete" "0: In progress,1: Complete" rbitfld.byte 0x3 6. "IAAS,Addressed As A Slave" "0: Not addressed,1: Addressed as a slave" newline rbitfld.byte 0x3 5. "IBB,Bus Busy" "0: Idle,1: Busy" eventfld.byte 0x3 4. "IBAL,Arbitration Lost" "0,1" newline rbitfld.byte 0x3 2. "SRW,Slave Read/Write" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave" eventfld.byte 0x3 1. "IBIF,Bus Interrupt Flag" "0,1" newline rbitfld.byte 0x3 0. "RXAK,Received Acknowledge" "0: Acknowledge received,1: No acknowledge received" line.byte 0x4 "IBDR,I2C Bus Data I/O" hexmask.byte 0x4 0.--7. 1. "DATA,Data transmitted or received" line.byte 0x5 "IBIC,I2C Bus Interrupt Configuration" bitfld.byte 0x5 7. "BIIE,Bus Idle Interrupt Enable" "0: Disable,1: Enable" bitfld.byte 0x5 6. "BYTERXIE,Byte Receive Interrupt Enable" "0,1" line.byte 0x6 "IBDBG,I2C Bus Debug" bitfld.byte 0x6 3. "GLFLT_EN,Glitch Filter Enable" "0: The I2C module allows all pulses on the SCL or..,1: The I2C module filters out any pulse (rising or.." eventfld.byte 0x6 2. "BYTE_RX,Byte Receive" "0,1" newline rbitfld.byte 0x6 1. "IPG_DEBUG_HALTED,Debug Halted" "0: Still executing a transaction,1: Entered DEBUG mode" bitfld.byte 0x6 0. "IPG_DEBUG_EN,Debug Enable" "0: Normal operation; the bus idle interrupts are..,1: In DEBUG mode" tree.end tree "I2C_2" base ad:0x401EC000 group.byte 0x0++0x6 line.byte 0x0 "IBAD,I2C Bus Address" hexmask.byte 0x0 1.--7. 1. "ADR,Slave Address" line.byte 0x1 "IBFD,I2C Bus Frequency Divider" hexmask.byte 0x1 0.--7. 1. "IBC,I-Bus Clock Rate" line.byte 0x2 "IBCR,I2C Bus Control" bitfld.byte 0x2 7. "MDIS,Module Disable" "0: The module is enabled. You must clear this field..,1: The module is reset and disabled. This is the.." bitfld.byte 0x2 6. "IBIE,Bus Interrupt Enable" "0: Interrupts from I2C are disabled. This does not..,1: Interrupts from I2C are enabled. An I2C.." newline bitfld.byte 0x2 5. "MSSL,Master/Slave Mode Select" "0: Slave,1: Master" bitfld.byte 0x2 4. "TXRX,Transmit/Receive Mode Select" "0: Receive,1: Transmit" newline bitfld.byte 0x2 3. "NOACK,Data Acknowledge Disable" "0: Send an acknowledge signal to the bus at the 9th..,1: Do not send an acknowledge-signal response (that.." bitfld.byte 0x2 2. "RSTA,Repeat START" "0: No effect,1: Generate repeated START condition" newline bitfld.byte 0x2 1. "DMAEN,DMA Enable" "0: Disable the DMA TX/RX request signals,1: Enable the DMA TX/RX request signals" line.byte 0x3 "IBSR,I2C Bus Status" rbitfld.byte 0x3 7. "TCF,Transfer Complete" "0: In progress,1: Complete" rbitfld.byte 0x3 6. "IAAS,Addressed As A Slave" "0: Not addressed,1: Addressed as a slave" newline rbitfld.byte 0x3 5. "IBB,Bus Busy" "0: Idle,1: Busy" eventfld.byte 0x3 4. "IBAL,Arbitration Lost" "0,1" newline rbitfld.byte 0x3 2. "SRW,Slave Read/Write" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave" eventfld.byte 0x3 1. "IBIF,Bus Interrupt Flag" "0,1" newline rbitfld.byte 0x3 0. "RXAK,Received Acknowledge" "0: Acknowledge received,1: No acknowledge received" line.byte 0x4 "IBDR,I2C Bus Data I/O" hexmask.byte 0x4 0.--7. 1. "DATA,Data transmitted or received" line.byte 0x5 "IBIC,I2C Bus Interrupt Configuration" bitfld.byte 0x5 7. "BIIE,Bus Idle Interrupt Enable" "0: Disable,1: Enable" bitfld.byte 0x5 6. "BYTERXIE,Byte Receive Interrupt Enable" "0,1" line.byte 0x6 "IBDBG,I2C Bus Debug" bitfld.byte 0x6 3. "GLFLT_EN,Glitch Filter Enable" "0: The I2C module allows all pulses on the SCL or..,1: The I2C module filters out any pulse (rising or.." eventfld.byte 0x6 2. "BYTE_RX,Byte Receive" "0,1" newline rbitfld.byte 0x6 1. "IPG_DEBUG_HALTED,Debug Halted" "0: Still executing a transaction,1: Entered DEBUG mode" bitfld.byte 0x6 0. "IPG_DEBUG_EN,Debug Enable" "0: Normal operation; the bus idle interrupts are..,1: In DEBUG mode" tree.end tree "I2C_3" base ad:0x402D8000 group.byte 0x0++0x6 line.byte 0x0 "IBAD,I2C Bus Address" hexmask.byte 0x0 1.--7. 1. "ADR,Slave Address" line.byte 0x1 "IBFD,I2C Bus Frequency Divider" hexmask.byte 0x1 0.--7. 1. "IBC,I-Bus Clock Rate" line.byte 0x2 "IBCR,I2C Bus Control" bitfld.byte 0x2 7. "MDIS,Module Disable" "0: The module is enabled. You must clear this field..,1: The module is reset and disabled. This is the.." bitfld.byte 0x2 6. "IBIE,Bus Interrupt Enable" "0: Interrupts from I2C are disabled. This does not..,1: Interrupts from I2C are enabled. An I2C.." newline bitfld.byte 0x2 5. "MSSL,Master/Slave Mode Select" "0: Slave,1: Master" bitfld.byte 0x2 4. "TXRX,Transmit/Receive Mode Select" "0: Receive,1: Transmit" newline bitfld.byte 0x2 3. "NOACK,Data Acknowledge Disable" "0: Send an acknowledge signal to the bus at the 9th..,1: Do not send an acknowledge-signal response (that.." bitfld.byte 0x2 2. "RSTA,Repeat START" "0: No effect,1: Generate repeated START condition" newline bitfld.byte 0x2 1. "DMAEN,DMA Enable" "0: Disable the DMA TX/RX request signals,1: Enable the DMA TX/RX request signals" line.byte 0x3 "IBSR,I2C Bus Status" rbitfld.byte 0x3 7. "TCF,Transfer Complete" "0: In progress,1: Complete" rbitfld.byte 0x3 6. "IAAS,Addressed As A Slave" "0: Not addressed,1: Addressed as a slave" newline rbitfld.byte 0x3 5. "IBB,Bus Busy" "0: Idle,1: Busy" eventfld.byte 0x3 4. "IBAL,Arbitration Lost" "0,1" newline rbitfld.byte 0x3 2. "SRW,Slave Read/Write" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave" eventfld.byte 0x3 1. "IBIF,Bus Interrupt Flag" "0,1" newline rbitfld.byte 0x3 0. "RXAK,Received Acknowledge" "0: Acknowledge received,1: No acknowledge received" line.byte 0x4 "IBDR,I2C Bus Data I/O" hexmask.byte 0x4 0.--7. 1. "DATA,Data transmitted or received" line.byte 0x5 "IBIC,I2C Bus Interrupt Configuration" bitfld.byte 0x5 7. "BIIE,Bus Idle Interrupt Enable" "0: Disable,1: Enable" bitfld.byte 0x5 6. "BYTERXIE,Byte Receive Interrupt Enable" "0,1" line.byte 0x6 "IBDBG,I2C Bus Debug" bitfld.byte 0x6 3. "GLFLT_EN,Glitch Filter Enable" "0: The I2C module allows all pulses on the SCL or..,1: The I2C module filters out any pulse (rising or.." eventfld.byte 0x6 2. "BYTE_RX,Byte Receive" "0,1" newline rbitfld.byte 0x6 1. "IPG_DEBUG_HALTED,Debug Halted" "0: Still executing a transaction,1: Entered DEBUG mode" bitfld.byte 0x6 0. "IPG_DEBUG_EN,Debug Enable" "0: Normal operation; the bus idle interrupts are..,1: In DEBUG mode" tree.end tree "I2C_4" base ad:0x402DC000 group.byte 0x0++0x6 line.byte 0x0 "IBAD,I2C Bus Address" hexmask.byte 0x0 1.--7. 1. "ADR,Slave Address" line.byte 0x1 "IBFD,I2C Bus Frequency Divider" hexmask.byte 0x1 0.--7. 1. "IBC,I-Bus Clock Rate" line.byte 0x2 "IBCR,I2C Bus Control" bitfld.byte 0x2 7. "MDIS,Module Disable" "0: The module is enabled. You must clear this field..,1: The module is reset and disabled. This is the.." bitfld.byte 0x2 6. "IBIE,Bus Interrupt Enable" "0: Interrupts from I2C are disabled. This does not..,1: Interrupts from I2C are enabled. An I2C.." newline bitfld.byte 0x2 5. "MSSL,Master/Slave Mode Select" "0: Slave,1: Master" bitfld.byte 0x2 4. "TXRX,Transmit/Receive Mode Select" "0: Receive,1: Transmit" newline bitfld.byte 0x2 3. "NOACK,Data Acknowledge Disable" "0: Send an acknowledge signal to the bus at the 9th..,1: Do not send an acknowledge-signal response (that.." bitfld.byte 0x2 2. "RSTA,Repeat START" "0: No effect,1: Generate repeated START condition" newline bitfld.byte 0x2 1. "DMAEN,DMA Enable" "0: Disable the DMA TX/RX request signals,1: Enable the DMA TX/RX request signals" line.byte 0x3 "IBSR,I2C Bus Status" rbitfld.byte 0x3 7. "TCF,Transfer Complete" "0: In progress,1: Complete" rbitfld.byte 0x3 6. "IAAS,Addressed As A Slave" "0: Not addressed,1: Addressed as a slave" newline rbitfld.byte 0x3 5. "IBB,Bus Busy" "0: Idle,1: Busy" eventfld.byte 0x3 4. "IBAL,Arbitration Lost" "0,1" newline rbitfld.byte 0x3 2. "SRW,Slave Read/Write" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave" eventfld.byte 0x3 1. "IBIF,Bus Interrupt Flag" "0,1" newline rbitfld.byte 0x3 0. "RXAK,Received Acknowledge" "0: Acknowledge received,1: No acknowledge received" line.byte 0x4 "IBDR,I2C Bus Data I/O" hexmask.byte 0x4 0.--7. 1. "DATA,Data transmitted or received" line.byte 0x5 "IBIC,I2C Bus Interrupt Configuration" bitfld.byte 0x5 7. "BIIE,Bus Idle Interrupt Enable" "0: Disable,1: Enable" bitfld.byte 0x5 6. "BYTERXIE,Byte Receive Interrupt Enable" "0,1" line.byte 0x6 "IBDBG,I2C Bus Debug" bitfld.byte 0x6 3. "GLFLT_EN,Glitch Filter Enable" "0: The I2C module allows all pulses on the SCL or..,1: The I2C module filters out any pulse (rising or.." eventfld.byte 0x6 2. "BYTE_RX,Byte Receive" "0,1" newline rbitfld.byte 0x6 1. "IPG_DEBUG_HALTED,Debug Halted" "0: Still executing a transaction,1: Entered DEBUG mode" bitfld.byte 0x6 0. "IPG_DEBUG_EN,Debug Enable" "0: Normal operation; the bus idle interrupts are..,1: In DEBUG mode" tree.end tree.end tree "JDC (JTAG Data Communication)" base ad:0x402F4000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 16. "JIN_IEN,JIN Interrupt Enable" "0: Setting MSR[JIN_INT] bit does not assert the JIN..,1: Setting MSR[JIN_INT] bit asserts the JIN interrupt" bitfld.long 0x0 0. "JOUT_IEN,JOUT Interrupt Enable" "0: Setting MSR[JOUT_INT] bit does not assert the..,1: Setting MSR[JOUT_INT] bit asserts the JOUT.." line.long 0x4 "MSR,Module Status Register" rbitfld.long 0x4 18. "JIN_RDY,JIN Ready (read only)" "0: Cleared upon software read of JIN_IPS contents..,1: Set when new data is written to the JIN_IPS.." eventfld.long 0x4 16. "JIN_INT,JIN Interrupt" "0: Cleared by writing logic 1,1: Set when new data is written to the JIN_IPS.." newline rbitfld.long 0x4 2. "JOUT_RDY,JOUT Ready (read only)" "0: Cleared upon tool read of JOUT register via JTAG..,1: Set when new data is written to the JOUT_IPS.." eventfld.long 0x4 0. "JOUT_INT,JOUT Interrupt" "0: Cleared by writing logic 1,1: Set when JOUT_RDY bit is cleared by tool reading.." line.long 0x8 "JOUT_IPS,JTAG Output Data Register" hexmask.long 0x8 0.--31. 1. "Data,JOUT_IPS Data" rgroup.long 0xC++0x3 line.long 0x0 "JIN_IPS,JTAG Input Data Register" hexmask.long 0x0 0.--31. 1. "Data,JIN_IPS data" tree.end tree "LINFLEXD" base ad:0x0 tree "LINFLEXD_0" base ad:0x401C8000 group.long 0x0++0x3F line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 16. "NLSE,LIN State Capture Enable on Bit Error Enables capture of LIN state LINSR[LINS] whenever bit error flag occur that is LINESR[BEF] set to 1" "0: LIN state LINSR[LINS] shows the current LIN..,1: LIN state LINSR[LINS] is captured whenever.." bitfld.long 0x0 15. "CCD,Checksum Calculation Disable You can read this field at any time and write to it only in Initialization mode" "0: Hardware performs the checksum calculation. When..,1: Checksum calculation disabled. When this field.." newline bitfld.long 0x0 14. "CFD,Checksum Field Disable You can read this field at any time and write to it only in Initialization mode" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup You can read this field at any time and write to it only in Initialization mode" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length Chooses the length of the Sync break that the master generates" bitfld.long 0x0 5. "LBKM,Loop Back mode See 'Loop back mode' in" "0: Loop Back mode disabled,1: Loop Back mode enabled" newline bitfld.long 0x0 4. "MME,Master Mode Enable You can read this field at any time and write to it only in Initialization mode." "0: Slave mode,1: Master mode" bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length You can read this field at any time and write to it only in Initialization mode" "0: 11-bit break length,1: 10-bit break length" newline bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode You can read this field at any time and write to it only in Initialization mode" "0: Receiver buffer not locked. Next incoming..,1: Receiver buffer locked against overrun. After.." bitfld.long 0x0 1. "SLEEP,Sleep Mode Request Write a 1 to this field to request LINFlexD to enter Sleep mode" "0,1" newline bitfld.long 0x0 0. "INIT,Initialization Mode Request Write a 1 to this field to request LINFlexD to enter Initialization mode" "0,1" line.long 0x4 "LINIER,LIN Interrupt Enable Register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable An interrupt is generated if this bit is set and the Stuck at Zero Flag (SZF) in LINESR or UARTSR is set" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable An interrupt is generated if this bit is set and the Checksum Error Flag (CEF) is set in LINESR" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable An interrupt is generated when this bit is set and either of the following flags are set: SFEF SDEF or IDPEF" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable An interrupt is generated if this bit is set and the Buffer Overrun Flag (BOF) is set in LINESR or UARTSR" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN State Interrupt Enable Interrupt is generated only when entering the above fields" "0: No interrupt,1: Interrupt generated when entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup Interrupt Enable If WUIE=1 and the WUF in LINSR or UARTSR is set then an interrupt is generated" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 3. "TOIE,Timeout Interrupt Enable An interrupt is generated if this bit is set and UARTSR[TO]=1 (in UART mode)" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 2. "DRIE,Data Reception Complete Interrupt Enable An interrupt is generated when this bit is set and Data Received flag (DRF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable An interrupt is generated when this bit is set and Data Transmitted flag (DTF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 0. "HRIE,Header Received Interrupt An interrupt is generated when this bit is set and the Header Received flag (HRF) in LINSR is set" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" rbitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count Contains the number of entries (bytes) in the Receive data buffer in LIN mode" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN State" newline eventfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free and is reset by hardware..,1: Buffer data ready to be read by software. This.." eventfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty LINFlexD writes a 1 to this field as soon as the first byte of response has been received and stored in BDRL (when there is at least one data byte in reception buffer)" "0,1" newline rbitfld.long 0x8 7. "RXBUSY,Receiver Busy In Slave mode after header reception if DIR bit is reset and reception starts then this bit is set" "0: Receiver idle,1: Reception ongoing" rbitfld.long 0x8 6. "RDI,Receiver Data Input Reflects the current status of the Rx pin After reset is released RDI reflects the actual value of Rx pin" "0,1" newline eventfld.long 0x8 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the Rx pin" "0,1" eventfld.long 0x8 2. "DRF,Data Reception Completed Flag This bit is set by hardware and indicates that data reception completed" "0,1" newline eventfld.long 0x8 1. "DTF,Data Transmission Completed Flag This bit is set by hardware and indicates that data transmission completed" "0,1" eventfld.long 0x8 0. "HRF,Header Received flag This bit is set when the header reception is completed" "0,1" line.long 0xC "LINESR,LIN Error Status Register" eventfld.long 0xC 15. "SZF,Stuck At Zero Flag This bit is set when there is a stuck-at-zero timeout error" "0,1" eventfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: In master mode LINESR[OCF] flag is set when.." newline eventfld.long 0xC 13. "BEF,Bit Error Flag LINFlexD writes a 1 to this field when a bit error occurs" "0,1" eventfld.long 0xC 12. "CEF,Checksum Error Flag LINFlexD writes a 1 to this field if the received checksum does not match the hardware-calculated checksum" "0,1" newline eventfld.long 0xC 11. "SFEF,Sync Field Error Flag LINFlexD writes a 1 to this field when the received Sync Field is inconsistent" "0,1" eventfld.long 0xC 10. "SDEF,Sync Delimiter Error Flag TLINFlexD writes a 1 to this field when the delimiter is too short (in other words less than one bit time)" "0,1" newline eventfld.long 0xC 9. "IDPEF,ID Parity Error Flag TLINFlexD writes a 1 to this field when an error in the ID parity occurs" "0,1" eventfld.long 0xC 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0,1" newline eventfld.long 0xC 7. "BOF,Buffer Overrun Flag This bit is set by hardware when there is a new byte received and RMB bit is not cleared" "0,1" eventfld.long 0xC 0. "NF,Noise Flag This bit is set by hardware when noise is detected in the received character" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State Controls what UARTCTO monitors" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point Decides the sample point during reduced oversampling" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR determines the oversampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frames" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop Bits In UART Reception Mode When the UART is used for transmission and reception you need to set the same number of stop bits in GCR and SBUR" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter TDFL defines the number of bytes to be transmitted in UART buffer mode (TFBM = 0)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter RDFL defines the number of bytes to be received in UART buffer mode (RFBM = 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9. "RFBM,Rx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" newline bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" bitfld.long 0x10 7. "WL1,Word Length In UART Mode Works with WL0 to configure word length as shown in the following table" "0,1" newline bitfld.long 0x10 6. "PC1,Parity Control Works with PC0 to configure parity as shown in the following table" "0,1" bitfld.long 0x10 5. "RxEn,Receiver Enable This bit can be programmed only when the UART bit is set." "0: Receiver disabled,1: Receiver enabled" newline bitfld.long 0x10 4. "TxEn,Transmitter Enable This bit can be programmed only when UART bit is set." "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." bitfld.long 0x10 3. "PC0,Parity Control Works with PC1 to configure parity" "0,1" newline bitfld.long 0x10 2. "PCE,Parity Control Enable Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Parity transmit/check disabled,1: Parity transmit/check enabled" bitfld.long 0x10 1. "WL0,Word Length in UART mode Works with WL1 to configure word length" "0,1" newline bitfld.long 0x10 0. "UART,UART Mode Register bit can be read in any mode written only in initialization mode." "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" eventfld.long 0x14 15. "SZF,Stuck At Zero Flag LINFlexD writes a 1 to this field when LINFlexD detects 100 dominant bits" "0,1" eventfld.long 0x14 14. "OCF,Output Compare Flag An interrupt will be generated if the OCIE bit in LINIER is set" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error Flag Indicates whether a parity error occurred in the corresponding byte" eventfld.long 0x14 9. "RMB,Release Message Buffer This bit must be cleared by software" "0: Buffer data is free,1: Buffer data ready for software to read" newline eventfld.long 0x14 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0: No framing error,1: Framing error occurs" eventfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag This bit is set by hardware when there is a new byte received and the RMB bit is not cleared in UART buffer mode" "0,1" newline rbitfld.long 0x14 6. "RDI,Receiver Data Input signal This bit reflects the current status of the RX pin when UART bit is set." "0,1" eventfld.long 0x14 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the RX pin in sleep mode" "0,1" newline rbitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty RFNE bit is set by hardware in UART FIFO mode (RFBM = 1) when there is at least one data byte present in the receive FIFO" "0,1" eventfld.long 0x14 3. "TO,Timeout This bit is set by hardware when a UART timeout occurs - in other words the value of UARTCTO becomes equal to the preset value of the timeout (UARTPTO register setting)" "0,1" newline eventfld.long 0x14 2. "DRFRFE,Data Reception Completed Flag /Rx FIFO Empty Flag DRF is set by hardware in UART buffer mode (RFBM = 0) and indicates that the number of bytes programmed in RDFL have been received" "0,1" eventfld.long 0x14 1. "DTFTFF,Data Transmission Completed Flag/ TX FIFO Full Flag DTF is set by hardware in UART buffer mode (TFBM = 0) and indicates that data transmission is completed" "0,1" newline eventfld.long 0x14 0. "NF,Noise flag This bit is set by hardware when noise is detected in the received character" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode This bit can be configured only during initialization" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout Register bit can be read in any mode written only in initialization mode" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable TOCE is always configurable by software in Initialization mode" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value These bits reflect the value of a counter used for timeout" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value This is the response timeout duration (in bit time) for 1 byte" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value This register contains the header timeout duration (in bit time)" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates Register bit can be read in any mode written only in initialization mode." line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates These bits along with the fractional baud rate bits decide the LIN baud rate" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits When the CCD bit is reset these bits are read-only and are calculated by hardware" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit This bit can be set in Initialization mode only" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error This bit can be set in Initialization mode only" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error This bit can be set in Initialization mode only" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request Setting this bit will generate a wakeup pulse" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request Set by software to stop data reception if the frame does not concern the node" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request Set by software in slave mode to request the transmission of the LIN Data field stored in the Buffer data register" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request Set by software to abort the current transmission" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request Set by software to request the transmission of the LIN Header" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" bitfld.long 0x34 10.--12. "DFL,Data Field Length Number of data bytes in the response part of the frame" "0,1,2,3,4,5,6,7" bitfld.long 0x34 9. "DIR,Direction This bit controls the direction of the data field." "0: LINFlexD receives the data and copy them in the..,1: LINFlexD transmits the data from the BDR registers" newline bitfld.long 0x34 8. "CCS,Classic Checksum This bit controls the type of checksum applied on the current message." "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data filed only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier Identifier part of the identifier field without the identifier parity" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3 Data byte 3 of the data field." hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2 Data byte 2 of the data field." newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1 Data byte 1of the data field." hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0 Data byte 0 of the data field." line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7 Data byte 7 of the data field." hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6 Data byte 6 of the data field." newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5 Data byte 5 of the data field." hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4 Data byte 4 of the data field." group.long 0x4C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB This bit controls the first bit of transmit data (payload only) as MSB/LSB in both UART and LIN modes" "0: The first bit of transmitted data is LSB - in..,1: The first bit of transmitted data is MSB - in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB This bit controls the first bit of received data (payload only) as MSB/LSB both in UART and LIN modes" "0: The first bit of received data is LSB - in other..,1: The first bit of received data is MSB - in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection This bit controls the data inversion of transmitted data (payload only) in both UART and LIN modes" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection This bit controls the data inversion of received data (payload only) in both UART and LIN modes" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration This bit controls the number of stop bit transmitted data in both UART and LIN modes" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset SR executes a soft reset of the LINFlexD controller (FSMs FIFO pointers counters timers status and error registers) without modifying the configuration registers when a 1 write operation is performed" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout PTO defines the preset value of timeout counter" rgroup.long 0x54++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout CTO defines the current value of the timeout counter" group.long 0x58++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE0,DMA Tx channel enable" "0: nth DMA Tx channel disabled,1: nth DMA Tx channel enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE0,DMA Rx channel enable The number of DRE bits varies and is equal to DMA_RX_CH_NUM" "0: nth DMA Rx channel disabled,1: nth DMA Rx channel enabled" tree.end tree "LINFLEXD_1" base ad:0x401CC000 group.long 0x0++0x3F line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 16. "NLSE,LIN State Capture Enable on Bit Error Enables capture of LIN state LINSR[LINS] whenever bit error flag occur that is LINESR[BEF] set to 1" "0: LIN state LINSR[LINS] shows the current LIN..,1: LIN state LINSR[LINS] is captured whenever.." bitfld.long 0x0 15. "CCD,Checksum Calculation Disable You can read this field at any time and write to it only in Initialization mode" "0: Hardware performs the checksum calculation. When..,1: Checksum calculation disabled. When this field.." newline bitfld.long 0x0 14. "CFD,Checksum Field Disable You can read this field at any time and write to it only in Initialization mode" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup You can read this field at any time and write to it only in Initialization mode" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length Chooses the length of the Sync break that the master generates" bitfld.long 0x0 5. "LBKM,Loop Back mode See 'Loop back mode' in" "0: Loop Back mode disabled,1: Loop Back mode enabled" newline bitfld.long 0x0 4. "MME,Master Mode Enable You can read this field at any time and write to it only in Initialization mode." "0: Slave mode,1: Master mode" bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length You can read this field at any time and write to it only in Initialization mode" "0: 11-bit break length,1: 10-bit break length" newline bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode You can read this field at any time and write to it only in Initialization mode" "0: Receiver buffer not locked. Next incoming..,1: Receiver buffer locked against overrun. After.." bitfld.long 0x0 1. "SLEEP,Sleep Mode Request Write a 1 to this field to request LINFlexD to enter Sleep mode" "0,1" newline bitfld.long 0x0 0. "INIT,Initialization Mode Request Write a 1 to this field to request LINFlexD to enter Initialization mode" "0,1" line.long 0x4 "LINIER,LIN Interrupt Enable Register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable An interrupt is generated if this bit is set and the Stuck at Zero Flag (SZF) in LINESR or UARTSR is set" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable An interrupt is generated if this bit is set and the Checksum Error Flag (CEF) is set in LINESR" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable An interrupt is generated when this bit is set and either of the following flags are set: SFEF SDEF or IDPEF" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable An interrupt is generated if this bit is set and the Buffer Overrun Flag (BOF) is set in LINESR or UARTSR" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN State Interrupt Enable Interrupt is generated only when entering the above fields" "0: No interrupt,1: Interrupt generated when entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup Interrupt Enable If WUIE=1 and the WUF in LINSR or UARTSR is set then an interrupt is generated" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 3. "TOIE,Timeout Interrupt Enable An interrupt is generated if this bit is set and UARTSR[TO]=1 (in UART mode)" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 2. "DRIE,Data Reception Complete Interrupt Enable An interrupt is generated when this bit is set and Data Received flag (DRF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable An interrupt is generated when this bit is set and Data Transmitted flag (DTF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 0. "HRIE,Header Received Interrupt An interrupt is generated when this bit is set and the Header Received flag (HRF) in LINSR is set" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" rbitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count Contains the number of entries (bytes) in the Receive data buffer in LIN mode" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN State" newline eventfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free and is reset by hardware..,1: Buffer data ready to be read by software. This.." eventfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty LINFlexD writes a 1 to this field as soon as the first byte of response has been received and stored in BDRL (when there is at least one data byte in reception buffer)" "0,1" newline rbitfld.long 0x8 7. "RXBUSY,Receiver Busy In Slave mode after header reception if DIR bit is reset and reception starts then this bit is set" "0: Receiver idle,1: Reception ongoing" rbitfld.long 0x8 6. "RDI,Receiver Data Input Reflects the current status of the Rx pin After reset is released RDI reflects the actual value of Rx pin" "0,1" newline eventfld.long 0x8 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the Rx pin" "0,1" eventfld.long 0x8 2. "DRF,Data Reception Completed Flag This bit is set by hardware and indicates that data reception completed" "0,1" newline eventfld.long 0x8 1. "DTF,Data Transmission Completed Flag This bit is set by hardware and indicates that data transmission completed" "0,1" eventfld.long 0x8 0. "HRF,Header Received flag This bit is set when the header reception is completed" "0,1" line.long 0xC "LINESR,LIN Error Status Register" eventfld.long 0xC 15. "SZF,Stuck At Zero Flag This bit is set when there is a stuck-at-zero timeout error" "0,1" eventfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: In master mode LINESR[OCF] flag is set when.." newline eventfld.long 0xC 13. "BEF,Bit Error Flag LINFlexD writes a 1 to this field when a bit error occurs" "0,1" eventfld.long 0xC 12. "CEF,Checksum Error Flag LINFlexD writes a 1 to this field if the received checksum does not match the hardware-calculated checksum" "0,1" newline eventfld.long 0xC 11. "SFEF,Sync Field Error Flag LINFlexD writes a 1 to this field when the received Sync Field is inconsistent" "0,1" eventfld.long 0xC 10. "SDEF,Sync Delimiter Error Flag TLINFlexD writes a 1 to this field when the delimiter is too short (in other words less than one bit time)" "0,1" newline eventfld.long 0xC 9. "IDPEF,ID Parity Error Flag TLINFlexD writes a 1 to this field when an error in the ID parity occurs" "0,1" eventfld.long 0xC 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0,1" newline eventfld.long 0xC 7. "BOF,Buffer Overrun Flag This bit is set by hardware when there is a new byte received and RMB bit is not cleared" "0,1" eventfld.long 0xC 0. "NF,Noise Flag This bit is set by hardware when noise is detected in the received character" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State Controls what UARTCTO monitors" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point Decides the sample point during reduced oversampling" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR determines the oversampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frames" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop Bits In UART Reception Mode When the UART is used for transmission and reception you need to set the same number of stop bits in GCR and SBUR" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter TDFL defines the number of bytes to be transmitted in UART buffer mode (TFBM = 0)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter RDFL defines the number of bytes to be received in UART buffer mode (RFBM = 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9. "RFBM,Rx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" newline bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" bitfld.long 0x10 7. "WL1,Word Length In UART Mode Works with WL0 to configure word length as shown in the following table" "0,1" newline bitfld.long 0x10 6. "PC1,Parity Control Works with PC0 to configure parity as shown in the following table" "0,1" bitfld.long 0x10 5. "RxEn,Receiver Enable This bit can be programmed only when the UART bit is set." "0: Receiver disabled,1: Receiver enabled" newline bitfld.long 0x10 4. "TxEn,Transmitter Enable This bit can be programmed only when UART bit is set." "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." bitfld.long 0x10 3. "PC0,Parity Control Works with PC1 to configure parity" "0,1" newline bitfld.long 0x10 2. "PCE,Parity Control Enable Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Parity transmit/check disabled,1: Parity transmit/check enabled" bitfld.long 0x10 1. "WL0,Word Length in UART mode Works with WL1 to configure word length" "0,1" newline bitfld.long 0x10 0. "UART,UART Mode Register bit can be read in any mode written only in initialization mode." "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" eventfld.long 0x14 15. "SZF,Stuck At Zero Flag LINFlexD writes a 1 to this field when LINFlexD detects 100 dominant bits" "0,1" eventfld.long 0x14 14. "OCF,Output Compare Flag An interrupt will be generated if the OCIE bit in LINIER is set" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error Flag Indicates whether a parity error occurred in the corresponding byte" eventfld.long 0x14 9. "RMB,Release Message Buffer This bit must be cleared by software" "0: Buffer data is free,1: Buffer data ready for software to read" newline eventfld.long 0x14 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0: No framing error,1: Framing error occurs" eventfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag This bit is set by hardware when there is a new byte received and the RMB bit is not cleared in UART buffer mode" "0,1" newline rbitfld.long 0x14 6. "RDI,Receiver Data Input signal This bit reflects the current status of the RX pin when UART bit is set." "0,1" eventfld.long 0x14 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the RX pin in sleep mode" "0,1" newline rbitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty RFNE bit is set by hardware in UART FIFO mode (RFBM = 1) when there is at least one data byte present in the receive FIFO" "0,1" eventfld.long 0x14 3. "TO,Timeout This bit is set by hardware when a UART timeout occurs - in other words the value of UARTCTO becomes equal to the preset value of the timeout (UARTPTO register setting)" "0,1" newline eventfld.long 0x14 2. "DRFRFE,Data Reception Completed Flag /Rx FIFO Empty Flag DRF is set by hardware in UART buffer mode (RFBM = 0) and indicates that the number of bytes programmed in RDFL have been received" "0,1" eventfld.long 0x14 1. "DTFTFF,Data Transmission Completed Flag/ TX FIFO Full Flag DTF is set by hardware in UART buffer mode (TFBM = 0) and indicates that data transmission is completed" "0,1" newline eventfld.long 0x14 0. "NF,Noise flag This bit is set by hardware when noise is detected in the received character" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode This bit can be configured only during initialization" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout Register bit can be read in any mode written only in initialization mode" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable TOCE is always configurable by software in Initialization mode" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value These bits reflect the value of a counter used for timeout" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value This is the response timeout duration (in bit time) for 1 byte" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value This register contains the header timeout duration (in bit time)" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates Register bit can be read in any mode written only in initialization mode." line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates These bits along with the fractional baud rate bits decide the LIN baud rate" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits When the CCD bit is reset these bits are read-only and are calculated by hardware" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit This bit can be set in Initialization mode only" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error This bit can be set in Initialization mode only" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error This bit can be set in Initialization mode only" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request Setting this bit will generate a wakeup pulse" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request Set by software to stop data reception if the frame does not concern the node" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request Set by software in slave mode to request the transmission of the LIN Data field stored in the Buffer data register" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request Set by software to abort the current transmission" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request Set by software to request the transmission of the LIN Header" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" bitfld.long 0x34 10.--12. "DFL,Data Field Length Number of data bytes in the response part of the frame" "0,1,2,3,4,5,6,7" bitfld.long 0x34 9. "DIR,Direction This bit controls the direction of the data field." "0: LINFlexD receives the data and copy them in the..,1: LINFlexD transmits the data from the BDR registers" newline bitfld.long 0x34 8. "CCS,Classic Checksum This bit controls the type of checksum applied on the current message." "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data filed only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier Identifier part of the identifier field without the identifier parity" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3 Data byte 3 of the data field." hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2 Data byte 2 of the data field." newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1 Data byte 1of the data field." hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0 Data byte 0 of the data field." line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7 Data byte 7 of the data field." hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6 Data byte 6 of the data field." newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5 Data byte 5 of the data field." hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4 Data byte 4 of the data field." group.long 0x4C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB This bit controls the first bit of transmit data (payload only) as MSB/LSB in both UART and LIN modes" "0: The first bit of transmitted data is LSB - in..,1: The first bit of transmitted data is MSB - in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB This bit controls the first bit of received data (payload only) as MSB/LSB both in UART and LIN modes" "0: The first bit of received data is LSB - in other..,1: The first bit of received data is MSB - in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection This bit controls the data inversion of transmitted data (payload only) in both UART and LIN modes" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection This bit controls the data inversion of received data (payload only) in both UART and LIN modes" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration This bit controls the number of stop bit transmitted data in both UART and LIN modes" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset SR executes a soft reset of the LINFlexD controller (FSMs FIFO pointers counters timers status and error registers) without modifying the configuration registers when a 1 write operation is performed" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout PTO defines the preset value of timeout counter" rgroup.long 0x54++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout CTO defines the current value of the timeout counter" group.long 0x58++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE0,DMA Tx channel enable" "0: nth DMA Tx channel disabled,1: nth DMA Tx channel enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE0,DMA Rx channel enable The number of DRE bits varies and is equal to DMA_RX_CH_NUM" "0: nth DMA Rx channel disabled,1: nth DMA Rx channel enabled" tree.end tree "LINFLEXD_2" base ad:0x402BC000 group.long 0x0++0x3F line.long 0x0 "LINCR1,LIN Control Register 1" bitfld.long 0x0 16. "NLSE,LIN State Capture Enable on Bit Error Enables capture of LIN state LINSR[LINS] whenever bit error flag occur that is LINESR[BEF] set to 1" "0: LIN state LINSR[LINS] shows the current LIN..,1: LIN state LINSR[LINS] is captured whenever.." bitfld.long 0x0 15. "CCD,Checksum Calculation Disable You can read this field at any time and write to it only in Initialization mode" "0: Hardware performs the checksum calculation. When..,1: Checksum calculation disabled. When this field.." newline bitfld.long 0x0 14. "CFD,Checksum Field Disable You can read this field at any time and write to it only in Initialization mode" "0: Checksum field is sent after the required number..,1: No checksum field is sent in the frame" bitfld.long 0x0 12. "AUTOWU,Auto Wakeup You can read this field at any time and write to it only in Initialization mode" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever WUF.." newline hexmask.long.byte 0x0 8.--11. 1. "MBL,Master Break Length Chooses the length of the Sync break that the master generates" bitfld.long 0x0 5. "LBKM,Loop Back mode See 'Loop back mode' in" "0: Loop Back mode disabled,1: Loop Back mode enabled" newline bitfld.long 0x0 4. "MME,Master Mode Enable You can read this field at any time and write to it only in Initialization mode." "0: Slave mode,1: Master mode" bitfld.long 0x0 3. "SSBL,Slave Mode Sync Break Length You can read this field at any time and write to it only in Initialization mode" "0: 11-bit break length,1: 10-bit break length" newline bitfld.long 0x0 2. "RBLM,Receiver Buffer Locked mode You can read this field at any time and write to it only in Initialization mode" "0: Receiver buffer not locked. Next incoming..,1: Receiver buffer locked against overrun. After.." bitfld.long 0x0 1. "SLEEP,Sleep Mode Request Write a 1 to this field to request LINFlexD to enter Sleep mode" "0,1" newline bitfld.long 0x0 0. "INIT,Initialization Mode Request Write a 1 to this field to request LINFlexD to enter Initialization mode" "0,1" line.long 0x4 "LINIER,LIN Interrupt Enable Register" bitfld.long 0x4 15. "SZIE,Stuck at Zero Interrupt Enable An interrupt is generated if this bit is set and the Stuck at Zero Flag (SZF) in LINESR or UARTSR is set" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.." newline bitfld.long 0x4 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is set" bitfld.long 0x4 12. "CEIE,Checksum Error Interrupt Enable An interrupt is generated if this bit is set and the Checksum Error Flag (CEF) is set in LINESR" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 11. "HEIE,Header Error Interrupt Enable An interrupt is generated when this bit is set and either of the following flags are set: SFEF SDEF or IDPEF" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).." newline bitfld.long 0x4 7. "BOIE,Buffer Overrun Error Interrupt Enable An interrupt is generated if this bit is set and the Buffer Overrun Flag (BOF) is set in LINESR or UARTSR" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 6. "LSIE,LIN State Interrupt Enable Interrupt is generated only when entering the above fields" "0: No interrupt,1: Interrupt generated when entering the following.." newline bitfld.long 0x4 5. "WUIE,Wakeup Interrupt Enable If WUIE=1 and the WUF in LINSR or UARTSR is set then an interrupt is generated" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 3. "TOIE,Timeout Interrupt Enable An interrupt is generated if this bit is set and UARTSR[TO]=1 (in UART mode)" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 2. "DRIE,Data Reception Complete Interrupt Enable An interrupt is generated when this bit is set and Data Received flag (DRF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled" bitfld.long 0x4 1. "DTIE,Data Transmitted Interrupt enable An interrupt is generated when this bit is set and Data Transmitted flag (DTF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled" newline bitfld.long 0x4 0. "HRIE,Header Received Interrupt An interrupt is generated when this bit is set and the Header Received flag (HRF) in LINSR is set" "0: No interrupt,1: Interrupt enabled" line.long 0x8 "LINSR,LIN Status Register" rbitfld.long 0x8 16.--18. "RDC,Receive Data Byte Count Contains the number of entries (bytes) in the Receive data buffer in LIN mode" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes" hexmask.long.byte 0x8 12.--15. 1. "LINS,LIN State" newline eventfld.long 0x8 9. "RMB,Release Message Buffer" "0: Buffer data is free and is reset by hardware..,1: Buffer data ready to be read by software. This.." eventfld.long 0x8 8. "DRBNE,Data Reception Buffer Not Empty LINFlexD writes a 1 to this field as soon as the first byte of response has been received and stored in BDRL (when there is at least one data byte in reception buffer)" "0,1" newline rbitfld.long 0x8 7. "RXBUSY,Receiver Busy In Slave mode after header reception if DIR bit is reset and reception starts then this bit is set" "0: Receiver idle,1: Reception ongoing" rbitfld.long 0x8 6. "RDI,Receiver Data Input Reflects the current status of the Rx pin After reset is released RDI reflects the actual value of Rx pin" "0,1" newline eventfld.long 0x8 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the Rx pin" "0,1" eventfld.long 0x8 2. "DRF,Data Reception Completed Flag This bit is set by hardware and indicates that data reception completed" "0,1" newline eventfld.long 0x8 1. "DTF,Data Transmission Completed Flag This bit is set by hardware and indicates that data transmission completed" "0,1" eventfld.long 0x8 0. "HRF,Header Received flag This bit is set when the header reception is completed" "0,1" line.long 0xC "LINESR,LIN Error Status Register" eventfld.long 0xC 15. "SZF,Stuck At Zero Flag This bit is set when there is a stuck-at-zero timeout error" "0,1" eventfld.long 0xC 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: In master mode LINESR[OCF] flag is set when.." newline eventfld.long 0xC 13. "BEF,Bit Error Flag LINFlexD writes a 1 to this field when a bit error occurs" "0,1" eventfld.long 0xC 12. "CEF,Checksum Error Flag LINFlexD writes a 1 to this field if the received checksum does not match the hardware-calculated checksum" "0,1" newline eventfld.long 0xC 11. "SFEF,Sync Field Error Flag LINFlexD writes a 1 to this field when the received Sync Field is inconsistent" "0,1" eventfld.long 0xC 10. "SDEF,Sync Delimiter Error Flag TLINFlexD writes a 1 to this field when the delimiter is too short (in other words less than one bit time)" "0,1" newline eventfld.long 0xC 9. "IDPEF,ID Parity Error Flag TLINFlexD writes a 1 to this field when an error in the ID parity occurs" "0,1" eventfld.long 0xC 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0,1" newline eventfld.long 0xC 7. "BOF,Buffer Overrun Flag This bit is set by hardware when there is a new byte received and RMB bit is not cleared" "0,1" eventfld.long 0xC 0. "NF,Noise Flag This bit is set by hardware when noise is detected in the received character" "0,1" line.long 0x10 "UARTCR,UART Mode Control Register" bitfld.long 0x10 31. "MIS,Monitor Idle State Controls what UARTCTO monitors" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the reception.." bitfld.long 0x10 28.--30. "CSP,Configurable Sample Point Decides the sample point during reduced oversampling" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--27. 1. "OSR,Over Sampling Rate" bitfld.long 0x10 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times.,1: OSR determines the oversampling rate." newline bitfld.long 0x10 20.--22. "NEF,Number of expected frames" "0,1,2,3,4,5,6,7" bitfld.long 0x10 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.." newline bitfld.long 0x10 17.--18. "SBUR,Stop Bits In UART Reception Mode When the UART is used for transmission and reception you need to set the same number of stop bits in GCR and SBUR" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?" bitfld.long 0x10 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter TDFL defines the number of bytes to be transmitted in UART buffer mode (TFBM = 0)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter RDFL defines the number of bytes to be received in UART buffer mode (RFBM = 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9. "RFBM,Rx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)" newline bitfld.long 0x10 8. "TFBM,Tx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)" bitfld.long 0x10 7. "WL1,Word Length In UART Mode Works with WL0 to configure word length as shown in the following table" "0,1" newline bitfld.long 0x10 6. "PC1,Parity Control Works with PC0 to configure parity as shown in the following table" "0,1" bitfld.long 0x10 5. "RxEn,Receiver Enable This bit can be programmed only when the UART bit is set." "0: Receiver disabled,1: Receiver enabled" newline bitfld.long 0x10 4. "TxEn,Transmitter Enable This bit can be programmed only when UART bit is set." "0: Transmitter disabled,1: Transmitter enabled transmission starts only.." bitfld.long 0x10 3. "PC0,Parity Control Works with PC1 to configure parity" "0,1" newline bitfld.long 0x10 2. "PCE,Parity Control Enable Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Parity transmit/check disabled,1: Parity transmit/check enabled" bitfld.long 0x10 1. "WL0,Word Length in UART mode Works with WL1 to configure word length" "0,1" newline bitfld.long 0x10 0. "UART,UART Mode Register bit can be read in any mode written only in initialization mode." "0: LIN mode,1: UART mode" line.long 0x14 "UARTSR,UART Mode Status Register" eventfld.long 0x14 15. "SZF,Stuck At Zero Flag LINFlexD writes a 1 to this field when LINFlexD detects 100 dominant bits" "0,1" eventfld.long 0x14 14. "OCF,Output Compare Flag An interrupt will be generated if the OCIE bit in LINIER is set" "0: No output compare event occurred,1: The content of the counter has matched the.." newline hexmask.long.byte 0x14 10.--13. 1. "PE,Parity Error Flag Indicates whether a parity error occurred in the corresponding byte" eventfld.long 0x14 9. "RMB,Release Message Buffer This bit must be cleared by software" "0: Buffer data is free,1: Buffer data ready for software to read" newline eventfld.long 0x14 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0: No framing error,1: Framing error occurs" eventfld.long 0x14 7. "BOF,FIFO/Buffer overrun flag This bit is set by hardware when there is a new byte received and the RMB bit is not cleared in UART buffer mode" "0,1" newline rbitfld.long 0x14 6. "RDI,Receiver Data Input signal This bit reflects the current status of the RX pin when UART bit is set." "0,1" eventfld.long 0x14 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the RX pin in sleep mode" "0,1" newline rbitfld.long 0x14 4. "RFNE,Receive FIFO Not Empty RFNE bit is set by hardware in UART FIFO mode (RFBM = 1) when there is at least one data byte present in the receive FIFO" "0,1" eventfld.long 0x14 3. "TO,Timeout This bit is set by hardware when a UART timeout occurs - in other words the value of UARTCTO becomes equal to the preset value of the timeout (UARTPTO register setting)" "0,1" newline eventfld.long 0x14 2. "DRFRFE,Data Reception Completed Flag /Rx FIFO Empty Flag DRF is set by hardware in UART buffer mode (RFBM = 0) and indicates that the number of bytes programmed in RDFL have been received" "0,1" eventfld.long 0x14 1. "DTFTFF,Data Transmission Completed Flag/ TX FIFO Full Flag DTF is set by hardware in UART buffer mode (TFBM = 0) and indicates that data transmission is completed" "0,1" newline eventfld.long 0x14 0. "NF,Noise flag This bit is set by hardware when noise is detected in the received character" "0,1" line.long 0x18 "LINTCSR,LIN Time-Out Control Status Register" bitfld.long 0x18 10. "MODE,Time-out counter mode This bit can be configured only during initialization" "0: LIN mode,1: Output compare mode" bitfld.long 0x18 9. "IOT,Idle on timeout Register bit can be read in any mode written only in initialization mode" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout event" newline bitfld.long 0x18 8. "TOCE,Time-out counter enable TOCE is always configurable by software in Initialization mode" "0: Time-out counter disable. OCF flag is not set on..,1: Time-out counter enable. OCF flag is set if an.." hexmask.long.byte 0x18 0.--7. 1. "CNT,Counter Value These bits reflect the value of a counter used for timeout" line.long 0x1C "LINOCR,LIN Output Compare Register" hexmask.long.byte 0x1C 8.--15. 1. "OC2,Output compare value 2" hexmask.long.byte 0x1C 0.--7. 1. "OC1,Output compare value 1" line.long 0x20 "LINTOCR,LIN Time-Out Control Register" hexmask.long.byte 0x20 8.--11. 1. "RTO,Response timeout value This is the response timeout duration (in bit time) for 1 byte" hexmask.long.byte 0x20 0.--6. 1. "HTO,Header timeout value This register contains the header timeout duration (in bit time)" line.long 0x24 "LINFBRR,LIN Fractional Baud Rate Register" hexmask.long.byte 0x24 0.--3. 1. "FBR,Fractional Baud rates Register bit can be read in any mode written only in initialization mode." line.long 0x28 "LINIBRR,LIN Integer Baud Rate Register" hexmask.long.tbyte 0x28 0.--19. 1. "IBR,Integer Baud rates These bits along with the fractional baud rate bits decide the LIN baud rate" line.long 0x2C "LINCFR,LIN Checksum Field Register" hexmask.long.byte 0x2C 0.--7. 1. "CF,Checksum bits When the CCD bit is reset these bits are read-only and are calculated by hardware" line.long 0x30 "LINCR2,LIN Control Register 2" bitfld.long 0x30 15. "TBDE,Two Bit delimiter bit This bit can be set in Initialization mode only" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits" bitfld.long 0x30 14. "IOBE,Idle on Bit Error This bit can be set in Initialization mode only" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine" newline bitfld.long 0x30 13. "IOPE,Idle on Identifier Parity Error This bit can be set in Initialization mode only" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine" bitfld.long 0x30 12. "WURQ,Wakeup Generate Request Setting this bit will generate a wakeup pulse" "0,1" newline bitfld.long 0x30 11. "DDRQ,Data Discard request Set by software to stop data reception if the frame does not concern the node" "0,1" bitfld.long 0x30 10. "DTRQ,Data Transmission Request Set by software in slave mode to request the transmission of the LIN Data field stored in the Buffer data register" "0,1" newline bitfld.long 0x30 9. "ABRQ,Abort Request Set by software to abort the current transmission" "0,1" bitfld.long 0x30 8. "HTRQ,Header Transmission Request Set by software to request the transmission of the LIN Header" "0,1" line.long 0x34 "BIDR,Buffer Identifier Register" bitfld.long 0x34 10.--12. "DFL,Data Field Length Number of data bytes in the response part of the frame" "0,1,2,3,4,5,6,7" bitfld.long 0x34 9. "DIR,Direction This bit controls the direction of the data field." "0: LINFlexD receives the data and copy them in the..,1: LINFlexD transmits the data from the BDR registers" newline bitfld.long 0x34 8. "CCS,Classic Checksum This bit controls the type of checksum applied on the current message." "0: Enhanced Checksum covering Identifier and Data..,1: Classic Checksum covering Data filed only. This.." hexmask.long.byte 0x34 0.--5. 1. "ID,Identifier Identifier part of the identifier field without the identifier parity" line.long 0x38 "BDRL,Buffer Data Register Least Significant" hexmask.long.byte 0x38 24.--31. 1. "DATA3,Data Byte 3 Data byte 3 of the data field." hexmask.long.byte 0x38 16.--23. 1. "DATA2,Data Byte 2 Data byte 2 of the data field." newline hexmask.long.byte 0x38 8.--15. 1. "DATA1,Data Byte 1 Data byte 1of the data field." hexmask.long.byte 0x38 0.--7. 1. "DATA0,Data Byte 0 Data byte 0 of the data field." line.long 0x3C "BDRM,Buffer Data Register Most Significant" hexmask.long.byte 0x3C 24.--31. 1. "DATA7,Data Byte 7 Data byte 7 of the data field." hexmask.long.byte 0x3C 16.--23. 1. "DATA6,Data Byte 6 Data byte 6 of the data field." newline hexmask.long.byte 0x3C 8.--15. 1. "DATA5,Data Byte 5 Data byte 5 of the data field." hexmask.long.byte 0x3C 0.--7. 1. "DATA4,Data Byte 4 Data byte 4 of the data field." group.long 0x4C++0x7 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x0 5. "TDFBM,Transmit data first bit MSB This bit controls the first bit of transmit data (payload only) as MSB/LSB in both UART and LIN modes" "0: The first bit of transmitted data is LSB - in..,1: The first bit of transmitted data is MSB - in.." bitfld.long 0x0 4. "RDFBM,Received data first bit MSB This bit controls the first bit of received data (payload only) as MSB/LSB both in UART and LIN modes" "0: The first bit of received data is LSB - in other..,1: The first bit of received data is MSB - in other.." newline bitfld.long 0x0 3. "TDLIS,Transmit data level inversion selection This bit controls the data inversion of transmitted data (payload only) in both UART and LIN modes" "0: Transmitted data is not inverted,1: Transmitted data is inverted" bitfld.long 0x0 2. "RDLIS,Received data level inversion selection This bit controls the data inversion of received data (payload only) in both UART and LIN modes" "0: Received data is not inverted,1: Received data is inverted" newline bitfld.long 0x0 1. "STOP,1/2 stop bit configuration This bit controls the number of stop bit transmitted data in both UART and LIN modes" "0: 1 stop bit,1: 2 stop bits" bitfld.long 0x0 0. "SR,Soft reset SR executes a soft reset of the LINFlexD controller (FSMs FIFO pointers counters timers status and error registers) without modifying the configuration registers when a 1 write operation is performed" "0,1" line.long 0x4 "UARTPTO,UART Preset Timeout Register" hexmask.long.word 0x4 0.--11. 1. "PTO,Preset Timeout PTO defines the preset value of timeout counter" rgroup.long 0x54++0x3 line.long 0x0 "UARTCTO,UART Current Timeout Register" hexmask.long.word 0x0 0.--11. 1. "CTO,Current Timeout CTO defines the current value of the timeout counter" group.long 0x58++0x7 line.long 0x0 "DMATXE,DMA Tx Enable Register" bitfld.long 0x0 0. "DTE0,DMA Tx channel enable" "0: nth DMA Tx channel disabled,1: nth DMA Tx channel enabled" line.long 0x4 "DMARXE,DMA Rx Enable Register" bitfld.long 0x4 0. "DRE0,DMA Rx channel enable The number of DRE bits varies and is equal to DMA_RX_CH_NUM" "0: nth DMA Rx channel disabled,1: nth DMA Rx channel enabled" tree.end tree.end tree "LLCE (Low Latency Communication Engine)" base ad:0x0 tree "LLCE_CORE_TO_CORE" base ad:0x43C26000 group.long 0x0++0xF line.long 0x0 "HINTC0R,HOST interrupt from Core 0 Register" bitfld.long 0x0 15. "FLG15,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 14. "FLG14,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 13. "FLG13,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 12. "FLG12,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 11. "FLG11,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 10. "FLG10,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x0 9. "FLG9,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 8. "FLG8,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 7. "FLG7,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 6. "FLG6,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 5. "FLG5,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 4. "FLG4,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x0 3. "FLG3,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 2. "FLG2,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 1. "FLG1,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 0. "FLG0,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: Event" line.long 0x4 "HINTC1R,HOST Interrupt from Core 1 Register" bitfld.long 0x4 15. "FLG15,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 14. "FLG14,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 13. "FLG13,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 12. "FLG12,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 11. "FLG11,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 10. "FLG10,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x4 9. "FLG9,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 8. "FLG8,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 7. "FLG7,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 6. "FLG6,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 5. "FLG5,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 4. "FLG4,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x4 3. "FLG3,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 2. "FLG2,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 1. "FLG1,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 0. "FLG0,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: Event" line.long 0x8 "HINTC2R,HOST Interrupt from Core 2 Register" bitfld.long 0x8 15. "FLG15,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 14. "FLG14,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 13. "FLG13,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 12. "FLG12,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 11. "FLG11,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 10. "FLG10,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x8 9. "FLG9,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 8. "FLG8,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 7. "FLG7,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 6. "FLG6,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 5. "FLG5,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 4. "FLG4,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x8 3. "FLG3,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 2. "FLG2,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 1. "FLG1,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 0. "FLG0,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: Event" line.long 0xC "HINTC3R,HOST Interrupt from Core 3 Register" bitfld.long 0xC 15. "FLG15,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 14. "FLG14,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 13. "FLG13,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 12. "FLG12,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 11. "FLG11,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 10. "FLG10,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0xC 9. "FLG9,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 8. "FLG8,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 7. "FLG7,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 6. "FLG6,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 5. "FLG5,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 4. "FLG4,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0xC 3. "FLG3,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 2. "FLG2,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 1. "FLG1,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 0. "FLG0,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: Event" group.long 0x20++0xF line.long 0x0 "C0INTHR,Core 0 Interrupt from HOST" bitfld.long 0x0 15. "FLG15,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 14. "FLG14,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 13. "FLG13,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 12. "FLG12,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 11. "FLG11,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 10. "FLG10,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x0 9. "FLG9,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 8. "FLG8,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 7. "FLG7,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 6. "FLG6,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 5. "FLG5,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 4. "FLG4,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x0 3. "FLG3,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 2. "FLG2,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 1. "FLG1,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x0 0. "FLG0,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" line.long 0x4 "C1INTHR,Core 1 Interrupt From HOST Register" bitfld.long 0x4 15. "FLG15,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 14. "FLG14,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 13. "FLG13,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 12. "FLG12,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 11. "FLG11,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 10. "FLG10,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x4 9. "FLG9,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 8. "FLG8,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 7. "FLG7,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 6. "FLG6,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 5. "FLG5,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 4. "FLG4,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x4 3. "FLG3,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 2. "FLG2,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 1. "FLG1,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x4 0. "FLG0,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" line.long 0x8 "C2INTHR,Core 2 Interrupt from HOST Register" bitfld.long 0x8 15. "FLG15,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 14. "FLG14,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 13. "FLG13,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 12. "FLG12,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 11. "FLG11,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 10. "FLG10,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x8 9. "FLG9,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 8. "FLG8,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 7. "FLG7,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 6. "FLG6,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 5. "FLG5,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 4. "FLG4,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0x8 3. "FLG3,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 2. "FLG2,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 1. "FLG1,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0x8 0. "FLG0,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" line.long 0xC "C3INTHR,Core 3 Interrupt from HOST Register" bitfld.long 0xC 15. "FLG15,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 14. "FLG14,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 13. "FLG13,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 12. "FLG12,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 11. "FLG11,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 10. "FLG10,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0xC 9. "FLG9,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 8. "FLG8,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 7. "FLG7,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 6. "FLG6,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 5. "FLG5,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 4. "FLG4,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" newline bitfld.long 0xC 3. "FLG3,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 2. "FLG2,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 1. "FLG1,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" bitfld.long 0xC 0. "FLG0,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: Event" group.long 0x60++0xF line.long 0x0 "HINTC0ER,HOST Interrupt from Core 0 Enable Register" bitfld.long 0x0 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" newline bitfld.long 0x0 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" newline bitfld.long 0x0 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x0 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" line.long 0x4 "HINTC1ER,HOST Interrupt from Core 1 Enable Register" bitfld.long 0x4 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" newline bitfld.long 0x4 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" newline bitfld.long 0x4 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x4 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" line.long 0x8 "HINTC2ER,HOST Interrupt from Core 2 Enable Register" bitfld.long 0x8 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" newline bitfld.long 0x8 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" newline bitfld.long 0x8 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0x8 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" line.long 0xC "HINTC3ER,HOST Interrupt from Core 3 Enable Register" bitfld.long 0xC 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" newline bitfld.long 0xC 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" newline bitfld.long 0xC 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" bitfld.long 0xC 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled" tree.end tree "LLCE_SYSCTRL" base ad:0x43FF8000 group.long 0x0++0x3 line.long 0x0 "LLCE_SYSRSTR,System Reset Control" bitfld.long 0x0 3. "CPU_RST3,CPU Reset 3" "0: CPU under reset,1: CPU out of reset" bitfld.long 0x0 2. "CPU_RST2,CPU Reset 2" "0: CPU under reset,1: CPU out of reset" bitfld.long 0x0 1. "CPU_RST1,CPU Reset 1" "0: CPU under reset,1: CPU out of reset" bitfld.long 0x0 0. "CPU_RST0,CPU Reset 0" "0: CPU under reset,1: CPU out of reset" tree.end tree.end tree "MC_CGM (Clock Generation Module)" base ad:0x0 tree "MC_CGM_0" base ad:0x40030000 group.long 0x0++0x3 line.long 0x0 "PCFS_SDUR,PCFS Step Duration" hexmask.long.word 0x0 0.--15. 1. "SDUR,Step duration" group.long 0x88++0xB line.long 0x0 "PCFS_DIVC12,PCFS Divider Change 12 Register" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider change rate" line.long 0x4 "PCFS_DIVE12,PCFS Divider End 12 Register" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider end value" line.long 0x8 "PCFS_DIVS12,PCFS Divider Start 12 Register" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider start value" group.long 0x300++0x3 line.long 0x0 "MUX_0_CSC,Clock Mux 0 Select Control Register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" bitfld.long 0x0 1. "RAMPDOWN,PCFS ramp-down" "0,1" newline bitfld.long 0x0 0. "RAMPUP,PCFS ramp-up" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "MUX_0_CSS,Clock Mux 0 Select Status Register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." bitfld.long 0x0 1. "RAMPDOWN,PCFS ramp-down" "0: No ramp-down operation was requested.,1: Ramp-down operation was requested." newline bitfld.long 0x0 0. "RAMPUP,PCFS ramp-up" "0: No ramp-up operation was requested.,1: Ramp-up operation was requested." group.long 0x308++0x7 line.long 0x0 "MUX_0_DC_0,Clock Mux 0 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" line.long 0x4 "MUX_0_DC_1,Clock Mux 0 Divider 1 Control Register" bitfld.long 0x4 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x4 16.--23. 1. "DIV,Division value" rgroup.long 0x33C++0x3 line.long 0x0 "MUX_0_DIV_UPD_STAT,Clock Mux 0 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 0" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x340++0x3 line.long 0x0 "MUX_1_CSC,Clock Mux 1 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "FCG,Force clock gate" "0,1" newline bitfld.long 0x0 2. "CG,Clock gate" "0,1" rgroup.long 0x344++0x3 line.long 0x0 "MUX_1_CSS,Clock Mux 1 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17. "CS,Clock status" "0: Clock is gated to logic-0 at output of clock mux,1: Clock mux is transparent. Active clock pulses at.." newline bitfld.long 0x0 16. "GRIP,Gating request is in progress." "0: Clock source gating or ungating has completed.,1: Clock source gating or ungating is in progress." group.long 0x348++0x3 line.long 0x0 "MUX_1_DC_0,Clock Mux 1 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x37C++0x3 line.long 0x0 "MUX_1_DIV_UPD_STAT,Clock Mux 1 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 1" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x380++0x3 line.long 0x0 "MUX_2_CSC,Clock Mux 2 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "FCG,Force clock gate" "0,1" newline bitfld.long 0x0 2. "CG,Clock gate" "0,1" rgroup.long 0x384++0x3 line.long 0x0 "MUX_2_CSS,Clock Mux 2 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17. "CS,Clock status" "0: Clock is gated to logic-0 at output of clock mux,1: Clock mux is transparent. Active clock pulses at.." newline bitfld.long 0x0 16. "GRIP,Gating request is in progress." "0: Clock source gating or ungating has completed.,1: Clock source gating or ungating is in progress." group.long 0x388++0x3 line.long 0x0 "MUX_2_DC_0,Clock Mux 2 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x3BC++0x3 line.long 0x0 "MUX_2_DIV_UPD_STAT,Clock Mux 2 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 2" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x3C0++0x3 line.long 0x0 "MUX_3_CSC,Clock Mux 3 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x3C4++0x3 line.long 0x0 "MUX_3_CSS,Clock Mux 3 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x3C8++0x3 line.long 0x0 "MUX_3_DC_0,Clock Mux 3 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x3FC++0x3 line.long 0x0 "MUX_3_DIV_UPD_STAT,Clock Mux 3 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 3" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x400++0x3 line.long 0x0 "MUX_4_CSC,Clock Mux 4 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x404++0x3 line.long 0x0 "MUX_4_CSS,Clock Mux 4 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x408++0x3 line.long 0x0 "MUX_4_DC_0,Clock Mux 4 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x43C++0x3 line.long 0x0 "MUX_4_DIV_UPD_STAT,Clock Mux 4 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 4" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x440++0x3 line.long 0x0 "MUX_5_CSC,Clock Mux 5 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x444++0x3 line.long 0x0 "MUX_5_CSS,Clock Mux 5 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x448++0x3 line.long 0x0 "MUX_5_DC_0,Clock Mux 5 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x47C++0x3 line.long 0x0 "MUX_5_DIV_UPD_STAT,Clock Mux 5 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 5" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x480++0x3 line.long 0x0 "MUX_6_CSC,Clock Mux 6 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x484++0x3 line.long 0x0 "MUX_6_CSS,Clock Mux 6 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x488++0x3 line.long 0x0 "MUX_6_DC_0,Clock Mux 6 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x4BC++0x3 line.long 0x0 "MUX_6_DIV_UPD_STAT,Clock Mux 6 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 6" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x4C0++0x3 line.long 0x0 "MUX_7_CSC,Clock Mux 7 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x4C4++0x3 line.long 0x0 "MUX_7_CSS,Clock Mux 7 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x500++0x3 line.long 0x0 "MUX_8_CSC,Clock Mux 8 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x504++0x3 line.long 0x0 "MUX_8_CSS,Clock Mux 8 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x540++0x3 line.long 0x0 "MUX_9_CSC,Clock Mux 9 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x544++0x3 line.long 0x0 "MUX_9_CSS,Clock Mux 9 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x548++0x3 line.long 0x0 "MUX_9_DC_0,Clock Mux 9 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x57C++0x3 line.long 0x0 "MUX_9_DIV_UPD_STAT,Clock Mux 9 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 9" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x580++0x3 line.long 0x0 "MUX_10_CSC,Clock Mux 10 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x584++0x3 line.long 0x0 "MUX_10_CSS,Clock Mux 10 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x588++0x3 line.long 0x0 "MUX_10_DC_0,Clock Mux 10 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x5BC++0x3 line.long 0x0 "MUX_10_DIV_UPD_STAT,Clock Mux 10 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 10" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x5C0++0x3 line.long 0x0 "MUX_11_CSC,Clock Mux 11 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x5C4++0x3 line.long 0x0 "MUX_11_CSS,Clock Mux 11 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x600++0x3 line.long 0x0 "MUX_12_CSC,Clock Mux 12 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x604++0x3 line.long 0x0 "MUX_12_CSS,Clock Mux 12 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x608++0x3 line.long 0x0 "MUX_12_DC_0,Clock Mux 12 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x63C++0x3 line.long 0x0 "MUX_12_DIV_UPD_STAT,Clock Mux 12 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 12" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x680++0x3 line.long 0x0 "MUX_14_CSC,Clock Mux 14 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x684++0x3 line.long 0x0 "MUX_14_CSS,Clock Mux 14 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x688++0x3 line.long 0x0 "MUX_14_DC_0,Clock Mux 14 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x6BC++0x3 line.long 0x0 "MUX_14_DIV_UPD_STAT,Clock Mux 14 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 14" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x6C0++0x3 line.long 0x0 "MUX_15_CSC,Clock Mux 15 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x6C4++0x3 line.long 0x0 "MUX_15_CSS,Clock Mux 15 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x6C8++0x3 line.long 0x0 "MUX_15_DC_0,Clock Mux 15 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" rgroup.long 0x6FC++0x3 line.long 0x0 "MUX_15_DIV_UPD_STAT,Clock Mux 15 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 15" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x700++0x3 line.long 0x0 "MUX_16_CSC,Clock Mux 16 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x704++0x3 line.long 0x0 "MUX_16_CSS,Clock Mux 16 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." tree.end tree "MC_CGM_1" base ad:0x40034000 group.long 0x0++0x3 line.long 0x0 "PCFS_SDUR,PCFS Step Duration" hexmask.long.word 0x0 0.--15. 1. "SDUR,Step duration" group.long 0x28++0xB line.long 0x0 "PCFS_DIVC4,PCFS Divider Change 4 Register" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider change rate" line.long 0x4 "PCFS_DIVE4,PCFS Divider End 4 Register" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider end value" line.long 0x8 "PCFS_DIVS4,PCFS Divider Start 4 Register" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider start value" group.long 0x300++0x3 line.long 0x0 "MUX_0_CSC,Clock Mux 0 Select Control Register" bitfld.long 0x0 24.--26. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,4: clk_src_4,?,?,?" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" bitfld.long 0x0 1. "RAMPDOWN,PCFS ramp-down" "0,1" newline bitfld.long 0x0 0. "RAMPUP,PCFS ramp-up" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "MUX_0_CSS,Clock Mux 0 Select Status Register" bitfld.long 0x0 24.--26. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,4: clk_src_4,?,?,?" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." bitfld.long 0x0 1. "RAMPDOWN,PCFS ramp-down" "0: No ramp-down operation was requested.,1: Ramp-down operation was requested." newline bitfld.long 0x0 0. "RAMPUP,PCFS ramp-up" "0: No ramp-up operation was requested.,1: Ramp-up operation was requested." tree.end tree "MC_CGM_2" base ad:0x44018000 group.long 0x0++0x3 line.long 0x0 "PCFS_SDUR,PCFS Step Duration" hexmask.long.word 0x0 0.--15. 1. "SDUR,Step duration" group.long 0x10C++0xB line.long 0x0 "PCFS_DIVC23,PCFS Divider Change 23 Register" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider change rate" line.long 0x4 "PCFS_DIVE23,PCFS Divider End 23 Register" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider end value" line.long 0x8 "PCFS_DIVS23,PCFS Divider Start 23 Register" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider start value" group.long 0x184++0xB line.long 0x0 "PCFS_DIVC33,PCFS Divider Change 33 Register" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider change rate" line.long 0x4 "PCFS_DIVE33,PCFS Divider End 33 Register" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider end value" line.long 0x8 "PCFS_DIVS33,PCFS Divider Start 33 Register" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider start value" group.long 0x220++0xD7 line.long 0x0 "PCFS_DIVC46,PCFS Divider Change 46 Register" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider change rate" line.long 0x4 "PCFS_DIVE46,PCFS Divider End 46 Register" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider end value" line.long 0x8 "PCFS_DIVS46,PCFS Divider Start 46 Register" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider start value" line.long 0xC "PCFS_DIVC47,PCFS Divider Change 47 Register" hexmask.long.word 0xC 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0xC 0.--7. 1. "RATE,Divider change rate" line.long 0x10 "PCFS_DIVE47,PCFS Divider End 47 Register" hexmask.long.tbyte 0x10 0.--19. 1. "DIVE,Divider end value" line.long 0x14 "PCFS_DIVS47,PCFS Divider Start 47 Register" hexmask.long.tbyte 0x14 0.--19. 1. "DIVS,Divider start value" line.long 0x18 "PCFS_DIVC48,PCFS Divider Change 48 Register" hexmask.long.word 0x18 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x18 0.--7. 1. "RATE,Divider change rate" line.long 0x1C "PCFS_DIVE48,PCFS Divider End 48 Register" hexmask.long.tbyte 0x1C 0.--19. 1. "DIVE,Divider end value" line.long 0x20 "PCFS_DIVS48,PCFS Divider Start 48 Register" hexmask.long.tbyte 0x20 0.--19. 1. "DIVS,Divider start value" line.long 0x24 "PCFS_DIVC49,PCFS Divider Change 49 Register" hexmask.long.word 0x24 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x24 0.--7. 1. "RATE,Divider change rate" line.long 0x28 "PCFS_DIVE49,PCFS Divider End 49 Register" hexmask.long.tbyte 0x28 0.--19. 1. "DIVE,Divider end value" line.long 0x2C "PCFS_DIVS49,PCFS Divider Start 49 Register" hexmask.long.tbyte 0x2C 0.--19. 1. "DIVS,Divider start value" line.long 0x30 "PCFS_DIVC50,PCFS Divider Change 50 Register" hexmask.long.word 0x30 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x30 0.--7. 1. "RATE,Divider change rate" line.long 0x34 "PCFS_DIVE50,PCFS Divider End 50 Register" hexmask.long.tbyte 0x34 0.--19. 1. "DIVE,Divider end value" line.long 0x38 "PCFS_DIVS50,PCFS Divider Start 50 Register" hexmask.long.tbyte 0x38 0.--19. 1. "DIVS,Divider start value" line.long 0x3C "PCFS_DIVC51,PCFS Divider Change 51 Register" hexmask.long.word 0x3C 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x3C 0.--7. 1. "RATE,Divider change rate" line.long 0x40 "PCFS_DIVE51,PCFS Divider End 51 Register" hexmask.long.tbyte 0x40 0.--19. 1. "DIVE,Divider end value" line.long 0x44 "PCFS_DIVS51,PCFS Divider Start 51 Register" hexmask.long.tbyte 0x44 0.--19. 1. "DIVS,Divider start value" line.long 0x48 "PCFS_DIVC52,PCFS Divider Change 52 Register" hexmask.long.word 0x48 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x48 0.--7. 1. "RATE,Divider change rate" line.long 0x4C "PCFS_DIVE52,PCFS Divider End 52 Register" hexmask.long.tbyte 0x4C 0.--19. 1. "DIVE,Divider end value" line.long 0x50 "PCFS_DIVS52,PCFS Divider Start 52 Register" hexmask.long.tbyte 0x50 0.--19. 1. "DIVS,Divider start value" line.long 0x54 "PCFS_DIVC53,PCFS Divider Change 53 Register" hexmask.long.word 0x54 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x54 0.--7. 1. "RATE,Divider change rate" line.long 0x58 "PCFS_DIVE53,PCFS Divider End 53 Register" hexmask.long.tbyte 0x58 0.--19. 1. "DIVE,Divider end value" line.long 0x5C "PCFS_DIVS53,PCFS Divider Start 53 Register" hexmask.long.tbyte 0x5C 0.--19. 1. "DIVS,Divider start value" line.long 0x60 "PCFS_DIVC54,PCFS Divider Change 54 Register" hexmask.long.word 0x60 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x60 0.--7. 1. "RATE,Divider change rate" line.long 0x64 "PCFS_DIVE54,PCFS Divider End 54 Register" hexmask.long.tbyte 0x64 0.--19. 1. "DIVE,Divider end value" line.long 0x68 "PCFS_DIVS54,PCFS Divider Start 54 Register" hexmask.long.tbyte 0x68 0.--19. 1. "DIVS,Divider start value" line.long 0x6C "PCFS_DIVC55,PCFS Divider Change 55 Register" hexmask.long.word 0x6C 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x6C 0.--7. 1. "RATE,Divider change rate" line.long 0x70 "PCFS_DIVE55,PCFS Divider End 55 Register" hexmask.long.tbyte 0x70 0.--19. 1. "DIVE,Divider end value" line.long 0x74 "PCFS_DIVS55,PCFS Divider Start 55 Register" hexmask.long.tbyte 0x74 0.--19. 1. "DIVS,Divider start value" line.long 0x78 "PCFS_DIVC56,PCFS Divider Change 56 Register" hexmask.long.word 0x78 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x78 0.--7. 1. "RATE,Divider change rate" line.long 0x7C "PCFS_DIVE56,PCFS Divider End 56 Register" hexmask.long.tbyte 0x7C 0.--19. 1. "DIVE,Divider end value" line.long 0x80 "PCFS_DIVS56,PCFS Divider Start 56 Register" hexmask.long.tbyte 0x80 0.--19. 1. "DIVS,Divider start value" line.long 0x84 "PCFS_DIVC57,PCFS Divider Change 57 Register" hexmask.long.word 0x84 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x84 0.--7. 1. "RATE,Divider change rate" line.long 0x88 "PCFS_DIVE57,PCFS Divider End 57 Register" hexmask.long.tbyte 0x88 0.--19. 1. "DIVE,Divider end value" line.long 0x8C "PCFS_DIVS57,PCFS Divider Start 57 Register" hexmask.long.tbyte 0x8C 0.--19. 1. "DIVS,Divider start value" line.long 0x90 "PCFS_DIVC58,PCFS Divider Change 58 Register" hexmask.long.word 0x90 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x90 0.--7. 1. "RATE,Divider change rate" line.long 0x94 "PCFS_DIVE58,PCFS Divider End 58 Register" hexmask.long.tbyte 0x94 0.--19. 1. "DIVE,Divider end value" line.long 0x98 "PCFS_DIVS58,PCFS Divider Start 58 Register" hexmask.long.tbyte 0x98 0.--19. 1. "DIVS,Divider start value" line.long 0x9C "PCFS_DIVC59,PCFS Divider Change 59 Register" hexmask.long.word 0x9C 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x9C 0.--7. 1. "RATE,Divider change rate" line.long 0xA0 "PCFS_DIVE59,PCFS Divider End 59 Register" hexmask.long.tbyte 0xA0 0.--19. 1. "DIVE,Divider end value" line.long 0xA4 "PCFS_DIVS59,PCFS Divider Start 59 Register" hexmask.long.tbyte 0xA4 0.--19. 1. "DIVS,Divider start value" line.long 0xA8 "PCFS_DIVC60,PCFS Divider Change 60 Register" hexmask.long.word 0xA8 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0xA8 0.--7. 1. "RATE,Divider change rate" line.long 0xAC "PCFS_DIVE60,PCFS Divider End 60 Register" hexmask.long.tbyte 0xAC 0.--19. 1. "DIVE,Divider end value" line.long 0xB0 "PCFS_DIVS60,PCFS Divider Start 60 Register" hexmask.long.tbyte 0xB0 0.--19. 1. "DIVS,Divider start value" line.long 0xB4 "PCFS_DIVC61,PCFS Divider Change 61 Register" hexmask.long.word 0xB4 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0xB4 0.--7. 1. "RATE,Divider change rate" line.long 0xB8 "PCFS_DIVE61,PCFS Divider End 61 Register" hexmask.long.tbyte 0xB8 0.--19. 1. "DIVE,Divider end value" line.long 0xBC "PCFS_DIVS61,PCFS Divider Start 61 Register" hexmask.long.tbyte 0xBC 0.--19. 1. "DIVS,Divider start value" line.long 0xC0 "PCFS_DIVC62,PCFS Divider Change 62 Register" hexmask.long.word 0xC0 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0xC0 0.--7. 1. "RATE,Divider change rate" line.long 0xC4 "PCFS_DIVE62,PCFS Divider End 62 Register" hexmask.long.tbyte 0xC4 0.--19. 1. "DIVE,Divider end value" line.long 0xC8 "PCFS_DIVS62,PCFS Divider Start 62 Register" hexmask.long.tbyte 0xC8 0.--19. 1. "DIVS,Divider start value" line.long 0xCC "PCFS_DIVC63,PCFS Divider Change 63 Register" hexmask.long.word 0xCC 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0xCC 0.--7. 1. "RATE,Divider change rate" line.long 0xD0 "PCFS_DIVE63,PCFS Divider End 63 Register" hexmask.long.tbyte 0xD0 0.--19. 1. "DIVE,Divider end value" line.long 0xD4 "PCFS_DIVS63,PCFS Divider Start 63 Register" hexmask.long.tbyte 0xD4 0.--19. 1. "DIVS,Divider start value" group.long 0x300++0x3 line.long 0x0 "MUX_0_CSC,Clock Mux 0 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" bitfld.long 0x0 1. "RAMPDOWN,PCFS ramp-down" "0,1" newline bitfld.long 0x0 0. "RAMPUP,PCFS ramp-up" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "MUX_0_CSS,Clock Mux 0 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." bitfld.long 0x0 1. "RAMPDOWN,PCFS ramp-down" "0: No ramp-down operation was requested.,1: Ramp-down operation was requested." newline bitfld.long 0x0 0. "RAMPUP,PCFS ramp-up" "0: No ramp-up operation was requested.,1: Ramp-up operation was requested." group.long 0x308++0x3 line.long 0x0 "MUX_0_DC_0,Clock Mux 0 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--19. 1. "DIV,Division value" rgroup.long 0x33C++0x3 line.long 0x0 "MUX_0_DIV_UPD_STAT,Clock Mux 0 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 0" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x340++0x3 line.long 0x0 "MUX_1_CSC,Clock Mux 1 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x344++0x3 line.long 0x0 "MUX_1_CSS,Clock Mux 1 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x348++0x7 line.long 0x0 "MUX_1_DC_0,Clock Mux 1 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" line.long 0x4 "MUX_1_DC_1,Clock Mux 1 Divider 1 Control Register" bitfld.long 0x4 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x4 16.--17. "DIV,Division value" "0,1,2,3" rgroup.long 0x37C++0x3 line.long 0x0 "MUX_1_DIV_UPD_STAT,Clock Mux 1 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 1" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x380++0x3 line.long 0x0 "MUX_2_CSC,Clock Mux 2 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x384++0x3 line.long 0x0 "MUX_2_CSS,Clock Mux 2 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x388++0x7 line.long 0x0 "MUX_2_DC_0,Clock Mux 2 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" line.long 0x4 "MUX_2_DC_1,Clock Mux 2 Divider 1 Control Register" bitfld.long 0x4 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x4 16.--17. "DIV,Division value" "0,1,2,3" rgroup.long 0x3BC++0x3 line.long 0x0 "MUX_2_DIV_UPD_STAT,Clock Mux 2 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 2" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x3C0++0x3 line.long 0x0 "MUX_3_CSC,Clock Mux 3 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x3C4++0x3 line.long 0x0 "MUX_3_CSS,Clock Mux 3 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x3C8++0x7 line.long 0x0 "MUX_3_DC_0,Clock Mux 3 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--23. 1. "DIV,Division value" line.long 0x4 "MUX_3_DC_1,Clock Mux 3 Divider 1 Control Register" bitfld.long 0x4 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x4 16.--17. "DIV,Division value" "0,1,2,3" rgroup.long 0x3FC++0x3 line.long 0x0 "MUX_3_DIV_UPD_STAT,Clock Mux 3 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 3" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x400++0x3 line.long 0x0 "MUX_4_CSC,Clock Mux 4 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x404++0x3 line.long 0x0 "MUX_4_CSS,Clock Mux 4 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x440++0x3 line.long 0x0 "MUX_5_CSC,Clock Mux 5 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x444++0x3 line.long 0x0 "MUX_5_CSS,Clock Mux 5 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x480++0x3 line.long 0x0 "MUX_6_CSC,Clock Mux 6 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x484++0x3 line.long 0x0 "MUX_6_CSS,Clock Mux 6 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x4C0++0x3 line.long 0x0 "MUX_7_CSC,Clock Mux 7 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x4C4++0x3 line.long 0x0 "MUX_7_CSS,Clock Mux 7 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x4C8++0x3 line.long 0x0 "MUX_7_DC_0,Clock Mux 7 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x4FC++0x3 line.long 0x0 "MUX_7_DIV_UPD_STAT,Clock Mux 7 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 7" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x500++0x3 line.long 0x0 "MUX_8_CSC,Clock Mux 8 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x504++0x3 line.long 0x0 "MUX_8_CSS,Clock Mux 8 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x508++0x3 line.long 0x0 "MUX_8_DC_0,Clock Mux 8 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x53C++0x3 line.long 0x0 "MUX_8_DIV_UPD_STAT,Clock Mux 8 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 8" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x540++0x3 line.long 0x0 "MUX_9_CSC,Clock Mux 9 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x544++0x3 line.long 0x0 "MUX_9_CSS,Clock Mux 9 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x548++0x3 line.long 0x0 "MUX_9_DC_0,Clock Mux 9 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x57C++0x3 line.long 0x0 "MUX_9_DIV_UPD_STAT,Clock Mux 9 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 9" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." tree.end tree "MC_CGM_5" base ad:0x40068000 group.long 0x300++0x3 line.long 0x0 "MUX_0_CSC,Clock Mux 0 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "MUX_0_CSS,Clock Mux 0 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to clk_src_0 because of a safe clock..,5: Switch to clk_src_0 because of a safe clock..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." tree.end tree.end tree "MC_ME (Mode Entry Module)" base ad:0x40088000 group.long 0x0++0xB line.long 0x0 "CTL_KEY,Control Key Register" hexmask.long.word 0x0 0.--15. 1. "KEY,Control key" line.long 0x4 "MODE_CONF,Mode Configuration Register" bitfld.long 0x4 15. "STANDBY,Standby request" "0,1" bitfld.long 0x4 1. "FUNC_RST,Functional reset request" "0,1" newline bitfld.long 0x4 0. "DEST_RST,Destructive reset request" "0,1" line.long 0x8 "MODE_UPD,Mode Update Register" bitfld.long 0x8 0. "MODE_UPD,Mode update" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "MODE_STAT,Mode Status Register" bitfld.long 0x0 0. "PREV_MODE,Previous mode" "0: The previous mode was reset (any reset).,1: The previous mode was standby." group.long 0x10++0x3 line.long 0x0 "MAIN_COREID,Main Core ID Register" hexmask.long.byte 0x0 8.--12. 1. "PIDX,Partition index" bitfld.long 0x0 0.--2. "CIDX,Core index" "0,1,2,3,4,5,6,7" group.long 0x100++0x7 line.long 0x0 "PRTN0_PCONF,Partition 0 Process Configuration Register" bitfld.long 0x0 0. "PCE,Partition clock enable" "0: Disable the clock to IPs,1: Enable the clock to IPs" line.long 0x4 "PRTN0_PUPD,Partition 0 Process Update Register" bitfld.long 0x4 0. "PCUD,Partition clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x108++0x3 line.long 0x0 "PRTN0_STAT,Partition 0 Status Register" bitfld.long 0x0 0. "PCS,Partition clock status" "0: Clock is inactive,1: Clock is active" rgroup.long 0x110++0x3 line.long 0x0 "PRTN0_COFB0_STAT,Partition 0 COFB Set 0 Clock Status Register" bitfld.long 0x0 31. "BLOCK31,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 30. "BLOCK30,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 29. "BLOCK29,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 28. "BLOCK28,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 27. "BLOCK27,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 26. "BLOCK26,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 25. "BLOCK25,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 24. "BLOCK24,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 23. "BLOCK23,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 22. "BLOCK22,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 21. "BLOCK21,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 20. "BLOCK20,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 19. "BLOCK19,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 18. "BLOCK18,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 17. "BLOCK17,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 16. "BLOCK16,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 15. "BLOCK15,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 14. "BLOCK14,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 13. "BLOCK13,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 12. "BLOCK12,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 11. "BLOCK11,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 10. "BLOCK10,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 9. "BLOCK9,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 8. "BLOCK8,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 7. "BLOCK7,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 6. "BLOCK6,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 5. "BLOCK5,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 4. "BLOCK4,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 3. "BLOCK3,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 2. "BLOCK2,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 1. "BLOCK1,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 0. "BLOCK0,IP block status" "0: Clock is not running.,1: Clock is running." group.long 0x130++0x3 line.long 0x0 "PRTN0_COFB0_CLKEN,Partition 0 COFB Set 0 Clock Enable Register" bitfld.long 0x0 31. "REQ31,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 30. "REQ30,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 29. "REQ29,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 28. "REQ28,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 27. "REQ27,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 26. "REQ26,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 25. "REQ25,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 24. "REQ24,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 23. "REQ23,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 22. "REQ22,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 21. "REQ21,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 20. "REQ20,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 19. "REQ19,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 18. "REQ18,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 17. "REQ17,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 16. "REQ16,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 15. "REQ15,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 14. "REQ14,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 13. "REQ13,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 12. "REQ12,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 11. "REQ11,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 10. "REQ10,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 9. "REQ9,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 8. "REQ8,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 7. "REQ7,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 6. "REQ6,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 5. "REQ5,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 4. "REQ4,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 3. "REQ3,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 2. "REQ2,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 1. "REQ1,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 0. "REQ0,Clock enable" "0: Clock is turned off.,1: Clock is turned on." group.long 0x140++0x7 line.long 0x0 "PRTN0_CORE0_PCONF,Partition 0 Core 0 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 0 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN0_CORE0_PUPD,Partition 0 Core 0 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 0 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x148++0x3 line.long 0x0 "PRTN0_CORE0_STAT,Partition 0 Core 0 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 0 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x14C++0x3 line.long 0x0 "PRTN0_CORE0_ADDR,Partition 0 Core 0 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x160++0x7 line.long 0x0 "PRTN0_CORE1_PCONF,Partition 0 Core 1 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 1 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN0_CORE1_PUPD,Partition 0 Core 1 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 1 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x168++0x3 line.long 0x0 "PRTN0_CORE1_STAT,Partition 0 Core 1 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 1 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x16C++0x3 line.long 0x0 "PRTN0_CORE1_ADDR,Partition 0 Core 1 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x180++0x7 line.long 0x0 "PRTN0_CORE2_PCONF,Partition 0 Core 2 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 2 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN0_CORE2_PUPD,Partition 0 Core 2 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 2 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x188++0x3 line.long 0x0 "PRTN0_CORE2_STAT,Partition 0 Core 2 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 2 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x18C++0x3 line.long 0x0 "PRTN0_CORE2_ADDR,Partition 0 Core 2 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x1A0++0x7 line.long 0x0 "PRTN0_CORE3_PCONF,Partition 0 Core 3 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 3 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN0_CORE3_PUPD,Partition 0 Core 3 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 3 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x1A8++0x3 line.long 0x0 "PRTN0_CORE3_STAT,Partition 0 Core 3 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 3 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x1AC++0x3 line.long 0x0 "PRTN0_CORE3_ADDR,Partition 0 Core 3 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x300++0x7 line.long 0x0 "PRTN1_PCONF,Partition 1 Process Configuration Register" bitfld.long 0x0 2. "OSSE,Output safe stating enable" "0: Disable output safe stating,1: Enable output safe stating" bitfld.long 0x0 0. "PCE,Partition clock enable" "0: Disable the clock to IPs,1: Enable the clock to IPs" line.long 0x4 "PRTN1_PUPD,Partition 1 Process Update Register" bitfld.long 0x4 2. "OSSUD,Output safe stating update" "0: Do not trigger the hardware process,1: Trigger the hardware process" bitfld.long 0x4 0. "PCUD,Partition clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x308++0x3 line.long 0x0 "PRTN1_STAT,Partition 1 Status Register" bitfld.long 0x0 2. "OSSS,Output safe stating status" "0: Output safe stating is inactive,1: Output safe stating is active" bitfld.long 0x0 0. "PCS,Partition clock status" "0: Clock is inactive,1: Clock is active" group.long 0x340++0x7 line.long 0x0 "PRTN1_CORE0_PCONF,Partition 1 Core 0 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 0 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN1_CORE0_PUPD,Partition 1 Core 0 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 0 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x348++0x3 line.long 0x0 "PRTN1_CORE0_STAT,Partition 1 Core 0 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 0 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x34C++0x3 line.long 0x0 "PRTN1_CORE0_ADDR,Partition 1 Core 0 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x360++0x7 line.long 0x0 "PRTN1_CORE1_PCONF,Partition 1 Core 1 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 1 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN1_CORE1_PUPD,Partition 1 Core 1 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 1 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x368++0x3 line.long 0x0 "PRTN1_CORE1_STAT,Partition 1 Core 1 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 1 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x36C++0x3 line.long 0x0 "PRTN1_CORE1_ADDR,Partition 1 Core 1 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x380++0x7 line.long 0x0 "PRTN1_CORE2_PCONF,Partition 1 Core 2 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 2 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN1_CORE2_PUPD,Partition 1 Core 2 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 2 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x388++0x3 line.long 0x0 "PRTN1_CORE2_STAT,Partition 1 Core 2 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 2 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x38C++0x3 line.long 0x0 "PRTN1_CORE2_ADDR,Partition 1 Core 2 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x3A0++0x7 line.long 0x0 "PRTN1_CORE3_PCONF,Partition 1 Core 3 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 3 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN1_CORE3_PUPD,Partition 1 Core 3 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 3 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x3A8++0x3 line.long 0x0 "PRTN1_CORE3_STAT,Partition 1 Core 3 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 3 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x3AC++0x3 line.long 0x0 "PRTN1_CORE3_ADDR,Partition 1 Core 3 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x500++0x7 line.long 0x0 "PRTN2_PCONF,Partition 2 Process Configuration Register" bitfld.long 0x0 2. "OSSE,Output safe stating enable" "0: Disable output safe stating,1: Enable output safe stating" bitfld.long 0x0 0. "PCE,Partition clock enable" "0: Disable the clock to IPs,1: Enable the clock to IPs" line.long 0x4 "PRTN2_PUPD,Partition 2 Process Update Register" bitfld.long 0x4 2. "OSSUD,Output safe stating update" "0: Do not trigger the hardware process,1: Trigger the hardware process" bitfld.long 0x4 0. "PCUD,Partition clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x508++0x3 line.long 0x0 "PRTN2_STAT,Partition 2 Status Register" bitfld.long 0x0 2. "OSSS,Output safe stating status" "0: Output safe stating is inactive,1: Output safe stating is active" bitfld.long 0x0 0. "PCS,Partition clock status" "0: Clock is inactive,1: Clock is active" rgroup.long 0x510++0x3 line.long 0x0 "PRTN2_COFB0_STAT,Partition 2 COFB Set 0 Clock Status Register" bitfld.long 0x0 31. "BLOCK31,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 30. "BLOCK30,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 29. "BLOCK29,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 28. "BLOCK28,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 27. "BLOCK27,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 26. "BLOCK26,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 25. "BLOCK25,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 24. "BLOCK24,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 23. "BLOCK23,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 22. "BLOCK22,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 21. "BLOCK21,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 20. "BLOCK20,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 19. "BLOCK19,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 18. "BLOCK18,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 17. "BLOCK17,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 16. "BLOCK16,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 15. "BLOCK15,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 14. "BLOCK14,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 13. "BLOCK13,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 12. "BLOCK12,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 11. "BLOCK11,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 10. "BLOCK10,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 9. "BLOCK9,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 8. "BLOCK8,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 7. "BLOCK7,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 6. "BLOCK6,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 5. "BLOCK5,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 4. "BLOCK4,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 3. "BLOCK3,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 2. "BLOCK2,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 1. "BLOCK1,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 0. "BLOCK0,IP block status" "0: Clock is not running.,1: Clock is running." group.long 0x530++0x3 line.long 0x0 "PRTN2_COFB0_CLKEN,Partition 2 COFB Set 0 Clock Enable Register" bitfld.long 0x0 31. "REQ31,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 30. "REQ30,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 29. "REQ29,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 28. "REQ28,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 27. "REQ27,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 26. "REQ26,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 25. "REQ25,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 24. "REQ24,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 23. "REQ23,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 22. "REQ22,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 21. "REQ21,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 20. "REQ20,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 19. "REQ19,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 18. "REQ18,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 17. "REQ17,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 16. "REQ16,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 15. "REQ15,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 14. "REQ14,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 13. "REQ13,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 12. "REQ12,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 11. "REQ11,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 10. "REQ10,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 9. "REQ9,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 8. "REQ8,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 7. "REQ7,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 6. "REQ6,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 5. "REQ5,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 4. "REQ4,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 3. "REQ3,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 2. "REQ2,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 1. "REQ1,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 0. "REQ0,Clock enable" "0: Clock is turned off.,1: Clock is turned on." group.long 0x700++0x7 line.long 0x0 "PRTN3_PCONF,Partition 3 Process Configuration Register" bitfld.long 0x0 2. "OSSE,Output safe stating enable" "0: Disable output safe stating,1: Enable output safe stating" bitfld.long 0x0 0. "PCE,Partition clock enable" "0: Disable the clock to IPs,1: Enable the clock to IPs" line.long 0x4 "PRTN3_PUPD,Partition 3 Process Update Register" bitfld.long 0x4 2. "OSSUD,Output safe stating update" "0: Do not trigger the hardware process,1: Trigger the hardware process" bitfld.long 0x4 0. "PCUD,Partition clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x708++0x3 line.long 0x0 "PRTN3_STAT,Partition 3 Status Register" bitfld.long 0x0 2. "OSSS,Output safe stating status" "0: Output safe stating is inactive,1: Output safe stating is active" bitfld.long 0x0 0. "PCS,Partition clock status" "0: Clock is inactive,1: Clock is active" rgroup.long 0x710++0x3 line.long 0x0 "PRTN3_COFB0_STAT,Partition 3 COFB Set 0 Clock Status Register" bitfld.long 0x0 31. "BLOCK31,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 30. "BLOCK30,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 29. "BLOCK29,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 28. "BLOCK28,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 27. "BLOCK27,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 26. "BLOCK26,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 25. "BLOCK25,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 24. "BLOCK24,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 23. "BLOCK23,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 22. "BLOCK22,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 21. "BLOCK21,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 20. "BLOCK20,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 19. "BLOCK19,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 18. "BLOCK18,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 17. "BLOCK17,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 16. "BLOCK16,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 15. "BLOCK15,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 14. "BLOCK14,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 13. "BLOCK13,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 12. "BLOCK12,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 11. "BLOCK11,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 10. "BLOCK10,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 9. "BLOCK9,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 8. "BLOCK8,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 7. "BLOCK7,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 6. "BLOCK6,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 5. "BLOCK5,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 4. "BLOCK4,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 3. "BLOCK3,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 2. "BLOCK2,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 1. "BLOCK1,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 0. "BLOCK0,IP block status" "0: Clock is not running.,1: Clock is running." group.long 0x730++0x3 line.long 0x0 "PRTN3_COFB0_CLKEN,Partition 3 COFB Set 0 Clock Enable Register" bitfld.long 0x0 31. "REQ31,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 30. "REQ30,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 29. "REQ29,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 28. "REQ28,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 27. "REQ27,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 26. "REQ26,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 25. "REQ25,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 24. "REQ24,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 23. "REQ23,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 22. "REQ22,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 21. "REQ21,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 20. "REQ20,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 19. "REQ19,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 18. "REQ18,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 17. "REQ17,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 16. "REQ16,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 15. "REQ15,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 14. "REQ14,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 13. "REQ13,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 12. "REQ12,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 11. "REQ11,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 10. "REQ10,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 9. "REQ9,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 8. "REQ8,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 7. "REQ7,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 6. "REQ6,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 5. "REQ5,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 4. "REQ4,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 3. "REQ3,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 2. "REQ2,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 1. "REQ1,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 0. "REQ0,Clock enable" "0: Clock is turned off.,1: Clock is turned on." tree.end tree "MC_RGM (Reset Generation Module)" base ad:0x40078000 group.long 0x0++0x3 line.long 0x0 "DES,Destructive Event Status Register" eventfld.long 0x0 31. "F_DR_31,Flag for 'Destructive' Reset F_DR_31" "0: 'Destructive' reset event F_DR_31 has not..,1: 'Destructive' reset event F_DR_31 has occurred." eventfld.long 0x0 30. "F_DR_30,Flag for 'Destructive' Reset F_DR_30" "0: 'Destructive' reset event F_DR_30 has not..,1: 'Destructive' reset event F_DR_30 has occurred." newline eventfld.long 0x0 18. "F_DR_18,Flag for 'Destructive' Reset F_DR_18" "0: 'Destructive' reset event F_DR_18 has not..,1: 'Destructive' reset event F_DR_18 has occurred." eventfld.long 0x0 17. "F_DR_17,Flag for 'Destructive' Reset F_DR_17" "0: 'Destructive' reset event F_DR_17 has not..,1: 'Destructive' reset event F_DR_17 has occurred." newline eventfld.long 0x0 16. "F_DR_16,Flag for 'Destructive' Reset F_DR_16" "0: 'Destructive' reset event F_DR_16 has not..,1: 'Destructive' reset event F_DR_16 has occurred." eventfld.long 0x0 13. "F_DR_13,Flag for 'Destructive' Reset F_DR_13" "0: 'Destructive' reset event F_DR_13 has not..,1: 'Destructive' reset event F_DR_13 has occurred." newline eventfld.long 0x0 12. "F_DR_12,Flag for 'Destructive' Reset F_DR_12" "0: 'Destructive' reset event F_DR_12 has not..,1: 'Destructive' reset event F_DR_12 has occurred." eventfld.long 0x0 11. "F_DR_11,Flag for 'Destructive' Reset F_DR_11" "0: 'Destructive' reset event F_DR_11 has not..,1: 'Destructive' reset event F_DR_11 has occurred." newline eventfld.long 0x0 10. "F_DR_10,Flag for 'Destructive' Reset F_DR_10" "0: 'Destructive' reset event F_DR_10 has not..,1: 'Destructive' reset event F_DR_10 has occurred." eventfld.long 0x0 9. "F_DR_9,Flag for 'Destructive' Reset F_DR_9" "0: 'Destructive' reset event F_DR_9 has not..,1: 'Destructive' reset event F_DR_9 has occurred." newline eventfld.long 0x0 8. "F_DR_8,Flag for 'Destructive' Reset F_DR_8" "0: 'Destructive' reset event F_DR_8 has not..,1: 'Destructive' reset event F_DR_8 has occurred." eventfld.long 0x0 6. "F_DR_6,Flag for 'Destructive' Reset F_DR_6" "0: 'Destructive' reset event F_DR_6 has not..,1: 'Destructive' reset event F_DR_6 has occurred." newline eventfld.long 0x0 4. "F_DR_4,Flag for 'Destructive' Reset F_DR_4" "0: 'Destructive' reset event F_DR_4 has not..,1: 'Destructive' reset event F_DR_4 has occurred." eventfld.long 0x0 3. "F_DR_3,Flag for 'Destructive' Reset F_DR_3" "0: 'Destructive' reset event F_DR_3 has not..,1: 'Destructive' reset event F_DR_3 has occurred." newline eventfld.long 0x0 1. "F_DR_1,Flag for 'Destructive' Reset F_DR_1" "0: 'Destructive' reset event F_DR_1 has not..,1: 'Destructive' reset event F_DR_1 has occurred." eventfld.long 0x0 0. "F_POR,Flag for power-on reset" "0: No power-on event has occurred since the last..,1: A power-on event has occurred." group.long 0x8++0x7 line.long 0x0 "FES,Functional /External Reset Status Register" eventfld.long 0x0 31. "F_FR_31,Flag for 'Functional' Reset F_FR_31" "0: 'Functional' reset event F_FR_31 has not..,1: 'Functional' reset event F_FR_31 has occurred." eventfld.long 0x0 30. "F_FR_30,Flag for 'Functional' Reset F_FR_30" "0: 'Functional' reset event F_FR_30 has not..,1: 'Functional' reset event F_FR_30 has occurred." newline eventfld.long 0x0 21. "F_FR_21,Flag for 'Functional' Reset F_FR_21" "0: 'Functional' reset event F_FR_21 has not..,1: 'Functional' reset event F_FR_21 has occurred." eventfld.long 0x0 20. "F_FR_20,Flag for 'Functional' Reset F_FR_20" "0: 'Functional' reset event F_FR_20 has not..,1: 'Functional' reset event F_FR_20 has occurred." newline eventfld.long 0x0 18. "F_FR_18,Flag for 'Functional' Reset F_FR_18" "0: 'Functional' reset event F_FR_18 has not..,1: 'Functional' reset event F_FR_18 has occurred." eventfld.long 0x0 6. "F_FR_6,Flag for 'Functional' Reset F_FR_6" "0: 'Functional' reset event F_FR_6 has not occurred..,1: 'Functional' reset event F_FR_6 has occurred." newline eventfld.long 0x0 4. "F_FR_4,Flag for 'Functional' Reset F_FR_4" "0: 'Functional' reset event F_FR_4 has not occurred..,1: 'Functional' reset event F_FR_4 has occurred." eventfld.long 0x0 3. "F_FR_3,Flag for 'Functional' Reset F_FR_3" "0: 'Functional' reset event F_FR_3 has not occurred..,1: 'Functional' reset event F_FR_3 has occurred." newline eventfld.long 0x0 0. "F_EXR,Flag for External Reset" "0: No external reset event has occurred since..,1: An external reset event has occurred." line.long 0x4 "FERD,Functional Event Reset Disable Register" bitfld.long 0x4 31. "D_F_FR_31,F_FR_31 Disable Control" "0: Functional reset event F_FR_31 triggers a reset..,1: Functional reset event F_FR_31 generates an.." bitfld.long 0x4 0. "D_EXR,External Reset event demote to interrupt" "0: 'External' reset event triggers a reset sequence.,1: 'External' reset event generates an interrupt.." group.long 0x14++0x13 line.long 0x0 "FREC,Functional Reset Escalation Counter Register" hexmask.long.byte 0x0 0.--3. 1. "FREC,Functional' Reset Escalation Counter" line.long 0x4 "FRET,Functional Reset Escalation Threshold Register" hexmask.long.byte 0x4 0.--3. 1. "FRET,'Functional' Reset Escalation Threshold" line.long 0x8 "DRET,Destructive Reset Escalation Threshold Register" hexmask.long.byte 0x8 0.--3. 1. "DRET,'Destructive' Reset Escalation Threshold" line.long 0xC "ERCTRL,External Reset Control Register" bitfld.long 0xC 0. "ERASSERT,ERASSERT" "0: No change,1: External reset is asserted" line.long 0x10 "RDSS,Reset During Standby Status Register" eventfld.long 0x10 0. "DES_RES,DES_RES" "0: No destructive reset event occurred during..,1: Destructive reset event occurred during standby.." group.long 0x40++0x3 line.long 0x0 "PRST0_0,Peripheral Reset" bitfld.long 0x0 17. "PERIPH_17_RST,Reset Control value for peripheral PERIPH_17_RST" "0: No forced reset on PERIPH_17_RST,1: Forced Reset on PERIPH_17_RST" bitfld.long 0x0 16. "PERIPH_16_RST,Reset Control value for peripheral PERIPH_16_RST" "0: No forced reset on PERIPH_16_RST,1: Forced Reset on PERIPH_16_RST" newline bitfld.long 0x0 5. "PERIPH_5_RST,Reset Control value for peripheral PERIPH_5_RST" "0: No forced reset on PERIPH_5_RST,1: Forced Reset on PERIPH_5_RST" bitfld.long 0x0 4. "PERIPH_4_RST,Reset Control value for peripheral PERIPH_4_RST" "0: No forced reset on PERIPH_4_RST,1: Forced Reset on PERIPH_4_RST" newline bitfld.long 0x0 3. "PERIPH_3_RST,Reset Control value for peripheral PERIPH_3_RST" "0: No forced reset on PERIPH_3_RST,1: Forced Reset on PERIPH_3_RST" bitfld.long 0x0 2. "PERIPH_2_RST,Reset Control value for peripheral PERIPH_2_RST" "0: No forced reset on PERIPH_2_RST,1: Forced Reset on PERIPH_2_RST" newline bitfld.long 0x0 1. "PERIPH_1_RST,Reset Control value for peripheral PERIPH_1_RST" "0: No forced reset on PERIPH_1_RST,1: Forced Reset on PERIPH_1_RST" bitfld.long 0x0 0. "PERIPH_0_RST,Reset Control value for peripheral PERIPH_0_RST" "0: No forced reset on PERIPH_0_RST,1: Forced Reset on PERIPH_0_RST" group.long 0x48++0x3 line.long 0x0 "PRST1_0,Peripheral Reset" bitfld.long 0x0 4. "PERIPH_68_RST,Reset Control value for peripheral PERIPH_68_RST" "0: No forced reset on PERIPH_68_RST,1: Forced Reset on PERIPH_68_RST" bitfld.long 0x0 3. "PERIPH_67_RST,Reset Control value for peripheral PERIPH_67_RST" "0: No forced reset on PERIPH_67_RST,1: Forced Reset on PERIPH_67_RST" newline bitfld.long 0x0 2. "PERIPH_66_RST,Reset Control value for peripheral PERIPH_66_RST" "0: No forced reset on PERIPH_66_RST,1: Forced Reset on PERIPH_66_RST" bitfld.long 0x0 1. "PERIPH_65_RST,Reset Control value for peripheral PERIPH_65_RST" "0: No forced reset on PERIPH_65_RST,1: Forced Reset on PERIPH_65_RST" newline bitfld.long 0x0 0. "PERIPH_64_RST,Reset Control value for peripheral PERIPH_64_RST" "0: No forced reset on PERIPH_64_RST,1: Forced Reset on PERIPH_64_RST" group.long 0x50++0x3 line.long 0x0 "PRST2_0,Peripheral Reset" bitfld.long 0x0 0. "PERIPH_128_RST,Reset Control value for peripheral PERIPH_128_RST" "0: No forced reset on PERIPH_128_RST,1: Forced Reset on PERIPH_128_RST" group.long 0x58++0x3 line.long 0x0 "PRST3_0,Peripheral Reset" bitfld.long 0x0 0. "PERIPH_192_RST,Reset Control value for peripheral PERIPH_192_RST" "0: No forced reset on PERIPH_192_RST,1: Forced Reset on PERIPH_192_RST" rgroup.long 0x140++0x3 line.long 0x0 "PSTAT0_0,Peripheral Reset Status Register" bitfld.long 0x0 17. "PERIPH_17_STAT,Reset Status for peripheral PERIPH_17_STAT" "0: Peripheral PERIPH_17_STAT is not in reset,1: Peripheral PERIPH_17_STAT is in reset" bitfld.long 0x0 16. "PERIPH_16_STAT,Reset Status for peripheral PERIPH_16_STAT" "0: Peripheral PERIPH_16_STAT is not in reset,1: Peripheral PERIPH_16_STAT is in reset" newline bitfld.long 0x0 5. "PERIPH_5_STAT,Reset Status for peripheral PERIPH_5_STAT" "0: Peripheral PERIPH_5_STAT is not in reset,1: Peripheral PERIPH_5_STAT is in reset" bitfld.long 0x0 4. "PERIPH_4_STAT,Reset Status for peripheral PERIPH_4_STAT" "0: Peripheral PERIPH_4_STAT is not in reset,1: Peripheral PERIPH_4_STAT is in reset" newline bitfld.long 0x0 3. "PERIPH_3_STAT,Reset Status for peripheral PERIPH_3_STAT" "0: Peripheral PERIPH_3_STAT is not in reset,1: Peripheral PERIPH_3_STAT is in reset" bitfld.long 0x0 2. "PERIPH_2_STAT,Reset Status for peripheral PERIPH_2_STAT" "0: Peripheral PERIPH_2_STAT is not in reset,1: Peripheral PERIPH_2_STAT is in reset" newline bitfld.long 0x0 1. "PERIPH_1_STAT,Reset Status for peripheral PERIPH_1_STAT" "0: Peripheral PERIPH_1_STAT is not in reset,1: Peripheral PERIPH_1_STAT is in reset" bitfld.long 0x0 0. "PERIPH_0_STAT,Reset Status for peripheral PERIPH_0_STAT" "0: Peripheral PERIPH_0_STAT is not in reset,1: Peripheral PERIPH_0_STAT is in reset" rgroup.long 0x148++0x3 line.long 0x0 "PSTAT1_0,Peripheral Reset Status Register" bitfld.long 0x0 4. "PERIPH_68_STAT,Reset Status for peripheral PERIPH_68_STAT" "0: Peripheral PERIPH_68_STAT is not in reset,1: Peripheral PERIPH_68_STAT is in reset" bitfld.long 0x0 3. "PERIPH_67_STAT,Reset Status for peripheral PERIPH_67_STAT" "0: Peripheral PERIPH_67_STAT is not in reset,1: Peripheral PERIPH_67_STAT is in reset" newline bitfld.long 0x0 2. "PERIPH_66_STAT,Reset Status for peripheral PERIPH_66_STAT" "0: Peripheral PERIPH_66_STAT is not in reset,1: Peripheral PERIPH_66_STAT is in reset" bitfld.long 0x0 1. "PERIPH_65_STAT,Reset Status for peripheral PERIPH_65_STAT" "0: Peripheral PERIPH_65_STAT is not in reset,1: Peripheral PERIPH_65_STAT is in reset" newline bitfld.long 0x0 0. "PERIPH_64_STAT,Reset Status for peripheral PERIPH_64_STAT" "0: Peripheral PERIPH_64_STAT is not in reset,1: Peripheral PERIPH_64_STAT is in reset" rgroup.long 0x150++0x3 line.long 0x0 "PSTAT2_0,Peripheral Reset Status Register" bitfld.long 0x0 0. "PERIPH_128_STAT,Reset Status for peripheral PERIPH_128_STAT" "0: Peripheral PERIPH_128_STAT is not in reset,1: Peripheral PERIPH_128_STAT is in reset" rgroup.long 0x158++0x3 line.long 0x0 "PSTAT3_0,Peripheral Reset Status Register" bitfld.long 0x0 0. "PERIPH_192_STAT,Reset Status for peripheral PERIPH_192_STAT" "0: Peripheral PERIPH_192_STAT is not in reset,1: Peripheral PERIPH_192_STAT is in reset" tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 rgroup.word 0x0++0x3 line.word 0x0 "PLREV,SoC-defined Platform Revision" hexmask.word 0x0 0.--15. 1. "PLREV,The PLREV[15:0] field is specified by a platform input signal to define a software-visible revision number." line.word 0x2 "PCT,Processor Core Type" hexmask.word 0x2 0.--15. 1. "PCT,This MCM design supports the Arm Cortex M7 core. The following value identifies this core complex." group.long 0xC++0x7 line.long 0x0 "CPCR,Core Platform Control" bitfld.long 0x0 27. "CM7_AHBSPRI,AHB Slave Priority" "0: Uses a round-robin arbitration scheme,1: AHB-slave access has priority over a core access" line.long 0x4 "ISCR,Interrupt Status and Control" bitfld.long 0x4 31. "FIDCE,FPU Input Denormal Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 28. "FIXCE,FPU Inexact Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 27. "FUFCE,FPU Underflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 26. "FOFCE,FPU Overflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 25. "FDZCE,FPU Divide-by-Zero Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 24. "FIOCE,FPU Invalid Operation Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 21. "WABE,TCM Write Abort Interrupt Enable" "0: Disable interrupt,1: Enable Interrupt" rbitfld.long 0x4 15. "FIDC,FPU Input Denormal Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 12. "FIXC,FPU Inexact Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 11. "FUFC,FPU Underflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 10. "FOFC,FPU Overflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 9. "FDZC,FPU Divide-by-Zero Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 8. "FIOC,FPU Invalid Operation Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 6. "WABSO,Write Abort on Slave Overrun" "0: No write abort overrun,1: Write abort overrun occurred" newline eventfld.long 0x4 5. "WABS,Write Abort on Slave" "0: No write abort occurred on AHBS interface,1: Write abort occurred on AHBS interface" rgroup.long 0x400++0x13 line.long 0x0 "LMEM_DESC_0,Local Memory Descriptor 0" bitfld.long 0x0 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x0 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x0 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x0 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x0 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x0 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x4 "LMEM_DESC_1,Local Memory Descriptor 1" bitfld.long 0x4 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x4 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x4 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x4 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x4 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x4 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x8 "LMEM_DESC_2,Local Memory Descriptor 2" bitfld.long 0x8 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x8 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x8 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x8 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x8 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x8 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0xC "LMEM_DESC_3,Local Memory Descriptor 3" bitfld.long 0xC 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0xC 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0xC 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0xC 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0xC 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0xC 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x10 "LMEM_DESC_4,Local Memory Descriptor 4" bitfld.long 0x10 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x10 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x10 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x10 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x10 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x10 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" tree.end tree "MDM_AP (Miscellaneous Debug Module Access Port)" base edp:0x600 rgroup.long 0x0++0x3 line.long 0x0 "STATUS,MDM_AP status" bitfld.long 0x0 30. "M7_2_DBGRSTRTD,Handshake ssignal for M7_2_DBGRSTRT" "0: Cortex-M7_2 is still in Debug mode,1: Cortex-M7_2 has returned to Normal mode from.." newline bitfld.long 0x0 29. "M7_1_DBGRSTRTD,Handshake signal for M7_1_DBGRSTRT" "0: Cortex-M7_1 is still in Debug mode,1: Cortex-M7_1 has returned to Normal mode from.." newline bitfld.long 0x0 28. "M7_0_DBGRSTRTD,Handshake signal for M7_0_DBGRSTRT" "0: Cortex-M7_0 is still in Debug mode,1: Cortex-M7_0 has returned to Normal mode from.." newline bitfld.long 0x0 22. "CM7_2_SLEEPING,Cortex-M7_2 Asserted Sleeping" "0: The processor is running or wants to leave sleep..,1: The processor and ETM are ready to enter a.." newline bitfld.long 0x0 21. "CM7_1_SLEEPING,Cortex-M7_1 Asserted Sleeping" "0: The processor is running or wants to leave sleep..,1: The processor and ETM are ready to enter a.." newline bitfld.long 0x0 20. "CM7_0_SLEEPING,Cortex-M7_0 Asserted Sleeping" "0: The processor is running or wants to leave sleep..,1: The processor and ETM are ready to enter a.." newline bitfld.long 0x0 18. "CM7_2_SLEEPDEEP,Cortex-M7_2 Asserted SLEEPDEEP" "0: Inactive value,1: The processor and ETM are ready to enter a.." newline bitfld.long 0x0 17. "CM7_1_SLEEPDEEP,Cortex-M7_1 Asserted SLEEPDEEP" "0: Inactive value,1: The processor and ETM are ready to enter a.." newline bitfld.long 0x0 16. "CM7_0_SLEEPDEEP,Cortex-M7_0 Asserted SLEEPDEEP" "0: Inactive value,1: The processor and ETM are ready to enter a.." newline bitfld.long 0x0 14. "CM7_2_HALTED,Cortex-M7_2 is halted due to Debug mode entry." "0: Normal mode,1: Debug mode" newline bitfld.long 0x0 13. "CM7_1_HALTED,Cortex-M7_1 is halted due to Debug mode entry." "0: Normal mode,1: Debug mode" newline bitfld.long 0x0 12. "CM7_0_HALTED,Cortex-M7_0 is halted due to Debug mode entry." "0: Normal mode,1: Debug mode" newline bitfld.long 0x0 8. "JTAG_ACTIVE,Status of Reset to AUX TAPs" "0: TRST of AUX TAPs are asserted,1: TRST of AUX TAPs are deasserted" newline bitfld.long 0x0 7. "CDBGPWRUPREQ,Status of CDBGPWRUPREQ from SWJ-DP" "0: CDBGPWRUPREQ is deasserted,1: CDBGPWRUPREQ is asserted" newline bitfld.long 0x0 6. "CSYSPWRUPREQ,Status of CSYSPWRUPREQ from SWJ-DP" "0: CSYSRUPREQ is deasserted,1: CSYSPWRUPREQ is asserted" newline bitfld.long 0x0 5. "READY_FOR_DBG,Status of ready for debug field is asserted by Boot Sequence routine." "0: Debugger to wait until the fields get asserted,1: Debugger can go ahead to run its routine" newline bitfld.long 0x0 2. "SYSTEM_RESET,System Reset State" "0: System is not in reset,1: System is in reset" group.long 0x4++0x3 line.long 0x0 "CONTROL,MDM_AP control" bitfld.long 0x0 30. "M7_2_DBGRSTRT,Cortex-M7 Debug Restart Input to Cortex-M7_2 Core" "0: Inactive value,1: Request asserted to restart the core" newline bitfld.long 0x0 29. "M7_1_DBGRSTRT,Cortex-M7 Debug Restart Input to Cortex-M7_1 Core" "0: Inactive value,1: Request asserted to restart the core" newline bitfld.long 0x0 28. "M7_0_DBGRSTRT,Cortex-M7 Debug Restart Input to Cortex-M7_0 Core" "0: Inactive value,1: Request asserted to restart the core" newline bitfld.long 0x0 24. "MSK_FCCU_RST_TRIGGER,Mask Reset Trigger from FCCU" "0: FCCU reset trigger is not masked,1: FCCU reset trigger is masked" newline bitfld.long 0x0 23. "MSK_DBG_FAULT,Mask Debug Faults" "0: Debug faults are not masked,1: Debug faults are masked" newline bitfld.long 0x0 21. "ETR_OVERRIDE,ETR Override" "0: ETR trace response is not overridden and the..,1: ETR trace response is overridden (default)" newline bitfld.long 0x0 20. "TPIU_OVERRIDE,TPIU Override" "0: TPIU trace response is not overridden and the..,1: TPIU trace response is overridden and forced.." newline bitfld.long 0x0 19. "CA53_B1_EDBGREQ,EDBGREQ Input for Cortex-A53 B1" "0: Inactive value,1: Request asserted to keep core in Debug mode" newline bitfld.long 0x0 18. "CA53_B0_EDBGREQ,EDBGREQ Input for Cortex-A53 B0" "0: Inactive value,1: Request asserted to keep core in Debug mode" newline bitfld.long 0x0 17. "CA53_A1_EDBGREQ,EDBGREQ Input for Cortex-A53 A1" "0: Inactive value,1: Request asserted to keep core in Debug mode" newline bitfld.long 0x0 16. "CA53_A0_EDBGREQ,EDBGREQ Input for Cortex-A53 A0" "0: Inactive value,1: Request asserted to keep core in Debug mode" newline bitfld.long 0x0 15. "DIS_POR_WDOG_MSK,POR Watchdog Timer" "0: Disables POR_WDOG timer (by default disabled),1: Enables POR_WDOG timer" newline bitfld.long 0x0 14. "MSK_LOCKSTEP_ALARM_CM72,Mask RCCU Alarm for Cortex M7_2" "0: Disables masking,1: Enables masking" newline bitfld.long 0x0 13. "MSK_LOCKSTEP_ALARM_CM71,Mask RCCU Alarm for Cortex M7_1" "0: Disables masking,1: Enables masking" newline bitfld.long 0x0 12. "MSK_LOCKSTEP_ALARM_CM70,Mask RCCU Alarm for Cortex M7_0" "0: Disables masking,1: Enables masking" newline bitfld.long 0x0 10. "CM7_2_EDBGREQ,EDBGREQ Input for Cortex-M7_2" "0: Inactive value,1: Request asserted to keep core in Debug mode" newline bitfld.long 0x0 9. "CM7_1_EDBGREQ,DEDBGREQ Input for Cortex-M7_1" "0: Inactive value,1: Request asserted to keep core in Debug mode" newline bitfld.long 0x0 8. "CM7_0_EDBGREQ,EDBGREQ Input for Cortex-M7_0" "0: Inactive value,1: Request asserted to keep core in Debug mode" newline bitfld.long 0x0 7. "ETR_HANDSHAKE_1,ETR Handshake_1" "0: Inactive value,1: Enables ETR" newline bitfld.long 0x0 6. "ETR_HANDSHAKE_0,ETR Handshake_0" "0: Disables ETR handshake with RGM,1: Enables ETR handshake with RGM" newline bitfld.long 0x0 5. "SYSFUNCRST,System Functional Reset" "0: Deasserts functional reset,1: Asserts functional reset" newline bitfld.long 0x0 4. "SYSRESETREQ,System Destructive Reset" "0: Deasserts destructive reset,1: Asserts destructive reset" newline bitfld.long 0x0 3. "DBG_SETUP_DONE,BootROM - Debugger Handshake field used with READY_FOR_DBG" "0: Inactive value,1: Debug setup is complete" group.long 0x30++0x3 line.long 0x0 "WIR_EN,WIR enable" bitfld.long 0x0 0. "STANDBY_EN,Setting this field enables debug through Standby mode." "0,1" group.long 0x38++0x3 line.long 0x0 "WIR_REL,WIR release" bitfld.long 0x0 0. "RESET_REL,Reset release" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "STATUS2,MDM_AP status 2" bitfld.long 0x0 11. "CA53_B1_WFE,MC_ME Low-Power Mode Entry using Cortex-A53 B1 Wait for Event (WFE)" "0: Core not in WFE low-power state,1: Core in WFE low-power state" newline bitfld.long 0x0 10. "CA53_B0_WFE,MC_ME Low-Power Mode Entry using Cortex-A53 B0 WFE" "0: Core not in WFE low-power state,1: Core in WFE low-power state" newline bitfld.long 0x0 9. "CA53_A1_WFE,MC_ME Low-Power Mode Entry using Cortex-A53 A1 WFE" "0: Core not in WFE low-power state,1: Core in WFE low-power state" newline bitfld.long 0x0 8. "CA53_A0_WFE,MC_ME Low-Power Mode Entry using Cortex-A53 A0 WFE (Wait For Event)" "0: Core not in WFE low-power state,1: Core in WFE low-power state" newline bitfld.long 0x0 7. "CA53_B1_WFI,MC_ME Low-Power Mode Entry using Cortex-A53 B1 WFI" "0: Core not in WFI low-power state,1: Core in WFI low-power state" newline bitfld.long 0x0 6. "CA53_B0_WFI,MC_ME Low-Power Mode Entry using Cortex-A53 B0 WFI" "0: Core not in WFI low-power state,1: Core in WFI low-power state" newline bitfld.long 0x0 5. "CA53_A1_WFI,MC_ME Low-Power Mode Entry using Cortex-A53 A1 WFI" "0: Core not in WFI low-power state,1: Core in WFI low-power state" newline bitfld.long 0x0 4. "CA53_A0_WFI,MC_ME Low-Power Mode Entry using Cortex-A53 A0 WFI (Wait For Interrupt)" "0: Core not in WFI low-power state,1: Core in WFI low-power state" newline bitfld.long 0x0 3. "CA53_B1_DBGMODE,Indicates that the Cortex-A53 B1 is halted due to Debug mode entry." "0: External debug request not acknowledged,1: External debug request acknowledged" newline bitfld.long 0x0 2. "CA53_B0_DBGMODE,Indicates that the Cortex-A53 B0 is halted due to Debug mode entry." "0: External debug request not acknowledged,1: External debug request acknowledged" newline bitfld.long 0x0 1. "CA53_A1_DBGMODE,Indicates that the Cortex-A53 A1 is halted due to Debug mode entry." "0: External debug request not acknowledged,1: External debug request acknowledged" newline bitfld.long 0x0 0. "CA53_A0_DBGMODE,Indicates that the Cortex-A53 A0 is halted due to Debug mode entry." "0: External debug request not acknowledged,1: External debug request acknowledged" group.long 0x70++0xB line.long 0x0 "CORTEX_A53_A0_IP_DBG,Cortex-A53 A0 debug" bitfld.long 0x0 0. "CA53_A0_IP_DBGDIS,If Cortex-A53 A0 enters Debug mode but you don't want the modules to enter Debug mode you must write a 1 to this field" "0: Modules also enter Debug mode when Cortex-A53 A0..,1: Modules do not enter Debug mode when Cortex-A53.." line.long 0x4 "CONTROL2,MDM_AP control 2" bitfld.long 0x4 7. "LLCE_C3_EDBGRQ,LLCE C3 EDBGRQ" "0,1" newline bitfld.long 0x4 6. "LLCE_C2_EDBGRQ,LLCE C2 EDBGRQ" "0,1" newline bitfld.long 0x4 5. "LLCE_C1_EDBGRQ,LLCE C1 EDBGRQ" "0,1" newline bitfld.long 0x4 4. "LLCE_C0_EDBGRQ,LLCE C0 EDBGRQ" "0,1" line.long 0x8 "CA53_A1_IP_DBG,Cortex-A53 A1 debug" bitfld.long 0x8 0. "CA53_A1_IP_DBGDIS,If Cortex-A53 A1 enters Debug mode but you don't want the modules to enter Debug mode you must write a 1 to this field" "0: Modules also enter Debug mode when Cortex-A53 A1..,1: Modules do not enter Debug mode when Cortex-A53.." group.long 0x80++0x3 line.long 0x0 "CORTEX_A53_B0_IP_DBG,Cortex-A53 B0 debug" bitfld.long 0x0 0. "CA53_B0_IP_DBGDIS,If Cortex-A53 B0 enters Debug mode but you don't want the modules to enter Debug mode you must write a 1 to this field" "0: Modules also enter Debug mode when Cortex-A53 B0..,1: Modules do not enter Debug mode when Cortex-A53.." group.long 0x88++0x3 line.long 0x0 "CORTEX_A53_B1_IP_DBG,Cortex-A53 B1 debug" bitfld.long 0x0 0. "CA53_B1_IP_DBGDIS,If Cortex-A53 B1 enters Debug mode but you don't want the modules to enter Debug mode you must write a 1 to this field" "0: Modules also enter Debug mode when Cortex-A53 B1..,1: Modules do not enter Debug mode when Cortex-A53.." group.long 0x90++0x3 line.long 0x0 "CORTEX_M7_0_IP_DBG,Cortex M7_0 debug" bitfld.long 0x0 0. "CM7_0_IP_DBGDIS,If Cortex-M7_0 enters Debug mode but you don't want the modules to enter Debug mode you must write a 1 to this field" "0: Modules also enter Debug mode when Cortex-M7_0..,1: Modules do not enter Debug mode when Cortex-M7_0.." group.long 0x98++0x3 line.long 0x0 "CORTEX_M7_1_IP_DBG,Cortex M7_1 debug" bitfld.long 0x0 0. "CM7_1_IP_DBGDIS,If Cortex-M7_1 enters Debug mode but you don't want the modules to enter Debug mode you must write a 1 to this field" "0: Modules also enter Debug mode when Cortex-M7_1..,1: Modules do not enter Debug mode when Cortex-M7_1.." group.long 0xA0++0x3 line.long 0x0 "CORTEX_M7_2_IP_DBG,Cortex M7_2 debug" bitfld.long 0x0 0. "CM7_2_IP_DBGDIS,If Cortex-M7_2 enters Debug mode but you don't want the modules to enter Debug mode you must write a 1 to this field" "0: Modules also enter Debug mode when Cortex-M7_2..,1: Modules do not enter Debug mode when Cortex-M7_2.." group.long 0xC0++0x3 line.long 0x0 "DAP_EN_CTRL,DAP enable control" bitfld.long 0x0 31. "CSPNIDEN,Controls SPNIDEN of debug blocks coupled with cores subsystem (ETM ITM CTIs)" "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "CSPIDEN,Controls SPIDEN of debug blocks coupled with cores subsystem (ETM ITM CTIs)" "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "CNIDEN,Controls NIDEN of debug blocks coupled with cores subsystem (ETM ITM CTIs)" "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "CDBGEN,Controls DBGEN of debug blocks coupled with cores subsystem (ETM ITM CTIs)" "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "GSPNIDEN,Controls SPNIDEN of NoC Probes/Observers. Secure privileged noninvasive debug enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "GSPIDEN,Controls SPIDEN of NoC Probes/Observers. Secure privileged invasive debug enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "GNIDEN,Controls NIDEN of NoC Probes/Observers CTIs. Noninvasive debug enable." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "GDBGEN,Controls DBGEN of AHB_AP AXI_AP CTIs and DEVICEEN of APB_AP. Invasive debug enable" "0: Disabled,1: Enabled" tree.end tree "MSCM (Miscellaneous System Control Module)" base ad:0x40198000 rgroup.long 0x0++0x1B line.long 0x0 "CPXTYPE,Processor X Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CPXNUM,Processor X Number" hexmask.long.byte 0x4 0.--7. 1. "CPN,Processor Number" line.long 0x8 "CPXREV,Processor X Revision" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CPXCFG0,Processor X Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,L1 Instruction Cache Size" hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CPXCFG1,Processor X Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CPXCFG2,Processor X Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "DTCMSZ,Tightly Coupled Data Memory Size" hexmask.long.byte 0x14 8.--15. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size" line.long 0x18 "CPXCFG3,Processor X Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0,1" bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0,1" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0,1" bitfld.long 0x18 1. "SIMD,SIMD/Neon Instruction Support" "0,1" newline bitfld.long 0x18 0. "HW_FPU,Floating Point Unit" "0,1" rgroup.long 0x20++0x1B line.long 0x0 "CP0TYPE,Processor Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP0NUM,Processor Number" hexmask.long.byte 0x4 0.--7. 1. "CPN,Processor Number" line.long 0x8 "CP0REV,Processor Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP0CFG0,Processor Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,L1 Instruction Cache Size" hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP0CFG1,Processor Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP0CFG2,Processor Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "TMLSZ,Tightly Coupled Memory Lower Size" hexmask.long.byte 0x14 8.--15. 1. "TMUSZ,Tightly Coupled Memory Upper Size" line.long 0x18 "CP0CFG3,Processor Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0,1" bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0,1" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0,1" bitfld.long 0x18 1. "SIMD,SIMD/Neon instruction support" "0,1" newline bitfld.long 0x18 0. "HW_FPU,Floating Point Unit" "0,1" rgroup.long 0x40++0x1B line.long 0x0 "CP1TYPE,Processor Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP1NUM,Processor Number" hexmask.long.byte 0x4 0.--7. 1. "CPN,Processor Number" line.long 0x8 "CP1REV,Processor Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP1CFG0,Processor Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,L1 Instruction Cache Size" hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP1CFG1,Processor Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP1CFG2,Processor Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "TMLSZ,Tightly Coupled Memory Lower Size" hexmask.long.byte 0x14 8.--15. 1. "TMUSZ,Tightly Coupled Memory Upper Size" line.long 0x18 "CP1CFG3,Processor Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0,1" bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0,1" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0,1" bitfld.long 0x18 1. "SIMD,SIMD/Neon instruction support" "0,1" newline bitfld.long 0x18 0. "HW_FPU,Floating Point Unit" "0,1" rgroup.long 0x60++0x1B line.long 0x0 "CP2TYPE,Processor Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP2NUM,Processor Number" hexmask.long.byte 0x4 0.--7. 1. "CPN,Processor Number" line.long 0x8 "CP2REV,Processor Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP2CFG0,Processor Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,L1 Instruction Cache Size" hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP2CFG1,Processor Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP2CFG2,Processor Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "TMLSZ,Tightly Coupled Memory Lower Size" hexmask.long.byte 0x14 8.--15. 1. "TMUSZ,Tightly Coupled Memory Upper Size" line.long 0x18 "CP2CFG3,Processor Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0,1" bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0,1" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0,1" bitfld.long 0x18 1. "SIMD,SIMD/Neon instruction support" "0,1" newline bitfld.long 0x18 0. "HW_FPU,Floating Point Unit" "0,1" rgroup.long 0x80++0x1B line.long 0x0 "CP3TYPE,Processor Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP3NUM,Processor Number" hexmask.long.byte 0x4 0.--7. 1. "CPN,Processor Number" line.long 0x8 "CP3REV,Processor Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP3CFG0,Processor Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,L1 Instruction Cache Size" hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP3CFG1,Processor Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP3CFG2,Processor Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "TMLSZ,Tightly Coupled Memory Lower Size" hexmask.long.byte 0x14 8.--15. 1. "TMUSZ,Tightly Coupled Memory Upper Size" line.long 0x18 "CP3CFG3,Processor Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0,1" bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0,1" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0,1" bitfld.long 0x18 1. "SIMD,SIMD/Neon instruction support" "0,1" newline bitfld.long 0x18 0. "HW_FPU,Floating Point Unit" "0,1" rgroup.long 0xA0++0x1B line.long 0x0 "CP4TYPE,Processor Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP4NUM,Processor Number" hexmask.long.byte 0x4 0.--7. 1. "CPN,Processor Number" line.long 0x8 "CP4REV,Processor Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP4CFG0,Processor Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,L1 Instruction Cache Size" hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP4CFG1,Processor Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP4CFG2,Processor Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "TMLSZ,Tightly Coupled Memory Lower Size" hexmask.long.byte 0x14 8.--15. 1. "TMUSZ,Tightly Coupled Memory Upper Size" line.long 0x18 "CP4CFG3,Processor Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0,1" bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0,1" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0,1" bitfld.long 0x18 1. "SIMD,SIMD/Neon instruction support" "0,1" newline bitfld.long 0x18 0. "HW_FPU,Floating Point Unit" "0,1" rgroup.long 0xC0++0x1B line.long 0x0 "CP5TYPE,Processor Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP5NUM,Processor Number" hexmask.long.byte 0x4 0.--7. 1. "CPN,Processor Number" line.long 0x8 "CP5REV,Processor Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP5CFG0,Processor Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,L1 Instruction Cache Size" hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP5CFG1,Processor Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP5CFG2,Processor Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "TMLSZ,Tightly Coupled Memory Lower Size" hexmask.long.byte 0x14 8.--15. 1. "TMUSZ,Tightly Coupled Memory Upper Size" line.long 0x18 "CP5CFG3,Processor Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0,1" bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0,1" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0,1" bitfld.long 0x18 1. "SIMD,SIMD/Neon instruction support" "0,1" newline bitfld.long 0x18 0. "HW_FPU,Floating Point Unit" "0,1" rgroup.long 0xE0++0x1B line.long 0x0 "CP6TYPE,Processor Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP6NUM,Processor Number" hexmask.long.byte 0x4 0.--7. 1. "CPN,Processor Number" line.long 0x8 "CP6REV,Processor Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP6CFG0,Processor Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,L1 Instruction Cache Size" hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP6CFG1,Processor Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP6CFG2,Processor Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "TMLSZ,Tightly Coupled Memory Lower Size" hexmask.long.byte 0x14 8.--15. 1. "TMUSZ,Tightly Coupled Memory Upper Size" line.long 0x18 "CP6CFG3,Processor Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0,1" bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0,1" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0,1" bitfld.long 0x18 1. "SIMD,SIMD/Neon instruction support" "0,1" newline bitfld.long 0x18 0. "HW_FPU,Floating Point Unit" "0,1" group.long 0x200++0xDF line.long 0x0 "IRCP0ISR0,Interrupt Router CP0 Interrupt0 Status" eventfld.long 0x0 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x0 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x0 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x0 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x0 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x0 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x0 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x4 "IRCP0IGR0,Interrupt Router CP0 Interrupt0 Generation" bitfld.long 0x4 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x8 "IRCP0ISR1,Interrupt Router CP0 Interrupt1 Status" eventfld.long 0x8 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x8 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x8 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x8 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x8 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x8 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x8 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0xC "IRCP0IGR1,Interrupt Router CP0 Interrupt1 Generation" bitfld.long 0xC 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x10 "IRCP0ISR2,Interrupt Router CP0 Interrupt2 Status" eventfld.long 0x10 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x10 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x10 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x10 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x10 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x10 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x10 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x14 "IRCP0IGR2,Interrupt Router CP0 Interrupt2 Generation" bitfld.long 0x14 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x18 "IRCP0ISR3,Interrupt Router CP0 Interrupt3 Status" eventfld.long 0x18 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x18 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x18 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x18 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x18 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x18 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x18 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x18 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x18 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x18 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x18 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x18 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x18 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x18 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x18 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x18 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x1C "IRCP0IGR3,Interrupt Router CPn Interruptx Generation" bitfld.long 0x1C 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x1C 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x1C 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x1C 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x1C 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x1C 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x1C 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x1C 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x1C 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x1C 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x1C 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x1C 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x1C 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x1C 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x1C 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x1C 0. "INT0_EN,Interrupt0 Enable" "0,1" line.long 0x20 "IRCP1ISR0,Interrupt Router CP1 Interrupt0 Status" eventfld.long 0x20 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x20 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x20 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x20 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x20 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x20 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x20 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x24 "IRCP1IGR0,Interrupt Router CP1 Interrupt0 Generation" bitfld.long 0x24 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x28 "IRCP1ISR1,Interrupt Router CP1 Interrupt1 Status" eventfld.long 0x28 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x28 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x28 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x28 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x28 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x28 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x28 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x2C "IRCP1IGR1,Interrupt Router CP1 Interrupt1 Generation" bitfld.long 0x2C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x30 "IRCP1ISR2,Interrupt Router CP1 Interrupt2 Status" eventfld.long 0x30 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x30 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x30 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x30 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x30 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x30 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x30 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x34 "IRCP1IGR2,Interrupt Router CP1 Interrupt2 Generation" bitfld.long 0x34 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x38 "IRCP1ISR3,Interrupt Router CP1 Interrupt3 Status" eventfld.long 0x38 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x38 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x38 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x38 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x38 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x38 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x38 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x38 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x38 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x38 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x38 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x38 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x38 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x38 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x38 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x38 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x3C "IRCP1IGR3,Interrupt Router CPn Interruptx Generation" bitfld.long 0x3C 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x3C 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x3C 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x3C 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x3C 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x3C 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x3C 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x3C 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x3C 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x3C 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x3C 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x3C 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x3C 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x3C 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x3C 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x3C 0. "INT0_EN,Interrupt0 Enable" "0,1" line.long 0x40 "IRCP2ISR0,Interrupt Router CP2 Interrupt0 Status" eventfld.long 0x40 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x40 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x40 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x40 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x40 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x40 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x40 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x44 "IRCP2IGR0,Interrupt Router CP2 Interrupt0 Generation" bitfld.long 0x44 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x48 "IRCP2ISR1,Interrupt Router CP2 Interrupt1 Status" eventfld.long 0x48 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x48 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x48 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x48 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x48 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x48 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x48 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x4C "IRCP2IGR1,Interrupt Router CP2 Interrupt1 Generation" bitfld.long 0x4C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x50 "IRCP2ISR2,Interrupt Router CP2 Interrupt2 Status" eventfld.long 0x50 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x50 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x50 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x50 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x50 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x50 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x50 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x54 "IRCP2IGR2,Interrupt Router CP2 Interrupt2 Generation" bitfld.long 0x54 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x58 "IRCP2ISR3,Interrupt Router CP2 Interrupt3 Status" eventfld.long 0x58 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x58 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x58 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x58 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x58 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x58 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x58 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x58 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x58 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x58 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x58 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x58 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x58 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x58 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x58 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x58 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x5C "IRCP2IGR3,Interrupt Router CPn Interruptx Generation" bitfld.long 0x5C 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x5C 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x5C 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x5C 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x5C 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x5C 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x5C 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x5C 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x5C 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x5C 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x5C 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x5C 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x5C 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x5C 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x5C 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x5C 0. "INT0_EN,Interrupt0 Enable" "0,1" line.long 0x60 "IRCP3ISR0,Interrupt Router CP3 Interrupt0 Status" eventfld.long 0x60 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x60 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x60 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x60 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x60 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x60 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x60 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x64 "IRCP3IGR0,Interrupt Router CP3 Interrupt0 Generation" bitfld.long 0x64 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x68 "IRCP3ISR1,Interrupt Router CP3 Interrupt1 Status" eventfld.long 0x68 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x68 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x68 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x68 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x68 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x68 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x68 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x6C "IRCP3IGR1,Interrupt Router CP3 Interrupt1 Generation" bitfld.long 0x6C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x70 "IRCP3ISR2,Interrupt Router CP3 Interrupt2 Status" eventfld.long 0x70 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x70 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x70 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x70 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x70 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x70 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x70 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x74 "IRCP3IGR2,Interrupt Router CP3 Interrupt2 Generation" bitfld.long 0x74 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x78 "IRCP3ISR3,Interrupt Router CP3 Interrupt3 Status" eventfld.long 0x78 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x78 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x78 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x78 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x78 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x78 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x78 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x78 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x78 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x78 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x78 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x78 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x78 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x78 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x78 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x78 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x7C "IRCP3IGR3,Interrupt Router CPn Interruptx Generation" bitfld.long 0x7C 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x7C 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x7C 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x7C 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x7C 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x7C 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x7C 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x7C 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x7C 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x7C 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x7C 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x7C 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x7C 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x7C 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x7C 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x7C 0. "INT0_EN,Interrupt0 Enable" "0,1" line.long 0x80 "IRCP4ISR0,Interrupt Router CP4 Interrupt0 Status" eventfld.long 0x80 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x80 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x80 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x80 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x80 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x80 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x80 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x84 "IRCP4IGR0,Interrupt Router CP4 Interrupt0 Generation" bitfld.long 0x84 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x88 "IRCP4ISR1,Interrupt Router CP4 Interrupt1 Status" eventfld.long 0x88 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x88 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x88 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x88 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x88 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x88 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x88 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x8C "IRCP4IGR1,Interrupt Router CP4 Interrupt1 Generation" bitfld.long 0x8C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x90 "IRCP4ISR2,Interrupt Router CP4 Interrupt2 Status" eventfld.long 0x90 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0x90 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0x90 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0x90 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0x90 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0x90 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0x90 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0x94 "IRCP4IGR2,Interrupt Router CP4 Interrupt2 Generation" bitfld.long 0x94 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x98 "IRCP4ISR3,Interrupt Router CP4 Interrupt3 Status" eventfld.long 0x98 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x98 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x98 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x98 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x98 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x98 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x98 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x98 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x98 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x98 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x98 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x98 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x98 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x98 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x98 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x98 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x9C "IRCP4IGR3,Interrupt Router CPn Interruptx Generation" bitfld.long 0x9C 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x9C 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x9C 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x9C 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x9C 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x9C 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x9C 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x9C 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x9C 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x9C 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x9C 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x9C 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x9C 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x9C 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x9C 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x9C 0. "INT0_EN,Interrupt0 Enable" "0,1" line.long 0xA0 "IRCP5ISR0,Interrupt Router CP5 Interrupt0 Status" eventfld.long 0xA0 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0xA0 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0xA0 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0xA0 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0xA0 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0xA0 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0xA0 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0xA4 "IRCP5IGR0,Interrupt Router CP5 Interrupt0 Generation" bitfld.long 0xA4 0. "INT_EN,Interrupt Enable" "0,1" line.long 0xA8 "IRCP5ISR1,Interrupt Router CP5 Interrupt1 Status" eventfld.long 0xA8 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0xA8 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0xA8 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0xA8 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0xA8 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0xA8 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0xA8 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0xAC "IRCP5IGR1,Interrupt Router CP5 Interrupt1 Generation" bitfld.long 0xAC 0. "INT_EN,Interrupt Enable" "0,1" line.long 0xB0 "IRCP5ISR2,Interrupt Router CP5 Interrupt2 Status" eventfld.long 0xB0 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0xB0 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0xB0 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0xB0 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0xB0 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0xB0 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0xB0 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0xB4 "IRCP5IGR2,Interrupt Router CP5 Interrupt2 Generation" bitfld.long 0xB4 0. "INT_EN,Interrupt Enable" "0,1" line.long 0xB8 "IRCP5ISR3,Interrupt Router CP5 Interrupt3 Status" eventfld.long 0xB8 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0xB8 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0xB8 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0xB8 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0xB8 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0xB8 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0xB8 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0xB8 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0xB8 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0xB8 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0xB8 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0xB8 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0xB8 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0xB8 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0xB8 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0xB8 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0xBC "IRCP5IGR3,Interrupt Router CPn Interruptx Generation" bitfld.long 0xBC 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0xBC 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0xBC 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0xBC 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0xBC 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0xBC 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0xBC 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0xBC 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0xBC 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0xBC 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0xBC 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0xBC 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0xBC 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0xBC 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0xBC 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0xBC 0. "INT0_EN,Interrupt0 Enable" "0,1" line.long 0xC0 "IRCP6ISR0,Interrupt Router CP6 Interrupt0 Status" eventfld.long 0xC0 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0xC0 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0xC0 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0xC0 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0xC0 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0xC0 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0xC0 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0xC4 "IRCP6IGR0,Interrupt Router CP6 Interrupt0 Generation" bitfld.long 0xC4 0. "INT_EN,Interrupt Enable" "0,1" line.long 0xC8 "IRCP6ISR1,Interrupt Router CP6 Interrupt1 Status" eventfld.long 0xC8 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0xC8 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0xC8 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0xC8 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0xC8 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0xC8 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0xC8 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0xCC "IRCP6IGR1,Interrupt Router CP6 Interrupt1 Generation" bitfld.long 0xCC 0. "INT_EN,Interrupt Enable" "0,1" line.long 0xD0 "IRCP6ISR2,Interrupt Router CP6 Interrupt2 Status" eventfld.long 0xD0 6. "CP6_INT,CP6-to-CPn Interrupt" "0: CP6 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP6 is asserted." eventfld.long 0xD0 5. "CP5_INT,CP5-to-CPn Interrupt" "0: CP5 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP5 is asserted." newline eventfld.long 0xD0 4. "CP4_INT,PCIe_1 Interrupt" "0: Not asserted,1: Asserted" eventfld.long 0xD0 3. "CP3_INT,PCIe_0 Interrupt" "0: Not asserted,1: Asserted" newline eventfld.long 0xD0 2. "CP2_INT,CP2-to-CPn Interrupt" "0: CP2 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP2 is asserted." eventfld.long 0xD0 1. "CP1_INT,CP1-to-CPn Interrupt" "0: CP1 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP1 is asserted." newline eventfld.long 0xD0 0. "CP0_INT,CP0-to-CPn Interrupt" "0: CP0 does not assert any interrupt to CPn.,1: Interrupt to CPn initiated by CP0 is asserted." line.long 0xD4 "IRCP6IGR2,Interrupt Router CP6 Interrupt2 Generation" bitfld.long 0xD4 0. "INT_EN,Interrupt Enable" "0,1" line.long 0xD8 "IRCP6ISR3,Interrupt Router CP6 Interrupt3 Status" eventfld.long 0xD8 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0xD8 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0xD8 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0xD8 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0xD8 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0xD8 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0xD8 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0xD8 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0xD8 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0xD8 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0xD8 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0xD8 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0xD8 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0xD8 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0xD8 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0xD8 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0xDC "IRCP6IGR3,Interrupt Router CPn Interruptx Generation" bitfld.long 0xDC 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0xDC 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0xDC 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0xDC 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0xDC 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0xDC 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0xDC 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0xDC 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0xDC 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0xDC 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0xDC 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0xDC 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0xDC 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0xDC 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0xDC 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0xDC 0. "INT0_EN,Interrupt0 Enable" "0,1" group.long 0x318++0x7 line.long 0x0 "IRCP0ISR4,Interrupt Router CP0 Interrupt4 Status" eventfld.long 0x0 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x0 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x0 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x0 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x0 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x0 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x0 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x0 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x0 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x4 "IRCP0IGR4,Interrupt Router CPn Interruptx Generation" bitfld.long 0x4 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x4 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x4 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x4 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x4 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x4 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x4 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x4 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x4 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x4 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x4 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x4 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x4 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x4 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x4 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x4 0. "INT0_EN,Interrupt0 Enable" "0,1" group.long 0x338++0x7 line.long 0x0 "IRCP1ISR4,Interrupt Router CP1 Interrupt4 Status" eventfld.long 0x0 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x0 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x0 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x0 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x0 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x0 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x0 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x0 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x0 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x4 "IRCP1IGR4,Interrupt Router CPn Interruptx Generation" bitfld.long 0x4 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x4 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x4 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x4 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x4 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x4 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x4 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x4 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x4 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x4 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x4 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x4 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x4 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x4 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x4 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x4 0. "INT0_EN,Interrupt0 Enable" "0,1" group.long 0x358++0x7 line.long 0x0 "IRCP2ISR4,Interrupt Router CP2 Interrupt4 Status" eventfld.long 0x0 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x0 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x0 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x0 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x0 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x0 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x0 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x0 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x0 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x4 "IRCP2IGR4,Interrupt Router CPn Interruptx Generation" bitfld.long 0x4 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x4 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x4 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x4 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x4 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x4 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x4 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x4 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x4 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x4 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x4 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x4 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x4 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x4 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x4 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x4 0. "INT0_EN,Interrupt0 Enable" "0,1" group.long 0x378++0x7 line.long 0x0 "IRCP3ISR4,Interrupt Router CP3 Interrupt4 Status" eventfld.long 0x0 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x0 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x0 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x0 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x0 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x0 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x0 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x0 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x0 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x4 "IRCP3IGR4,Interrupt Router CPn Interruptx Generation" bitfld.long 0x4 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x4 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x4 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x4 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x4 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x4 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x4 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x4 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x4 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x4 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x4 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x4 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x4 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x4 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x4 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x4 0. "INT0_EN,Interrupt0 Enable" "0,1" group.long 0x398++0x7 line.long 0x0 "IRCP4ISR4,Interrupt Router CP4 Interrupt4 Status" eventfld.long 0x0 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x0 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x0 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x0 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x0 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x0 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x0 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x0 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x0 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x4 "IRCP4IGR4,Interrupt Router CPn Interruptx Generation" bitfld.long 0x4 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x4 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x4 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x4 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x4 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x4 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x4 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x4 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x4 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x4 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x4 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x4 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x4 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x4 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x4 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x4 0. "INT0_EN,Interrupt0 Enable" "0,1" group.long 0x3B8++0x7 line.long 0x0 "IRCP5ISR4,Interrupt Router CP5 Interrupt4 Status" eventfld.long 0x0 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x0 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x0 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x0 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x0 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x0 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x0 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x0 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x0 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x4 "IRCP5IGR4,Interrupt Router CPn Interruptx Generation" bitfld.long 0x4 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x4 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x4 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x4 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x4 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x4 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x4 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x4 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x4 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x4 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x4 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x4 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x4 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x4 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x4 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x4 0. "INT0_EN,Interrupt0 Enable" "0,1" group.long 0x3D8++0x7 line.long 0x0 "IRCP6ISR4,Interrupt Router CP6 Interrupt4 Status" eventfld.long 0x0 15. "PCIE_INT15,PCIe-to-CPn Interrupt15" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt15 to CPn initiated by PCIe is asserted." eventfld.long 0x0 14. "PCIE_INT14,PCIe-to-CPn Interrupt14" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt14 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 13. "PCIE_INT13,PCIe-to-CPn Interrupt13" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt13 to CPn initiated by PCIe is asserted." eventfld.long 0x0 12. "PCIE_INT12,PCIe-to-CPn Interrupt12" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt12 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 11. "PCIE_INT11,PCIe-to-CPn Interrupt11" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt11 to CPn initiated by PCIe is asserted." eventfld.long 0x0 10. "PCIE_INT10,PCIe-to-CPn Interrupt10" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt10 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 9. "PCIE_INT9,PCIe-to-CPn Interrupt9" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt9 to CPn initiated by PCIe is asserted." eventfld.long 0x0 8. "PCIE_INT8,PCIe-to-CPn Interrupt8" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt8 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 7. "PCIE_INT7,PCIe-to-CPn Interrupt7" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt7 to CPn initiated by PCIe is asserted." eventfld.long 0x0 6. "PCIE_INT6,PCIe-to-CPn Interrupt6" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt6 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 5. "PCIE_INT5,PCIe-to-CPn Interrupt5" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt5 to CPn initiated by PCIe is asserted." eventfld.long 0x0 4. "PCIE_INT4,PCIe-to-CPn Interrupt4" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt4 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 3. "PCIE_INT3,PCIe-to-CPn Interrupt3" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt3 to CPn initiated by PCIe is asserted." eventfld.long 0x0 2. "PCIE_INT2,PCIe-to-CPn Interrupt2" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt2 to CPn initiated by PCIe is asserted." newline eventfld.long 0x0 1. "PCIE_INT1,PCIe-to-CPn Interrupt1" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt1 to CPn initiated by PCIe is asserted." eventfld.long 0x0 0. "PCIE_INT0,PCIe-to-CPn Interrupt0" "0: PCIe does not assert any interrupt to CPn.,1: Interrupt0 to CPn initiated by PCIe is asserted." line.long 0x4 "IRCP6IGR4,Interrupt Router CPn Interruptx Generation" bitfld.long 0x4 15. "INT15_EN,Interrupt15 Enable" "0,1" bitfld.long 0x4 14. "INT14_EN,Interrupt14 Enable" "0,1" newline bitfld.long 0x4 13. "INT13_EN,Interrupt13 Enable" "0,1" bitfld.long 0x4 12. "INT12_EN,Interrupt12 Enable" "0,1" newline bitfld.long 0x4 11. "INT11_EN,Interrupt11 Enable" "0,1" bitfld.long 0x4 10. "INT10_EN,Interrupt10 Enable" "0,1" newline bitfld.long 0x4 9. "INT9_EN,Interrupt9 Enable" "0,1" bitfld.long 0x4 8. "INT8_EN,Interrupt8 Enable" "0,1" newline bitfld.long 0x4 7. "INT7_EN,Interrupt7 Enable" "0,1" bitfld.long 0x4 6. "INT6_EN,Interrupt6 Enable" "0,1" newline bitfld.long 0x4 5. "INT5_EN,Interrupt5 Enable" "0,1" bitfld.long 0x4 4. "INT4_EN,Interrupt4 Enable" "0,1" newline bitfld.long 0x4 3. "INT3_EN,Interrupt3 Enable" "0,1" bitfld.long 0x4 2. "INT2_EN,Interrupt2 Enable" "0,1" newline bitfld.long 0x4 1. "INT1_EN,Interrupt1 Enable" "0,1" bitfld.long 0x4 0. "INT0_EN,Interrupt0 Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "IRCPCFG,Interrupt Router Configuration" bitfld.long 0x0 31. "LOCK,Provides a locking mechanism that can be used to limit the ability to write to the register" "0: Register can be written to by any privileged..,1: Register is locked (read-only) until the next.." bitfld.long 0x0 6. "CP6_TR,Indicates whether CP6 is a trusted core with access to read the full contents of the IRCPnISRx register" "0: Not trusted,1: Trusted" newline bitfld.long 0x0 5. "CP5_TR,Indicates whether CP5 is a trusted core with access to read the full contents of the IRCPnISRx register" "0: Not trusted,1: Trusted" bitfld.long 0x0 4. "CP4_TR,Indicates whether CP4 is a trusted core with access to read the full contents of the IRCPnISRx register" "0: Not trusted,1: Trusted" newline bitfld.long 0x0 3. "CP3_TR,Indicates whether CP3 is a trusted core with access to read the full contents of the IRCPnISRx register" "0: Not trusted,1: Trusted" bitfld.long 0x0 2. "CP2_TR,Indicates whether CP2 is a trusted core with access to read the full contents of the IRCPnISRx register" "0: Not trusted,1: Trusted" newline bitfld.long 0x0 1. "CP1_TR,Indicates whether CP1 is a trusted core with access to read the full contents of the IRCPnISRx register" "0: Not trusted,1: Trusted" bitfld.long 0x0 0. "CP0_TR,Indicates whether CP0 is a trusted core with access to read the full contents of the IRCPnISRx register" "0: Not trusted,1: Trusted" group.long 0x800++0x3 line.long 0x0 "IRNMIC,Interrupt Router Nonmaskable Interrupt Control" bitfld.long 0x0 6. "CP6_NMI_EN,Enables CP6 NMI interrupt steering to Cortex-M7 core 2 NMI." "0: Disabled,1: Enabled" bitfld.long 0x0 5. "CP5_NMI_EN,Enables CP5 NMI interrupt steering to Cortex-M7 core 1 NMI." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "CP4_NMI_EN,Enables CP4 NMI interrupt steering to Cortex-M7 core 0 NMI." "0: Disabled,1: Enabled" bitfld.long 0x0 3. "CP3_NMI_EN,Enables CP3 NMI interrupt steering to Cortex-A53 cluster 1 core 1 nSEI." "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "CP2_NMI_EN,Enables CP2 NMI interrupt steering to Cortex-A53 cluster 1 core 0 nSEI." "0: Disabled,1: Enabled" bitfld.long 0x0 1. "CP1_NMI_EN,Enables CP1 NMI interrupt steering to Cortex-A53 cluster 0 core 1 nSEI." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "CP0_NMI_EN,Enables CP0 NMI interrupt steering to Cortex-A53 cluster 0 core 0 nSEI." "0: Disabled,1: Enabled" repeat 240. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x880)++0x1 line.word 0x0 "IRSPRC[$1],Interrupt Router Shared Peripheral Routing Control" bitfld.word 0x0 15. "LOCK,Lock Interrupt Request" "0: Writes to IRSPRCn are allowed.,1: Writes to IRSPRCn are ignored." bitfld.word 0x0 3. "M7_2,Enable Cortex-M7_2 Interrupt Steering" "0,1" newline bitfld.word 0x0 2. "M7_1,Enable Cortex-M7_1 Interrupt Steering" "0,1" bitfld.word 0x0 1. "M7_0,Enable Cortex-M7_0 Interrupt Steering" "0,1" newline bitfld.word 0x0 0. "GIC500,Enable GIC500 Interrupt Steering" "0,1" repeat.end tree.end tree "MU (Messaging Unit)" base ad:0x0 tree "MU0__MUA" base ad:0x23258000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter Register" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status Register" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending" "0: Processor B did not issue MU reset.,1: Processor B issued MU reset." newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state.,1: MUA or MUB is in reset state." line.long 0x8 "CCR0,Core Control Register 0" bitfld.long 0x8 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status Register 0" eventfld.long 0x0 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control Register" bitfld.long 0x0 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status Register" bitfld.long 0x0 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-purpose Interrupt Enable Register" bitfld.long 0x0 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-purpose Control Register" bitfld.long 0x4 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status Register" eventfld.long 0x8 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control Register" bitfld.long 0x0 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status Register" bitfld.long 0x0 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control Register" bitfld.long 0x0 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status Register" bitfld.long 0x0 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit Register" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive Register" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU0__MUB" base ad:0x40210000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter Register" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status Register" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending" "0: Processor B did not issue MU reset.,1: Processor B issued MU reset." newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state.,1: MUA or MUB is in reset state." line.long 0x8 "CCR0,Core Control Register 0" bitfld.long 0x8 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status Register 0" eventfld.long 0x0 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control Register" bitfld.long 0x0 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status Register" bitfld.long 0x0 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-purpose Interrupt Enable Register" bitfld.long 0x0 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-purpose Control Register" bitfld.long 0x4 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status Register" eventfld.long 0x8 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control Register" bitfld.long 0x0 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status Register" bitfld.long 0x0 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control Register" bitfld.long 0x0 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status Register" bitfld.long 0x0 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit Register" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive Register" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU1__MUA" base ad:0x23259000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter Register" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status Register" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending" "0: Processor B did not issue MU reset.,1: Processor B issued MU reset." newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state.,1: MUA or MUB is in reset state." line.long 0x8 "CCR0,Core Control Register 0" bitfld.long 0x8 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status Register 0" eventfld.long 0x0 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control Register" bitfld.long 0x0 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status Register" bitfld.long 0x0 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-purpose Interrupt Enable Register" bitfld.long 0x0 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-purpose Control Register" bitfld.long 0x4 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status Register" eventfld.long 0x8 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control Register" bitfld.long 0x0 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status Register" bitfld.long 0x0 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control Register" bitfld.long 0x0 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status Register" bitfld.long 0x0 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit Register" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive Register" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU1__MUB" base ad:0x40211000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter Register" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status Register" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending" "0: Processor B did not issue MU reset.,1: Processor B issued MU reset." newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state.,1: MUA or MUB is in reset state." line.long 0x8 "CCR0,Core Control Register 0" bitfld.long 0x8 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status Register 0" eventfld.long 0x0 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control Register" bitfld.long 0x0 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status Register" bitfld.long 0x0 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-purpose Interrupt Enable Register" bitfld.long 0x0 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-purpose Control Register" bitfld.long 0x4 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status Register" eventfld.long 0x8 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control Register" bitfld.long 0x0 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status Register" bitfld.long 0x0 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control Register" bitfld.long 0x0 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status Register" bitfld.long 0x0 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit Register" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive Register" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU2__MUA" base ad:0x2325A000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter Register" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status Register" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending" "0: Processor B did not issue MU reset.,1: Processor B issued MU reset." newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state.,1: MUA or MUB is in reset state." line.long 0x8 "CCR0,Core Control Register 0" bitfld.long 0x8 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status Register 0" eventfld.long 0x0 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control Register" bitfld.long 0x0 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status Register" bitfld.long 0x0 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-purpose Interrupt Enable Register" bitfld.long 0x0 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-purpose Control Register" bitfld.long 0x4 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status Register" eventfld.long 0x8 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control Register" bitfld.long 0x0 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status Register" bitfld.long 0x0 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control Register" bitfld.long 0x0 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status Register" bitfld.long 0x0 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit Register" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive Register" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU2__MUB" base ad:0x40212000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter Register" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status Register" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending" "0: Processor B did not issue MU reset.,1: Processor B issued MU reset." newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state.,1: MUA or MUB is in reset state." line.long 0x8 "CCR0,Core Control Register 0" bitfld.long 0x8 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status Register 0" eventfld.long 0x0 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control Register" bitfld.long 0x0 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status Register" bitfld.long 0x0 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-purpose Interrupt Enable Register" bitfld.long 0x0 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-purpose Control Register" bitfld.long 0x4 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status Register" eventfld.long 0x8 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control Register" bitfld.long 0x0 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status Register" bitfld.long 0x0 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control Register" bitfld.long 0x0 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status Register" bitfld.long 0x0 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit Register" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive Register" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU3__MUA" base ad:0x2325B000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter Register" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status Register" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending" "0: Processor B did not issue MU reset.,1: Processor B issued MU reset." newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state.,1: MUA or MUB is in reset state." line.long 0x8 "CCR0,Core Control Register 0" bitfld.long 0x8 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status Register 0" eventfld.long 0x0 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control Register" bitfld.long 0x0 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status Register" bitfld.long 0x0 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-purpose Interrupt Enable Register" bitfld.long 0x0 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-purpose Control Register" bitfld.long 0x4 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status Register" eventfld.long 0x8 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control Register" bitfld.long 0x0 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status Register" bitfld.long 0x0 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control Register" bitfld.long 0x0 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status Register" bitfld.long 0x0 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit Register" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive Register" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU3__MUB" base ad:0x40213000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter Register" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control Register" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status Register" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending" "0: Processor B did not issue MU reset.,1: Processor B issued MU reset." newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state.,1: MUA or MUB is in reset state." line.long 0x8 "CCR0,Core Control Register 0" bitfld.long 0x8 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status Register 0" eventfld.long 0x0 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control Register" bitfld.long 0x0 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status Register" bitfld.long 0x0 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-purpose Interrupt Enable Register" bitfld.long 0x0 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-purpose Control Register" bitfld.long 0x4 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status Register" eventfld.long 0x8 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control Register" bitfld.long 0x0 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status Register" bitfld.long 0x0 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control Register" bitfld.long 0x0 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status Register" bitfld.long 0x0 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB TRn.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit Register" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive Register" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree.end tree "NCBU (Non-coherent Bridge Unit)" base ad:0x0 tree "NCBU0" base ad:0x50460000 group.long 0x0++0x3 line.long 0x0 "NCBUTC,NCBU Transaction Control" bitfld.long 0x0 0. "TRANSEN,Agent Transaction Enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "NCBUTA,NCBU Transaction Activity" bitfld.long 0x0 2. "COHACTV,Coherent Transaction Active" "0,1" bitfld.long 0x0 1. "SNPACTV,Snoop Transaction Active" "0,1" bitfld.long 0x0 0. "TRANSACTV,Transaction Active" "0,1" group.long 0x100++0xF line.long 0x0 "NCBUCEC,NCBU Correctable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Correctable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Correctable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Correctable Error Detection Enable" "0: Disable correctable error detection and logging..,1: Enable correctable error detection and logging.." line.long 0x4 "NCBUCES,NCBU Correctable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "NCBUCELR0,NCBU Correctable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry (or Set)" line.long 0xC "NCBUCELR1,NCBU Correctable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x124++0x3 line.long 0x0 "NCBUCESA,NCBU Correctable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" group.long 0x140++0xF line.long 0x0 "NCBUUEC,NCBU Uncorrectable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Uncorrectable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Uncorrectable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Uncorrectable Error Detection Enable" "0: Disable uncorrectable error detection and..,1: Enable uncorrectable error detection and logging.." line.long 0x4 "NCBUUES,NCBU Uncorrectable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "NCBUUELR0,NCBU Uncorrectable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry (or Set)" line.long 0xC "NCBUUELR1,NCBU Uncorrectable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x164++0x3 line.long 0x0 "NCBUUESA,NCBU Uncorrectable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "NCBUID,NCBU Identification Register" hexmask.long.byte 0x0 20.--24. 1. "SFID,Snoop Filter Identifier" hexmask.long.byte 0x0 16.--19. 1. "TYPE,Type" bitfld.long 0x0 15. "CA,Caching Agent" "0,1" hexmask.long.byte 0x0 8.--14. 1. "NCBID,Non-Coherent Bridge Identifier" newline hexmask.long.byte 0x0 0.--7. 1. "IMPLVER,Implementation Version" tree.end tree "NCBU1" base ad:0x50461000 group.long 0x0++0x3 line.long 0x0 "NCBUTC,NCBU Transaction Control" bitfld.long 0x0 0. "TRANSEN,Agent Transaction Enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "NCBUTA,NCBU Transaction Activity" bitfld.long 0x0 2. "COHACTV,Coherent Transaction Active" "0,1" bitfld.long 0x0 1. "SNPACTV,Snoop Transaction Active" "0,1" bitfld.long 0x0 0. "TRANSACTV,Transaction Active" "0,1" group.long 0x100++0xF line.long 0x0 "NCBUCEC,NCBU Correctable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Correctable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Correctable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Correctable Error Detection Enable" "0: Disable correctable error detection and logging..,1: Enable correctable error detection and logging.." line.long 0x4 "NCBUCES,NCBU Correctable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "NCBUCELR0,NCBU Correctable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry (or Set)" line.long 0xC "NCBUCELR1,NCBU Correctable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x124++0x3 line.long 0x0 "NCBUCESA,NCBU Correctable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" group.long 0x140++0xF line.long 0x0 "NCBUUEC,NCBU Uncorrectable Error Control" hexmask.long.byte 0x0 4.--11. 1. "ERRTHRESHOLD,Uncorrectable Error Threshold" bitfld.long 0x0 1. "ERRINTEN,Uncorrectable Error Interrupt Enable" "0: Disable assertion,1: Enable assertion" bitfld.long 0x0 0. "ERRDETEN,Uncorrectable Error Detection Enable" "0: Disable uncorrectable error detection and..,1: Enable uncorrectable error detection and logging.." line.long 0x4 "NCBUUES,NCBU Uncorrectable Error Status" hexmask.long.byte 0x4 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x4 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x4 4.--11. 1. "ERRCOUNT,Error Count" eventfld.long 0x4 1. "ERROVF,Error Overflow" "0,1" newline eventfld.long 0x4 0. "ERRVLD,Error Valid" "0,1" line.long 0x8 "NCBUUELR0,NCBU Uncorrectable Error Location Register 0" hexmask.long.byte 0x8 26.--31. 1. "ERRWORD,Error Word" hexmask.long.byte 0x8 20.--25. 1. "ERRWAY,Error Way" hexmask.long.tbyte 0x8 0.--19. 1. "ERRENTRY,Error Entry (or Set)" line.long 0xC "NCBUUELR1,NCBU Uncorrectable Error Location Register 1" hexmask.long.word 0xC 0.--11. 1. "ERRADDR,Error Address" group.long 0x164++0x3 line.long 0x0 "NCBUUESA,NCBU Uncorrectable Error Status Alias" hexmask.long.byte 0x0 16.--23. 1. "ERRINFO,Error Info" hexmask.long.byte 0x0 12.--15. 1. "ERRTYPE,Error Type" hexmask.long.byte 0x0 4.--11. 1. "ERRCOUNT,Error Count" bitfld.long 0x0 1. "ERROVF,Error Overflow" "0,1" newline bitfld.long 0x0 0. "ERRVLD,Error Valid" "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "NCBUID,NCBU Identification Register" hexmask.long.byte 0x0 20.--24. 1. "SFID,Snoop Filter Identifier" hexmask.long.byte 0x0 16.--19. 1. "TYPE,Type" bitfld.long 0x0 15. "CA,Caching Agent" "0,1" hexmask.long.byte 0x0 8.--14. 1. "NCBID,Non-Coherent Bridge Identifier" newline hexmask.long.byte 0x0 0.--7. 1. "IMPLVER,Implementation Version" tree.end tree.end tree "OCOTP (On-Chip One Time Programmable)" base ad:0x400A4000 group.long 0x0++0xB line.long 0x0 "CTRL_SYS,System master's control" hexmask.long.word 0x0 16.--31. 1. "AUTH_KEY,Key to unlock read and write operation" hexmask.long.byte 0x0 2.--5. 1. "RD_WR,eFuse read and write control for the system master" newline bitfld.long 0x0 1. "CRC_TEST,CRC (Polynomial CRC-32/MPEG-2) test for system master" "?,1: CRC test enable for eFuses" line.long 0x4 "ADDR_SYS,System master's eFuse address for read or write operation" hexmask.long.word 0x4 0.--15. 1. "ADDR,eFuse read or write address" line.long 0x8 "WRDATA_SYS,System master's eFuse write data" hexmask.long 0x8 0.--31. 1. "DATA,eFuse data for eFuse write operation" rgroup.long 0xC++0x3 line.long 0x0 "RDATA_SYS,System master's eFuse read data" hexmask.long 0x0 0.--31. 1. "DATA,Read data" group.long 0x30++0xB line.long 0x0 "CTRL_FBX,FBXC control" eventfld.long 0x0 18. "IPG_STOP_ACK,Low-power mode acknowledgment" "0,1" bitfld.long 0x0 17. "IPG_STOP,Low Power entry" "0,1" newline bitfld.long 0x0 16. "FBX_PD,Fusebox Power Down" "?,1: Enable fusebox power-down mode" bitfld.long 0x0 8. "SEC_MODE,Indicates that the FBXC is in Secure mode." "?,1: FBXC is in secure mode" line.long 0x4 "CRC_RGN_SYS,eFuse region for CRC validation" hexmask.long.word 0x4 16.--31. 1. "END_ADDR,End eFuse address for CRC calculation" hexmask.long.word 0x4 0.--15. 1. "START_ADDR,Start eFuse address for CRC calculation" line.long 0x8 "CRC_ADDR_SYS,Pre-calculated CRC eFuse address for comparison" hexmask.long.word 0x8 0.--15. 1. "ADDR,CRC eFuse address used for comparison in CRC test" rgroup.long 0x3C++0x3 line.long 0x0 "CRC_VALUE_SYS,CRC calculated from the eFuses" hexmask.long 0x0 0.--31. 1. "CRC,CRC value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "GPR[$1],General purpose" hexmask.long 0x0 0.--31. 1. "GPR,General-purpose field that you can use to store information for your application" repeat.end group.long 0x50++0x3 line.long 0x0 "STATUS_SYS,System master's access status" eventfld.long 0x0 2. "ERROR,Error status flag" "0,1" eventfld.long 0x0 1. "CRC_FAIL,CRC compare status" "0,1" newline rbitfld.long 0x0 0. "BUSY,OCOTP busy indication" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "VERSION,OCOTP design version" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,The major part of the design version" hexmask.long.byte 0x0 16.--23. 1. "MINOR,The minor part of the design version" newline hexmask.long.word 0x0 0.--15. 1. "STEP,The step part of the design version" rgroup.long 0x70++0xF line.long 0x0 "SEC0,ECC status for single-bit ECC error" bitfld.long 0x0 31. "SEC32,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 30. "SEC31,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 29. "SEC30,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 28. "SEC29,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 27. "SEC28,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 26. "SEC27,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 25. "SEC26,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 24. "SEC25,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 23. "SEC24,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 22. "SEC23,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 21. "SEC22,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 20. "SEC21,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 19. "SEC20,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 18. "SEC19,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 17. "SEC18,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 16. "SEC17,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 15. "SEC16,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 14. "SEC15,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 13. "SEC14,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 12. "SEC13,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 11. "SEC12,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 10. "SEC11,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 9. "SEC10,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 8. "SEC9,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 7. "SEC8,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 6. "SEC7,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 5. "SEC6,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 4. "SEC5,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 3. "SEC4,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 2. "SEC3,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x0 1. "SEC2,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x0 0. "SEC1,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" line.long 0x4 "SEC1,ECC status for single-bit ECC error" bitfld.long 0x4 31. "SEC64,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 30. "SEC63,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 29. "SEC62,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 28. "SEC61,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 27. "SEC60,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 26. "SEC59,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 25. "SEC58,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 24. "SEC57,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 23. "SEC56,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 22. "SEC55,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 21. "SEC54,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 20. "SEC53,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 19. "SEC52,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 18. "SEC51,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 17. "SEC50,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 16. "SEC49,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 15. "SEC48,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 14. "SEC47,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 13. "SEC46,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 12. "SEC45,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 11. "SEC44,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 10. "SEC43,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 9. "SEC42,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 8. "SEC41,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 7. "SEC40,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 6. "SEC39,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 5. "SEC38,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 4. "SEC37,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 3. "SEC36,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 2. "SEC35,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x4 1. "SEC34,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x4 0. "SEC33,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" line.long 0x8 "SEC2,ECC status for single-bit ECC error" bitfld.long 0x8 31. "SEC96,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 30. "SEC95,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 29. "SEC94,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 28. "SEC93,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 27. "SEC92,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 26. "SEC91,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 25. "SEC90,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 24. "SEC89,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 23. "SEC88,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 22. "SEC87,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 21. "SEC86,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 20. "SEC85,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 19. "SEC84,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 18. "SEC83,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 17. "SEC82,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 16. "SEC81,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 15. "SEC80,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 14. "SEC79,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 13. "SEC78,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 12. "SEC77,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 11. "SEC76,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 10. "SEC75,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 9. "SEC74,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 8. "SEC73,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 7. "SEC72,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 6. "SEC71,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 5. "SEC70,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 4. "SEC69,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 3. "SEC68,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 2. "SEC67,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" newline bitfld.long 0x8 1. "SEC66,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" bitfld.long 0x8 0. "SEC65,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected" line.long 0xC "SEC3,ECC status for single-bit ECC error" rgroup.long 0xB0++0xF line.long 0x0 "DED0,ECC status for double-bit ECC error" bitfld.long 0x0 31. "DED32,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 30. "DED31,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 29. "DED30,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 28. "DED29,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 27. "DED28,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 26. "DED27,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 25. "DED26,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 24. "DED25,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 23. "DED24,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 22. "DED23,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 21. "DED22,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 20. "DED21,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 19. "DED20,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 18. "DED19,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 17. "DED18,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 16. "DED17,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 15. "DED16,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 14. "DED15,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 13. "DED14,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 12. "DED13,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 11. "DED12,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 10. "DED11,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 9. "DED10,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 8. "DED9,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 7. "DED8,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 6. "DED7,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 5. "DED6,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 4. "DED5,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 3. "DED4,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 2. "DED3,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x0 1. "DED2,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x0 0. "DED1,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" line.long 0x4 "DED1,ECC status for double-bit ECC error" bitfld.long 0x4 31. "DED64,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 30. "DED63,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 29. "DED62,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 28. "DED61,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 27. "DED60,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 26. "DED59,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 25. "DED58,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 24. "DED57,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 23. "DED56,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 22. "DED55,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 21. "DED54,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 20. "DED53,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 19. "DED52,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 18. "DED51,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 17. "DED50,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 16. "DED49,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 15. "DED48,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 14. "DED47,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 13. "DED46,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 12. "DED45,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 11. "DED44,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 10. "DED43,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 9. "DED42,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 8. "DED41,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 7. "DED40,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 6. "DED39,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 5. "DED38,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 4. "DED37,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 3. "DED36,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 2. "DED35,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x4 1. "DED34,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x4 0. "DED33,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" line.long 0x8 "DED2,ECC status for double-bit ECC error" bitfld.long 0x8 31. "DED96,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 30. "DED95,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 29. "DED94,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 28. "DED93,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 27. "DED92,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 26. "DED91,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 25. "DED90,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 24. "DED89,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 23. "DED88,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 22. "DED87,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 21. "DED86,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 20. "DED85,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 19. "DED84,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 18. "DED83,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 17. "DED82,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 16. "DED81,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 15. "DED80,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 14. "DED79,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 13. "DED78,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 12. "DED77,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 11. "DED76,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 10. "DED75,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 9. "DED74,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 8. "DED73,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 7. "DED72,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 6. "DED71,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 5. "DED70,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 4. "DED69,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 3. "DED68,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 2. "DED67,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" newline bitfld.long 0x8 1. "DED66,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" bitfld.long 0x8 0. "DED65,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected" line.long 0xC "DED3,ECC status for double-bit ECC error" group.long 0xF0++0x3 line.long 0x0 "ERR_INJCTR,ECC error injector" hexmask.long.word 0x0 0.--11. 1. "ADDR,The address of the bit in the shadow register where you want to inject the single-bit ECC error. The OCOTP inverts that bit." group.long 0x200++0x17F line.long 0x0 "SHADOWS0,Shadow" hexmask.long 0x0 0.--31. 1. "EFUSES,OTP data" line.long 0x4 "SHADOWS1,Shadow" hexmask.long 0x4 0.--31. 1. "EFUSES,OTP data" line.long 0x8 "SHADOWS2,Shadow" hexmask.long 0x8 0.--31. 1. "EFUSES,OTP data" line.long 0xC "SHADOWS3,Shadow" hexmask.long 0xC 0.--31. 1. "EFUSES,OTP data" line.long 0x10 "SHADOWS4,Shadow" hexmask.long 0x10 0.--31. 1. "EFUSES,OTP data" line.long 0x14 "SHADOWS5,Shadow" hexmask.long 0x14 0.--31. 1. "EFUSES,OTP data" line.long 0x18 "SHADOWS6,Shadow" hexmask.long 0x18 0.--31. 1. "EFUSES,OTP data" line.long 0x1C "SHADOWS7,Shadow" hexmask.long 0x1C 0.--31. 1. "EFUSES,OTP data" line.long 0x20 "SHADOWS8,Shadow" hexmask.long 0x20 0.--31. 1. "EFUSES,OTP data" line.long 0x24 "SHADOWS9,Shadow" hexmask.long 0x24 0.--31. 1. "EFUSES,OTP data" line.long 0x28 "SHADOWS10,Shadow" hexmask.long 0x28 0.--31. 1. "EFUSES,OTP data" line.long 0x2C "SHADOWS11,Shadow" hexmask.long 0x2C 0.--31. 1. "EFUSES,OTP data" line.long 0x30 "SHADOWS12,Shadow" hexmask.long 0x30 0.--31. 1. "EFUSES,OTP data" line.long 0x34 "SHADOWS13,Shadow" hexmask.long 0x34 0.--31. 1. "EFUSES,OTP data" line.long 0x38 "SHADOWS14,Shadow" hexmask.long 0x38 0.--31. 1. "EFUSES,OTP data" line.long 0x3C "SHADOWS15,Shadow" hexmask.long 0x3C 0.--31. 1. "EFUSES,OTP data" line.long 0x40 "SHADOWS16,Shadow" hexmask.long 0x40 0.--31. 1. "EFUSES,OTP data" line.long 0x44 "SHADOWS17,Shadow" hexmask.long 0x44 0.--31. 1. "EFUSES,OTP data" line.long 0x48 "SHADOWS18,Shadow" hexmask.long 0x48 0.--31. 1. "EFUSES,OTP data" line.long 0x4C "SHADOWS19,Shadow" hexmask.long 0x4C 0.--31. 1. "EFUSES,OTP data" line.long 0x50 "SHADOWS20,Shadow" hexmask.long 0x50 0.--31. 1. "EFUSES,OTP data" line.long 0x54 "SHADOWS21,Shadow" hexmask.long 0x54 0.--31. 1. "EFUSES,OTP data" line.long 0x58 "SHADOWS22,Shadow" hexmask.long 0x58 0.--31. 1. "EFUSES,OTP data" line.long 0x5C "SHADOWS23,Shadow" hexmask.long 0x5C 0.--31. 1. "EFUSES,OTP data" line.long 0x60 "SHADOWS24,Shadow" hexmask.long 0x60 0.--31. 1. "EFUSES,OTP data" line.long 0x64 "SHADOWS25,Shadow" hexmask.long 0x64 0.--31. 1. "EFUSES,OTP data" line.long 0x68 "SHADOWS26,Shadow" hexmask.long 0x68 0.--31. 1. "EFUSES,OTP data" line.long 0x6C "SHADOWS27,Shadow" hexmask.long 0x6C 0.--31. 1. "EFUSES,OTP data" line.long 0x70 "SHADOWS28,Shadow" hexmask.long 0x70 0.--31. 1. "EFUSES,OTP data" line.long 0x74 "SHADOWS29,Shadow" hexmask.long 0x74 0.--31. 1. "EFUSES,OTP data" line.long 0x78 "SHADOWS30,Shadow" hexmask.long 0x78 0.--31. 1. "EFUSES,OTP data" line.long 0x7C "SHADOWS31,Shadow" hexmask.long 0x7C 0.--31. 1. "EFUSES,OTP data" line.long 0x80 "SHADOWS32,Shadow" hexmask.long 0x80 0.--31. 1. "EFUSES,OTP data" line.long 0x84 "SHADOWS33,Shadow" hexmask.long 0x84 0.--31. 1. "EFUSES,OTP data" line.long 0x88 "SHADOWS34,Shadow" hexmask.long 0x88 0.--31. 1. "EFUSES,OTP data" line.long 0x8C "SHADOWS35,Shadow" hexmask.long 0x8C 0.--31. 1. "EFUSES,OTP data" line.long 0x90 "SHADOWS36,Shadow" hexmask.long 0x90 0.--31. 1. "EFUSES,OTP data" line.long 0x94 "SHADOWS37,Shadow" hexmask.long 0x94 0.--31. 1. "EFUSES,OTP data" line.long 0x98 "SHADOWS38,Shadow" hexmask.long 0x98 0.--31. 1. "EFUSES,OTP data" line.long 0x9C "SHADOWS39,Shadow" hexmask.long 0x9C 0.--31. 1. "EFUSES,OTP data" line.long 0xA0 "SHADOWS40,Shadow" hexmask.long 0xA0 0.--31. 1. "EFUSES,OTP data" line.long 0xA4 "SHADOWS41,Shadow" hexmask.long 0xA4 0.--31. 1. "EFUSES,OTP data" line.long 0xA8 "SHADOWS42,Shadow" hexmask.long 0xA8 0.--31. 1. "EFUSES,OTP data" line.long 0xAC "SHADOWS43,Shadow" hexmask.long 0xAC 0.--31. 1. "EFUSES,OTP data" line.long 0xB0 "SHADOWS44,Shadow" hexmask.long 0xB0 0.--31. 1. "EFUSES,OTP data" line.long 0xB4 "SHADOWS45,Shadow" hexmask.long 0xB4 0.--31. 1. "EFUSES,OTP data" line.long 0xB8 "SHADOWS46,Shadow" hexmask.long 0xB8 0.--31. 1. "EFUSES,OTP data" line.long 0xBC "SHADOWS47,Shadow" hexmask.long 0xBC 0.--31. 1. "EFUSES,OTP data" line.long 0xC0 "SHADOWS48,Shadow" hexmask.long 0xC0 0.--31. 1. "EFUSES,OTP data" line.long 0xC4 "SHADOWS49,Shadow" hexmask.long 0xC4 0.--31. 1. "EFUSES,OTP data" line.long 0xC8 "SHADOWS50,Shadow" hexmask.long 0xC8 0.--31. 1. "EFUSES,OTP data" line.long 0xCC "SHADOWS51,Shadow" hexmask.long 0xCC 0.--31. 1. "EFUSES,OTP data" line.long 0xD0 "SHADOWS52,Shadow" hexmask.long 0xD0 0.--31. 1. "EFUSES,OTP data" line.long 0xD4 "SHADOWS53,Shadow" hexmask.long 0xD4 0.--31. 1. "EFUSES,OTP data" line.long 0xD8 "SHADOWS54,Shadow" hexmask.long 0xD8 0.--31. 1. "EFUSES,OTP data" line.long 0xDC "SHADOWS55,Shadow" hexmask.long 0xDC 0.--31. 1. "EFUSES,OTP data" line.long 0xE0 "SHADOWS56,Shadow" hexmask.long 0xE0 0.--31. 1. "EFUSES,OTP data" line.long 0xE4 "SHADOWS57,Shadow" hexmask.long 0xE4 0.--31. 1. "EFUSES,OTP data" line.long 0xE8 "SHADOWS58,Shadow" hexmask.long 0xE8 0.--31. 1. "EFUSES,OTP data" line.long 0xEC "SHADOWS59,Shadow" hexmask.long 0xEC 0.--31. 1. "EFUSES,OTP data" line.long 0xF0 "SHADOWS60,Shadow" hexmask.long 0xF0 0.--31. 1. "EFUSES,OTP data" line.long 0xF4 "SHADOWS61,Shadow" hexmask.long 0xF4 0.--31. 1. "EFUSES,OTP data" line.long 0xF8 "SHADOWS62,Shadow" hexmask.long 0xF8 0.--31. 1. "EFUSES,OTP data" line.long 0xFC "SHADOWS63,Shadow" hexmask.long 0xFC 0.--31. 1. "EFUSES,OTP data" line.long 0x100 "SHADOWS64,Shadow" hexmask.long 0x100 0.--31. 1. "EFUSES,OTP data" line.long 0x104 "SHADOWS65,Shadow" hexmask.long 0x104 0.--31. 1. "EFUSES,OTP data" line.long 0x108 "SHADOWS66,Shadow" hexmask.long 0x108 0.--31. 1. "EFUSES,OTP data" line.long 0x10C "SHADOWS67,Shadow" hexmask.long 0x10C 0.--31. 1. "EFUSES,OTP data" line.long 0x110 "SHADOWS68,Shadow" hexmask.long 0x110 0.--31. 1. "EFUSES,OTP data" line.long 0x114 "SHADOWS69,Shadow" hexmask.long 0x114 0.--31. 1. "EFUSES,OTP data" line.long 0x118 "SHADOWS70,Shadow" hexmask.long 0x118 0.--31. 1. "EFUSES,OTP data" line.long 0x11C "SHADOWS71,Shadow" hexmask.long 0x11C 0.--31. 1. "EFUSES,OTP data" line.long 0x120 "SHADOWS72,Shadow" hexmask.long 0x120 0.--31. 1. "EFUSES,OTP data" line.long 0x124 "SHADOWS73,Shadow" hexmask.long 0x124 0.--31. 1. "EFUSES,OTP data" line.long 0x128 "SHADOWS74,Shadow" hexmask.long 0x128 0.--31. 1. "EFUSES,OTP data" line.long 0x12C "SHADOWS75,Shadow" hexmask.long 0x12C 0.--31. 1. "EFUSES,OTP data" line.long 0x130 "SHADOWS76,Shadow" hexmask.long 0x130 0.--31. 1. "EFUSES,OTP data" line.long 0x134 "SHADOWS77,Shadow" hexmask.long 0x134 0.--31. 1. "EFUSES,OTP data" line.long 0x138 "SHADOWS78,Shadow" hexmask.long 0x138 0.--31. 1. "EFUSES,OTP data" line.long 0x13C "SHADOWS79,Shadow" hexmask.long 0x13C 0.--31. 1. "EFUSES,OTP data" line.long 0x140 "SHADOWS80,Shadow" hexmask.long 0x140 0.--31. 1. "EFUSES,OTP data" line.long 0x144 "SHADOWS81,Shadow" hexmask.long 0x144 0.--31. 1. "EFUSES,OTP data" line.long 0x148 "SHADOWS82,Shadow" hexmask.long 0x148 0.--31. 1. "EFUSES,OTP data" line.long 0x14C "SHADOWS83,Shadow" hexmask.long 0x14C 0.--31. 1. "EFUSES,OTP data" line.long 0x150 "SHADOWS84,Shadow" hexmask.long 0x150 0.--31. 1. "EFUSES,OTP data" line.long 0x154 "SHADOWS85,Shadow" hexmask.long 0x154 0.--31. 1. "EFUSES,OTP data" line.long 0x158 "SHADOWS86,Shadow" hexmask.long 0x158 0.--31. 1. "EFUSES,OTP data" line.long 0x15C "SHADOWS87,Shadow" hexmask.long 0x15C 0.--31. 1. "EFUSES,OTP data" line.long 0x160 "SHADOWS88,Shadow" hexmask.long 0x160 0.--31. 1. "EFUSES,OTP data" line.long 0x164 "SHADOWS89,Shadow" hexmask.long 0x164 0.--31. 1. "EFUSES,OTP data" line.long 0x168 "SHADOWS90,Shadow" hexmask.long 0x168 0.--31. 1. "EFUSES,OTP data" line.long 0x16C "SHADOWS91,Shadow" hexmask.long 0x16C 0.--31. 1. "EFUSES,OTP data" line.long 0x170 "SHADOWS92,Shadow" hexmask.long 0x170 0.--31. 1. "EFUSES,OTP data" line.long 0x174 "SHADOWS93,Shadow" hexmask.long 0x174 0.--31. 1. "EFUSES,OTP data" line.long 0x178 "SHADOWS94,Shadow" hexmask.long 0x178 0.--31. 1. "EFUSES,OTP data" line.long 0x17C "SHADOWS95,Shadow" hexmask.long 0x17C 0.--31. 1. "EFUSES,OTP data" rgroup.long 0x380++0x7F line.long 0x0 "SHADOWS96,Shadow" hexmask.long 0x0 0.--31. 1. "EFUSES,OTP data" line.long 0x4 "SHADOWS97,Shadow" hexmask.long 0x4 0.--31. 1. "EFUSES,OTP data" line.long 0x8 "SHADOWS98,Shadow" hexmask.long 0x8 0.--31. 1. "EFUSES,OTP data" line.long 0xC "SHADOWS99,Shadow" hexmask.long 0xC 0.--31. 1. "EFUSES,OTP data" line.long 0x10 "SHADOWS100,Shadow" hexmask.long 0x10 0.--31. 1. "EFUSES,OTP data" line.long 0x14 "SHADOWS101,Shadow" hexmask.long 0x14 0.--31. 1. "EFUSES,OTP data" line.long 0x18 "SHADOWS102,Shadow" hexmask.long 0x18 0.--31. 1. "EFUSES,OTP data" line.long 0x1C "SHADOWS103,Shadow" hexmask.long 0x1C 0.--31. 1. "EFUSES,OTP data" line.long 0x20 "SHADOWS104,Shadow" hexmask.long 0x20 0.--31. 1. "EFUSES,OTP data" line.long 0x24 "SHADOWS105,Shadow" hexmask.long 0x24 0.--31. 1. "EFUSES,OTP data" line.long 0x28 "SHADOWS106,Shadow" hexmask.long 0x28 0.--31. 1. "EFUSES,OTP data" line.long 0x2C "SHADOWS107,Shadow" hexmask.long 0x2C 0.--31. 1. "EFUSES,OTP data" line.long 0x30 "SHADOWS108,Shadow" hexmask.long 0x30 0.--31. 1. "EFUSES,OTP data" line.long 0x34 "SHADOWS109,Shadow" hexmask.long 0x34 0.--31. 1. "EFUSES,OTP data" line.long 0x38 "SHADOWS110,Shadow" hexmask.long 0x38 0.--31. 1. "EFUSES,OTP data" line.long 0x3C "SHADOWS111,Shadow" hexmask.long 0x3C 0.--31. 1. "EFUSES,OTP data" line.long 0x40 "SHADOWS112,Shadow" hexmask.long 0x40 0.--31. 1. "EFUSES,OTP data" line.long 0x44 "SHADOWS113,Shadow" hexmask.long 0x44 0.--31. 1. "EFUSES,OTP data" line.long 0x48 "SHADOWS114,Shadow" hexmask.long 0x48 0.--31. 1. "EFUSES,OTP data" line.long 0x4C "SHADOWS115,Shadow" hexmask.long 0x4C 0.--31. 1. "EFUSES,OTP data" line.long 0x50 "SHADOWS116,Shadow" hexmask.long 0x50 0.--31. 1. "EFUSES,OTP data" line.long 0x54 "SHADOWS117,Shadow" hexmask.long 0x54 0.--31. 1. "EFUSES,OTP data" line.long 0x58 "SHADOWS118,Shadow" hexmask.long 0x58 0.--31. 1. "EFUSES,OTP data" line.long 0x5C "SHADOWS119,Shadow" hexmask.long 0x5C 0.--31. 1. "EFUSES,OTP data" line.long 0x60 "SHADOWS120,Shadow" hexmask.long 0x60 0.--31. 1. "EFUSES,OTP data" line.long 0x64 "SHADOWS121,Shadow" hexmask.long 0x64 0.--31. 1. "EFUSES,OTP data" line.long 0x68 "SHADOWS122,Shadow" hexmask.long 0x68 0.--31. 1. "EFUSES,OTP data" line.long 0x6C "SHADOWS123,Shadow" hexmask.long 0x6C 0.--31. 1. "EFUSES,OTP data" line.long 0x70 "SHADOWS124,Shadow" hexmask.long 0x70 0.--31. 1. "EFUSES,OTP data" line.long 0x74 "SHADOWS125,Shadow" hexmask.long 0x74 0.--31. 1. "EFUSES,OTP data" line.long 0x78 "SHADOWS126,Shadow" hexmask.long 0x78 0.--31. 1. "EFUSES,OTP data" line.long 0x7C "SHADOWS127,Shadow" hexmask.long 0x7C 0.--31. 1. "EFUSES,OTP data" tree.end tree "OCOTP_GPR (OCOTP General Purpose Register)" base ad:0x400A040 group.long 0x0++0x7 line.long 0x0 "OCOTP_GPR_0,Boot Configuration Register 1" line.long 0x4 "OCOTP_GPR_1,Boot Configuration Register 1" tree.end tree "PCIE (Peripheral Component Interconnect Express)" base ad:0x0 tree "PCIE_DMA" base ad:0x70000 group.long 0x0++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA arbitration scheme for TRGT1 interface" bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" group.long 0x8++0xB line.long 0x0 "DMA_CTRL_OFF,DMA number of channels" bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "0: Disable,1: Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell" bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number" "0,1,2,3,4,5,6,7" group.long 0x18++0x3 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA write engine channel arbitration weight low" hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long 0x2C++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "0: Disable,1: Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell" bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number" "0,1,2,3,4,5,6,7" group.long 0x38++0x3 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA read engine channel arbitration weight low" hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long 0x4C++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status" hexmask.long.byte 0x0 16.--19. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status" newline hexmask.long.byte 0x0 0.--3. 1. "WR_DONE_INT_STATUS,Done Interrupt Status" group.long 0x54++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA write interrupt mask" hexmask.long.byte 0x0 16.--19. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 0.--3. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA write interrupt clear" hexmask.long.byte 0x4 16.--19. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 0.--3. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long 0x5C++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status" hexmask.long.byte 0x0 16.--19. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected" newline hexmask.long.byte 0x0 0.--3. 1. "APP_READ_ERR_DETECT,Application Read Error Detected" group.long 0x60++0x17 line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA write done IMWr address low" hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA write done IMWr interrupt address high" hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA write abort IMWr address low" hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA write abort IMWr address high" hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA write channel 0 and 1 IMWr data" hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA write channel 2 and 3 IMWr data" hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: R/W" group.long 0x90++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA write linked list error enable" hexmask.long.byte 0x0 16.--19. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 0.--3. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long 0xA0++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status" hexmask.long.byte 0x0 16.--19. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status" newline hexmask.long.byte 0x0 0.--3. 1. "RD_DONE_INT_STATUS,Done Interrupt Status" group.long 0xA8++0x3 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA read interrupt mask" hexmask.long.byte 0x0 16.--19. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 0.--3. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." wgroup.long 0xAC++0x3 line.long 0x0 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear" hexmask.long.byte 0x0 16.--19. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear" newline hexmask.long.byte 0x0 0.--3. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear" rgroup.long 0xB4++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low" hexmask.long.byte 0x0 16.--19. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected" newline hexmask.long.byte 0x0 0.--3. 1. "APP_WR_ERR_DETECT,Application Write Error Detected" line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High" hexmask.long.byte 0x4 24.--27. 1. "DATA_POISIONING,Data Poisoning" newline hexmask.long.byte 0x4 16.--19. 1. "CPL_TIMEOUT,Completion Time Out" newline hexmask.long.byte 0x4 8.--11. 1. "CPL_ABORT,Completer Abort" newline hexmask.long.byte 0x4 0.--3. 1. "UNSUPPORTED_REQ,Unsupported Request" group.long 0xC4++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA read linked list error enable" hexmask.long.byte 0x0 16.--19. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 0.--3. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long 0xCC++0x17 line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA read done IMWr address low" hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA read done IMWr address high" hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low" hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,DMA Read Abort Low" line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High" hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,DMA Read Abort High" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 0 And 1 IMWr Data" hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,Read Channel 1 Data" newline hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,Read Channel 0 Data" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 2 And 3 IMWr Data" hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,Read Channel 3 Data" newline hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,Read Channel 2 Data" rgroup.long 0x108++0x3 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA write engine handshake counter channel 0/1/2/3" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long 0x118++0x3 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA read engine handshake counter channel 0/1/2/3" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." group.long 0x200++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x208++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA write transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." line.long 0x4 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_WRCH_0,DMA write SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA write DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA write linked list pointer low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA write linked list pointer high" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." group.long 0x300++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_0,DMA Read Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x308++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_0,DMA read transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." line.long 0x4 "DMA_SAR_LOW_OFF_RDCH_0,DMA Read SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_RDCH_0,DMA read SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_RDCH_0,DMA Read DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 Bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_RDCH_0,DMA read DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_RDCH_0,DMA Read Linked List Pointer Low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower Bits" line.long 0x18 "DMA_LLP_HIGH_OFF_RDCH_0,DMA Read Linked List Pointer High" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper Bits" group.long 0x400++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_1,DMA Write Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x408++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_1,DMA write transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." line.long 0x4 "DMA_SAR_LOW_OFF_WRCH_1,DMA Write SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_WRCH_1,DMA write SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_WRCH_1,DMA Write DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_1,DMA write DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_1,DMA write linked list pointer low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_1,DMA write linked list pointer high" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." group.long 0x500++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_1,DMA Read Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x508++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_1,DMA read transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." line.long 0x4 "DMA_SAR_LOW_OFF_RDCH_1,DMA Read SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_RDCH_1,DMA read SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_RDCH_1,DMA Read DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 Bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_RDCH_1,DMA read DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_RDCH_1,DMA Read Linked List Pointer Low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower Bits" line.long 0x18 "DMA_LLP_HIGH_OFF_RDCH_1,DMA Read Linked List Pointer High" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper Bits" group.long 0x600++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_2,DMA Write Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x608++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_2,DMA write transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." line.long 0x4 "DMA_SAR_LOW_OFF_WRCH_2,DMA Write SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_WRCH_2,DMA write SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_WRCH_2,DMA Write DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_2,DMA write DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_2,DMA write linked list pointer low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_2,DMA write linked list pointer high" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." group.long 0x700++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_2,DMA Read Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x708++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_2,DMA read transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." line.long 0x4 "DMA_SAR_LOW_OFF_RDCH_2,DMA Read SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_RDCH_2,DMA read SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_RDCH_2,DMA Read DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 Bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_RDCH_2,DMA read DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_RDCH_2,DMA Read Linked List Pointer Low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower Bits" line.long 0x18 "DMA_LLP_HIGH_OFF_RDCH_2,DMA Read Linked List Pointer High" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper Bits" group.long 0x800++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_3,DMA Write Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x808++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_3,DMA write transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." line.long 0x4 "DMA_SAR_LOW_OFF_WRCH_3,DMA Write SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_WRCH_3,DMA write SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_WRCH_3,DMA Write DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_3,DMA write DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_3,DMA write linked list pointer low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_3,DMA write linked list pointer high" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." group.long 0x900++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_3,DMA Read Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x908++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_3,DMA read transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." line.long 0x4 "DMA_SAR_LOW_OFF_RDCH_3,DMA Read SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_RDCH_3,DMA read SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_RDCH_3,DMA Read DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 Bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_RDCH_3,DMA read DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_RDCH_3,DMA Read Linked List Pointer Low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower Bits" line.long 0x18 "DMA_LLP_HIGH_OFF_RDCH_3,DMA Read Linked List Pointer High" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper Bits" tree.end base ad:0x0 tree "PCIE_EP" rgroup.long 0x0++0x3 line.long 0x0 "DEVICE_VENDOR_ID,Device ID And Vendor ID" hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID" newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID" group.long 0x4++0x3 line.long 0x0 "COMMAND,Command And Status" eventfld.long 0x0 31. "DETECTED_PARITY_ERR,Detected parity error" "0,1" newline eventfld.long 0x0 30. "SIGNALED_SYS_ERR,Signaled system error" "0,1" newline eventfld.long 0x0 29. "RCVD_MASTER_ABORT,Received master abort" "0,1" newline eventfld.long 0x0 28. "RCVD_TARGET_ABORT,Received target abort" "0,1" newline eventfld.long 0x0 27. "SIGNALED_TARGET_ABORT,Signaled target abort" "0,1" newline eventfld.long 0x0 24. "MASTER_DPE,Master data parity error" "0,1" newline rbitfld.long 0x0 19. "INT_STATUS,Emulation interrupt pending" "0: No INTx emulation interrupt is pending.,1: An INTX emulation interrupt is pending." newline bitfld.long 0x0 10. "INT_EN,Interrupt enable/disable" "0: PCIe allows Functions to assert INTx interrupts.,1: PCIe prevents Functions from asserting INTx.." newline bitfld.long 0x0 8. "SERREN,SERR# Enable" "0,1" newline bitfld.long 0x0 6. "PARITY_ERR_RESPONSE,Parity error response" "0,1" newline bitfld.long 0x0 2. "BUS_MASTER_EN,Bus_Master_Enable" "0,1" newline bitfld.long 0x0 1. "MEM_SPACE_EN,Memory_Space_Enable" "0,1" newline bitfld.long 0x0 0. "IO_SPACE_EN,I_O_Space_Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CLASS_CODE_REVISION_ID,Class Code And Revision ID" hexmask.long.byte 0x0 24.--31. 1. "BASE_CLASS_CODE,Base class code" newline hexmask.long.byte 0x0 16.--23. 1. "SUBCLASS_CODE,Sub-class code" newline hexmask.long.byte 0x0 8.--15. 1. "PROGRAM_INTERFACE,Programming interface" newline hexmask.long.byte 0x0 0.--7. 1. "REVISION_ID,Revision ID" group.long 0xC++0x7 line.long 0x0 "BHTLCLS,BIST. Header Type. Latency Timer. And Cache Line Size" hexmask.long.byte 0x0 24.--31. 1. "BIST,BIST control and status" newline rbitfld.long 0x0 23. "MULTI_FUNC,Multi-function device" "0: Software must not probe for Functions other than..,1: The device may contain multiple Functions." newline hexmask.long.byte 0x0 16.--22. 1. "HEADER_TYPE,Header layout" newline hexmask.long.byte 0x0 0.--7. 1. "CACHE_LINE_SIZE,Cache line size" line.long 0x4 "BAR0,Base Address 0" hexmask.long 0x4 4.--31. 1. "ADDRESS,ADDRESS" newline rbitfld.long 0x4 3. "PREF,PREF" "0: Non-prefetchable,1: Prefetchable" newline bitfld.long 0x4 1.--2. "TYPE,TYPE" "0: = 32-bit BAR,?,2: = 64-bit BAR,?" newline rbitfld.long 0x4 0. "Mem_I_O,Mem_I_O" "0: = BAR 0 is a memory BAR,1: = BAR 0 is an I/O BAR" rgroup.long 0x14++0x3 line.long 0x0 "BAR1,Base Address 1" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x18++0x3 line.long 0x0 "BAR2,Base Address 2" hexmask.long 0x0 4.--31. 1. "ADDRESS,ADDRESS" newline rbitfld.long 0x0 3. "PREF,PREF" "0: Non-prefetchable,1: Prefetchable" newline bitfld.long 0x0 1.--2. "TYPE,TYPE" "0: = 32-bit BAR,?,2: = 64-bit BAR,?" newline rbitfld.long 0x0 0. "MEM_I_O,MEM_I_O" "0: BAR 2 is a memory BAR,1: BAR 2 is an I/O BAR" rgroup.long 0x1C++0x3 line.long 0x0 "BAR3,Base Address 3" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x20++0x3 line.long 0x0 "BAR4,Base Address 4" hexmask.long 0x0 4.--31. 1. "ADDRESS,ADDRESS" newline rbitfld.long 0x0 3. "PREF,PREF" "0: = Non-prefetchable,1: = Prefetchable" newline bitfld.long 0x0 1.--2. "TYPE,TYPE" "0: = 32-bit BAR,?,2: = 64-bit BAR,?" newline bitfld.long 0x0 0. "MEM_I_O,MEM_I_O" "0: = BAR 4 is a memory BAR,1: = BAR 4 is an I/O BAR" rgroup.long 0x24++0x3 line.long 0x0 "BAR5,Base Address 5" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" rgroup.long 0x2C++0x3 line.long 0x0 "SSID,Subsystem ID And Subsystem Vendor ID" hexmask.long.word 0x0 16.--31. 1. "SUBSYS_DEV_ID,Subsystem ID" newline hexmask.long.word 0x0 0.--15. 1. "SUBSYS_VENDOR_ID,Subsystem vendor ID" group.long 0x30++0x3 line.long 0x0 "EROMBAR,Expansion ROM Base Address" hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS,ADDRESS" newline bitfld.long 0x0 0. "ENABLE,ENABLE" "0,1" group.long 0x30++0x3 line.long 0x0 "EROMBARMASK,Expansion ROM BAR Mask" hexmask.long 0x0 1.--31. 1. "ROM_MASK,Expansion ROM Mask" newline rbitfld.long 0x0 0. "ROM_BAR_ENABLED,Expansion ROM Bar Mask Register Enabled" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "CAPPR,Capabilities Pointer" hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities pointer" group.long 0x3C++0x3 line.long 0x0 "MLMGIPIL,Max_Lat. Min_Gnt. Interrupt Pin. And Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. "INT_PIN,INT_PIN" newline hexmask.long.byte 0x0 0.--7. 1. "INT_LINE,Interrupt line" rgroup.long 0x40++0x3 line.long 0x0 "PMCAP,Power Management Capabilities" hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,Power Management Event Support" newline bitfld.long 0x0 26. "D2_SUPPORT,D2 State Support" "0: The Function does not support the D2 power..,1: The Function supports the D2 power management.." newline bitfld.long 0x0 25. "D1_SUPPORT,D1 State Support" "0: The Function does not support the D1 power..,1: The Function supports the D1 power management.." newline bitfld.long 0x0 22.--24. "AUX_CURR,Auxiliary Current Requirements" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device-Specific Initialization" "0: The Function does not require a device-specific..,1: The Function requires a device-specific.." newline bitfld.long 0x0 16.--18. "PM_SPEC_VER,Power management spec version" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next capability pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Power management capability ID" group.long 0x44++0x3 line.long 0x0 "PMCSR,Power Management Control And Status" hexmask.long.byte 0x0 24.--31. 1. "DATA,Power data information" newline rbitfld.long 0x0 23. "BPCC_EN,Bus power/clock control enable" "0: The bus power/clock control policies defined in..,1: The bus power/clock control policies defined in.." newline rbitfld.long 0x0 22. "B2_B3_SUPPORT,B2/B3 support" "0: B3,1: B2" newline eventfld.long 0x0 15. "PME_STATUS,PME status" "0,1" newline rbitfld.long 0x0 13.--14. "DATA_SCALE,Data scaling factor" "0,1,2,3" newline bitfld.long 0x0 8. "PME_ENABLE,PME# enable" "0: The Function cannot assert PME#.,1: The Function can assert PME#." newline bitfld.long 0x0 3. "NO_SOFT_RST,No Soft Reset" "0: Internal reset,1: No internal reset" newline bitfld.long 0x0 0.--1. "POWER_STATE,Power state" "0: D0,1: D1,2: D2,3: D3hot" group.long 0x50++0x13 line.long 0x0 "MSI_CIDNC,PCI Express MSI Message Capability ID" bitfld.long 0x0 26. "EXT_DATA_EN,Extended Message Data Enable" "0: Not configured,1: Configured" newline rbitfld.long 0x0 25. "EXT_DATA_CAP,Extended Message Data Capable" "0: The Function is incapable of providing..,1: The Function is capable of providing.." newline rbitfld.long 0x0 24. "PVM_SUPPORT,MSI per-vector masking capable" "0: The Function does not support MSI per-vector..,1: The Function supports MSI per-vector masking." newline rbitfld.long 0x0 23. "ADDR_CAP_64,MSI 64-bit address capable" "0: The Function is incapable of sending a 64-bit..,1: The Function is capable of sending a 64-bit.." newline bitfld.long 0x0 20.--22. "MULTI_MSG_EN,MSI multiple message enable" "0: 1 vector allocated.,1: 2 vectors allocated.,2: 4 vectors allocated.,3: 8 vectors allocated.,4: 16 vectors allocated.,5: 32 vectors allocated.,?,?" newline rbitfld.long 0x0 17.--19. "MULTI_MSG_CAP,MSI multiple message capable" "0: 1 vector requested.,1: 2 vectors requested.,2: 4 vectors requested.,3: 8 vectors requested.,4: 16 vectors requested.,5: 32 vectors requested.,?,?" newline bitfld.long 0x0 16. "ENABLE,MSI enable" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "CAP_NEXT_PTR,MSI capability next pointer" newline hexmask.long.byte 0x0 0.--7. 1. "CAP_ID,MSI capability ID" line.long 0x4 "MSI_MLADDR,MSI message lower address" hexmask.long 0x4 2.--31. 1. "MSG_LOWER_ADDR,System-specified message lower address" line.long 0x8 "MSI_MUADDR_DATA,MSI message upper address or data" hexmask.long.word 0x8 16.--31. 1. "EMDATA_UADDRU,Extended MSI data or upper 16 bits of the upper address" newline hexmask.long.word 0x8 0.--15. 1. "DATA_UADDRL,Data or lower 16 bits of the upper address" line.long 0xC "MSI_DATA_MASK,MSI data or mask bits" hexmask.long.word 0xC 16.--31. 1. "DATA_UMB,Data or upper mask bits" newline hexmask.long.word 0xC 0.--15. 1. "DATA_LMB,Data or lower mask bits" line.long 0x10 "MSI_PEND_MASK_BITS,MSI pending or mask bits" hexmask.long 0x10 0.--31. 1. "PEND_MASK_BITS,Pending or mask bits" rgroup.long 0x64++0x3 line.long 0x0 "MSI_PEND_BITS,MSI pending bits" hexmask.long 0x0 0.--31. 1. "PEND_BITS,Pending bits" rgroup.long 0x70++0x7 line.long 0x0 "CINCPCR,Capabilities ID and next pointer" hexmask.long.byte 0x0 25.--29. 1. "INT_MSG_NUM,PCIe Interrupt Message Number" newline bitfld.long 0x0 24. "SLOT_IMP,PCIe Slot Implemented Valid" "0: The link associated with this port is either..,1: The link associated with this port is connected.." newline hexmask.long.byte 0x0 20.--23. 1. "DEV_PORT_TYPE,PCIe device/port type" newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,PCIe capability version number" newline hexmask.long.byte 0x0 8.--15. 1. "CAP_NEXT_PTR,PCIe Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "CAP_ID,PCIe capability ID" line.long 0x4 "DEV_CAPABILITIES,Device capabilities" bitfld.long 0x4 28. "FLR_CAP,Function-level reset (FLR) capability" "0: The Function does not support FLR.,1: The Function supports FLR." newline bitfld.long 0x4 26.--27. "CSPLS,Captured slot power limit scale" "0,1,2,3" newline hexmask.long.byte 0x4 18.--25. 1. "CSPLV,Captured slot power limit value" newline bitfld.long 0x4 15. "ROLE_BASED_ERR_REPORT,Role-based error reporting" "?,1: Role-based error reporting is implemented." newline bitfld.long 0x4 9.--11. "EP_L1_ACCPT_LAT,EP L1 acceptable latency" "0: Maximum of 1 us.,1: Maximum of 2 us.,2: Maximum of 4 us.,3: Maximum of 8 us.,4: Maximum of 16 us.,5: Maximum of 32 us.,6: Maximum of 64 us.,7: No limit." newline bitfld.long 0x4 6.--8. "EP_L0S_ACCPT_LAT,EP L0s acceptable latency" "0: Maximum of 64 ns.,1: Maximum of 128 ns.,2: Maximum of 256 ns.,3: Maximum of 512 ns.,4: Maximum of 1 us.,5: Maximum of 2 us.,6: Maximum of 4 us.,7: No limit." newline bitfld.long 0x4 5. "EXT_TAG_SUP,Extended Tag Field Supported" "0: 5-bit Tag field supported.,1: 8-bit Tag field supported." newline bitfld.long 0x4 3.--4. "PHAN_FUNC_SUP,Phantom Functions Supported" "0,1,2,3" newline bitfld.long 0x4 0.--2. "MAX_PL_SIZE_SUP,Max Payload Size Supported" "0: Max payload size is 128 bytes.,1: Max payload size is 256 bytes.,2: Max payload size is 512 bytes.,3: Max payload size is 1024 bytes.,4: Max payload size is 2048 bytes.,5: Max payload size is 4096 bytes.,?,?" group.long 0x78++0x3 line.long 0x0 "DEV_CONTROL_STATUS,Device control and status" rbitfld.long 0x0 21. "TRANS_PENDING,TP" "0: All outstanding non-posted requests have..,1: The Function has issued non-posted requests that.." newline rbitfld.long 0x0 20. "APD,Aux power detected status" "0,1" newline eventfld.long 0x0 19. "URD,Unsupported request detected status" "0,1" newline eventfld.long 0x0 18. "FED,Fatal error detected status" "0,1" newline eventfld.long 0x0 17. "NFED,Non-fatal error detected status" "0,1" newline eventfld.long 0x0 16. "CED,Correctable error detected status" "0,1" newline bitfld.long 0x0 15. "INITIATE_FLR,Initiate FLR" "0,1" newline bitfld.long 0x0 12.--14. "MAX_READ_REQ_SIZE,Max read request size" "0: Maximum read request size is 128 bytes.,1: Maximum read request size is 256 bytes.,2: Maximum read request size is 512 bytes.,3: Maximum read request size is 1024 bytes.,4: Maximum read request size is 2048 bytes.,5: Maximum read request size is 4096 bytes.,?,?" newline rbitfld.long 0x0 11. "EN_NO_SNOOP,Enable no snoop" "0,1" newline bitfld.long 0x0 10. "APE,Aux power PM enable" "0,1" newline bitfld.long 0x0 9. "PHANTOM_FUNC_EN,Phantom Functions enable" "0: The Function cannot use Phantom functions.,1: The Function is allowed to use Phantom functions." newline bitfld.long 0x0 8. "EXT_TAG_EN,Extended Tag field enable" "0: The Function is restricted to using a 5-bit Tag..,1: The Function is allowed to use an 8-bit Tag field." newline bitfld.long 0x0 5.--7. "MAX_PAYLOAD_SIZE,Max payload size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "EN_REL_ORDER,Enable relaxed ordering" "0,1" newline bitfld.long 0x0 3. "URR,Unsupported request reporting enable" "0,1" newline bitfld.long 0x0 2. "FER,Fatal error reporting" "0,1" newline bitfld.long 0x0 1. "NFER,Non-fatal error reporting enable" "0,1" newline bitfld.long 0x0 0. "CER,Correctable error reporting enable" "0,1" rgroup.long 0x7C++0x3 line.long 0x0 "LINK_CAPABILITIES,Link Capabilities" hexmask.long.byte 0x0 24.--31. 1. "PORT_NUM,Port number" newline bitfld.long 0x0 18. "CLOCK_POWER_MAN,Clock power management" "0,1" newline bitfld.long 0x0 15.--17. "L1_EXIT_LATENCY,L1 exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "L0S_EXIT_LATENCY,L0s exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10.--11. "ASPM_SUPPORT,Active State Power Management (ASPM) support" "0: No ASPM support,1: L0s supported,2: L1 supported,3: L0s and L1 supported" newline hexmask.long.byte 0x0 4.--9. 1. "MAX_LINK_WIDTH,Maximum link width" newline hexmask.long.byte 0x0 0.--3. 1. "MAX_LINK_SPEED,Max link speed" group.long 0x80++0x3 line.long 0x0 "LINK_CONTROL_STATUS,Link Control And Status" rbitfld.long 0x0 29. "DLL_ACTIVE,Data link layer active" "0,1" newline rbitfld.long 0x0 28. "SLOT_CLK_CONFIG,Slot Clock Configuration" "0,1" newline hexmask.long.byte 0x0 20.--25. 1. "NEGO_LINK_WIDTH,Current link speed" newline hexmask.long.byte 0x0 16.--19. 1. "LINK_SPEED,Current link speed" newline bitfld.long 0x0 9. "HW_AUTO_WIDTH_DISABLE,Hardware autonomous width disable" "0,1" newline bitfld.long 0x0 8. "EN_CLK_POWER_MAN,Enable clock power management" "0,1" newline bitfld.long 0x0 7. "EXTENDED_SYNCH,Extended synch" "0,1" newline bitfld.long 0x0 6. "COMMON_CLK_CONFIG,Common clock configuration" "0,1" newline bitfld.long 0x0 3. "RCB,Read Completion Boundary (RCB)" "0: 64 byte,1: 128 byte" newline bitfld.long 0x0 0.--1. "ASPM_CONTROL,Active State Power Management (ASPM) control" "0: Disabled,1: L0s entry enabled,2: L1 entry enabled,3: L0s and L1 entry enabled" rgroup.long 0x94++0x3 line.long 0x0 "DEVICE_CAPABILITIES2_REG,Device capabilities 2" bitfld.long 0x0 18.--19. "PCIE_CAP_OBFF_SUPPORT,(OBFF) Optimized Buffer Flush/fill Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" newline bitfld.long 0x0 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1" newline bitfld.long 0x0 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1" newline bitfld.long 0x0 14.--15. "PCIE_CAP2_LN_SYS_CLS,LN System CLS. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No Relaxed Ordering Enabled PR-PR Passing. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 9. "PCIE_CAP_128_CAS_CPL_SUPP,128 Bit CAS Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64 Bit AtomicOp Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32 Bit AtomicOp Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,Atomic Operation Routing Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x98++0x3 line.long 0x0 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device control 2 and status 2" rbitfld.long 0x0 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable" "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable" "0: Enable completion timeout,1: Disable completion timeout" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value" rgroup.long 0x9C++0x3 line.long 0x0 "LINK_CAPABILITIES_2,Link capabilities 2" bitfld.long 0x0 8. "CROSSLINK_SUPPORTED,Crosslink supported" "0: The meaning depends on the port speed as..,1: The associated port supports crosslinks." newline hexmask.long.byte 0x0 1.--7. 1. "SUPPORT_LINK_SPEED_VECTOR,Support_Link_Speed_Vector" group.long 0xA0++0x3 line.long 0x0 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 And Status 2" rbitfld.long 0x0 31. "DRS_MESSAGE_RECEIVED,DRS Message Received" "0,1" newline rbitfld.long 0x0 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence" "0,1,2,3,4,5,6,7" newline eventfld.long 0x0 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0GT/s" "0,1" newline rbitfld.long 0x0 20. "PCIE_CAP_EQ_CPL_P3,Equalization 8.0GT/s Phase 3 Successful" "0,1" newline rbitfld.long 0x0 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0GT/s Phase 2 Successful" "0,1" newline rbitfld.long 0x0 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0GT/s Phase 1 Successful" "0,1" newline rbitfld.long 0x0 17. "PCIE_CAP_EQ_CPL,Equalization 8.0GT/s Complete" "0,1" newline rbitfld.long 0x0 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s" newline bitfld.long 0x0 11. "PCIE_CAP_COMPLIANCE_SOS,Sets Compliance Skip Ordered Sets transmission." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance" "0,1" newline bitfld.long 0x0 7.--9. "PCIE_CAP_TX_MARGIN,Controls Transmit Margin for Debug or Compliance" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis For 5 GT/s" "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance Mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed" group.long 0xB0++0x3 line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control" bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable" "0,1" newline bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size" newline hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID" rgroup.long 0xB4++0x7 line.long 0x0 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset And BIR" hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table Bar Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is.." "0,1,2,3,4,5,6,7" line.long 0x4 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset And BIR" hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline bitfld.long 0x4 0.--2. "PCI_MSIX_PBA,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." "0,1,2,3,4,5,6,7" rgroup.long 0x100++0x3 line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header" hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." group.long 0x104++0x17 line.long 0x0 "UNCORR_ERR_STATUS_OFF,Uncorrectable error status" eventfld.long 0x0 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" newline eventfld.long 0x0 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status" "0,1" newline eventfld.long 0x0 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "UNCORR_ERR_MASK_OFF,Uncorrectable error mask" rbitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note:.." "0,1" newline rbitfld.long 0x4 24. "ATOMIC_EGRESS_BLOCKED_ERR_MASK,AtomicOp Egress Block Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This register field is sticky." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x4 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x8 "UNCORR_ERR_SEV_OFF,Uncorrectable error severity" rbitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" newline rbitfld.long 0x8 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R/W (sticky).." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This register field is sticky." "0,1" newline bitfld.long 0x8 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0xC "CORR_ERR_STATUS_OFF,Correctable error status" eventfld.long 0xC 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory non-fatal error status" "0,1" newline eventfld.long 0xC 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x10 "CORR_ERR_MASK_OFF,Correctable error mask" bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x14 "ADV_ERR_CAP_CTRL_OFF,Advanced error capabilities and control" rbitfld.long 0x14 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long 0x11C++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long 0x138++0x17 line.long 0x0 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1." hexmask.long.byte 0x0 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header." hexmask.long.word 0x10 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.byte 0x10 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.word 0x10 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register.." line.long 0x14 "LINK_CONTROL3_REG,Link control 3" bitfld.long 0x14 1. "EQ_REQ_INT_EN,Link equalization request interrupt enable" "0,1" newline bitfld.long 0x14 0. "PERFORM_EQ,Perform equalization" "0,1" group.long 0x150++0x3 line.long 0x0 "LANE_ERR_STATUS_REG,Lane error status" eventfld.long 0x0 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" rgroup.long 0x154++0xB line.long 0x0 "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control For Lanes 1 And 0" bitfld.long 0x0 28.--30. "USP_RX_PRESET_HINT1,Upstream port 8.0 GT/s receiver preset hint 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "USP_TX_PRESET1,Upstream port 8.0 GT/s transmitter preset 1" newline bitfld.long 0x0 20.--22. "DSP_RX_PRESET_HINT1,Downstream port 8.0 GT/s receiver preset hint 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "DSP_TX_PRESET1,Downstream port 8.0 GT/s transmitter preset 1" newline bitfld.long 0x0 12.--14. "USP_RX_PRESET_HINT0,Upstream port 8.0 GT/s receiver preset hint 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "USP_TX_PRESET0,Upstream port 8.0 GT/s transmitter preset 0" newline bitfld.long 0x0 4.--6. "DSP_RX_PRESET_HINT0,Downstream port 8.0 GT/s receiver preset hint 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "DSP_TX_PRESET0,Downstream port 8.0 GT/s transmitter preset 0" line.long 0x4 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header." hexmask.long.word 0x4 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." line.long 0x8 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header." hexmask.long.word 0x8 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x8 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x8 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x160++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control" hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select" newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "0: no change,1: per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "0: no change,1: per clear,?,?" rgroup.long 0x164++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event counter data" hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long 0x168++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control" hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select" newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select" newline bitfld.long 0x0 0. "TIMER_START,Timer Start" "0: Stop,1: Start/restart" rgroup.long 0x16C++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-Based Analysis Data" hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time-Based Analysis Data" group.long 0x188++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable" bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error)." hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error)" hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error)." bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error)" bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error Injection Count" line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error)." hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error)." bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "0: Generates duplicate TLPs by handling ACK DLLP as..,1: Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0)." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1)." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2)." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3)." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0)." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1)." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2)." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3)." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0)." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1)." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2)." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3)." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0)." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1)." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2)." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3)." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error)." bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "0: TLP Header,1: TLP Prefix 1st 4-DWORDs,2: TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long 0x1F8++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1" bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0: 40ns,1: 160ns,2: 320ns,3: 640ns Note: This register field is sticky" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification." "0: 2,1: 8,2: 16,3: 32 Note: This register field is sticky" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2" bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long 0x208++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status (Layer1 Per-lane)" hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status (Layer1 LTSSM)" hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline eventfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer" line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status (PM)" hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline eventfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long 0x214++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status (Layer2)" bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long 0x218++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon debug status (layer3 FC)" hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit data1" newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit data0" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit select(header data)" "0: Header credit,1: Data credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit select (TLP type)" "0: Posted,1: Non-posted,2: Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit select (credit type)" "0: Rx,1: Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit select (VC)" "0,1,2,3,4,5,6,7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status (Layer3)" eventfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long 0x228++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1" hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0: 500ns,1: 1us,?,?" newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0: 32ms,1: 56ms,?,?" newline bitfld.long 0x0 4. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed -.." "0: 8,1: 16" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2" bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. Note: This register field is sticky." newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3" bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." rgroup.long 0x238++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1" bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "0: Equalization is not attempted,1: Equalization finished successfully,2: Equalization finished unsuccessfully,3: Reserved This bit is automatically cleared when.." newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2" hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3" hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." rgroup.long 0x258++0x7 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended Capability ID. Capability Version. And Next Capability Offset" hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." line.long 0x4 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header." hexmask.long.word 0x4 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long 0x260++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control." bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control" hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "0: counters are frozen The counters are enabled by..,1: counters increment when the controller detects a.." newline eventfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long 0x268++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long 0x26C++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "0: counters are frozen The counters are enabled by..,1: enables the counters to increment on detected.." newline eventfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long 0x270++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long 0x274++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "0: none,1: 1-bit,2: 2-bit,?" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long 0x278++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations" hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations" hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." group.long 0x280++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable" bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode" eventfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long 0x288++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected" hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected" hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." group.long 0x700++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack latency timer and replay timer" hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor-specific DLLP" hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type -.." line.long 0x8 "PORT_FORCE_OFF,Port force link" hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline eventfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control" bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "0: Core enters ASPM L1 only after idle period..,1: Core enters ASPM L1 after a period in which it.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used .." "0: 1 us,1: 2 us,?,?,?,?,?,?" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us Note: This register field is sticky." "0: 1 us,1: 2 us,?,?,?,?,?,?" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS" newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature is turned off. The controller schedules a low-priority ACK DLLP.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control" bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link mode enable" newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline eventfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew" bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "GEN34_ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode in Gen3 or Gen4 rate: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode This register bit only affects Gen3 or Gen4 operating rate. For Gen1 or Gen2 operating rate the.." "0: Nominal Half Full Buffer mode,1: Nominal Empty Buffer Mode This register bit only.." newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer control and max function number" bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling.." "0: Scaling Factor is 1024,1: Scaling Factor is 256,2: Scaling Factor is 64,3: Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack latency timer modifier" newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay timer limit modifier" newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request" line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer and Filter Mask 1" hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1" newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2" hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2" line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control" bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. You.." "0,1" rgroup.long 0x728++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,Debug Field 0" line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,Debug Field 1" line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0 .." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long 0x73C++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline eventfld.long 0x0 15. "RX_SERIALIZATION_Q_READ_ERR,Receive Serialization Read Error. Indicates the serialization queue has attempted to read an incorrectly formatted TLP." "0,1" newline eventfld.long 0x0 14. "RX_SERIALIZATION_Q_WRITE_ERR,Receive Serialization Queue Write Error. Indicates insufficient buffer space available to write to the serialization queue." "0,1" newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline eventfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long 0x740++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: R" group.long 0x748++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "0: Round robin Note: This register field is sticky,1: Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "0: Strict ordering: posted,1: PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register.." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This.." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register.." group.long 0x80C++0x3 line.long 0x0 "GEN2_CTRL_OFF,Link Width And Speed Change Control" bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "0: Use RxElecIdle signal to infer Electrical Idle,1: Use RxValid signal to infer Electrical Idle.." newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This.." "0: -6 dB,1: -3" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing Note: The access attributes of this field are as.." "0: Full Swing,1: Low Swing Note: The access attributes of this.." newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto Flipping Of The Lanes" "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane For Auto Flip" "0: Connect logical Lane0 to physical lane 0 or 1..,1: Connect logical Lane0 to physical lane 1,2: Connect logical Lane0 to physical lane 3,3: Connect logical Lane0 to physical lane 7,4: Connect logical Lane0 to physical lane 15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long 0x810++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY status" hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY status" group.long 0x814++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY control" hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long 0x81C++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable target map control" hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: RSVDP" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: RSVDP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) address" hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,iMRM address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register; and.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,iMRM Upper Address" hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,iMRM upper address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,iMRM Interrupt #0 Enable" hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt #0 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,iMRM Interrupt #0 Mask" hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt #0 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,iMRM Interrupt #0 Status" hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt #0 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,iMRM Interrupt #1 Enable" hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt #1 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,iMRM Interrupt #1 Mask" hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt #1 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,iMRM Interrupt #1 Status" hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt #1 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,iMRM Interrupt #2 Enable" hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt #2 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,iMRM Interrupt #2 Mask" hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt #2 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,iMRM Interrupt #2 Status" hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt #2 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,iMRM Interrupt #3 Enable" hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt #3 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,iMRM Interrupt #3 Mask" hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt #3 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,iMRM Interrupt #3 Status" hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt #3 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,iMRM Interrupt #4 Enable" hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt #4 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,iMRM Interrupt #4 Mask" hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt #4 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,iMRM Interrupt #4 Status" hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt #4 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,iMRM Interrupt #5 Enable" hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt #5 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,iMRM Interrupt #5 Mask" hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt #5 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,iMRM Interrupt #5 Status" hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt #5 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,iMRM Interrupt #6 Enable" hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt #6 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,iMRM Interrupt #6 Mask" hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt #6 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,iMRM Interrupt #6 Status" hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt #6 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,iMRM Interrupt #7 Enable" hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt #7 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,iMRM Interrupt #7 Mask" hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt #7 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,iMRM Interrupt #7 Status" hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt #7 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,iMRM general-purpose IO" hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,RADM clock gating enable control" bitfld.long 0x70 0. "RADM_CLK_GATING_EN,Enable Radm clock gating feature. - 0: Disable - 1: Enable(default)" "0: Disable,1: Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 control" bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable." "0,1" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable" "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable" "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable" "0,1" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,Assert RxEqEval" "0: mac_phy_rxeqeval asserts after 1us and 2 TS1..,1: mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable" "0,1" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable" "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable" "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 And Phase 3 Disable" "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler For Gen3 and Gen4 Data Rate" "0,1" newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant" "0: The receiver complies with the ZRX-DC parameter..,1: The receiver does not comply with the ZRX-DC.." group.long 0x8A8++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control" bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "0: Do not request,1: request Note: Gen3 and Gen4 share the same.." newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM" "0: Do not include,1: Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "0: not support,1: support Note: Gen3 and Gen4 share the same.." newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable" "0: Abort the current evaluation stop any attempt to..,1: ignore the 2ms timeout and continue as normal." newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (When Optimal Settings Are Not Found)" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode" line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control" hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture For C+1" newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture For C-1" newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth" newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase" group.long 0x8B4++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order rule control" hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE loopback control" bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable" bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4)" "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,Suppress" "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status will be generated for.." "0: The controller drops all incoming I/O or MEM..,1: The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write To Read-Only Fields Using DBI" "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,Up-configure multi-lane control" bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY interoperability control" bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1. Note: This register field is sticky." "0: Controller requests aux_clk switch and core_clk..,1: Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access attributes of this field are as.." "0: Core waits for the PHY to acknowledge transition..,1: Core does not wait for PHY to acknowledge.." newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS and.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control" eventfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link reset request flush control" hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response" hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping" "0: OKAY,1: OKAY with all FFFF_FFFF data for all CRS..,2: OKAY with FFFF_0001 data for CRS completions to..,3: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping" "0: OKAY (with FFFF data),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping" "0: OKAY (with FFFF data for non-posted requests),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout" bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control" bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward To The Application" "0: The zero-length read terminates at the PCIe AXI..,1: The zero-length read is forwarded to the.." newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector" "0: B'last event: wait for the all of the write..,1: AW'last event: wait until the complete Posted..,?,?" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable" "0,1" group.long 0x8E0++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "0: lower = Peripheral,1: lower = Memory type" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline bitfld.long 0x8 24.--25. "CFG_MSTR_AWDOMAIN_VALUE,Master Write DOMAIN Signal Value. Value of the individual bits in mstr_awdomain when CFG_MSTR_AWDOMAIN_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awdomain is always '11' Note:.." "0,1,2,3" newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline bitfld.long 0x8 16.--17. "CFG_MSTR_ARDOMAIN_VALUE,Master Read DOMAIN Signal Value. Value of the individual bits in mstr_ardomain when CFG_MSTR_ARDOMAIN_MODE is '1' Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline bitfld.long 0x8 8.--9. "CFG_MSTR_AWDOMAIN_MODE,Master Write DOMAIN Signal Behavior. Defines how the individual bits in mstr_awdomain[1:0] are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWDOMAIN_VALUE field.." "0: set automatically by the AXI master,1: set by the value of the corresponding bit of the..,?,?" newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." newline bitfld.long 0x8 0.--1. "CFG_MSTR_ARDOMAIN_MODE,Master Read DOMAIN Signal Behavior. Defines how the individual bits in mstr_ardomain[1:0] are controlled: - 0: set automatically by the AXI master - 1: set the value of the corresponding bit of the CFG_MSTR_ARDOMAIN_VALUE field.." "0: set automatically by the AXI master,1: set the value of the corresponding bit of the..,?,?" group.long 0x8F0++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long 0x8F8++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long 0x930++0xB line.long 0x0 "INTERFACE_TIMER_CONTROL_OFF,Interface Timer Control" bitfld.long 0x0 4. "FORCE_PENDING,Writing to this bit forces the value of the pending flags. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2.--3. "INTERFACE_TIMER_SCALING,Interface timer scaling. This field can be used to reduce the timer duration for verification purpose. This field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 1. "INTERFACE_TIMER_AER_EN,Interface timer AER generation enable. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "INTERFACE_TIMER_EN,Interface timer enable. Note: This register field is sticky." "0,1" line.long 0x4 "INTERFACE_TIMER_TARGET_OFF,Interface Timer Target" hexmask.long.word 0x4 0.--15. 1. "INTERFACE_TIMER_TARGET,Interface timer target value. This field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register field is sticky." line.long 0x8 "INTERFACE_TIMER_STATUS_OFF,Interface Timer Status Register." eventfld.long 0x8 11. "SLAVE_RD_ADD_TIMEOUT,Slave read address channel timeout." "0,1" newline eventfld.long 0x8 10. "SLAVE_WR_DATA_TIMEOUT,Slave write data channel timeout." "0,1" newline eventfld.long 0x8 9. "SLAVE_WR_ADD_TIMEOUT,Slave write address channel timeout." "0,1" newline eventfld.long 0x8 6. "MASTER_RD_DATA_TIMEOUT,Master read data channel timeout." "0,1" newline eventfld.long 0x8 5. "MASTER_WR_RES_TIMEOUT,Master write response channel timeout." "0,1" newline eventfld.long 0x8 4. "CLIENT2_INTERFACE_TIMEOUT,Client2 interface timeout." "0,1" newline eventfld.long 0x8 3. "CLIENT1_INTERFACE_TIMEOUT,Client1 interface timeout." "0,1" newline eventfld.long 0x8 1. "CPL_INTERFACE_TIMEOUT,CPL interface timeout." "0,1" newline eventfld.long 0x8 0. "MESSAGE_INTERFACE_TIMEOUT,Message interface timeout." "0,1" group.long 0x940++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low" hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High" hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long 0x948++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell" bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long 0x94C++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM Power Mode And Debug Control" hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long 0x960++0x7 line.long 0x0 "SAFETY_MASK_OFF,Masks for functional safety interrupt events." bitfld.long 0x0 5. "SAFETY_INT_MASK_5,Mask for functional safety interrupt event 5 (RASDP correctable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "SAFETY_INT_MASK_4,Mask for functional safety interrupt event 4 (PCIe correctable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "SAFETY_INT_MASK_3,Mask for functional safety interrupt event 3 (PCIe uncorrectable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "SAFETY_INT_MASK_2,Mask for functional safety interrupt event 2 (Interface timers). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "SAFETY_INT_MASK_1,Mask for functional safety interrupt event 1 (CDM register checker). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "SAFETY_INT_MASK_0,Mask for functional safety interrupt event 0 (RASDP). Note: This register field is sticky." "0,1" line.long 0x4 "SAFETY_STATUS_OFF,Status for functional safety interrupt events." eventfld.long 0x4 5. "SAFETY_INT_STATUS_5,Status for functional safety interrupt event 5 (RASDP correctable)." "0,1" newline eventfld.long 0x4 4. "SAFETY_INT_STATUS_4,Status for functional safety interrupt event 4 (PCIe correctable)." "0,1" newline eventfld.long 0x4 3. "SAFETY_INT_STATUS_3,Status for functional safety interrupt event 3 (PCIe uncorrectable)." "0,1" newline eventfld.long 0x4 2. "SAFETY_INT_STATUS_2,Status for functional safety interrupt event 2 (Interface timers)." "0,1" newline eventfld.long 0x4 1. "SAFETY_INT_STATUS_1,Status for functional safety interrupt event 1 (CDM register checker)." "0,1" newline eventfld.long 0x4 0. "SAFETY_INT_STATUS_0,Status for functional safety interrupt event 0 (RASDP)." "0,1" group.long 0xB20++0x7 line.long 0x0 "PL_CHK_REG_CONTROL_STATUS_OFF,CDM Register Checking Control and Status" eventfld.long 0x0 18. "CHK_REG_COMPLETE,The system has completed a checking cycle." "0,1" newline eventfld.long 0x0 17. "CHK_REG_LOGIC_ERROR,The system has detected an error in its own checking logic." "0,1" newline eventfld.long 0x0 16. "CHK_REG_COMPARISON_ERROR,The system has detected that there is a bit error in the CDM Register Data." "0,1" newline bitfld.long 0x0 1. "CHK_REG_CONTINUOUS,Set Continuous Checking Sequence. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "CHK_REG_START,Begins a checking sequence. Note: This register field is sticky." "0,1" line.long 0x4 "PL_CHK_REG_START_END_OFF,CDM Register Checking First and Last address to check." hexmask.long.word 0x4 16.--31. 1. "CHK_REG_END_ADDR,The last address that is checked by the system. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "CHK_REG_START_ADDR,The first address that is checked by the system. Note: This register field is sticky." rgroup.long 0xB28++0x7 line.long 0x0 "PL_CHK_REG_ERR_ADDR_OFF,CDM Register Checking Error Address." hexmask.long 0x0 0.--31. 1. "CHK_REG_ERR_ADDR,The address at which an error has been detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." line.long 0x4 "PL_CHK_REG_ERR_PF_VF_OFF,CDM Register Checking error PF and VF Numbers." hexmask.long.word 0x4 16.--27. 1. "CHK_REG_VF_ERR_NUMBER,The VF number at which the error was detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--4. 1. "CHK_REG_PF_ERR_NUMBER,The PF number at which the error was detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." group.long 0xB40++0x3 line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control" hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x20010)++0x3 line.long 0x0 "BAR_MASK[$1],BARn Mask" hexmask.long 0x0 1.--31. 1. "PCI_TYPE0_BAR0_MASK,BAR0 Mask" newline bitfld.long 0x0 0. "PCI_TYPE0_BAR0_ENABLED,BAR0 Mask Enabled" "0: Disabled,1: Enabled" repeat.end group.long 0x60000++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60020++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60100++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_0,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Start Address High" newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Start Address Low" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60120++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60200++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_1,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60220++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60300++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_1,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_1,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Start Address High" newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Start Address Low" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_1,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60320++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60400++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_2,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60420++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60500++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_2,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_2,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Start Address High" newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Start Address Low" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_2,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60520++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60600++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_3,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60620++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60700++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_3,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_3,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Start Address High" newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Start Address Low" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_3,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60720++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60800++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_4,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_4,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60820++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60A00++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_5,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_5,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60A20++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." tree.end tree "PCIE_RC" rgroup.long 0x0++0x3 line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID And Vendor ID" hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID" newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID" group.long 0x4++0x3 line.long 0x0 "TYPE1_STATUS_COMMAND_REG,Status and Command" eventfld.long 0x0 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline eventfld.long 0x0 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline eventfld.long 0x0 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline eventfld.long 0x0 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline eventfld.long 0x0 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x0 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline eventfld.long 0x0 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x0 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x0 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x0 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x0 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x0 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline bitfld.long 0x0 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x0 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x0 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Specification." "0,1" newline rbitfld.long 0x0 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x0 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x0 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x0 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x0 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x0 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code And Revision ID" hexmask.long.byte 0x0 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x0 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x0 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x0 0.--7. 1. "REVISION_ID,Revision ID" group.long 0xC++0x3 line.long 0x0 "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size" hexmask.long.byte 0x0 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0x0 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0x0 16.--22. 1. "HEADER_TYPE,Header Layout" newline hexmask.long.byte 0x0 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0x0 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." group.long 0x18++0xF line.long 0x0 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number" hexmask.long.byte 0x0 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x0 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x0 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x0 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x4 "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. I/O Limit. And Base" eventfld.long 0x4 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline eventfld.long 0x4 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline eventfld.long 0x4 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline eventfld.long 0x4 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline eventfld.long 0x4 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline eventfld.long 0x4 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline hexmask.long.byte 0x4 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x4 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x4 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 8. "IO_DECODE_BIT8,I/O Addressing Encode (I/O Limit Address)" "0: The bridge supports only 16-bit I/O addressing..,1: The bridge supports 32-bit I/O address decoding." newline hexmask.long.byte 0x4 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x4 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 0. "IO_DECODE,I/O addressing encode (I/O base address)" "0: The bridge supports only 16-bit I/O addressing..,1: The bridge supports 32-bit I/O address decoding.." line.long 0x8 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base" hexmask.long.word 0x8 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x8 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x8 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x8 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0xC "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit And Base" hexmask.long.word 0xC 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0xC 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. The value of PREF_MEM_LIMIT_DECODE indicates the following: - 0b: Indicates that the bridge supports only 32 bit addresses - 1b:.." "0,1" newline hexmask.long.word 0xC 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0xC 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode" "0: The bridge supports only 32-bit addresses.,1: The bridge supports 64 bit addresses;.." rgroup.long 0x28++0xF line.long 0x0 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits" hexmask.long 0x0 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit" line.long 0x4 "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits" hexmask.long 0x4 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit" line.long 0x8 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit And Base Upper 16 Bits" hexmask.long.word 0x8 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x8 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." line.long 0xC "TYPE1_CAP_PTR_REG,Capabilities Pointer" hexmask.long.byte 0xC 0.--7. 1. "CAP_POINTER,Capabilities Pointer" group.long 0x38++0x7 line.long 0x0 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address" hexmask.long.tbyte 0x0 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline bitfld.long 0x0 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x4 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. And Interrupt Line" hexmask.long.word 0x4 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x4 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x4 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x4 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x4 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely .." "0,1" newline bitfld.long 0x4 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "0,1" newline bitfld.long 0x4 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x4 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "INT_PIN,Interrupt PIN" newline hexmask.long.byte 0x4 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." rgroup.long 0x40++0x3 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities" hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,Power Management Event Support" newline bitfld.long 0x0 26. "D2_SUPPORT,D2 State Support" "0,1" newline bitfld.long 0x0 25. "D1_SUPPORT,D1 State Support" "0,1" newline bitfld.long 0x0 22.--24. "AUX_CURR,Auxiliary Current Requirements" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization" "0,1" newline bitfld.long 0x0 19. "PME_CLK,PCI Clock Requirement" "0,1" newline bitfld.long 0x0 16.--18. "PM_SPEC_VER,Power Management Spec Version" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Power Management Capability ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x44++0x3 line.long 0x0 "CON_STATUS_REG,Power Management Control And Status" hexmask.long.byte 0x0 24.--31. 1. "DATA_REG_ADD_INFO,Power data information" newline rbitfld.long 0x0 23. "BUS_PWR_CLK_CON_EN,Bus power/clock control enable" "0,1" newline rbitfld.long 0x0 22. "B2_B3_SUPPORT,B2B3 support for D3hot" "0,1" newline eventfld.long 0x0 15. "PME_STATUS,PME status" "0,1" newline rbitfld.long 0x0 13.--14. "DATA_SCALE,Data scaling factor" "0,1,2,3" newline hexmask.long.byte 0x0 9.--12. 1. "DATA_SELECT,Data select" newline bitfld.long 0x0 8. "PME_ENABLE,PME enable" "0,1" newline rbitfld.long 0x0 3. "NO_SOFT_RST,No Soft Reset" "0,1" newline bitfld.long 0x0 0.--1. "POWER_STATE,Power State" "0,1,2,3" group.long 0x50++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID. Next Pointer. Capability And Control" rbitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended message data enable" "0,1" newline rbitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable" "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,MSI Per Vector Masking Capable" "0,1" newline rbitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,MSI 64-bit Address Capable" "0,1" newline bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,MSI Multiple Message Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,MSI Multiple Message Capable" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,MSI Capability Next Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,MSI Capability ID. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x4 "MSI_CAP_OFF_04H_REG,MSI message lower address" hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,MSI Message Lower Address Field. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x8 "MSI_CAP_OFF_08H_REG,Data or upper address" hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a 32 bit MSI Message this field contains Ext MSI Data. For 64-bit it contains upper 16 bits of the Upper Address. For a description of this standard PCIe register field see the PCI Express Specification Note: The access.." newline hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a 32-bit MSI Message this field contains Data. For 64-bit it contains lower 16 bits of the Upper Address. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of.." line.long 0xC "MSI_CAP_OFF_0CH_REG,Data or mask bits" hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a 64-bit MSI Message this field contains Data. For 32-bit it contains the upper Mask Bits if PVM is enabled. For a description of this standard PCIe register field see the PCI Express Specification Note: The access attributes.." newline hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a 64-bit MSI Message this field contains Data. For 32-bit it contains the lower Mask Bits if PVM is enabled. For a description of this standard PCIe register field see the PCI Express Specification Note: The access attributes.." line.long 0x10 "MSI_CAP_OFF_10H_REG,Pending or Mask Bits" hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when Vector Masking Capable. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this.." rgroup.long 0x64++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits" hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Used for MSI 64-bit messaging when Vector Masking Capable. Contains Pending Bits. For a description of this standard PCIe register field see the PCI Express Specification." rgroup.long 0x70++0x7 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer" bitfld.long 0x0 30. "RSVD,Reserved. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIe Interrupt Message Number" newline bitfld.long 0x0 24. "PCIE_SLOT_IMP,PCIe Slot Implemented Valid" "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,PCIe device/port type" newline hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,PCIE Capability Version Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,PCIE Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,PCIE Capability ID. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities" bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-based Error Reporting Implemented. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max Payload Size Supported. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is.." "0,1,2,3,4,5,6,7" group.long 0x78++0x3 line.long 0x0 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status" rbitfld.long 0x0 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 20. "PCIE_CAP_AUX_POWER_DETECTED,Aux Power Detected Status. For a description of this standard PCIe register field see the PCI Express Specification. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" newline eventfld.long 0x0 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (for endpoints). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max Read Request Size. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux power PM enable" "0,1" newline rbitfld.long 0x0 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom functions enable" "0,1" newline rbitfld.long 0x0 8. "PCIE_CAP_EXT_TAG_EN,Extended tag field enable" "0,1" newline bitfld.long 0x0 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long 0x7C++0x3 line.long 0x0 "LINK_CAPABILITIES_REG,Link Capabilities" hexmask.long.byte 0x0 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." "0,1" newline bitfld.long 0x0 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x0 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock power management" "0,1" newline bitfld.long 0x0 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,LOs exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Level of ASPM (Active State Power Management) Support. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No.." "0,1,2,3" newline hexmask.long.byte 0x0 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum link width" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Maximum link speed" group.long 0x80++0x3 line.long 0x0 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status" eventfld.long 0x0 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. For a description of this standard PCIe register field see the PCI Express Specification. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG." "0,1" newline eventfld.long 0x0 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. For a description of this standard PCIe register field see the PCI Express Specification. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG." "0,1" newline rbitfld.long 0x0 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Active. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration" "0,1" newline rbitfld.long 0x0 27. "PCIE_CAP_LINK_TRAINING,LTSSM is in Configuration or Recovery State. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. For a description of this standard PCIe register field see the PCI Express Specification." newline rbitfld.long 0x0 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS signaling control" "0,1,2,3" newline rbitfld.long 0x0 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link autonomous bandwidth management interrupt enable" "0,1" newline rbitfld.long 0x0 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link bandwidth management interrupt enable" "0,1" newline bitfld.long 0x0 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline rbitfld.long 0x0 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. For a description of this standard PCIe register field see the PCI Express Specification. The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The.." "0,1" newline bitfld.long 0x0 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 5. "PCIE_CAP_RETRAIN_LINK,Initiate link retrain" "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_LINK_DISABLE,Initiate link disable" "0,1" newline rbitfld.long 0x0 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB)" "0,1" newline bitfld.long 0x0 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. Software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s; otherwise the result is undefined. For a.." "0,1,2,3" rgroup.long 0x84++0x3 line.long 0x0 "SLOT_CAPABILITIES_REG,Slot Capabilities" hexmask.long.word 0x0 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1,2,3" newline hexmask.long.byte 0x0 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot Plug Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot Plug Surprise possible. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 2. "PCIE_CAP_MRL_SENSOR,MRL Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" group.long 0x88++0xB line.long 0x0 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status" eventfld.long 0x0 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline rbitfld.long 0x0 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 20. "PCIE_CAP_CMD_CPLD,Command Completed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" newline bitfld.long 0x0 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" newline bitfld.long 0x0 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot Plug Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Write value is gated with PCIE_CAP_NO_CMD_CPL_SUPPORT field in SLOT_CAPABILITIES_REG. Note: The access.." "0,1" newline bitfld.long 0x0 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities" rbitfld.long 0x4 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable" "0,1" newline rbitfld.long 0x4 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,Configuration request retry status (CRS) software visibility enable" "0,1" newline bitfld.long 0x4 3. "PCIE_CAP_PME_INT_EN,PME interrupt enable" "0,1" newline bitfld.long 0x4 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System error on fatal error enable" "0,1" newline bitfld.long 0x4 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System error on non-fatal error enable" "0,1" newline bitfld.long 0x4 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System error on correctable error enable" "0,1" line.long 0x8 "ROOT_STATUS_REG,Root Status" rbitfld.long 0x8 17. "PCIE_CAP_PME_PENDING,PME Pending. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x8 16. "PCIE_CAP_PME_STATUS,PME Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.word 0x8 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. For a description of this standard PCIe register field see the PCI Express Specification." rgroup.long 0x94++0x3 line.long 0x0 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2" bitfld.long 0x0 18.--19. "PCIE_CAP_OBFF_SUPPORT,(OBFF) Optimized Buffer Flush/fill Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" newline bitfld.long 0x0 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1" newline bitfld.long 0x0 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1" newline bitfld.long 0x0 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No Relaxed Ordering Enabled PR-PR Passing. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 9. "PCIE_CAP_128_CAS_CPL_SUPP,128 Bit CAS Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64 Bit AtomicOp Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32 Bit AtomicOp Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,Atomic Operation Routing Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x98++0x3 line.long 0x0 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2" rbitfld.long 0x0 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable" "0: Enable completion timeout,1: Disable completion timeout" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." rgroup.long 0x9C++0x3 line.long 0x0 "LINK_CAPABILITIES2_REG,Link Capabilities 2" bitfld.long 0x0 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Cross Link Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. For a description of this standard PCIe register field see the PCI Express Specification. This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED.." group.long 0xA0++0x3 line.long 0x0 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2" rbitfld.long 0x0 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline rbitfld.long 0x0 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1,2,3,4,5,6,7" newline eventfld.long 0x0 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0GT/s. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 20. "PCIE_CAP_EQ_CPL_P3,Equalization 8.0GT/s Phase 3 Successful. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0GT/s Phase 2 Successful. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0GT/s Phase 1 Successful. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PCIE_CAP_EQ_CPL,Equalization 8.0GT/s Complete. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. For a description of this standard PCIe register field see the PCI Express Specification. In C-PCIe mode its contents are derived by sampling the PIPE" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 11. "PCIE_CAP_COMPLIANCE_SOS,Sets Compliance Skip Ordered Sets transmission. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." "0,1" newline bitfld.long 0x0 7.--9. "PCIE_CAP_TX_MARGIN,Controls Transmit Margin for Debug or Compliance. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 6. "PCIE_CAP_SEL_DEEMPHASIS,Controls Selectable De-emphasis for 5 GT/s" "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance Mode. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long 0xB0++0x3 line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control" bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size" newline hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Specification." rgroup.long 0xB4++0x7 line.long 0x0 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR" hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table Bar Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is.." "0,1,2,3,4,5,6,7" line.long 0x4 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR" hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline bitfld.long 0x4 0.--2. "PCI_MSIX_PBA,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." "0,1,2,3,4,5,6,7" rgroup.long 0x100++0x3 line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header" hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." group.long 0x104++0x17 line.long 0x0 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status" eventfld.long 0x0 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" newline eventfld.long 0x0 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" newline eventfld.long 0x0 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask" rbitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. Note:.." "0,1" newline rbitfld.long 0x4 24. "ATOMIC_EGRESS_BLOCKED_ERR_MASK,AtomicOp Egress Block Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x4 5. "SURPRISE_DOWN_ERR_MASK,Surprise down error mask" "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x8 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity" rbitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" newline rbitfld.long 0x8 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note:.." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise down error severity (optional)" "0,1" newline bitfld.long 0x8 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0xC "CORR_ERR_STATUS_OFF,Correctable Error Status" eventfld.long 0xC 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x10 "CORR_ERR_MASK_OFF,Correctable Error Mask" bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x14 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control" rbitfld.long 0x14 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long 0x11C++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0" hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1" hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2" hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3" hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long 0x12C++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command" bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status" hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number" newline eventfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long 0x134++0x17 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification" hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2" hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3" hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4" hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x14 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header" hexmask.long.word 0x14 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.byte 0x14 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.word 0x14 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." group.long 0x14C++0x7 line.long 0x0 "LINK_CONTROL3_REG,Link control 3" bitfld.long 0x0 1. "EQ_REQ_INT_EN,Link equalization request interrupt enable" "0,1" newline bitfld.long 0x0 0. "PERFORM_EQ,Perform equalization" "0,1" line.long 0x4 "LANE_ERR_STATUS_REG,Lane Error Status" eventfld.long 0x4 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" rgroup.long 0x154++0xB line.long 0x0 "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register For Lanes 1 And 0" bitfld.long 0x0 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." newline bitfld.long 0x0 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." newline bitfld.long 0x0 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header" hexmask.long.word 0x4 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." line.long 0x8 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header" hexmask.long.word 0x8 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x8 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x8 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x160++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control" hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select" newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "0: no change,1: per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "0: no change,1: per clear,?,?" rgroup.long 0x164++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data" hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long 0x168++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control" hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select" newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select" newline bitfld.long 0x0 0. "TIMER_START,Timer Start" "0: Stop,1: Start/restart" rgroup.long 0x16C++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-Based Analysis Data" hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time-Based Analysis Data" group.long 0x188++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable" bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error)" hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error)" hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error)" bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error)" bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error Injection Count" line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error)" hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error)" bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "0: Generates duplicate TLPs by handling ACK DLLP as..,1: Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0)" hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1)" hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2)" hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3)" hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0)" hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1)" hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2)" hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3)" hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0)" hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1)" hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2)" hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3)" hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0)" hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1)" hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2)" hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3)" hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error)" bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "0: TLP Header,1: TLP Prefix 1st 4-DWORDs,2: TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long 0x1F8++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1" bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0: 40ns,1: 160ns,2: 320ns,3: 640ns Note: This register field is sticky" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification." "0: 2,1: 8,2: 16,3: 32 Note: This register field is sticky" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2" bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long 0x208++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status (Layer1 Per-lane)" hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status (Layer1 LTSSM)" hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline eventfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer" line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status (PM)" hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline eventfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long 0x214++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status (Layer2)" bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long 0x218++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status (Layer3 FC)" hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "0: Header Credit,1: Data Credit Note: This register field is sticky" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "0: Posted,1: Non-Posted,2: Completion Note: This register field is sticky,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "0: Rx,1: Tx Note: This register field is sticky" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "0: VC0,1: VC1,2: VC2,?,?,?,?,7: VC7 Note: This register field is sticky" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status (Layer3)" eventfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long 0x228++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1" hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0: 500ns,1: 1us,?,?" newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0: 32ms,1: 56ms,?,?" newline bitfld.long 0x0 4. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed -.." "0: 8,1: 16" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2" bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. Note: This register field is sticky." newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3" bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." rgroup.long 0x238++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1" bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event" "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation" "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation" "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info" "0,1,2,3" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence" "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2" hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3" hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." rgroup.long 0x258++0x7 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended Capability ID. Capability Version And Next Capability Offset" hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." line.long 0x4 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header" hexmask.long.word 0x4 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long 0x260++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control" bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control" hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "0: counters are frozen The counters are enabled by..,1: counters increment when the controller detects a.." newline eventfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long 0x268++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data" hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long 0x26C++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control" hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "0: counters are frozen The counters are enabled by..,1: enables the counters to increment on detected.." newline eventfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long 0x270++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data" hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long 0x274++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control" hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "0: none,1: 1-bit,2: 2-bit,?" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long 0x278++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations" hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations" hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." group.long 0x280++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable" bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode" eventfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long 0x288++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected" hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected" hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." group.long 0x700++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer" hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP" hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link" bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew for SRIS instead of using received SKP OS if DO_DESKEW_FOR_SRIS is set to 1. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline eventfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control" bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "0: Core enters ASPM L1 only after idle period..,1: Core enters ASPM L1 after a period in which it.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used .." "0: 1 us,1: 2 us,?,?,?,?,?,?" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us Note: This register field is sticky." "0: 1 us,1: 2 us,?,?,?,?,?,?" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS" newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature is turned off. The controller schedules a low-priority ACK DLLP.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control" bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable" newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline eventfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew" bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "GEN34_ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode in Gen3 or Gen4 rate: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode This register bit only affects Gen3 or Gen4 operating rate. For Gen1 or Gen2 operating rate the.." "0: Nominal Half Full Buffer mode,1: Nominal Empty Buffer Mode This register bit only.." newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number" bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling.." "0: Scaling Factor is 1024,1: Scaling Factor is 256,2: Scaling Factor is 64,3: Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay timer limit modifier" newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer and Filter Mask 1" hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1" newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2" hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2" line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control" bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests" "0,1" rgroup.long 0x728++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The bits in this field have the following meaning: Bits 31:26: Reserved Bit 25: Receiver is receiving logical idle Bit 24: 2n symbol is also idle (16bit PHY interface only) Bits 23:8: PIPE transmit data Bits 7:6: PIPE transmit K indication Bits.." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The bits in this field have the following meaning: Bit 31: Scrambling disabled for the link Bit 30: TSSM in DISABLE state; link inoperable Bit 29: LTSSM performing link training Bit 28: LTSSM is in Polling" line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0 .." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long 0x73C++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline eventfld.long 0x0 15. "RX_SERIALIZATION_Q_READ_ERR,Receive Serialization Read Error. Indicates the serialization queue has attempted to read an incorrectly formatted TLP." "0,1" newline eventfld.long 0x0 14. "RX_SERIALIZATION_Q_WRITE_ERR,Receive Serialization Queue Write Error. Indicates insufficient buffer space available to write to the serialization queue." "0,1" newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline eventfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long 0x740++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access." group.long 0x748++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control" bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "0: Round robin Note: This register field is sticky,1: Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "0: Strict ordering: posted,1: PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control" hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control" hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." group.long 0x80C++0x3 line.long 0x0 "GEN2_CTRL_OFF,Link Width And Speed Change Control" bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "0: Use RxElecIdle signal to infer Electrical Idle,1: Use RxValid signal to infer Electrical Idle.." newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." "0: -6 dB,1: -3" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing Note: The access attributes of this field are as.." "0: Full Swing,1: Low Swing Note: The access attributes of this.." newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto Flipping Of The Lanes" "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane For Auto Flip" "0: Connect logical Lane0 to physical lane 0 or 1..,1: Connect logical Lane0 to physical lane 1,2: Connect logical Lane0 to physical lane 3,3: Connect logical Lane0 to physical lane 7,4: Connect logical Lane0 to physical lane 15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long 0x810++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status" hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY status" group.long 0x814++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control" hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long 0x81C++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control" hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address" hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address" hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt #0 Enable" hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt #0 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt #0 Mask" hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt #0 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt #0 Status" hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt #0 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt #1 Enable" hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt #1 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt #1 Mask" hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt #1 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt #1 Status" hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt #1 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt #2 Enable" hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt #2 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt #2 Mask" hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt #2 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt #2 Status" hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt #2 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt #3 Enable" hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt #3 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt #3 Mask" hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt #3 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt #3 Status" hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt #3 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt #4 Enable" hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt #4 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt #4 Mask" hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt #4 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt #4 Status" hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt #4 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt #5 Enable" hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt #5 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt #5 Mask" hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt #5 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt #5 Status" hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt #5 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt #6 Enable" hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt #6 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt #6 Mask" hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt #6 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt #6 Status" hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt #6 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt #7 Enable" hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt #7 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt #7 Mask" hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt #7 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt #7 Status" hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt #7 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO" hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,RADM clock gating enable control" bitfld.long 0x70 0. "RADM_CLK_GATING_EN,Enable Radm clock gating feature. - 0: Disable - 1: Enable(default)" "0: Disable,1: Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control" bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable." "0,1" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable" "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable" "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable" "0,1" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request" "0: mac_phy_rxeqeval asserts after 1us and 2 TS1..,1: mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable" "0,1" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable" "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable" "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 And Phase 3 Disable" "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler For Gen3 and Gen4 Data Rate" "0,1" newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant" "0: The receiver complies with the ZRX-DC parameter..,1: The receiver does not comply with the ZRX-DC.." group.long 0x8A8++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control" bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "0: Do not request,1: request Note: Gen3 and Gen4 share the same.." newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM" "0: Do not include,1: Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "0: not support,1: support Note: Gen3 and Gen4 share the same.." newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable" "0: Abort the current evaluation stop any attempt to..,1: ignore the 2ms timeout and continue as normal." newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (When Optimal Settings Are Not Found)" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode" line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control" hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture For C+1" newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture For C-1" newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth" newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase" group.long 0x8B4++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control" hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control" bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable" bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). Simplified Replay Timer Values are: - A value from 24 000 to 31 000 Symbol Times when Extended Synch is 0b. - A value from 80 000 to 100 000 Symbol Times when Extended Synch is 1b. Must not.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,This field only applies to request TLPs (with UR filtering status) that you have chosen to forward to the application (when you set DEFAULT_TARGET in this register)" "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status will be generated for.." "0: The controller drops all incoming I/O or MEM..,1: The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write To Read-Only Fields Using DBI" "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control" bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control" bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1. Note: This register field is sticky." "0: Controller requests aux_clk switch and core_clk..,1: Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access attributes of this field are as.." "0: Core waits for the PHY to acknowledge transition..,1: Core does not wait for PHY to acknowledge.." newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS and.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control" eventfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control" hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response" hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping" "0: OKAY,1: OKAY with all FFFF_FFFF data for all CRS..,2: OKAY with FFFF_0001 data for CRS completions to..,3: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping" "0: OKAY (with FFFF data),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping" "0: OKAY (with FFFF data for non-posted requests),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout" bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control" bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward To The Application" "0: The zero-length read terminates at the PCIe AXI..,1: The zero-length read is forwarded to the.." newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector" "0: B'last event: wait for the all of the write..,1: AW'last event: wait until the complete Posted..,?,?" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable" "0,1" group.long 0x8E0++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "0: lower = Peripheral,1: lower = Memory type" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline bitfld.long 0x8 24.--25. "CFG_MSTR_AWDOMAIN_VALUE,Master Write DOMAIN Signal Value. Value of the individual bits in mstr_awdomain when CFG_MSTR_AWDOMAIN_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awdomain is always '11' Note:.." "0,1,2,3" newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline bitfld.long 0x8 16.--17. "CFG_MSTR_ARDOMAIN_VALUE,Master Read DOMAIN Signal Value. Value of the individual bits in mstr_ardomain when CFG_MSTR_ARDOMAIN_MODE is '1' Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline bitfld.long 0x8 8.--9. "CFG_MSTR_AWDOMAIN_MODE,Master Write DOMAIN Signal Behavior. Defines how the individual bits in mstr_awdomain[1:0] are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWDOMAIN_VALUE field.." "0: set automatically by the AXI master,1: set by the value of the corresponding bit of the..,?,?" newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." newline bitfld.long 0x8 0.--1. "CFG_MSTR_ARDOMAIN_MODE,Master Read DOMAIN Signal Behavior. Defines how the individual bits in mstr_ardomain[1:0] are controlled: - 0: set automatically by the AXI master - 1: set the value of the corresponding bit of the CFG_MSTR_ARDOMAIN_VALUE field.." "0: set automatically by the AXI master,1: set the value of the corresponding bit of the..,?,?" group.long 0x8F0++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to" hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to" hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long 0x8F8++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number" hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type" hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long 0x930++0xB line.long 0x0 "INTERFACE_TIMER_CONTROL_OFF,Interface Timer Control" bitfld.long 0x0 4. "FORCE_PENDING,Writing to this bit forces the value of the pending flags. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2.--3. "INTERFACE_TIMER_SCALING,Interface timer scaling. This field can be used to reduce the timer duration for verification purpose. This field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 1. "INTERFACE_TIMER_AER_EN,Interface timer AER generation enable. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "INTERFACE_TIMER_EN,Interface timer enable. Note: This register field is sticky." "0,1" line.long 0x4 "INTERFACE_TIMER_TARGET_OFF,Interface Timer Target" hexmask.long.word 0x4 0.--15. 1. "INTERFACE_TIMER_TARGET,Interface timer target value. This field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register field is sticky." line.long 0x8 "INTERFACE_TIMER_STATUS_OFF,Interface Timer Status" eventfld.long 0x8 11. "SLAVE_RD_ADD_TIMEOUT,Slave read address channel timeout." "0,1" newline eventfld.long 0x8 10. "SLAVE_WR_DATA_TIMEOUT,Slave write data channel timeout." "0,1" newline eventfld.long 0x8 9. "SLAVE_WR_ADD_TIMEOUT,Slave write address channel timeout." "0,1" newline eventfld.long 0x8 6. "MASTER_RD_DATA_TIMEOUT,Master read data channel timeout." "0,1" newline eventfld.long 0x8 5. "MASTER_WR_RES_TIMEOUT,Master write response channel timeout." "0,1" newline eventfld.long 0x8 4. "CLIENT2_INTERFACE_TIMEOUT,Client2 interface timeout." "0,1" newline eventfld.long 0x8 3. "CLIENT1_INTERFACE_TIMEOUT,Client1 interface timeout." "0,1" newline eventfld.long 0x8 1. "CPL_INTERFACE_TIMEOUT,CPL interface timeout." "0,1" newline eventfld.long 0x8 0. "MESSAGE_INTERFACE_TIMEOUT,Message interface timeout." "0,1" group.long 0x940++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low" hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High" hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long 0x948++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell" bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long 0x94C++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM Power Mode And Debug Control" hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long 0x960++0x7 line.long 0x0 "SAFETY_MASK_OFF,Masks for functional safety interrupt events" bitfld.long 0x0 5. "SAFETY_INT_MASK_5,Mask for functional safety interrupt event 5 (RASDP correctable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "SAFETY_INT_MASK_4,Mask for functional safety interrupt event 4 (PCIe correctable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "SAFETY_INT_MASK_3,Mask for functional safety interrupt event 3 (PCIe uncorrectable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "SAFETY_INT_MASK_2,Mask for functional safety interrupt event 2 (Interface timers). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "SAFETY_INT_MASK_1,Mask for functional safety interrupt event 1 (CDM register checker). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "SAFETY_INT_MASK_0,Mask for functional safety interrupt event 0 (RASDP). Note: This register field is sticky." "0,1" line.long 0x4 "SAFETY_STATUS_OFF,Status for functional safety interrupt events." eventfld.long 0x4 5. "SAFETY_INT_STATUS_5,Status for functional safety interrupt event 5 (RASDP correctable)." "0,1" newline eventfld.long 0x4 4. "SAFETY_INT_STATUS_4,Status for functional safety interrupt event 4 (PCIe correctable)." "0,1" newline eventfld.long 0x4 3. "SAFETY_INT_STATUS_3,Status for functional safety interrupt event 3 (PCIe uncorrectable)." "0,1" newline eventfld.long 0x4 2. "SAFETY_INT_STATUS_2,Status for functional safety interrupt event 2 (Interface timers)." "0,1" newline eventfld.long 0x4 1. "SAFETY_INT_STATUS_1,Status for functional safety interrupt event 1 (CDM register checker)." "0,1" newline eventfld.long 0x4 0. "SAFETY_INT_STATUS_0,Status for functional safety interrupt event 0 (RASDP)." "0,1" group.long 0xB20++0x7 line.long 0x0 "PL_CHK_REG_CONTROL_STATUS_OFF,CDM Register Checking Control and Status" eventfld.long 0x0 18. "CHK_REG_COMPLETE,The system has completed a checking cycle." "0,1" newline eventfld.long 0x0 17. "CHK_REG_LOGIC_ERROR,The system has detected an error in its own checking logic." "0,1" newline eventfld.long 0x0 16. "CHK_REG_COMPARISON_ERROR,The system has detected that there is a bit error in the CDM Register Data." "0,1" newline bitfld.long 0x0 1. "CHK_REG_CONTINUOUS,Set Continuous Checking Sequence. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "CHK_REG_START,Begins a checking sequence. Note: This register field is sticky." "0,1" line.long 0x4 "PL_CHK_REG_START_END_OFF,CDM Register Checking First and Last address to check" hexmask.long.word 0x4 16.--31. 1. "CHK_REG_END_ADDR,The last address that is checked by the system. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "CHK_REG_START_ADDR,The first address that is checked by the system. Note: This register field is sticky." rgroup.long 0xB28++0x7 line.long 0x0 "PL_CHK_REG_ERR_ADDR_OFF,CDM Register Checking Error Address." hexmask.long 0x0 0.--31. 1. "CHK_REG_ERR_ADDR,The address at which an error has been detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." line.long 0x4 "PL_CHK_REG_ERR_PF_VF_OFF,CDM Register Checking error PF and VF Numbers" hexmask.long.word 0x4 16.--27. 1. "CHK_REG_VF_ERR_NUMBER,The VF number at which the error was detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--4. 1. "CHK_REG_PF_ERR_NUMBER,The PF number at which the error was detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." group.long 0xB40++0x3 line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control" hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x20010)++0x3 line.long 0x0 "BAR_MASK[$1],BARn Mask" hexmask.long 0x0 1.--31. 1. "PCI_TYPE1_BAR0_MASK,BAR0 Mask" newline bitfld.long 0x0 0. "PCI_TYPE1_BAR0_ENABLED,BAR0 Mask Enabled" "0: Disabled,1: Enabled" repeat.end group.long 0x60000++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60020++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60100++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_0,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated. This field is sticky." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60120++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60200++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_1,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60220++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60300++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_1,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_1,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated. This field is sticky." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_1,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60320++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60400++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_2,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60420++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60500++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_2,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_2,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated. This field is sticky." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_2,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60520++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60600++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_3,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60620++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60700++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_3,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_3,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated. This field is sticky." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_3,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60720++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60800++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_4,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_4,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60820++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60A00++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_5,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_5,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60A20++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." tree.end tree.end tree "PERF_REGISTERS (Performance Monitor Register)" base ad:0x403E0000 group.long 0x0++0xF line.long 0x0 "COUNTER_0_CTRL_REG_ADDR,Counter control 0" bitfld.long 0x0 2. "CNTR_EN,Counter enable" "0: Disable (clock gated),1: Enable. If CNT_CLR is 1 the counter begins.." newline bitfld.long 0x0 1. "CNTR_CLR,Counter clear" "0: Set counter to 0 and clear counter overflow..,1: If the counter is enabled (CNTR_EN) the counter.." newline rbitfld.long 0x0 0. "CNTR_OFL,Counter overflow" "0: Expired (and no longer counting),1: Not expired (and still counting)" line.long 0x4 "COUNTER_1_CTRL_REG_ADDR,Counter control 1" hexmask.long.byte 0x4 24.--31. 1. "CSV,Count_value_select[7:0]" newline hexmask.long.byte 0x4 16.--23. 1. "COUNT_PR,Count_parameter[7:0]" newline bitfld.long 0x4 2. "CNTR_EN,Counter Enable" "0: Disable (clock gated),1: Enable." newline bitfld.long 0x4 1. "CNTR_CLR,Counter clear" "0: Set counter value to 0 and clear counter..,1: No clearing effect. Normal counter operation." newline rbitfld.long 0x4 0. "CNTR_OFL,Counter overflow" "0: Counting with/without expired state.,1: Expired and waiting for next selected event." line.long 0x8 "COUNTER_2_CTRL_REG_ADDR,Counter control 2" hexmask.long.byte 0x8 24.--31. 1. "CSV,CSV[7:0]" newline hexmask.long.byte 0x8 16.--23. 1. "COUNT_PR,Count_parameter[7:0]" newline bitfld.long 0x8 2. "CNTR_EN,Counter Enable" "0: Disable (clock gated),1: Enable." newline bitfld.long 0x8 1. "CNTR_CLR,Counter clear" "0: Set counter value to 0 and clear counter..,1: No clearing effect. Normal counter operation." newline rbitfld.long 0x8 0. "CNTR_OFL,Counter overflow" "0: Counting with/without expired state.,1: Expired and waiting for next selected event." line.long 0xC "COUNTER_3_CTRL_REG_ADDR,Counter control 3" hexmask.long.byte 0xC 24.--31. 1. "CSV,CSV[7:0]" newline hexmask.long.byte 0xC 16.--23. 1. "COUNT_PR,Count_parameter[7:0]" newline bitfld.long 0xC 2. "CNTR_EN,Counter Enable" "0: Disable (clock gated),1: Enable" newline bitfld.long 0xC 1. "CNTR_CLR,Counter clear" "0: Set counter value to 0 and clear counter..,1: No clearing effect. Normal counter operation." newline rbitfld.long 0xC 0. "CNTR_OFL,Counter overflow" "0: Counting with/without expired state.,1: Expired and waiting for next selected event." repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x20)++0x3 line.long 0x0 "COUNTER__DATA_REG_ADDR[$1],Counter Data" hexmask.long 0x0 0.--31. 1. "COUNT_VL,Count Value" repeat.end group.long 0x40++0x3 line.long 0x0 "MRR_0_DATA_REG_ADDR,Mode Register Read 0 address" rbitfld.long 0x0 3. "VALID_OUT,Valid out" "0,1" newline bitfld.long 0x0 2. "MPR_VALID_CLR_REG,MPR_VALID_CLR_REG = 1 clears the VALID_OUT of 'Mode Register Read 0 address' and also clears the 'Mode Register Read 1 address'." "0,1" newline bitfld.long 0x0 1. "MPR_MODE_SEL_REG,Set MPR_MODE_SEL_REG = 1 to enable serial mode and Set MPR_MODE_SEL_REG = 0 to enable parallel mode." "0,1" newline bitfld.long 0x0 0. "MRR_DDR_SEL_REG,Set MPR_MODE_SEL_REG = 1 to enable LPDDR4 mode and Set MPR_MODE_SEL_REG = 0 to enable DDR4 mode." "0,1" rgroup.long 0x44++0x3 line.long 0x0 "MRR_1_DATA_REG_ADDR,Mode Register Read 1 address" hexmask.long 0x0 0.--31. 1. "MRR_VL,MRR value" tree.end tree "PIT (Periodic Interrupt Timer)" base ad:0x0 tree "PIT_0" base ad:0x40188000 group.long 0x0++0x3 line.long 0x0 "MCR,PIT Module Control" bitfld.long 0x0 1. "MDIS,Module Disable for PIT" "0: Enables,1: Disables" bitfld.long 0x0 0. "FRZ,Freeze" "0: Timers run in Debug mode,1: Timers stop in Debug mode" rgroup.long 0xE0++0x7 line.long 0x0 "LTMR64H,PIT Upper Lifetimer" hexmask.long 0x0 0.--31. 1. "LTH,Lifetimer Value" line.long 0x4 "LTMR64L,PIT Lower Lifetimer" hexmask.long 0x4 0.--31. 1. "LTL,Lifetimer Value" repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x40188100 ad:0x40188110 ad:0x40188120 ad:0x40188130 ad:0x40188140 ad:0x40188150 ad:0x40188160) tree "TIMER[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "LDVAL,Timer Load Value" hexmask.long 0x0 0.--31. 1. "TSV,Timer Start Value" rgroup.long ($2+0x4)++0x3 line.long 0x0 "CVAL,Current Timer Value" hexmask.long 0x0 0.--31. 1. "TVL,Timer Value" group.long ($2+0x8)++0x7 line.long 0x0 "TCTRL,Timer Control" bitfld.long 0x0 2. "CHN,Chain Mode" "0: Unchains,1: Chains" bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disables,1: Enables. The timer begins counting down." line.long 0x4 "TFLG,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Timer has not expired,1: Timer expired" tree.end repeat.end tree.end tree "PIT_1" base ad:0x40288000 group.long 0x0++0x3 line.long 0x0 "MCR,PIT Module Control" bitfld.long 0x0 1. "MDIS,Module Disable for PIT" "0: Enables,1: Disables" bitfld.long 0x0 0. "FRZ,Freeze" "0: Timers run in Debug mode,1: Timers stop in Debug mode" rgroup.long 0xE0++0x7 line.long 0x0 "LTMR64H,PIT Upper Lifetimer" hexmask.long 0x0 0.--31. 1. "LTH,Lifetimer Value" line.long 0x4 "LTMR64L,PIT Lower Lifetimer" hexmask.long 0x4 0.--31. 1. "LTL,Lifetimer Value" repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x40288100 ad:0x40288110 ad:0x40288120 ad:0x40288130 ad:0x40288140 ad:0x40288150 ad:0x40288160) tree "TIMER[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "LDVAL,Timer Load Value" hexmask.long 0x0 0.--31. 1. "TSV,Timer Start Value" rgroup.long ($2+0x4)++0x3 line.long 0x0 "CVAL,Current Timer Value" hexmask.long 0x0 0.--31. 1. "TVL,Timer Value" group.long ($2+0x8)++0x7 line.long 0x0 "TCTRL,Timer Control" bitfld.long 0x0 2. "CHN,Chain Mode" "0: Unchains,1: Chains" bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disables,1: Enables. The timer begins counting down." line.long 0x4 "TFLG,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Timer has not expired,1: Timer expired" tree.end repeat.end tree.end tree.end tree "PLLDIG (PLL Digital Interface)" base ad:0x0 tree "ACCEL_PLL" base ad:0x40040000 group.long 0x0++0x13 line.long 0x0 "PLLCR,PLL Control" bitfld.long 0x0 31. "PLLPD,PLL Power Down" "0: Powered up,1: Powered down" line.long 0x4 "PLLSR,PLL Status" eventfld.long 0x4 3. "LOL,Loss-Of-Lock Flag" "0: No loss of lock detected,1: Loss of lock detected" rbitfld.long 0x4 2. "LOCK,Lock Status" "0: Unlocked,1: Locked" line.long 0x8 "PLLDV,PLL Divider" bitfld.long 0x8 12.--14. "RDIV,Input Clock Predivider" "0: Divide by 1,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,5: Divide by 5,6: Divide by 6,7: Divide by 7" hexmask.long.byte 0x8 0.--7. 1. "MFI,Integer Portion Of Loop Divider" line.long 0xC "PLLFM,PLL Frequency Modulation" bitfld.long 0xC 30. "SSCGBYP,Frequency Modulation (Spread Spectrum Clock Generation) Bypass" "0: Not bypassed,1: Bypassed" bitfld.long 0xC 29. "SPREADCTL,Modulation Type Selection" "0: Centered around nominal frequency,?" hexmask.long.word 0xC 16.--25. 1. "STEPSIZE,Frequency Modulation Step Size" hexmask.long.word 0xC 0.--10. 1. "STEPNO,Number Of Steps Of Modulation Period Or Frequency Modulation" line.long 0x10 "PLLFD,PLL Fractional Divider" bitfld.long 0x10 30. "SDMEN,Fractional Mode Enable" "0: Disabled,1: Enabled" hexmask.long.word 0x10 0.--14. 1. "MFN,Numerator Of Fractional Loop Division Factor" group.long 0x20++0x3 line.long 0x0 "PLLCLKMUX,PLL Clock Multiplexer" bitfld.long 0x0 0. "REFCLKSEL,Reference Clock Select" "0: FIRC_CLK,1: FXOSC_CLK" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "PLLODIV_[$1],PLL Output Divider" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disabled,1: Enabled" hexmask.long.byte 0x0 16.--23. 1. "DIV,Division Value" repeat.end tree.end tree "CORE_PLL" base ad:0x40038000 group.long 0x0++0x13 line.long 0x0 "PLLCR,PLL Control" bitfld.long 0x0 31. "PLLPD,PLL Power Down" "0: Powered up,1: Powered down" line.long 0x4 "PLLSR,PLL Status" eventfld.long 0x4 3. "LOL,Loss-Of-Lock Flag" "0: No loss of lock detected,1: Loss of lock detected" rbitfld.long 0x4 2. "LOCK,Lock Status" "0: Unlocked,1: Locked" line.long 0x8 "PLLDV,PLL Divider" bitfld.long 0x8 12.--14. "RDIV,Input Clock Predivider" "0: Divide by 1,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,5: Divide by 5,6: Divide by 6,7: Divide by 7" hexmask.long.byte 0x8 0.--7. 1. "MFI,Integer Portion Of Loop Divider" line.long 0xC "PLLFM,PLL Frequency Modulation" bitfld.long 0xC 30. "SSCGBYP,Frequency Modulation (Spread Spectrum Clock Generation) Bypass" "0: Not bypassed,1: Bypassed" bitfld.long 0xC 29. "SPREADCTL,Modulation Type Selection" "0: Centered around nominal frequency,?" hexmask.long.word 0xC 16.--25. 1. "STEPSIZE,Frequency Modulation Step Size" hexmask.long.word 0xC 0.--10. 1. "STEPNO,Number Of Steps Of Modulation Period Or Frequency Modulation" line.long 0x10 "PLLFD,PLL Fractional Divider" bitfld.long 0x10 30. "SDMEN,Fractional Mode Enable" "0: Disabled,1: Enabled" hexmask.long.word 0x10 0.--14. 1. "MFN,Numerator Of Fractional Loop Division Factor" group.long 0x20++0x3 line.long 0x0 "PLLCLKMUX,PLL Clock Multiplexer" bitfld.long 0x0 0. "REFCLKSEL,Reference Clock Select" "0: FIRC_CLK,1: FXOSC_CLK" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "PLLODIV_[$1],PLL Output Divider" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disabled,1: Enabled" hexmask.long.byte 0x0 16.--23. 1. "DIV,Division Value" repeat.end tree.end tree "DDR_PLL" base ad:0x40044000 group.long 0x0++0x13 line.long 0x0 "PLLCR,PLL Control" bitfld.long 0x0 31. "PLLPD,PLL Power Down" "0: Powered up,1: Powered down" line.long 0x4 "PLLSR,PLL Status" eventfld.long 0x4 3. "LOL,Loss-Of-Lock Flag" "0: No loss of lock detected,1: Loss of lock detected" rbitfld.long 0x4 2. "LOCK,Lock Status" "0: Unlocked,1: Locked" line.long 0x8 "PLLDV,PLL Divider" bitfld.long 0x8 12.--14. "RDIV,Input Clock Predivider" "0: Divide by 1,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,5: Divide by 5,6: Divide by 6,7: Divide by 7" hexmask.long.byte 0x8 0.--7. 1. "MFI,Integer Portion Of Loop Divider" line.long 0xC "PLLFM,PLL Frequency Modulation" bitfld.long 0xC 30. "SSCGBYP,Frequency Modulation (Spread Spectrum Clock Generation) Bypass" "0: Not bypassed,1: Bypassed" bitfld.long 0xC 29. "SPREADCTL,Modulation Type Selection" "0: Centered around nominal frequency,?" hexmask.long.word 0xC 16.--25. 1. "STEPSIZE,Frequency Modulation Step Size" hexmask.long.word 0xC 0.--10. 1. "STEPNO,Number Of Steps Of Modulation Period Or Frequency Modulation" line.long 0x10 "PLLFD,PLL Fractional Divider" bitfld.long 0x10 30. "SDMEN,Fractional Mode Enable" "0: Disabled,1: Enabled" hexmask.long.word 0x10 0.--14. 1. "MFN,Numerator Of Fractional Loop Division Factor" group.long 0x20++0x3 line.long 0x0 "PLLCLKMUX,PLL Clock Multiplexer" bitfld.long 0x0 0. "REFCLKSEL,Reference Clock Select" "0: FIRC_CLK,1: FXOSC_CLK" group.long 0x80++0x3 line.long 0x0 "PLLODIV_0,PLL Output Divider" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disabled,1: Enabled" hexmask.long.byte 0x0 16.--23. 1. "DIV,Division Value" tree.end tree "PERIPH_PLL" base ad:0x4003C000 group.long 0x0++0xB line.long 0x0 "PLLCR,PLL Control" bitfld.long 0x0 31. "PLLPD,PLL Power Down" "0: Powered up,1: Powered down" line.long 0x4 "PLLSR,PLL Status" eventfld.long 0x4 3. "LOL,Loss-Of-Lock Flag" "0: No loss of lock detected,1: Loss of lock detected" rbitfld.long 0x4 2. "LOCK,Lock Status" "0: Unlocked,1: Locked" line.long 0x8 "PLLDV,PLL Divider" bitfld.long 0x8 12.--14. "RDIV,Input Clock Predivider" "0: Divide by 1,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,5: Divide by 5,6: Divide by 6,7: Divide by 7" hexmask.long.byte 0x8 0.--7. 1. "MFI,Integer Portion Of Loop Divider" group.long 0x10++0x3 line.long 0x0 "PLLFD,PLL Fractional Divider" bitfld.long 0x0 30. "SDMEN,Fractional Mode Enable" "0: Disabled,1: Enabled" hexmask.long.word 0x0 0.--14. 1. "MFN,Numerator Of Fractional Loop Division Factor" group.long 0x20++0x3 line.long 0x0 "PLLCLKMUX,PLL Clock Multiplexer" bitfld.long 0x0 0. "REFCLKSEL,Reference Clock Select" "0: FIRC_CLK,1: FXOSC_CLK" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "PLLODIV_[$1],PLL Output Divider" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disabled,1: Enabled" hexmask.long.byte 0x0 16.--23. 1. "DIV,Division Value" repeat.end tree.end tree.end tree "PMC (Power Management Controller)" base ad:0x4008C000 group.long 0x0++0x7 line.long 0x0 "SSR,Source of System Reset" eventfld.long 0x0 2. "POR_WDOG_EVENT,POR watchdog event flag" "0: No event detected after the last clearing of the..,1: An event was detected" newline eventfld.long 0x0 1. "CSPD_EVENT,Critical supply presence detector event flag" "0: No event detected after last clearing of the bit,1: An event was detected" newline eventfld.long 0x0 0. "POR_SUP,POR on core supply CSPD event flag" "0: No event detected after the last time this field..,1: An event was detected" line.long 0x4 "NCSPD_CTL,Non-Critical Supply Presence Detector Control" bitfld.long 0x4 31. "NCSPD_CTL31,NCSPD31 control" "0: NCSPD31 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE31],1: NCSPD31 can set NCSPDEF[NCSPD_EVENT_CAPTURE31]" newline bitfld.long 0x4 30. "NCSPD_CTL30,NCSPD30 control" "0: NCSPD30 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE30],1: NCSPD30 can set NCSPDEF[NCSPD_EVENT_CAPTURE30]" newline bitfld.long 0x4 29. "NCSPD_CTL29,NCSPD29 control" "0: NCSPD29 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE29],1: NCSPD29 can set NCSPDEF[NCSPD_EVENT_CAPTURE29]" newline bitfld.long 0x4 28. "NCSPD_CTL28,NCSPD28 control" "0: NCSPD28 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE28],1: NCSPD28 can set NCSPDEF[NCSPD_EVENT_CAPTURE28]" newline bitfld.long 0x4 23. "NCSPD_CTL23,NCSPD23 control" "0: NCSPD23 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE23],1: NCSPD23 can set NCSPDEF[NCSPD_EVENT_CAPTURE23]" newline bitfld.long 0x4 22. "NCSPD_CTL22,NCSPD22 control" "0: NCSPD22 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE22],1: NCSPD22 can set NCSPDEF[NCSPD_EVENT_CAPTURE22]" newline bitfld.long 0x4 21. "NCSPD_CTL21,NCSPD21 control" "0: NCSPD21 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE21],1: NCSPD21 can set NCSPDEF[NCSPD_EVENT_CAPTURE21]" newline bitfld.long 0x4 18. "NCSPD_CTL18,NCSPD18 control" "0: NCSPD18 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE18],1: NCSPD18 can set NCSPDEF[NCSPD_EVENT_CAPTURE18]" newline bitfld.long 0x4 17. "NCSPD_CTL17,NCSPD17 control" "0: NCSPD17 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE17],1: NCSPD17 can set NCSPDEF[NCSPD_EVENT_CAPTURE17]" newline bitfld.long 0x4 11. "NCSPD_CTL11,NCSPD11 control" "0: NCSPD11 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE11],1: NCSPD11 can set NCSPDEF[NCSPD_EVENT_CAPTURE11]" newline bitfld.long 0x4 10. "NCSPD_CTL10,NCSPD10 control" "0: NCSPD10 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE10],1: NCSPD10 can set NCSPDEF[NCSPD_EVENT_CAPTURE10]" newline bitfld.long 0x4 9. "NCSPD_CTL9,NCSPD9 control" "0: NCSPD9 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE9],1: NCSPD9 can set NCSPDEF[NCSPD_EVENT_CAPTURE9]" newline bitfld.long 0x4 8. "NCSPD_CTL8,NCSPD8 control" "0: NCSPD8 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE8],1: NCSPD8 can set NCSPDEF[NCSPD_EVENT_CAPTURE8]" newline bitfld.long 0x4 7. "NCSPD_CTL7,NCSPD7 control" "0: NCSPD7 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE7],1: NCSPD7 can set NCSPDEF[NCSPD_EVENT_CAPTURE7]" newline bitfld.long 0x4 6. "NCSPD_CTL6,NCSPD6 control" "0: NCSPD6 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE6],1: NCSPD6 can set NCSPDEF[NCSPD_EVENT_CAPTURE6]" newline bitfld.long 0x4 5. "NCSPD_CTL5,NCSPD5 control" "0: NCSPD5 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE5],1: NCSPD5 can set NCSPDEF[NCSPD_EVENT_CAPTURE5]" newline bitfld.long 0x4 4. "NCSPD_CTL4,NCSPD4 control" "0: NCSPD4 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE4],1: NCSPD4 can set NCSPDEF[NCSPD_EVENT_CAPTURE4]" newline bitfld.long 0x4 3. "NCSPD_CTL3,NCSPD3 control" "0: NCSPD3 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE3],1: NCSPD3 can set NCSPDEF[NCSPD_EVENT_CAPTURE3]" newline bitfld.long 0x4 2. "NCSPD_CTL2,NCSPD2 control" "0: NCSPD2 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE2],1: NCSPD2 can set NCSPDEF[NCSPD_EVENT_CAPTURE2]" newline bitfld.long 0x4 1. "NCSPD_CTL1,NCSPD1 control" "0: NCSPD1 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE1],1: NCSPD1 can set NCSPDEF[NCSPD_EVENT_CAPTURE1]" newline bitfld.long 0x4 0. "NCSPD_CTL0,NCSPD0 control" "0: NCSPD0 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE0],1: NCSPD0 can set NCSPDEF[NCSPD_EVENT_CAPTURE0]" rgroup.long 0xC++0x3 line.long 0x0 "NCSPD_STAT,NCSPD Status Register" bitfld.long 0x0 31. "NCSPD_STAT31,NCSPD31 status" "0: NCSPD31 has not detected an error condition.,1: NCPSD31 has detected an error condition." newline bitfld.long 0x0 30. "NCSPD_STAT30,NCSPD30 status" "0: NCSPD30 has not detected an error condition.,1: NCPSD30 has detected an error condition." newline bitfld.long 0x0 29. "NCSPD_STAT29,NCSPD29 status" "0: NCSPD29 has not detected an error condition.,1: NCPSD29 has detected an error condition." newline bitfld.long 0x0 28. "NCSPD_STAT28,NCSPD28 status" "0: NCSPD28 has not detected an error condition.,1: NCPSD28 has detected an error condition." newline bitfld.long 0x0 23. "NCSPD_STAT23,NCSPD23 status" "0: NCSPD23 has not detected an error condition.,1: NCPSD23 has detected an error condition." newline bitfld.long 0x0 22. "NCSPD_STAT22,NCSPD22 status" "0: NCSPD22 has not detected an error condition.,1: NCPSD22 has detected an error condition." newline bitfld.long 0x0 21. "NCSPD_STAT21,NCSPD21 status" "0: NCSPD21 has not detected an error condition.,1: NCPSD21 has detected an error condition." newline bitfld.long 0x0 18. "NCSPD_STAT18,NCSPD18 status" "0: NCSPD18 has not detected an error condition.,1: NCPSD18 has detected an error condition." newline bitfld.long 0x0 17. "NCSPD_STAT17,NCSPD17 status" "0: NCSPD17 has not detected an error condition.,1: NCPSD17 has detected an error condition." newline bitfld.long 0x0 11. "NCSPD_STAT11,NCSPD11 status" "0: NCSPD11 has not detected an error condition.,1: NCPSD11 has detected an error condition." newline bitfld.long 0x0 10. "NCSPD_STAT10,NCSPD10 status" "0: NCSPD10 has not detected an error condition.,1: NCPSD10 has detected an error condition." newline bitfld.long 0x0 9. "NCSPD_STAT9,NCSPD9 status" "0: NCSPD9 has not detected an error condition.,1: NCPSD9 has detected an error condition." newline bitfld.long 0x0 8. "NCSPD_STAT8,NCSPD8 status" "0: NCSPD8 has not detected an error condition.,1: NCPSD8 has detected an error condition." newline bitfld.long 0x0 7. "NCSPD_STAT7,NCSPD7 status" "0: NCSPD7 has not detected an error condition.,1: NCPSD7 has detected an error condition." newline bitfld.long 0x0 6. "NCSPD_STAT6,NCSPD6 status" "0: NCSPD6 has not detected an error condition.,1: NCPSD6 has detected an error condition." newline bitfld.long 0x0 5. "NCSPD_STAT5,NCSPD5 status" "0: NCSPD5 has not detected an error condition.,1: NCPSD5 has detected an error condition." newline bitfld.long 0x0 4. "NCSPD_STAT4,NCSPD4 status" "0: NCSPD4 has not detected an error condition.,1: NCPSD4 has detected an error condition." newline bitfld.long 0x0 3. "NCSPD_STAT3,NCSPD3 status" "0: NCSPD3 has not detected an error condition.,1: NCPSD3 has detected an error condition." newline bitfld.long 0x0 2. "NCSPD_STAT2,NCSPD2 status" "0: NCSPD2 has not detected an error condition.,1: NCPSD2 has detected an error condition." newline bitfld.long 0x0 1. "NCSPD_STAT1,NCSPD1 status" "0: NCSPD1 has not detected an error condition.,1: NCPSD1 has detected an error condition." newline bitfld.long 0x0 0. "NCSPD_STAT0,NCSPD0 status" "0: NCSPD0 has not detected an error condition.,1: NCPSD0 has detected an error condition." group.long 0x10++0x7 line.long 0x0 "CSPD_EVENT_CAPTURE,CSPD Event Capture (CSPDEF)" eventfld.long 0x0 2. "CSPD_EVENT_CAPTURE1,CSPD1 event flag" "0: No CSPD1 error condition detected after last..,1: CSPD1 error condition detected." newline eventfld.long 0x0 1. "CSPD_EVENT_CAPTURE0,CSPD0 event flag" "0: No CSPD0 error condition detected after last..,1: CSPD0 error condition detected." newline eventfld.long 0x0 0. "HVCPOREF,PMC supply CSPD event flag" "0: PMC Supply did not cross the lower voltage limit,1: PMC Supply was below the lower voltage limit" line.long 0x4 "NCSPD_EVENT_CAPTURE,NCSPD Event Flag (NCSPDEF)" eventfld.long 0x4 31. "NCSPD_EVENT_CAPTURE31,NCSPD31 event flag" "0: No NCSPD31 error condition occurred after last..,1: NCSPD31 error condition occurred." newline eventfld.long 0x4 30. "NCSPD_EVENT_CAPTURE30,NCSPD30 event flag" "0: No NCSPD30 error condition occurred after last..,1: NCSPD30 error condition occurred." newline eventfld.long 0x4 29. "NCSPD_EVENT_CAPTURE29,NCSPD29 event flag" "0: No NCSPD29 error condition occurred after last..,1: NCSPD29 error condition occurred." newline eventfld.long 0x4 28. "NCSPD_EVENT_CAPTURE28,NCSPD28 event flag" "0: No NCSPD28 error condition occurred after last..,1: NCSPD28 error condition occurred." newline eventfld.long 0x4 23. "NCSPD_EVENT_CAPTURE23,NCSPD23 event flag" "0: No NCSPD23 error condition occurred after last..,1: NCSPD23 error condition occurred." newline eventfld.long 0x4 22. "NCSPD_EVENT_CAPTURE22,NCSPD22 event flag" "0: No NCSPD22 error condition occurred after last..,1: NCSPD22 error condition occurred." newline eventfld.long 0x4 21. "NCSPD_EVENT_CAPTURE21,NCSPD21 event flag" "0: No NCSPD21 error condition occurred after last..,1: NCSPD21 error condition occurred." newline eventfld.long 0x4 18. "NCSPD_EVENT_CAPTURE18,NCSPD18 event flag" "0: No NCSPD18 error condition occurred after last..,1: NCSPD18 error condition occurred." newline eventfld.long 0x4 17. "NCSPD_EVENT_CAPTURE17,NCSPD17 event flag" "0: No NCSPD17 error condition occurred after last..,1: NCSPD17 error condition occurred." newline eventfld.long 0x4 11. "NCSPD_EVENT_CAPTURE11,NCSPD11 event flag" "0: No NCSPD11 error condition occurred after last..,1: NCSPD11 error condition occurred." newline eventfld.long 0x4 10. "NCSPD_EVENT_CAPTURE10,NCSPD10 event flag" "0: No NCSPD10 error condition occurred after last..,1: NCSPD10 error condition occurred." newline eventfld.long 0x4 9. "NCSPD_EVENT_CAPTURE9,NCSPD9 event flag" "0: No NCSPD9 error condition occurred after last..,1: NCSPD9 error condition occurred." newline eventfld.long 0x4 8. "NCSPD_EVENT_CAPTURE8,NCSPD8 event flag" "0: No NCSPD8 error condition occurred after last..,1: NCSPD8 error condition occurred." newline eventfld.long 0x4 7. "NCSPD_EVENT_CAPTURE7,NCSPD7 event flag" "0: No NCSPD7 error condition occurred after last..,1: NCSPD7 error condition occurred." newline eventfld.long 0x4 6. "NCSPD_EVENT_CAPTURE6,NCSPD6 event flag" "0: No NCSPD6 error condition occurred after last..,1: NCSPD6 error condition occurred." newline eventfld.long 0x4 5. "NCSPD_EVENT_CAPTURE5,NCSPD5 event flag" "0: No NCSPD5 error condition occurred after last..,1: NCSPD5 error condition occurred." newline eventfld.long 0x4 4. "NCSPD_EVENT_CAPTURE4,NCSPD4 event flag" "0: No NCSPD4 error condition occurred after last..,1: NCSPD4 error condition occurred." newline eventfld.long 0x4 3. "NCSPD_EVENT_CAPTURE3,NCSPD3 event flag" "0: No NCSPD3 error condition occurred after last..,1: NCSPD3 error condition occurred." newline eventfld.long 0x4 2. "NCSPD_EVENT_CAPTURE2,NCSPD2 event flag" "0: No NCSPD2 error condition occurred after last..,1: NCSPD2 error condition occurred." newline eventfld.long 0x4 1. "NCSPD_EVENT_CAPTURE1,NCSPD1 event flag" "0: No NCSPD1 error condition occurred after last..,1: NCSPD1 error condition occurred." newline eventfld.long 0x4 0. "NCSPD_EVENT_CAPTURE0,NCSPD0 event flag" "0: No NCSPD0 error condition occurred after last..,1: NCSPD0 error condition occurred." repeat 3. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C)++0x3 line.long 0x0 "POR_WDOG_EVENT_CAPTURE[$1],Device Status Flag (DSFindex)" hexmask.long 0x0 0.--31. 1. "DSFBIT0,See the 'Chip-specific PMC information' at the beginning of this chapter for the mapping between these fields and the 'Device status' signals of the chip (see )" repeat.end tree.end tree "PMUEVENTOBSERVER" base ad:0x0 repeat 30. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "CTL[$1],PMUEVENT Observer Control Register" bitfld.long 0x0 9. "CLRCNTR,This bit is used to clear the counter value." "0: Do not clear the counter value.,1: Clear the counter value." bitfld.long 0x0 8. "CPYCOUNT,This bit is used to copy the counter value to the status register for software to read." "0: Do not copy the counter value to the status..,1: Copy the counter value to the status register" newline bitfld.long 0x0 6.--7. "CTRSTPSEL,Input to select the counter stop trigger" "?,1: Falling edge detect signal used as stop trigger,?,?" bitfld.long 0x0 4.--5. "CTRSTRTSEL,Input to select the counter start trigger" "?,1: Input to select the counter start trigger,?,?" newline bitfld.long 0x0 0.--1. "REVTINPSEL,Rise event input select to counter" "?,1: Rise level of signal used as input to counter,?,?" repeat.end repeat 30. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "STAT[$1],PMUEVENT Observer Status Register" hexmask.long 0x0 0.--31. 1. "COUNT_VAL,Number of events counted by the counter corresponding to PMUEVENT[a]" repeat.end tree.end tree "QUADSPI (Quad Serial Peripheral Interface)" base ad:0x0 tree "QUADSPI" base ad:0x40134000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "CK2_DCARS_FB,CK2 DDR center-aligned read strobe for flash memory B" "0,1" newline bitfld.long 0x0 30. "CKN_FB_EN,Enable clock on differential CKN pad of flash memory B" "0,1" newline bitfld.long 0x0 28.--29. "DQS_FB_SEL,DQS clock for sampling read data at flash memory B" "0,1,2,3" newline bitfld.long 0x0 27. "CK2_DCARS_FA,CK2 DDR center-aligned read strobe for flash memory A" "0,1" newline bitfld.long 0x0 26. "CKN_FA_EN,CKN pad for flash memory A" "0,1" newline bitfld.long 0x0 24.--25. "DQS_FA_SEL,DQS clock for sampling read data at flash memory A" "0,1,2,3" newline bitfld.long 0x0 19. "ISD3FB,Idle signal drive IOFB[3] flash memory B" "0: IOFB[3] is driven to logic L.,1: IOFB[3] is driven to logic H." newline bitfld.long 0x0 18. "ISD2FB,Idle signal drive IOFB[2] flash memory B" "0: IOFB[2] is driven to logic L.,1: IOFB[2] is driven to logic H." newline bitfld.long 0x0 17. "ISD3FA,Idle signal drive IOFA[3] flash memory A" "0: IOFA[3] is driven to logic L,1: IOFA[3] is driven to logic H" newline bitfld.long 0x0 16. "ISD2FA,Idle signal drive IOFA[2] flash memory A" "0: IOFA[2] is driven to logic L.,1: IOFA[2] is driven to logic H." newline bitfld.long 0x0 14. "MDIS,Module disable" "0: Enable QuadSPI clocks,1: Allow external logic to disable QuadSPI clocks" newline bitfld.long 0x0 12. "DLPEN,Data learning pattern enable" "0,1" newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO/buffer" "0: No action,1: Read and write pointers of the TX buffer are.." newline bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: No action,1: Read and write pointers of the RX buffer are.." newline bitfld.long 0x0 7. "DDR_EN,DDR mode enable" "0: 2x clock disabled for SDR instructions only,1: 2x clock enabled for DDR instructions. Note: 2x.." newline bitfld.long 0x0 6. "DQS_EN,DQS enable" "?,1: DQS enabled" newline bitfld.long 0x0 5. "DQS_LAT_EN,DQS latency enable" "0: DQS latency is disabled.,1: DQS feature with latency included is enabled." newline bitfld.long 0x0 1. "SWRSTHD,Software reset for AHB domain" "0,1" newline bitfld.long 0x0 0. "SWRSTSD,Software reset for serial flash memory domain" "0,1" group.long 0x8++0x1B line.long 0x0 "IPCR,IP Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "SEQID,Points to a sequence in the LUT" newline bitfld.long 0x0 16. "PAR_EN,If the value of this field is 1 a transaction to two serial flash memory devices is triggered in the parallel mode" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "IDATSZ,IP data transfer size" line.long 0x4 "FLSHCR,Flash Memory Configuration Register" bitfld.long 0x4 16.--17. "TDH,Serial flash memory data in hold time" "0: Data aligned with the posedge of internal..,1: Data aligned with 2x serial flash memory half..,?,?" newline hexmask.long.byte 0x4 8.--11. 1. "TCSH,Serial flash memory CS hold time" newline hexmask.long.byte 0x4 0.--3. 1. "TCSS,Serial flash memory CS setup time" line.long 0x8 "BUF0CR,Buffer 0 Configuration Register" hexmask.long.byte 0x8 8.--15. 1. "ADATSZ,AHB data transfer size" newline hexmask.long.byte 0x8 0.--5. 1. "MSTRID,Master ID" line.long 0xC "BUF1CR,Buffer 1 Configuration Register" hexmask.long.byte 0xC 8.--15. 1. "ADATSZ,AHB data transfer size" newline hexmask.long.byte 0xC 0.--5. 1. "MSTRID,Master ID" line.long 0x10 "BUF2CR,Buffer 2 Configuration Register" hexmask.long.byte 0x10 8.--15. 1. "ADATSZ,AHB data transfer size" newline hexmask.long.byte 0x10 0.--5. 1. "MSTRID,Master ID" line.long 0x14 "BUF3CR,Buffer 3 Configuration Register" bitfld.long 0x14 31. "ALLMST,All master enable" "0,1" newline hexmask.long.byte 0x14 8.--15. 1. "ADATSZ,AHB data transfer size" newline hexmask.long.byte 0x14 0.--5. 1. "MSTRID,Master ID" line.long 0x18 "BFGENCR,Buffer Generic Configuration Register" bitfld.long 0x18 16. "PAR_EN,Parallel mode enable" "0,1" newline hexmask.long.byte 0x18 12.--15. 1. "SEQID,Points to a sequence in the LUT." group.long 0x30++0xB line.long 0x0 "BUF0IND,Buffer 0 Top Index Register" hexmask.long.byte 0x0 3.--10. 1. "TPINDX0,Top index of buffer 0" line.long 0x4 "BUF1IND,Buffer 1 Top Index Register" hexmask.long.byte 0x4 3.--10. 1. "TPINDX1,Top index of buffer 1" line.long 0x8 "BUF2IND,Buffer 2 Top Index Register" hexmask.long.byte 0x8 3.--10. 1. "TPINDX2,Top index of buffer 2" group.long 0x50++0x3 line.long 0x0 "AWRCR,AHB Write Configuration Register" bitfld.long 0x0 15. "PPW_WR_DIS,Page program wait write disabled" "0: Enables subsequent writes,1: Disables subsequent writes to the flash memory." newline bitfld.long 0x0 14. "PPW_RD_DIS,Page program wait read disabled" "0: Enables subsequent reads,1: Disables subsequent reads to the flash memory." newline hexmask.long.byte 0x0 0.--3. 1. "AWTRGLVL,AHB write trigger level" group.long 0x60++0x7 line.long 0x0 "DLLCRA,DLL Flash Memory A Configuration Register" bitfld.long 0x0 31. "DLLEN,DLL enable" "0: DLL reference logic remains in reset and should..,1: Enables DLL logic. Set it to 1 after all the.." newline bitfld.long 0x0 30. "FREQEN,Frequency enable" "0: Selects delay chain for low frequency of operation,1: Selects delay chain for high frequency of.." newline hexmask.long.byte 0x0 24.--27. 1. "DLL_REFCNTR,DLL reference counter" newline hexmask.long.byte 0x0 20.--23. 1. "DLLRES,DLL resolution" newline hexmask.long.byte 0x0 16.--19. 1. "SLV_FINE_OFFSET,Fine offset delay elements in incoming DQS" newline bitfld.long 0x0 12.--14. "SLV_DLY_OFFSET,T/16 offset delay elements in incoming DQS" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "SLV_DLY_COARSE,Delay elements in each delay tap" newline bitfld.long 0x0 3. "SLAVE_AUTO_UPDT,Slave chain update" "0: Auto-update feature is disabled.,1: Auto-update feature is enabled." newline bitfld.long 0x0 2. "SLV_EN,Slave enable" "0: DLL slave logic remains in reset and its value..,1: Enables DQS slave delay chain and should be 1.." newline bitfld.long 0x0 1. "SLV_DLL_BYPASS,Slave DLL bypass" "0: Disables manual selection of coarse delays in..,1: Enables selection of number of delays in each.." newline bitfld.long 0x0 0. "SLV_UPD,Slave update" "0: Disables any further update on DQS slave delay..,1: Updates the DQS slave delay chain with either.." line.long 0x4 "DLLCRB,DLL Flash Memory B Configuration Register" bitfld.long 0x4 31. "DLLEN,DLL enable" "0: DLL reference logic remains in reset keep in '0'..,1: Enables DLL logic. Set it to '1' after all.." newline bitfld.long 0x4 30. "FREQEN,Frequency enable" "0: Selects delay chain for low frequency of operation,1: Selects delay chain for high frequency of.." newline hexmask.long.byte 0x4 24.--27. 1. "DLL_REFCNTR,DLL reference counter" newline hexmask.long.byte 0x4 20.--23. 1. "DLLRES,DLL resolution" newline hexmask.long.byte 0x4 16.--19. 1. "SLV_FINE_OFFSET,Number of delay elements in each delay tap" newline bitfld.long 0x4 12.--14. "SLV_DLY_OFFSET,Number of delay elements in each delay tap" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "SLV_DLY_COARSE,Number of delay elements in each delay tap" newline bitfld.long 0x4 3. "SLAVE_AUTO_UPDT,Update slave chain" "0: Auto-update feature is disabled.,1: Auto-update feature is enabled." newline bitfld.long 0x4 2. "SLV_EN,Slave enable" "0: DLL slave logic remains in reset. Keep it '0'..,1: Enables DQS slave delay chain. Set to '1' before.." newline bitfld.long 0x4 1. "SLV_DLL_BYPASS,Slave DLL Bypass" "0: Disables manual selection of coarse delays in..,1: Enables selection of number of delay in each.." newline bitfld.long 0x4 0. "SLV_UPD,Slave update" "0: Disables any further update on DQS slave delay..,1: Updates DQS slave delay chain with either the.." group.long 0x6C++0x3 line.long 0x0 "PARITYCR,Parity Configuration Register" bitfld.long 0x0 31. "CRC_WNDW_FB,CRC address window configuration" "0: Calculates parity (CRC) over fixed address..,1: Calculates parity (CRC) over incremental window.." newline hexmask.long.byte 0x0 25.--30. 1. "CHUNKSIZE_FB,Chunk size for flash memory B" newline bitfld.long 0x0 24. "BYTE_SIZE_FB,Byte size for flash memory B" "0,1" newline bitfld.long 0x0 23. "CRCEN_FB,CRC parity checker logic" "0: Disables parity mechanism. In case of parity..,1: Enables CRC parity checker logic for flash.." newline bitfld.long 0x0 22. "CRCBEN_FB,Adds CRC bar parity from flash memory B output to QuadSPI controller." "0,1" newline bitfld.long 0x0 21. "CRCBIN_FB,Adds CRC bar parity to flash memory B input from QuadSPI controller" "0,1" newline bitfld.long 0x0 15. "CRC_WNDW_FA,CRC address window configuration" "0: Calculates parity (CRC) over fixed address..,1: Calculates parity (CRC) over incremental window.." newline hexmask.long.byte 0x0 9.--14. 1. "CHUNKSIZE_FA,Chunk size for flash memory A" newline bitfld.long 0x0 8. "BYTE_SIZE_FA,Byte size for flash memory A" "0,1" newline bitfld.long 0x0 7. "CRCEN_FA,CRC parity checker logic" "0: Disables parity mechanism. In case of parity..,1: CRC parity checker logic for flash memory A read.." newline bitfld.long 0x0 6. "CRCBEN_FA,Adds CRC bar parity from flash memory A output to QuadSPI controller" "0,1" newline bitfld.long 0x0 5. "CRCBIN_FA,Adds CRC bar parity to flash memory A input from QuadSPI controller" "0,1" group.long 0x100++0xB line.long 0x0 "SFAR,Serial Flash Memory Address Register" hexmask.long 0x0 0.--31. 1. "SFADR,Serial flash memory address" line.long 0x4 "SFACR,Serial Flash Memory Address Configuration Register" bitfld.long 0x4 17. "BYTE_SWAP,Byte swapping" "0: One word of two bytes at [nth n+1th] address,1: One word of two bytes at [n+1th nth] address" newline bitfld.long 0x4 16. "WA,Word addressable" "0: Byte addressable serial flash memory mode,1: Word (2-byte) addressable serial flash memory mode" newline hexmask.long.byte 0x4 8.--12. 1. "PPWB,Page program boundary" newline hexmask.long.byte 0x4 0.--3. 1. "CAS,Column address space" line.long 0x8 "SMPR,Sampling Register" bitfld.long 0x8 28.--30. "DLLFSMPFB,Selects the nth tap provided by slave delay chain for flash memory B" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 24.--26. "DLLFSMPFA,Selects the nth tap provided by slave delay chain for flash memory A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6. "FSDLY,Full-speed delay selection for internal/pad loop back DQS sampling" "0,1" newline bitfld.long 0x8 5. "FSPHS,Full-speed phase selection for SDR instructions" "0,1" rgroup.long 0x10C++0x3 line.long 0x0 "RBSR,RX Buffer Status Register" hexmask.long.word 0x0 16.--31. 1. "RDCTR,Read counter" newline hexmask.long.byte 0x0 0.--7. 1. "RDBFL,RX buffer fill level" group.long 0x110++0x3 line.long 0x0 "RBCT,RX Buffer Control Register" hexmask.long.byte 0x0 0.--6. 1. "WMRK,RX buffer watermark" rgroup.long 0x120++0x3 line.long 0x0 "AWRSR,AHB Write Status Register" bitfld.long 0x0 2. "SEQAUJOIN,Sequence auto join" "0,1" rgroup.long 0x12C++0x3 line.long 0x0 "DLLSR,DLL Status Register" bitfld.long 0x0 31. "DLLB_LOCK,DLL B lock status" "0,1" newline bitfld.long 0x0 30. "SLVB_LOCK,High frequency slave delay chain locked" "0,1" newline bitfld.long 0x0 29. "DLLB_RANGE_ERR,DLL master delay chain" "0,1" newline bitfld.long 0x0 28. "DLLB_FINE_UNDERFLOW,Fine delay chain underflow" "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "DLLB_SLV_FINE_VAL,Fine delay cells in slave delay chain" newline hexmask.long.byte 0x0 16.--19. 1. "DLLB_SLV_COARSE_VAL,Coarse delay cells" newline bitfld.long 0x0 15. "DLLA_LOCK,DLL A lock status" "0,1" newline bitfld.long 0x0 14. "SLVA_LOCK,Slave high lock status" "0,1" newline bitfld.long 0x0 13. "DLLA_RANGE_ERR,DLL master delay chain" "0,1" newline bitfld.long 0x0 12. "DLLA_FINE_UNDERFLOW,Fine delay chain underflow" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "DLLA_SLV_FINE_VAL,Fine delay cells in slave delay chain" newline hexmask.long.byte 0x0 0.--3. 1. "DLLA_SLV_COARSE_VAL,Coarse delay cells in slave delay chain" group.long 0x130++0x3 line.long 0x0 "DLCR,Data Learning Configuration Register" bitfld.long 0x0 30.--31. "DLP_SEL_FB,Selects a pattern matching IO pads" "0: Pattern matching is ignored. This is only for..,1: IO1 is used for matching.,2: IO3 is used for matching. This is only for..,3: Both IO1 and IO3 are used for pattern matching." newline bitfld.long 0x0 24. "DL_NONDLP_FLSH,Data learning enabled for non-DLP flash memory" "0,1" newline bitfld.long 0x0 14.--15. "DLP_SEL_FA,Selects pattern matching IO pads" "0: Pattern matching is ignored. This is only for..,1: IO1 is used for matching,2: IO3 is used for matching. This is only for..,3: Both IO1 and IO3 are used for pattern matching" rgroup.long 0x134++0x7 line.long 0x0 "DLSR_FA,Data Learning Status Flash Memory A Register" bitfld.long 0x0 31. "DLPFFA,Data learning pattern fail" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "POS_EDGE,DLP positive edge match signature for flash memory A" newline hexmask.long.byte 0x0 0.--7. 1. "NEG_EDGE,DLP negative edge match signature for flash memory A" line.long 0x4 "DLSR_FB,Data Learning Status Flash Memory B Register" bitfld.long 0x4 31. "DLPFFB,Data learning pattern fail" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "POS_EDGE,DLP pos edge match signature for flash memory B" newline hexmask.long.byte 0x4 0.--7. 1. "NEG_EDGE,DLP neg edge match signature for flash memory B" rgroup.long 0x150++0x3 line.long 0x0 "TBSR,TX Buffer Status Register" hexmask.long.word 0x0 16.--31. 1. "TRCTR,Transmit counter" newline hexmask.long.word 0x0 0.--8. 1. "TRBFL,TX buffer fill level" group.long 0x154++0x7 line.long 0x0 "TBDR,TX Buffer Data Register" hexmask.long 0x0 0.--31. 1. "TXDATA,TX data" line.long 0x4 "TBCT,TX Buffer Control Register" hexmask.long.byte 0x4 0.--7. 1. "WMRK,Watermark for TX buffer" rgroup.long 0x15C++0x3 line.long 0x0 "SR,Status Register" bitfld.long 0x0 27. "TXFULL,TX buffer full" "0,1" newline bitfld.long 0x0 26. "TXDMA,TX DMA" "0,1" newline bitfld.long 0x0 25. "TXWA,TX buffer watermark available" "0,1" newline bitfld.long 0x0 24. "TXNE,TX buffer not empty" "0,1" newline bitfld.long 0x0 23. "RXDMA,RX buffer DMA" "0,1" newline bitfld.long 0x0 19. "RXFULL,RX buffer full" "0,1" newline bitfld.long 0x0 16. "RXWE,RX buffer watermark exceeded" "0,1" newline bitfld.long 0x0 14. "AHB3FUL,AHB 3 buffer full" "0,1" newline bitfld.long 0x0 13. "AHB2FUL,AHB 2 buffer full" "0,1" newline bitfld.long 0x0 12. "AHB1FUL,AHB 1 buffer full" "0,1" newline bitfld.long 0x0 11. "AHB0FUL,AHB 0 buffer full" "0,1" newline bitfld.long 0x0 10. "AHB3NE,AHB 3 buffer not empty" "0,1" newline bitfld.long 0x0 9. "AHB2NE,AHB 2 buffer not empty" "0,1" newline bitfld.long 0x0 8. "AHB1NE,AHB 1 buffer not empty" "0,1" newline bitfld.long 0x0 7. "AHB0NE,AHB 0 buffer not empty" "0,1" newline bitfld.long 0x0 6. "AHBTRN,AHB access transaction pending" "0,1" newline bitfld.long 0x0 4. "AWRACC,AHB write access" "0,1" newline bitfld.long 0x0 2. "AHB_ACC,AHB read access" "0,1" newline bitfld.long 0x0 1. "IP_ACC,IP access" "0,1" newline bitfld.long 0x0 0. "BUSY,Module busy" "0,1" group.long 0x160++0x7 line.long 0x0 "FR,Flag Register" eventfld.long 0x0 31. "DLPFF,Data learning pattern failure flag" "0,1" newline eventfld.long 0x0 28. "DLLABRT,DLL abort" "?,1: This field is set whenever DLL is unlocked while.." newline eventfld.long 0x0 27. "TBFF,TX buffer fill flag" "0,1" newline eventfld.long 0x0 26. "TBUF,TX buffer underrun flag" "0,1" newline eventfld.long 0x0 24. "DLLUNLCK,DLL unlock" "?,1: This field is set whenever DLL unlock event.." newline eventfld.long 0x0 23. "ILLINE,Illegal instruction error flag" "0,1" newline eventfld.long 0x0 17. "RBOF,RX buffer overflow flag" "0,1" newline eventfld.long 0x0 16. "RBDF,RX buffer drain flag" "0,1" newline eventfld.long 0x0 15. "AAEF,AHB abort error flag" "0,1" newline eventfld.long 0x0 14. "AITEF,AHB illegal transaction error flag" "0,1" newline eventfld.long 0x0 13. "AIBSEF,AHB illegal burst size error flag" "0,1" newline eventfld.long 0x0 12. "ABOF,AHB buffer overflow flag" "0,1" newline eventfld.long 0x0 11. "IUEF,IP command usage error flag" "0,1" newline eventfld.long 0x0 10. "CRCAEF,Sets when there is CRC or ECC error for flash memory A" "0: CRCEF interrupt is not generated.,1: CRCEF interrupt is generated." newline eventfld.long 0x0 9. "CRCBEF,Sets when there is CRC or ECC error for flash memory B" "0: CRCEF interrupt is not generated.,1: CRCEF interrupt is generated." newline eventfld.long 0x0 8. "PPWF,Page-program wait flag after flash memory write flag" "0,1" newline eventfld.long 0x0 7. "IPAEF,IP command trigger during AHB access error flag" "0,1" newline eventfld.long 0x0 6. "IPIEF,IP command trigger could not be executed error flag" "0,1" newline eventfld.long 0x0 0. "TFF,IP command transaction finished flag" "0,1" line.long 0x4 "RSER,Interrupt and DMA Request Select and Enable Register" bitfld.long 0x4 31. "DLPFIE,Data learning pattern failure interrupt enable" "0: No DLPFF interrupt is generated.,1: DLPFF interrupt is generated." newline bitfld.long 0x4 27. "TBFIE,TX buffer fill interrupt enable flag" "0: No TBFF interrupt is generated.,1: TBFF interrupt is generated." newline bitfld.long 0x4 26. "TBUIE,TX buffer underrun interrupt enable flag" "0: No TBUF interrupt is generated,1: TBUF interrupt is generated" newline bitfld.long 0x4 25. "TBFDE,TX buffer fill DMA enable" "0: No DMA request is generated,1: DMA request is generated" newline bitfld.long 0x4 24. "DLLULIE,DLL unlock interrupt enable" "?,1: Write 1 to this to enable generation of.." newline bitfld.long 0x4 23. "ILLINIE,Illegal instruction error interrupt enable" "0: No ILLINE interrupt is generated.,1: ILLINE interrupt is generated." newline bitfld.long 0x4 21. "RBDDE,RX buffer drain DMA enable" "0: No DMA request is generated.,1: DMA request is generated." newline bitfld.long 0x4 17. "RBOIE,RX buffer overflow interrupt enable" "0: No RBOF interrupt is generated.,1: RBOF interrupt is generated." newline bitfld.long 0x4 16. "RBDIE,RX buffer drain interrupt enable" "0: No RBDF interrupt is generated.,1: RBDF Interrupt is generated." newline bitfld.long 0x4 15. "AAIE,AHB abort error interrupt enable" "0: No AAEF interrupt is generated,1: AAEF interrupt is generated" newline bitfld.long 0x4 14. "AITIE,AHB illegal transaction interrupt enable flag" "0: No AITEF interrupt is generated.,1: AITEF interrupt is generated." newline bitfld.long 0x4 13. "AIBSIE,AHB illegal burst size interrupt enable flag" "0: No AIBSEF interrupt is generated.,1: AIBSEF interrupt is generated." newline bitfld.long 0x4 12. "ABOIE,AHB buffer overflow interrupt enable flag" "0: No ABOF interrupt is generated.,1: ABOF interrupt is generated." newline bitfld.long 0x4 11. "IUEIE,IP command usage error interrupt enable flag" "0: No IUEF interrupt is generated,1: IUEF interrupt is generated" newline bitfld.long 0x4 10. "CRCAIE,CRC and ECC interrupt enable for flash memory A" "0: CRCAEF interrupt is not generated.,1: CRCAEF interrupt is generated." newline bitfld.long 0x4 9. "CRCBIE,Sets when there is CRC or ECC error for flash memory B" "0: CRCBEF interrupt is not generated.,1: CRCBEF interrupt is generated." newline bitfld.long 0x4 8. "PPWIE,Page-program wait interrupt flag" "0: No PPWIE interrupt is generated,1: PPWIE interrupt is generated" newline bitfld.long 0x4 7. "IPAEIE,IP command trigger during AHB read access error interrupt enable flag" "0: No IPAEF interrupt is generated,1: IPAEF interrupt is generated" newline bitfld.long 0x4 6. "IPIEIE,IP command trigger during IP access error interrupt enable flag" "0: No IPIEF interrupt is generated,1: IPIEF interrupt is generated" newline bitfld.long 0x4 0. "TFIE,Transaction finished interrupt enable flag" "0: No TFF interrupt is generated.,1: TFF interrupt is generated." group.long 0x16C++0x3 line.long 0x0 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x0 17. "PREFETCH_DIS,Prefetch disable" "0,1" newline bitfld.long 0x0 16. "ABRT_CLR,Flash memory Abort/AHB buffer clear" "0,1" newline bitfld.long 0x0 8. "IPPTRC,IP pointer clear" "?,1: Clears the sequence pointer for IP accesses as.." newline bitfld.long 0x0 0. "BFPTRC,Buffer pointer clear" "?,1: Clears the sequence pointer for AHB read.." group.long 0x180++0x13 line.long 0x0 "SFA1AD,Serial Flash Memory A1 Top Address Register" hexmask.long.tbyte 0x0 10.--31. 1. "TPADA1,Top address for serial flash memory A1" line.long 0x4 "SFA2AD,Serial Flash Memory A2 Top Address Register" hexmask.long.tbyte 0x4 10.--31. 1. "TPADA2,Top address for serial flash memory A2" line.long 0x8 "SFB1AD,Serial Flash Memory B1 Top Address Register" hexmask.long.tbyte 0x8 10.--31. 1. "TPADB1,Top address for serial flash memory B1." line.long 0xC "SFB2AD,Serial Flash Memory B2 Top Address Register" hexmask.long.tbyte 0xC 10.--31. 1. "TPADB2,Top address for serial flash memory B2." line.long 0x10 "DLPR,Data Learn Pattern Register" hexmask.long 0x10 0.--31. 1. "DLPV,Data learning pattern value" rgroup.long 0x194++0x7 line.long 0x0 "FAILA_ADDR,Flash Memory A Failing Address Status Register" hexmask.long 0x0 0.--31. 1. "ADDR,Failing address for flash memory A" line.long 0x4 "FAILB_ADDR,flash Memory B Failing Address Status Register" hexmask.long 0x4 0.--31. 1. "ADDR,Failing address for flash memory B" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x200)++0x3 line.long 0x0 "RBDR[$1],RX Buffer Data Register" hexmask.long 0x0 0.--31. 1. "RXDATA,RX data" repeat.end group.long 0x300++0x7 line.long 0x0 "LUTKEY,LUT Key Register" hexmask.long 0x0 0.--31. 1. "KEY,Key to lock or unlock the LUT" line.long 0x4 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x4 1. "UNLOCK,Unlock LUT" "0,1" newline bitfld.long 0x4 0. "LOCK,Lock LUT" "0,1" group.long 0x310++0x13F line.long 0x0 "LUT0,LUT Register" hexmask.long.byte 0x0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x4 "LUT1,LUT Register" hexmask.long.byte 0x4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x8 "LUT2,LUT Register" hexmask.long.byte 0x8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xC "LUT3,LUT Register" hexmask.long.byte 0xC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x10 "LUT4,LUT Register" hexmask.long.byte 0x10 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x10 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x10 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x10 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x10 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x10 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x14 "LUT5,LUT Register" hexmask.long.byte 0x14 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x14 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x14 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x14 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x14 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x14 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x18 "LUT6,LUT Register" hexmask.long.byte 0x18 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x18 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x18 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x18 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x18 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x18 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x1C "LUT7,LUT Register" hexmask.long.byte 0x1C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x1C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x1C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x1C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x1C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x1C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x20 "LUT8,LUT Register" hexmask.long.byte 0x20 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x20 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x20 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x20 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x20 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x20 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x24 "LUT9,LUT Register" hexmask.long.byte 0x24 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x24 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x24 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x24 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x24 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x24 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x28 "LUT10,LUT Register" hexmask.long.byte 0x28 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x28 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x28 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x28 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x28 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x28 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x2C "LUT11,LUT Register" hexmask.long.byte 0x2C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x2C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x2C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x2C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x2C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x2C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x30 "LUT12,LUT Register" hexmask.long.byte 0x30 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x30 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x30 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x30 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x30 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x30 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x34 "LUT13,LUT Register" hexmask.long.byte 0x34 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x34 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x34 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x34 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x34 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x34 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x38 "LUT14,LUT Register" hexmask.long.byte 0x38 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x38 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x38 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x38 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x38 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x38 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x3C "LUT15,LUT Register" hexmask.long.byte 0x3C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x3C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x3C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x3C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x3C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x3C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x40 "LUT16,LUT Register" hexmask.long.byte 0x40 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x40 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x40 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x40 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x40 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x40 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x44 "LUT17,LUT Register" hexmask.long.byte 0x44 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x44 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x44 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x44 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x44 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x44 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x48 "LUT18,LUT Register" hexmask.long.byte 0x48 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x48 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x48 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x48 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x48 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x48 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x4C "LUT19,LUT Register" hexmask.long.byte 0x4C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x4C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x4C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x4C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x4C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x4C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x50 "LUT20,LUT Register" hexmask.long.byte 0x50 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x50 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x50 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x50 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x50 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x50 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x54 "LUT21,LUT Register" hexmask.long.byte 0x54 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x54 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x54 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x54 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x54 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x54 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x58 "LUT22,LUT Register" hexmask.long.byte 0x58 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x58 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x58 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x58 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x58 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x58 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x5C "LUT23,LUT Register" hexmask.long.byte 0x5C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x5C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x5C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x5C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x5C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x5C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x60 "LUT24,LUT Register" hexmask.long.byte 0x60 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x60 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x60 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x60 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x60 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x60 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x64 "LUT25,LUT Register" hexmask.long.byte 0x64 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x64 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x64 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x64 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x64 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x64 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x68 "LUT26,LUT Register" hexmask.long.byte 0x68 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x68 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x68 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x68 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x68 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x68 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x6C "LUT27,LUT Register" hexmask.long.byte 0x6C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x6C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x6C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x6C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x6C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x6C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x70 "LUT28,LUT Register" hexmask.long.byte 0x70 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x70 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x70 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x70 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x70 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x70 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x74 "LUT29,LUT Register" hexmask.long.byte 0x74 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x74 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x74 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x74 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x74 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x74 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x78 "LUT30,LUT Register" hexmask.long.byte 0x78 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x78 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x78 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x78 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x78 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x78 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x7C "LUT31,LUT Register" hexmask.long.byte 0x7C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x7C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x7C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x7C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x7C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x7C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x80 "LUT32,LUT Register" hexmask.long.byte 0x80 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x80 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x80 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x80 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x80 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x80 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x84 "LUT33,LUT Register" hexmask.long.byte 0x84 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x84 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x84 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x84 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x84 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x84 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x88 "LUT34,LUT Register" hexmask.long.byte 0x88 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x88 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x88 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x88 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x88 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x88 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x8C "LUT35,LUT Register" hexmask.long.byte 0x8C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x8C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x8C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x8C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x8C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x8C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x90 "LUT36,LUT Register" hexmask.long.byte 0x90 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x90 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x90 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x90 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x90 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x90 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x94 "LUT37,LUT Register" hexmask.long.byte 0x94 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x94 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x94 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x94 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x94 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x94 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x98 "LUT38,LUT Register" hexmask.long.byte 0x98 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x98 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x98 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x98 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x98 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x98 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x9C "LUT39,LUT Register" hexmask.long.byte 0x9C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x9C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x9C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x9C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x9C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x9C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xA0 "LUT40,LUT Register" hexmask.long.byte 0xA0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xA0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xA0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xA0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xA0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xA0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xA4 "LUT41,LUT Register" hexmask.long.byte 0xA4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xA4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xA4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xA4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xA4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xA4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xA8 "LUT42,LUT Register" hexmask.long.byte 0xA8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xA8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xA8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xA8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xA8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xA8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xAC "LUT43,LUT Register" hexmask.long.byte 0xAC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xAC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xAC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xAC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xAC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xAC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xB0 "LUT44,LUT Register" hexmask.long.byte 0xB0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xB0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xB0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xB0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xB0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xB0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xB4 "LUT45,LUT Register" hexmask.long.byte 0xB4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xB4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xB4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xB4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xB4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xB4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xB8 "LUT46,LUT Register" hexmask.long.byte 0xB8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xB8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xB8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xB8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xB8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xB8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xBC "LUT47,LUT Register" hexmask.long.byte 0xBC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xBC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xBC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xBC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xBC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xBC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xC0 "LUT48,LUT Register" hexmask.long.byte 0xC0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xC0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xC0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xC0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xC0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xC0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xC4 "LUT49,LUT Register" hexmask.long.byte 0xC4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xC4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xC4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xC4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xC4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xC4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xC8 "LUT50,LUT Register" hexmask.long.byte 0xC8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xC8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xC8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xC8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xC8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xC8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xCC "LUT51,LUT Register" hexmask.long.byte 0xCC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xCC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xCC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xCC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xCC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xCC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xD0 "LUT52,LUT Register" hexmask.long.byte 0xD0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xD0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xD0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xD0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xD0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xD0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xD4 "LUT53,LUT Register" hexmask.long.byte 0xD4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xD4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xD4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xD4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xD4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xD4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xD8 "LUT54,LUT Register" hexmask.long.byte 0xD8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xD8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xD8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xD8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xD8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xD8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xDC "LUT55,LUT Register" hexmask.long.byte 0xDC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xDC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xDC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xDC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xDC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xDC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xE0 "LUT56,LUT Register" hexmask.long.byte 0xE0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xE0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xE0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xE0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xE0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xE0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xE4 "LUT57,LUT Register" hexmask.long.byte 0xE4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xE4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xE4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xE4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xE4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xE4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xE8 "LUT58,LUT Register" hexmask.long.byte 0xE8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xE8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xE8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xE8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xE8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xE8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xEC "LUT59,LUT Register" hexmask.long.byte 0xEC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xEC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xEC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xEC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xEC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xEC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xF0 "LUT60,LUT Register" hexmask.long.byte 0xF0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xF0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xF0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xF0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xF0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xF0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xF4 "LUT61,LUT Register" hexmask.long.byte 0xF4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xF4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xF4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xF4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xF4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xF4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xF8 "LUT62,LUT Register" hexmask.long.byte 0xF8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xF8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xF8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xF8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xF8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xF8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xFC "LUT63,LUT Register" hexmask.long.byte 0xFC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xFC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xFC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xFC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xFC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0xFC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x100 "LUT64,LUT Register" hexmask.long.byte 0x100 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x100 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x100 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x100 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x100 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x100 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x104 "LUT65,LUT Register" hexmask.long.byte 0x104 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x104 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x104 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x104 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x104 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x104 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x108 "LUT66,LUT Register" hexmask.long.byte 0x108 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x108 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x108 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x108 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x108 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x108 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x10C "LUT67,LUT Register" hexmask.long.byte 0x10C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x10C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x10C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x10C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x10C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x10C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x110 "LUT68,LUT Register" hexmask.long.byte 0x110 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x110 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x110 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x110 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x110 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x110 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x114 "LUT69,LUT Register" hexmask.long.byte 0x114 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x114 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x114 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x114 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x114 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x114 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x118 "LUT70,LUT Register" hexmask.long.byte 0x118 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x118 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x118 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x118 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x118 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x118 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x11C "LUT71,LUT Register" hexmask.long.byte 0x11C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x11C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x11C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x11C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x11C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x11C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x120 "LUT72,LUT Register" hexmask.long.byte 0x120 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x120 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x120 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x120 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x120 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x120 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x124 "LUT73,LUT Register" hexmask.long.byte 0x124 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x124 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x124 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x124 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x124 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x124 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x128 "LUT74,LUT Register" hexmask.long.byte 0x128 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x128 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x128 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x128 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x128 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x128 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x12C "LUT75,LUT Register" hexmask.long.byte 0x12C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x12C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x12C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x12C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x12C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x12C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x130 "LUT76,LUT Register" hexmask.long.byte 0x130 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x130 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x130 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x130 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x130 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x130 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x134 "LUT77,LUT Register" hexmask.long.byte 0x134 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x134 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x134 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x134 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x134 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x134 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x138 "LUT78,LUT Register" hexmask.long.byte 0x138 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x138 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x138 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x138 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x138 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x138 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x13C "LUT79,LUT Register" hexmask.long.byte 0x13C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x13C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x13C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x13C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x13C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads" newline hexmask.long.byte 0x13C 0.--7. 1. "OPRND0,Operand for INSTR0" tree.end tree "QUADSPI_ARDB" base ad:0x41000000 repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2)++0x3 line.long 0x0 "ARDB[$1],AHB RX Data Buffer Register" hexmask.long 0x0 0.--31. 1. "ARXD,ARDB provided RX buffer data" repeat.end tree.end tree.end tree "RDC (Reset Domain Controller)" base ad:0x40080000 group.long 0x4++0xB line.long 0x0 "RD1_CTRL_REG,Software Reset Domain 1 Control" bitfld.long 0x0 31. "RD1_CTRL_UNLOCK,Reset Domain 1 Control Register Unlock" "0: Software Reset Domain 1 Control register fields..,1: Software Reset Domain 1 Control register fields.." newline bitfld.long 0x0 3. "RD1_INTERCONNECT_INTERFACE_DISABLE,Interconnect interface Disable of Software Reset Domain 1" "0: Enable interconnect interface of Software Reset..,1: Disable interconnect interface of Software Reset.." line.long 0x4 "RD2_CTRL_REG,Software Reset Domain 2 Control" bitfld.long 0x4 31. "RD2_CTRL_UNLOCK,Reset Domain 2 Control Register Unlock" "0: Software Reset Domain 2 control register fields..,1: Software Reset Domain 2 control register fields.." newline bitfld.long 0x4 3. "RD2_INTERCONNECT_INTERFACE_DISABLE,Interconnect interface Disable of Software Reset Domain 2" "0: Enable interconnect interface of Software Reset..,1: Disable interconnect interface of Software Reset.." line.long 0x8 "RD3_CTRL_REG,Software Reset Domain 3 Control" bitfld.long 0x8 31. "RD3_CTRL_UNLOCK,Reset Domain 3 Control Register Unlock" "0: Software Reset Domain 3 control register fields..,1: Software Reset Domain 3 control register fields.." newline bitfld.long 0x8 3. "RD3_INTERCONNECT_INTERFACE_DISABLE,Interconnect interface Disable of Software Reset Domain 3" "0: Enable interconnect interface of Software Reset..,1: Disable interconnect interface of Software Reset.." rgroup.long 0x84++0xB line.long 0x0 "RD1_STAT_REG,Software Reset Domain 1 Status" bitfld.long 0x0 4. "RD1_INTERCONNECT_INTERFACE_DISABLE_STAT,Interconnect Interface Disable Acknowledgment Status of Software Reset Domain 1" "0: Interconnect interface not disabled for Software..,1: Interconnect interface disabled for Software.." newline bitfld.long 0x0 3. "RD1_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT,Interconnect Interface Disable Request Acknowledgment Status of Software Reset Domain 1" "0: Interconnect interface disable request not..,1: Interconnect interface disable request.." line.long 0x4 "RD2_STAT_REG,Software Reset Domain 2 Status" bitfld.long 0x4 4. "RD2_INTERCONNECT_INTERFACE_DISABLE_STAT,Interconnect Interface Disable Acknowledgment Status of Software Reset Domain 2" "0: Interconnect interface not disabled for Software..,1: Interconnect interface disabled for Software.." newline bitfld.long 0x4 3. "RD2_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT,Interconnect Interface Disable Request Acknowledgment Status of Software Reset Domain 2" "0: Interconnect interface disable request not..,1: Interconnect interface disable request.." line.long 0x8 "RD3_STAT_REG,Software Reset Domain 3 Status" bitfld.long 0x8 4. "RD3_INTERCONNECT_INTERFACE_DISABLE_STAT,Interconnect Interface Disable Acknowledgment Status of Software Reset Domain 3" "0: Interconnect interface not disabled for Software..,1: Interconnect interface disabled for Software.." newline bitfld.long 0x8 3. "RD3_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT,Interconnect Interface Disable Request Acknowledgment Status of Software Reset Domain 3" "0: Interconnect interface disable request not..,1: Interconnect interface disable request.." tree.end tree "RTC" base ad:0x0 tree "RTC (RTC)" base ad:0x40060000 group.long 0x0++0xB line.long 0x0 "RTCSUPV,RTC Supervisor control register" bitfld.long 0x0 31. "SUPV,RTC Supervisor Bit" "0: All registers are accessible in both user as..,1: All other registers are accessible in the.." line.long 0x4 "RTCC,RTC Control register" bitfld.long 0x4 31. "CNTEN,Counter Enable" "0: Counter disabled,1: Counter enabled" bitfld.long 0x4 30. "RTCIE,RTC Interrupt Enable" "0: RTC interrupts disabled,1: RTC interrupts enabled" newline bitfld.long 0x4 29. "FRZEN,Freeze Enable Bit" "0: Counter does not freeze in debug mode,1: Counter freezes in debug mode" bitfld.long 0x4 28. "ROVREN,Counter Roll Over Interrupt Enable" "0: RTC rollover interrupt disabled,1: RTC rollover interrupt enabled" newline bitfld.long 0x4 15. "APIEN,Autonomous Periodic Interrupt Enable" "0: API disabled,1: API enabled" bitfld.long 0x4 14. "APIIE,API Interrupt Enable" "0: API interrupts disabled,1: API interrupts enabled" newline bitfld.long 0x4 12.--13. "CLKSEL,Clock select" "0: Clock source 0,1: Clock source 1,2: Clock source 2,3: Clock source 3" bitfld.long 0x4 11. "DIV512EN,Divide by 512 enable" "0: Divide by 512 is disabled,1: Divide by 512 is enabled" newline bitfld.long 0x4 10. "DIV32EN,Divide by 32 enable" "0: Divide by 32 is disabled,1: Divide by 32 is enabled" line.long 0x8 "RTCS,RTC Status register" eventfld.long 0x8 29. "RTCF,RTC Interrupt Flag" "0: RTC counter is not equal to RTCVAL,1: RTC counter matches RTCVAL" rbitfld.long 0x8 18. "INV_RTC,Invalid RTC write" "0,1" newline rbitfld.long 0x8 17. "INV_API,Invalid APIVAL write" "0,1" eventfld.long 0x8 13. "APIF,API Interrupt Flag" "0: Counter is not equal to API offset value,1: Counter matches the API offset value" newline eventfld.long 0x8 10. "ROVRF,Counter Roll Over Interrupt Flag" "0: RTC has not rolled over,1: RTC has rolled over" rgroup.long 0xC++0x3 line.long 0x0 "RTCCNT,RTC Counter register" hexmask.long 0x0 0.--31. 1. "RTCCNT,RTC Counter Value" group.long 0x10++0x7 line.long 0x0 "APIVAL,API Compare value register" hexmask.long 0x0 0.--31. 1. "APIVAL,API Compare Value" line.long 0x4 "RTCVAL,RTC Compare value register" hexmask.long 0x4 0.--31. 1. "RTCVAL,RTC Compare Value" tree.end tree.end tree "S32G (Main General Purpose Registers)" base ad:0x0 tree "S32G_GPR" base ad:0x4007CA00 group.long 0x0++0x7 line.long 0x0 "PFE_COH_EN,PFE Port Coherency Enable" bitfld.long 0x0 5. "UTIL,PFE UTIL Coherency Enable" "0: PFE UTIL interface not coherent,1: PFE UTIL interface coherent to A53" newline bitfld.long 0x0 4. "HIF3,PFE_HIF Data Read Coherency Enable You must set this field to 1 for coherency over HIF channels. Setting this field to 1 changes the awdomain/ardomain of the master to shareable and you must configure Ncore for this case." "0: PFE_HIF data read interface not coherent.,1: PFE_HIF data read interface coherent to A53." newline bitfld.long 0x0 3. "HIF2,PFE_HIF Data Write Coherency Enable. You must set this field to 1 for coherency over HIF channels. Setting this field to 1 changes the awdomain/ardomain of the master to shareable and you must configure Ncore for this case." "0: PFE_HIF data write interface not coherent.,1: PFE_HIF data write interface coherent to A53." newline bitfld.long 0x0 2. "HIF1,PFE_HIF Data Write Coherency Enable You must set this field to 1 for coherency over HIF channels. Setting this field to 1 changes the awdomain/ardomain of the master to shareable and you must configure Ncore for this case." "0: PFE_HIF BD update interface not coherent.,1: PFE_HIF BD fetch interface coherent to A53." newline bitfld.long 0x0 1. "HIF0,PFE_HIF BD Update Coherency Enable You must set this field to 1 for coherency over HIF channels. Setting this field to 1 changes the awdomain/ardomain of the master to shareable and you must configure Ncore for this case." "0: PFE HIF0 interface not coherent.,1: PFE HIF0 interface coherent to A53." newline bitfld.long 0x0 0. "DDR,PFE DDR Coherency Enable" "0: PFE DDR interface not coherent,1: PFE DDR interface coherent to A53" line.long 0x4 "PFE_EMACX_INTF_SEL,PFE EMAC Interface Mode" hexmask.long.byte 0x4 8.--11. 1. "EMAC2,EMAC2 Interface Select" newline hexmask.long.byte 0x4 4.--7. 1. "EMAC1,EMAC1 Interface Select" newline hexmask.long.byte 0x4 0.--3. 1. "EMAC0,EMAC0 Interface Select" group.long 0x20++0x3 line.long 0x0 "PFE_PWR_CTRL,PFE EMACX Power Control" rbitfld.long 0x0 9.--11. "PWRACK,Power Down Acknoledge" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "PWRISO,Power Isolate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "PWRDWN,Power Down" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "PWRCLAMP,PFE Power Clamp" "0,1,2,3,4,5,6,7" rgroup.long 0x40++0x3 line.long 0x0 "LLCE_STAT,LLCE Subsystem Status" hexmask.long.byte 0x0 12.--15. 1. "LLCE_LSPI_TRIG_FM,LLCE LSPI Trigger Frame" newline hexmask.long.byte 0x0 8.--11. 1. "LLCE_LSPI_TRIG_RX,LLCE LSPI Trigger Receive" newline hexmask.long.byte 0x0 4.--7. 1. "SYSRESETREQ,System Reset Request" newline hexmask.long.byte 0x0 0.--3. 1. "SLEEPING,Sleeping" group.long 0x44++0x3 line.long 0x0 "LLCE_CTRL,LLCE Power Control" bitfld.long 0x0 11. "PFE_2_LLCE_INT_HS_BP,PFE 2 LLCE Interrupt Bypass" "0: Interrupt bypass disabled,1: Interrupt bypass enabled" newline bitfld.long 0x0 10. "LLCE_HTM1_TRC_DIS,LLCE HTM1 Trace Disable" "0,1" newline bitfld.long 0x0 9. "LLCE_HTM0_TRC_DIS,LLCE HTM0 Trace Disable" "0,1" newline hexmask.long.byte 0x0 5.--8. 1. "LLCE_LSPI_TRIG_IN,LLCE LSPI Trigger" newline bitfld.long 0x0 4. "LINDIVSEL,LINFlexD Divide Select" "0: LIN_CLK (a divided-by-2 version of LIN_BAUD_CLK)..,1: LIN_BAUD_CLK drives the ipg_clk_lin_pe_div2xE2 pin" newline hexmask.long.byte 0x0 0.--3. 1. "EXEVENT,External Event" wgroup.long 0x4C++0x3 line.long 0x0 "FLXTIM_CTRL,FlexTimer Global Load Control" bitfld.long 0x0 1. "GLOBAL_LDOK_IN1,Global LDOK Input 1" "0,1" newline bitfld.long 0x0 0. "GLOBAL_LDOK_IN0,Global LDOK Input 0" "0,1" rgroup.long 0x50++0x3 line.long 0x0 "FLXTIM_STAT,FlexTimer LDOK Status" bitfld.long 0x0 1. "GLB_LDOK_OUT1,Global Load OK Out 1" "0,1" newline bitfld.long 0x0 0. "GLB_LDOK_OUT0,Global Load OK Out 0" "0,1" group.long 0x54++0x3 line.long 0x0 "CMU_STAT,Top CMU_FC Status" hexmask.long.word 0x0 0.--13. 1. "FLL_FHH,CMU FLL FHH Status" rgroup.long 0x58++0x3 line.long 0x0 "NOC_NOPEND_TRANS,Accelerator NoC NoPendingTrans Status" hexmask.long 0x0 0.--31. 1. "STAT,Port Status" group.long 0x90++0x3 line.long 0x0 "PCIE_TOGGLE,SerDes RD/WD Toggle Control" hexmask.long.byte 0x0 12.--15. 1. "PCIE0_RD_TOGG,Drives the RD TOGGLE [3:0] inputs of SerDes_0." newline hexmask.long.byte 0x0 8.--11. 1. "PCIE0_WD_TOGG,Drives the WD TOGGLE [3:0] inputs of SerDes_0." newline hexmask.long.byte 0x0 4.--7. 1. "PCIE1_RD_TOGG,Drives the RD TOGGLE [3:0] inputs of SerDes_1." newline hexmask.long.byte 0x0 0.--3. 1. "PCIE1_WD_TOGG,Drives the WD TOGGLE [3:0] inputs of SerDes_1." rgroup.long 0x94++0x3 line.long 0x0 "PCIE_TOGGLEDONE_STAT,SerDes Toggle Done Status" hexmask.long.byte 0x0 12.--15. 1. "PCIE0_RD_TOGG_DONE_STAT,Status of the RD TOGGLE [3:0] outputs of SerDes_0." newline hexmask.long.byte 0x0 8.--11. 1. "PCIE0_WD_TOGG_DONE_STAT,Status of the WD TOGGLE [3:0] outputs of SerDes_0." newline hexmask.long.byte 0x0 4.--7. 1. "PCIE1_RD_TOGG_DONE_STAT,Status of the RD TOGGLE [3:0] outputs of SerDes_1." newline hexmask.long.byte 0x0 0.--3. 1. "PCIE1_WD_TOGG_DONE_STAT,Status of the WD TOGGLE [3:0] outputs of SerDes_1." group.long 0xE0++0x7 line.long 0x0 "GENCTRL0,Generic Control 0" bitfld.long 0x0 3. "ACCEL_FLXNC_RD0_IDLEREQ,Accelerator NoC RD0 IdleReq" "0: Accelerator NoC in normal operation,1: Request accelerator NoC to go into Idle state" newline bitfld.long 0x0 1.--2. "ACCEL_FLXNC_REF_DIV,Accelerator NoC Reference Divide" "0: Divide by 2,1: Divide by 4,2: Divide by 8,3: Divide by 16" newline bitfld.long 0x0 0. "USBPWRFLT,USB Power Fault" "0,1" line.long 0x4 "GENCTRL1,Generic Control 1" hexmask.long 0x4 0.--31. 1. "CTRL,Bit 0 - SGMII_CSEL 0b - Not running PFE EMAC0 in SGMII mode 1b - Running PFE EMAC0 in SGMII mode Bits 32:1 - Reserved" rgroup.long 0xF0++0x3 line.long 0x0 "GENSTAT0,Generic Status 0" hexmask.long 0x0 0.--31. 1. "STAT,Status" tree.end base ad:0x0 tree "S32G_STDBY_GPR" tree "S32G_STDBY_GPR (S32G_STDBY_GPR)" base ad:0x4007CB00 group.long 0x4++0x3 line.long 0x0 "WKUP_PUS,WKUP Pad Pullup/Pulldown Select" bitfld.long 0x0 31. "WKUP_PU_OVERRIDE,WKUP Pullup Override" "0: Use SIUL2's MSCR[PUE] and MSCR[PUS] fields,1: Use WKPU and GPR modules" bitfld.long 0x0 22. "WKUP_PUS26,WKUP Pad 26 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 21. "WKUP_PUS25,WKUP Pad 25 Pullup Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x0 20. "WKUP_PUS24,WKUP Pad 24 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 19. "WKUP_PUS23,WKUP Pad 23 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 18. "WKUP_PUS22,WKUP Pad 22 Pullup Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x0 17. "WKUP_PUS21,WKUP Pad 21 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 16. "WKUP_PUS20,WKUP Pad 20 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 15. "WKUP_PUS19,WKUP Pad 19 Pullup Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x0 14. "WKUP_PUS18,WKUP Pad 18 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 13. "WKUP_PUS17,WKUP Pad 17 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 12. "WKUP_PUS16,WKUP Pad 16 Pullup Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x0 11. "WKUP_PUS15,WKUP Pad 15 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 10. "WKUP_PUS14,WKUP Pad 14 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 9. "WKUP_PUS13,WKUP Pad 13 Pullup Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x0 8. "WKUP_PUS12,WKUP Pad 12 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 7. "WKUP_PUS11,WKUP Pad 11 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 6. "WKUP_PUS10,WKUP Pad 10 Pullup Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x0 5. "WKUP_PUS9,WKUP Pad 9 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 4. "WKUP_PUS8,WKUP Pad 8 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 3. "WKUP_PUS7,WKUP Pad 7 Pullup Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x0 2. "WKUP_PUS6,WKUP Pad 6 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 1. "WKUP_PUS5,WKUP Pad 5 Pullup Select" "0: Pulldown,1: Pullup" bitfld.long 0x0 0. "WKUP_PUS4,WKUP Pad 4 Pullup Select" "0: Pulldown,1: Pullup" tree.end tree.end tree.end tree "SBSW (Safety by Software)" base ad:0x40310000 wgroup.long 0x0++0x7 line.long 0x0 "TMC_CONFIG_UNLOCK,TMC Configuration Unlock" hexmask.long 0x0 0.--31. 1. "KEY,Key" line.long 0x4 "TMWDP_CONFIG_UNLOCK,TMWDP Configuration Unlock" hexmask.long 0x4 0.--31. 1. "KEY,Key" rgroup.long 0x8++0x7 line.long 0x0 "TMC_CONFIG_STATUS,TMC Configuration Status" bitfld.long 0x0 0. "STATUS,Status" "0: Locked,1: Unlocked" line.long 0x4 "TMWDP_CONFIG_STATUS,TMWDP Configuration Status" bitfld.long 0x4 0. "STATUS,Status" "0: Locked,1: Unlocked" group.long 0x10++0x3 line.long 0x0 "DEBUG_MODE,Debug Mode" bitfld.long 0x0 31. "MODE,Mode" "0: Debug mode does not affect the SBSW behavior.,1: All counters/timers within the SBSW stop in the.." rgroup.long 0x14++0x7 line.long 0x0 "TMC_FAULT_STATUS,TMC Fault Status" bitfld.long 0x0 31. "STATUS31,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 30. "STATUS30,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 29. "STATUS29,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 28. "STATUS28,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 27. "STATUS27,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 26. "STATUS26,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 25. "STATUS25,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 24. "STATUS24,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 23. "STATUS23,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 22. "STATUS22,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 21. "STATUS21,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 20. "STATUS20,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 19. "STATUS19,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 18. "STATUS18,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 17. "STATUS17,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 16. "STATUS16,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 15. "STATUS15,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 14. "STATUS14,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 13. "STATUS13,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 12. "STATUS12,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 11. "STATUS11,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 10. "STATUS10,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 9. "STATUS9,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 8. "STATUS8,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 7. "STATUS7,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 6. "STATUS6,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 5. "STATUS5,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 4. "STATUS4,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 3. "STATUS3,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 2. "STATUS2,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 1. "STATUS1,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x0 0. "STATUS0,Status n" "0: Fault is not detected.,1: Fault is detected." line.long 0x4 "TMWDP_FAULT_STATUS,TMWDP Fault Status" bitfld.long 0x4 31. "STATUS31,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 30. "STATUS30,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 29. "STATUS29,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 28. "STATUS28,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 27. "STATUS27,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 26. "STATUS26,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 25. "STATUS25,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 24. "STATUS24,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 23. "STATUS23,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 22. "STATUS22,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 21. "STATUS21,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 20. "STATUS20,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 19. "STATUS19,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 18. "STATUS18,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 17. "STATUS17,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 16. "STATUS16,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 15. "STATUS15,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 14. "STATUS14,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 13. "STATUS13,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 12. "STATUS12,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 11. "STATUS11,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 10. "STATUS10,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 9. "STATUS9,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 8. "STATUS8,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 7. "STATUS7,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 6. "STATUS6,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 5. "STATUS5,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 4. "STATUS4,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 3. "STATUS3,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 2. "STATUS2,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 1. "STATUS1,Status n" "0: Fault is not detected.,1: Fault is detected." newline bitfld.long 0x4 0. "STATUS0,Status n" "0: Fault is not detected.,1: Fault is detected." repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40310020 ad:0x40310040 ad:0x40310060 ad:0x40310080 ad:0x403100A0 ad:0x403100C0 ad:0x403100E0 ad:0x40310100 ad:0x40310120 ad:0x40310140 ad:0x40310160 ad:0x40310180 ad:0x403101A0 ad:0x403101C0 ad:0x403101E0 ad:0x40310200) tree "TMC[$1]" base $2 group.long ($2)++0x1B line.long 0x0 "TMC__CONFIG,TMC Configuration" bitfld.long 0x0 1.--2. "COMPARE_MODE,Compare mode" "0: (R0 == R1),1: (R0 < R1),2: (R0 > R1),3: (|R1 - R0| <= D)" bitfld.long 0x0 0. "TIMING_MODE,Timing mode" "0: Watchdog Mode,1: Window Mode" line.long 0x4 "TMC__DISTANCE,TMC Distance" hexmask.long 0x4 0.--31. 1. "DISTANCE,Distance value" line.long 0x8 "TMC__TIMEOUT,TMC Timeout" hexmask.long 0x8 0.--31. 1. "TIMEOUT,Timeout interval" line.long 0xC "TMC__CONTROL,TMC Control" bitfld.long 0xC 0. "ENABLE,Enable" "0: TMC is disabled.,1: TMC is enabled." line.long 0x10 "TMC__R0,TMC R0 Data" hexmask.long 0x10 0.--31. 1. "R0,R0 data value" line.long 0x14 "TMC__R1,TMC R1 Data" hexmask.long 0x14 0.--31. 1. "R1,R1 data value" line.long 0x18 "TMC__STATUS,TMC Status" rbitfld.long 0x18 4. "OVERWRITTEN,Overwritten" "0: Neither R0 nor R1 is overwritten.,1: R0 or R1 is overwritten." eventfld.long 0x18 2.--3. "FAULT,Fault indicator" "0: No fault,1: False comparison,2: Timeout or overwritten R0/R1,?" newline rbitfld.long 0x18 1. "R1_WRITTEN,R1 written" "0: R1 has not been written in the current cycle.,1: TMC is in the Timing state." rbitfld.long 0x18 0. "R0_WRITTEN,R0 written" "0: R0 has not been written in the current cycle.,1: TMC is in the Timing state." rgroup.long ($2+0x1C)++0x3 line.long 0x0 "TMC__TIMER,TMC Timer" hexmask.long 0x0 0.--31. 1. "TIMER,Timer value" tree.end repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40310220 ad:0x40310240 ad:0x40310260 ad:0x40310280 ad:0x403102A0 ad:0x403102C0 ad:0x403102E0 ad:0x40310300 ad:0x40310320 ad:0x40310340 ad:0x40310360 ad:0x40310380 ad:0x403103A0 ad:0x403103C0 ad:0x403103E0 ad:0x40310400) tree "TMC[$1]" base $2 group.long ($2)++0x1B line.long 0x0 "TMC__CONFIG,TMC Configuration" bitfld.long 0x0 1.--2. "COMPARE_MODE,Compare mode" "0: (R0 == R1),1: (R0 < R1),2: (R0 > R1),3: (|R1 - R0| <= D)" bitfld.long 0x0 0. "TIMING_MODE,Timing mode" "0: Watchdog Mode,1: Window Mode" line.long 0x4 "TMC__DISTANCE,TMC Distance" hexmask.long 0x4 0.--31. 1. "DISTANCE,Distance value" line.long 0x8 "TMC__TIMEOUT,TMC Timeout" hexmask.long 0x8 0.--31. 1. "TIMEOUT,Timeout interval" line.long 0xC "TMC__CONTROL,TMC Control" bitfld.long 0xC 0. "ENABLE,Enable" "0: TMC is disabled.,1: TMC is enabled." line.long 0x10 "TMC__R0,TMC R0 Data" hexmask.long 0x10 0.--31. 1. "R0,R0 data value" line.long 0x14 "TMC__R1,TMC R1 Data" hexmask.long 0x14 0.--31. 1. "R1,R1 data value" line.long 0x18 "TMC__STATUS,TMC Status" rbitfld.long 0x18 4. "OVERWRITTEN,Overwritten" "0: Neither R0 nor R1 is overwritten.,1: R0 or R1 is overwritten." eventfld.long 0x18 2.--3. "FAULT,Fault indicator" "0: No fault,1: False comparison,2: Timeout or overwritten R0/R1,?" newline rbitfld.long 0x18 1. "R1_WRITTEN,R1 written" "0: R1 has not been written in the current cycle.,1: TMC is in the Timing state." rbitfld.long 0x18 0. "R0_WRITTEN,R0 written" "0: R0 has not been written in the current cycle.,1: TMC is in the Timing state." rgroup.long ($2+0x1C)++0x3 line.long 0x0 "TMC__TIMER,TMC Timer" hexmask.long 0x0 0.--31. 1. "TIMER,Timer value" tree.end repeat.end base ad:0x40310000 group.long 0x420++0x7 line.long 0x0 "TMWDP_CONFIG_ADDR,TMWDP Configuration Address" hexmask.long 0x0 0.--31. 1. "ADDRESS,Configuration address" line.long 0x4 "TMWDP_CONTROL,TMWDP Control" bitfld.long 0x4 0. "ENABLE,Enable" "0: TMWDP is disabled.,1: TMWDP is enabled." rgroup.long 0x428++0xF line.long 0x0 "TMWDP_STATUS,TMWDP Status" bitfld.long 0x0 2. "RUNNING,TMWDP running" "0: TMWDP is stopped or has encountered an error or..,1: TMWDP is running." newline bitfld.long 0x0 1. "CONFIG_ERROR,Configuration error" "0: No TMWDP configuration error.,1: TMWDP configuration error is detected." newline bitfld.long 0x0 0. "INTERNAL_ERROR,TMWDP internal error" "0: No TMWDP internal error.,1: TMWDP internal error is detected." line.long 0x4 "TMWDP_AUTOMATA_STATUS,TMWDP Automata Status" bitfld.long 0x4 31. "STATUS31,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 30. "STATUS30,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 29. "STATUS29,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 28. "STATUS28,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 27. "STATUS27,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 26. "STATUS26,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 25. "STATUS25,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 24. "STATUS24,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 23. "STATUS23,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 22. "STATUS22,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 21. "STATUS21,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 20. "STATUS20,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 19. "STATUS19,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 18. "STATUS18,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 17. "STATUS17,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 16. "STATUS16,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 15. "STATUS15,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 14. "STATUS14,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 13. "STATUS13,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 12. "STATUS12,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 11. "STATUS11,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 10. "STATUS10,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 9. "STATUS9,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 8. "STATUS8,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 7. "STATUS7,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 6. "STATUS6,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 5. "STATUS5,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 4. "STATUS4,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 3. "STATUS3,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 2. "STATUS2,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 1. "STATUS1,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." newline bitfld.long 0x4 0. "STATUS0,Status n" "0: Automaton has stopped (initial or fault state).,1: Automaton is running." line.long 0x8 "TMWDP_AUTOMATA_ILLGL_TRANS,TMWDP Automata Illegal Transition" bitfld.long 0x8 31. "STATUS31,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 30. "STATUS30,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 29. "STATUS29,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 28. "STATUS28,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 27. "STATUS27,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 26. "STATUS26,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 25. "STATUS25,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 24. "STATUS24,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 23. "STATUS23,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 22. "STATUS22,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 21. "STATUS21,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 20. "STATUS20,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 19. "STATUS19,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 18. "STATUS18,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 17. "STATUS17,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 16. "STATUS16,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 15. "STATUS15,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 14. "STATUS14,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 13. "STATUS13,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 12. "STATUS12,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 11. "STATUS11,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 10. "STATUS10,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 9. "STATUS9,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 8. "STATUS8,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 7. "STATUS7,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 6. "STATUS6,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 5. "STATUS5,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 4. "STATUS4,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 3. "STATUS3,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 2. "STATUS2,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 1. "STATUS1,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." newline bitfld.long 0x8 0. "STATUS0,Status n" "0: Automaton has not detected a faulty transition.,1: Automaton has detected a faulty transition." line.long 0xC "TMWDP_AUTOMATA_TIME_VIOLATION,TMWDP Automata Time Violation" bitfld.long 0xC 31. "STATUS31,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 30. "STATUS30,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 29. "STATUS29,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 28. "STATUS28,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 27. "STATUS27,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 26. "STATUS26,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 25. "STATUS25,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 24. "STATUS24,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 23. "STATUS23,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 22. "STATUS22,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 21. "STATUS21,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 20. "STATUS20,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 19. "STATUS19,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 18. "STATUS18,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 17. "STATUS17,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 16. "STATUS16,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 15. "STATUS15,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 14. "STATUS14,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 13. "STATUS13,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 12. "STATUS12,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 11. "STATUS11,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 10. "STATUS10,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 9. "STATUS9,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 8. "STATUS8,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 7. "STATUS7,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 6. "STATUS6,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 5. "STATUS5,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 4. "STATUS4,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 3. "STATUS3,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 2. "STATUS2,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 1. "STATUS1,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." newline bitfld.long 0xC 0. "STATUS0,Status n" "0: Automaton has not detected a time violation.,1: Automaton has detected a time violation." repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40310450 ad:0x40310458 ad:0x40310460 ad:0x40310468 ad:0x40310470 ad:0x40310478 ad:0x40310480 ad:0x40310488 ad:0x40310490 ad:0x40310498 ad:0x403104A0 ad:0x403104A8 ad:0x403104B0 ad:0x403104B8 ad:0x403104C0 ad:0x403104C8) tree "AUT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "AUT__STATUS,TMWDP Automaton Status" bitfld.long 0x0 18. "TIME_VIOLATION,Time violation" "0: Time violation is not detected.,1: Time violation is detected." bitfld.long 0x0 17. "ILLEGAL_TRANSITION,Illegal transition" "0: Illegal transition is not detected.,1: Illegal transition is detected." newline bitfld.long 0x0 16. "STATUS,Automaton status" "0: Stopped (initial or fault state),1: Running state" hexmask.long.word 0x0 0.--15. 1. "CURRENT_STATE,Automaton current state" group.long ($2+0x4)++0x3 line.long 0x0 "AUT__PRGS_REQ,TMWDP Automaton Progress Request" rbitfld.long 0x0 17. "OVERWRITTEN,Overwritten" "0: PROGRESS_REQ is not overwritten.,1: PROGRESS_REQ is overwritten." rbitfld.long 0x0 16. "WRITTEN,Written" "0: PROGRESS_REQ is not written.,1: PROGRESS_REQ is written." newline hexmask.long.word 0x0 0.--15. 1. "PROGRESS_REQ,Application progress request" tree.end repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x403104D0 ad:0x403104D8 ad:0x403104E0 ad:0x403104E8 ad:0x403104F0 ad:0x403104F8 ad:0x40310500 ad:0x40310508 ad:0x40310510 ad:0x40310518 ad:0x40310520 ad:0x40310528 ad:0x40310530 ad:0x40310538 ad:0x40310540 ad:0x40310548) tree "AUT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "AUT__STATUS,TMWDP Automaton Status" bitfld.long 0x0 18. "TIME_VIOLATION,Time violation" "0: Time violation is not detected.,1: Time violation is detected." bitfld.long 0x0 17. "ILLEGAL_TRANSITION,Illegal transition" "0: Illegal transition is not detected.,1: Illegal transition is detected." newline bitfld.long 0x0 16. "STATUS,Automaton status" "0: Stopped (initial or fault state),1: Running state" hexmask.long.word 0x0 0.--15. 1. "CURRENT_STATE,Automaton current state" group.long ($2+0x4)++0x3 line.long 0x0 "AUT__PRGS_REQ,TMWDP Automaton Progress Request" rbitfld.long 0x0 17. "OVERWRITTEN,Overwritten" "0: PROGRESS_REQ is not overwritten.,1: PROGRESS_REQ is overwritten." rbitfld.long 0x0 16. "WRITTEN,Written" "0: PROGRESS_REQ is not written.,1: PROGRESS_REQ is written." newline hexmask.long.word 0x0 0.--15. 1. "PROGRESS_REQ,Application progress request" tree.end repeat.end base ad:0x40310000 group.long 0xFFC++0x3 line.long 0x0 "TC_ID,TMWDP Core Domain ID" rbitfld.long 0x0 8. "WRITTEN,TC ID status" "0: Domain ID is not written.,1: Domain ID is written." newline hexmask.long.byte 0x0 0.--3. 1. "ID,TC domain ID value" tree.end tree "SECURITY" base ad:0x4007C900 rgroup.long 0x8++0x3 line.long 0x0 "EXT_DBGSTAT,External Debugger Status" bitfld.long 0x0 0. "EDB,External debugger indication" "0: External debugger is not connected.,1: External debugger (JTAG) is connected." group.long 0x1C++0xB line.long 0x0 "HSE_GPR0,HSE GPR 0" hexmask.long 0x0 7.--31. 1. "DATA1,General purpose data" hexmask.long.byte 0x0 0.--5. 1. "DATA0,General purpose data" line.long 0x4 "HSE_GPR1,HSE GPR n" hexmask.long 0x4 0.--31. 1. "DATA,General purpose data" line.long 0x8 "HSE_GPR2,HSE GPR n" hexmask.long 0x8 0.--31. 1. "DATA,General purpose data" repeat 9. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x28)++0x3 line.long 0x0 "HSE_GPR$1,HSE GPR n" hexmask.long 0x0 0.--31. 1. "DATA,General purpose data" repeat.end tree.end tree "SELFTEST_GPR (SELFTEST General Purpose Registers)" base ad:0x0 tree "SELFTEST_GPR" base ad:0x4001C000 group.long 0x0++0x7 line.long 0x0 "Generic_Reg0,Generic 0" bitfld.long 0x0 8. "pcs_enable_end,PCS enable end" "0,1" bitfld.long 0x0 7. "pcs_enable_start,PCS enable start" "0,1" bitfld.long 0x0 4.--6. "pcs_step_size,PCS step size" "0,1,2,3,4,5,6,7" line.long 0x4 "Generic_Reg1,Generic 1" hexmask.long 0x4 0.--31. 1. "hard_macro_bypass,Hard Macro Bypass" group.long 0x14++0x3 line.long 0x0 "LBIST_Prog_Reg,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_shift_count,LBIST Shift Count" tree.end tree "SELFTEST_GPR_CHIPTOP" base ad:0x4001C560 group.long 0x0++0x7 line.long 0x0 "Generic_Reg0,Generic 0" bitfld.long 0x0 8. "pcs_enable_end,PCS enable end" "0,1" bitfld.long 0x0 7. "pcs_enable_start,PCS enable start" "0,1" bitfld.long 0x0 4.--6. "pcs_step_size,PCS step size" "0,1,2,3,4,5,6,7" line.long 0x4 "Generic_Reg1,Generic 1" hexmask.long 0x4 0.--31. 1. "hard_macro_bypass,Hard Macro Bypass" group.long 0x14++0x3 line.long 0x0 "LBIST_Prog_Reg,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_shift_count,LBIST Shift Count" tree.end tree "SELFTEST_GPR_MEM_NOC_0" base ad:0x4001C520 group.long 0x0++0x7 line.long 0x0 "Generic_Reg0,Generic 0" bitfld.long 0x0 8. "pcs_enable_end,PCS enable end" "0,1" bitfld.long 0x0 7. "pcs_enable_start,PCS enable start" "0,1" bitfld.long 0x0 4.--6. "pcs_step_size,PCS step size" "0,1,2,3,4,5,6,7" line.long 0x4 "Generic_Reg1,Generic 1" hexmask.long 0x4 0.--31. 1. "hard_macro_bypass,Hard Macro Bypass" group.long 0x14++0x3 line.long 0x0 "LBIST_Prog_Reg,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_shift_count,LBIST Shift Count" tree.end tree "SELFTEST_GPR_MEM_NOC_1" base ad:0x4001C540 group.long 0x0++0x7 line.long 0x0 "Generic_Reg0,Generic 0" bitfld.long 0x0 8. "pcs_enable_end,PCS enable end" "0,1" bitfld.long 0x0 7. "pcs_enable_start,PCS enable start" "0,1" bitfld.long 0x0 4.--6. "pcs_step_size,PCS step size" "0,1,2,3,4,5,6,7" line.long 0x4 "Generic_Reg1,Generic 1" hexmask.long 0x4 0.--31. 1. "hard_macro_bypass,Hard Macro Bypass" group.long 0x14++0x3 line.long 0x0 "LBIST_Prog_Reg,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_shift_count,LBIST Shift Count" tree.end tree "SELFTEST_GPR_MISC" base ad:0x4001C500 group.long 0x0++0x7 line.long 0x0 "Generic_Reg0,Generic 0" bitfld.long 0x0 8. "pcs_enable_end,PCS enable end" "0,1" bitfld.long 0x0 7. "pcs_enable_start,PCS enable start" "0,1" bitfld.long 0x0 4.--6. "pcs_step_size,PCS step size" "0,1,2,3,4,5,6,7" line.long 0x4 "Generic_Reg1,Generic 1" hexmask.long 0x4 0.--31. 1. "hard_macro_bypass,Hard Macro Bypass" group.long 0x14++0x3 line.long 0x0 "LBIST_Prog_Reg,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_shift_count,LBIST Shift Count" tree.end tree "SELFTEST_GPR_NOC_PART1" base ad:0x4001C480 group.long 0x0++0x7 line.long 0x0 "Generic_Reg0,Generic 0" bitfld.long 0x0 8. "pcs_enable_end,PCS enable end" "0,1" bitfld.long 0x0 7. "pcs_enable_start,PCS enable start" "0,1" bitfld.long 0x0 4.--6. "pcs_step_size,PCS step size" "0,1,2,3,4,5,6,7" line.long 0x4 "Generic_Reg1,Generic 1" hexmask.long 0x4 0.--31. 1. "hard_macro_bypass,Hard Macro Bypass" group.long 0x14++0x3 line.long 0x0 "LBIST_Prog_Reg,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_shift_count,LBIST Shift Count" tree.end tree "SELFTEST_GPR_NOC_PART2" base ad:0x4001C4A0 group.long 0x0++0x7 line.long 0x0 "Generic_Reg0,Generic 0" bitfld.long 0x0 8. "pcs_enable_end,PCS enable end" "0,1" bitfld.long 0x0 7. "pcs_enable_start,PCS enable start" "0,1" bitfld.long 0x0 4.--6. "pcs_step_size,PCS step size" "0,1,2,3,4,5,6,7" line.long 0x4 "Generic_Reg1,Generic 1" hexmask.long 0x4 0.--31. 1. "hard_macro_bypass,Hard Macro Bypass" group.long 0x14++0x3 line.long 0x0 "LBIST_Prog_Reg,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_shift_count,LBIST Shift Count" tree.end tree "SELFTEST_GPR_NOC_PART3" base ad:0x4001C4C0 group.long 0x0++0x7 line.long 0x0 "Generic_Reg0,Generic 0" bitfld.long 0x0 8. "pcs_enable_end,PCS enable end" "0,1" bitfld.long 0x0 7. "pcs_enable_start,PCS enable start" "0,1" bitfld.long 0x0 4.--6. "pcs_step_size,PCS step size" "0,1,2,3,4,5,6,7" line.long 0x4 "Generic_Reg1,Generic 1" hexmask.long 0x4 0.--31. 1. "hard_macro_bypass,Hard Macro Bypass" group.long 0x14++0x3 line.long 0x0 "LBIST_Prog_Reg,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_shift_count,LBIST Shift Count" tree.end tree "SELFTEST_GPR_NOC_PART4" base ad:0x4001C4E0 group.long 0x0++0x7 line.long 0x0 "Generic_Reg0,Generic 0" bitfld.long 0x0 8. "pcs_enable_end,PCS enable end" "0,1" bitfld.long 0x0 7. "pcs_enable_start,PCS enable start" "0,1" bitfld.long 0x0 4.--6. "pcs_step_size,PCS step size" "0,1,2,3,4,5,6,7" line.long 0x4 "Generic_Reg1,Generic 1" hexmask.long 0x4 0.--31. 1. "hard_macro_bypass,Hard Macro Bypass" group.long 0x14++0x3 line.long 0x0 "LBIST_Prog_Reg,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_shift_count,LBIST Shift Count" tree.end tree.end tree "SELFTEST_GPR_TOP (SELFTEST Top General Purpose Registers)" base ad:0x4001CFE0 group.long 0x0++0x7 line.long 0x0 "Reset_Domain_Selftest_Enable_Register,Reset Domain Self-test Enable" bitfld.long 0x0 3. "RESET_DOMAIN_3_SELFTEST_ENABLE,Reset Domain Self-Test Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "RESET_DOMAIN_2_SELFTEST_ENABLE,Reset Domain Self-Test Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "RESET_DOMAIN_1_SELFTEST_ENABLE,Reset Domain Self-Test Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "RESET_DOMAIN_0_SELFTEST_ENABLE,Reset Domain Self-Test Enable" "0: Disabled,1: Enabled" line.long 0x4 "Reset_Domain_Selftest_Enable_Status_Register,Reset Domain Self-test Enable Status" eventfld.long 0x4 19. "RESET_DOMAIN_3_SELFTEST_ENABLE_LAST_RUN_STATUS,Reset Domain Self-Test Enable Last Run Status" "0: Disabled,1: Enabled" newline eventfld.long 0x4 18. "RESET_DOMAIN_2_SELFTEST_ENABLE_LAST_RUN_STATUS,Reset Domain Self-Test Enable Last Run Status" "0: Disabled,1: Enabled" newline eventfld.long 0x4 17. "RESET_DOMAIN_1_SELFTEST_ENABLE_LAST_RUN_STATUS,Reset Domain Self-Test Enable Last Run Status" "0: Disabled,1: Enabled" newline eventfld.long 0x4 16. "RESET_DOMAIN_0_SELFTEST_ENABLE_LAST_RUN_STATUS,Reset Domain Self-Test Enable Last Run Status" "0: Disabled,1: Enabled" newline rbitfld.long 0x4 3. "RESET_DOMAIN_3_SELFTEST_ENABLE_STATUS,Reset Domain Self-Test Enable Status" "0: Disabled,1: Enabled" newline rbitfld.long 0x4 2. "RESET_DOMAIN_2_SELFTEST_ENABLE_STATUS,Reset Domain Self-Test Enable Status" "0: Disabled,1: Enabled" newline rbitfld.long 0x4 1. "RESET_DOMAIN_1_SELFTEST_ENABLE_STATUS,Reset Domain Self-Test Enable Status" "0: Disabled,1: Enabled" newline rbitfld.long 0x4 0. "RESET_DOMAIN_0_SELFTEST_ENABLE_STATUS,Reset Domain Self-Test Enable Status" "0: Disabled,1: Enabled" tree.end tree "SEMA42 (Semaphores2)" base ad:0x40298000 group.byte 0x0++0xF line.byte 0x0 "GATE3,Gate" hexmask.byte 0x0 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x1 "GATE2,Gate" hexmask.byte 0x1 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x2 "GATE1,Gate" hexmask.byte 0x2 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x3 "GATE0,Gate" hexmask.byte 0x3 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x4 "GATE7,Gate" hexmask.byte 0x4 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x5 "GATE6,Gate" hexmask.byte 0x5 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x6 "GATE5,Gate" hexmask.byte 0x6 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x7 "GATE4,Gate" hexmask.byte 0x7 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x8 "GATE11,Gate" hexmask.byte 0x8 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x9 "GATE10,Gate" hexmask.byte 0x9 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xA "GATE9,Gate" hexmask.byte 0xA 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xB "GATE8,Gate" hexmask.byte 0xB 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xC "GATE15,Gate" hexmask.byte 0xC 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xD "GATE14,Gate" hexmask.byte 0xD 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xE "GATE13,Gate" hexmask.byte 0xE 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xF "GATE12,Gate" hexmask.byte 0xF 0.--3. 1. "GTFSM,Gate Finite State Machine" rgroup.word 0x42++0x1 line.word 0x0 "RSTGT_R,Reset Gate Read" bitfld.word 0x0 12.--13. "RSTGSM,Reset Gate Finite State Machine" "0: Idle waiting for the first data pattern write.,1: Waiting for the second data pattern write,2: The 2-write sequence has completed. Generate the..,?" hexmask.word.byte 0x0 8.--11. 1. "RSTGMS,Reset Gate Domain" hexmask.word.byte 0x0 0.--7. 1. "RSTGTN,Reset Gate Number" wgroup.word 0x42++0x1 line.word 0x0 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x0 8.--15. 1. "RSTGDP,Reset Gate Data Pattern" hexmask.word.byte 0x0 0.--7. 1. "RSTGTN,Reset Gate Number" tree.end tree "SERDES (SerDes Subsystem)" base ad:0x0 tree "SERDES_0_GPR" base ad:0x4007C500 group.long 0x0++0x3 line.long 0x0 "PCIE_Config_0,PCIE Configuration 0" eventfld.long 0x0 3. "parity_chk_slv_rdatap_err,parity_chk_slv_rdatap_err Parity Check Error Status" "0: Parity error did not occur,1: Parity error occurred" eventfld.long 0x0 2. "parity_chk_mstr_wdatap_err,parity_chk_mstr_wdatap_err Parity Check Error Status" "0: Parity error did not occur,1: Parity error occurred" newline eventfld.long 0x0 1. "parity_chk_mstr_awaddrp_err,mstr_awaddrp Parity Check Error Status" "0: Parity error did not occur,1: Parity error occurred" eventfld.long 0x0 0. "parity_chk_mstr_araddrp_err,mstr_araddrp Parity Check Error Status" "0: Parity error did not occur,1: Parity error occurred" tree.end tree "SERDES_1_GPR" base ad:0x4007CC00 group.long 0x0++0x3 line.long 0x0 "PCIE_Config_0,PCIE Configuration 0" eventfld.long 0x0 3. "parity_chk_slv_rdatap_err,parity_chk_slv_rdatap_err Parity Check Error Status" "0: Parity error did not occur,1: Parity error occurred" eventfld.long 0x0 2. "parity_chk_mstr_wdatap_err,parity_chk_mstr_wdatap_err Parity Check Error Status" "0: Parity error did not occur,1: Parity error occurred" newline eventfld.long 0x0 1. "parity_chk_mstr_awaddrp_err,mstr_awaddrp Parity Check Error Status" "0: Parity error did not occur,1: Parity error occurred" eventfld.long 0x0 0. "parity_chk_mstr_araddrp_err,mstr_araddrp Parity Check Error Status" "0: Parity error did not occur,1: Parity error occurred" tree.end tree "SERDES_DMA_PCIE_1" base ad:0x44170000 group.long 0x0++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA arbitration scheme for TRGT1 interface" bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" group.long 0x8++0xB line.long 0x0 "DMA_CTRL_OFF,DMA number of channels" bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "0: Disable,1: Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell" bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number" "0,1,2,3,4,5,6,7" group.long 0x18++0x3 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA write engine channel arbitration weight low" hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long 0x2C++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "0: Disable,1: Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell" bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number" "0,1,2,3,4,5,6,7" group.long 0x38++0x3 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA read engine channel arbitration weight low" hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long 0x4C++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status" hexmask.long.byte 0x0 16.--19. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status" newline hexmask.long.byte 0x0 0.--3. 1. "WR_DONE_INT_STATUS,Done Interrupt Status" group.long 0x54++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA write interrupt mask" hexmask.long.byte 0x0 16.--19. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 0.--3. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA write interrupt clear" hexmask.long.byte 0x4 16.--19. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 0.--3. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long 0x5C++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status" hexmask.long.byte 0x0 16.--19. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected" newline hexmask.long.byte 0x0 0.--3. 1. "APP_READ_ERR_DETECT,Application Read Error Detected" group.long 0x60++0x17 line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA write done IMWr address low" hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA write done IMWr interrupt address high" hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA write abort IMWr address low" hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA write abort IMWr address high" hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA write channel 0 and 1 IMWr data" hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA write channel 2 and 3 IMWr data" hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: R/W" group.long 0x90++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA write linked list error enable" hexmask.long.byte 0x0 16.--19. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 0.--3. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long 0xA0++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status" hexmask.long.byte 0x0 16.--19. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status" newline hexmask.long.byte 0x0 0.--3. 1. "RD_DONE_INT_STATUS,Done Interrupt Status" group.long 0xA8++0x3 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA read interrupt mask" hexmask.long.byte 0x0 16.--19. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 0.--3. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." wgroup.long 0xAC++0x3 line.long 0x0 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear" hexmask.long.byte 0x0 16.--19. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear" newline hexmask.long.byte 0x0 0.--3. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear" rgroup.long 0xB4++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low" hexmask.long.byte 0x0 16.--19. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected" newline hexmask.long.byte 0x0 0.--3. 1. "APP_WR_ERR_DETECT,Application Write Error Detected" line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High" hexmask.long.byte 0x4 24.--27. 1. "DATA_POISIONING,Data Poisoning" newline hexmask.long.byte 0x4 16.--19. 1. "CPL_TIMEOUT,Completion Time Out" newline hexmask.long.byte 0x4 8.--11. 1. "CPL_ABORT,Completer Abort" newline hexmask.long.byte 0x4 0.--3. 1. "UNSUPPORTED_REQ,Unsupported Request" group.long 0xC4++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA read linked list error enable" hexmask.long.byte 0x0 16.--19. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 0.--3. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long 0xCC++0x17 line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA read done IMWr address low" hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA read done IMWr address high" hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low" hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,DMA Read Abort Low" line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High" hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,DMA Read Abort High" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 0 And 1 IMWr Data" hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,Read Channel 1 Data" newline hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,Read Channel 0 Data" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 2 And 3 IMWr Data" hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,Read Channel 3 Data" newline hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,Read Channel 2 Data" rgroup.long 0x108++0x3 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA write engine handshake counter channel 0/1/2/3" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long 0x118++0x3 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA read engine handshake counter channel 0/1/2/3" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." group.long 0x200++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_0,DMA Write Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x208++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_0,DMA write transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." line.long 0x4 "DMA_SAR_LOW_OFF_WRCH_0,DMA Write SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_WRCH_0,DMA write SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_WRCH_0,DMA Write DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_0,DMA write DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_0,DMA write linked list pointer low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_0,DMA write linked list pointer high" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." group.long 0x300++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_0,DMA Read Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x308++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_0,DMA read transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." line.long 0x4 "DMA_SAR_LOW_OFF_RDCH_0,DMA Read SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_RDCH_0,DMA read SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_RDCH_0,DMA Read DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 Bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_RDCH_0,DMA read DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_RDCH_0,DMA Read Linked List Pointer Low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower Bits" line.long 0x18 "DMA_LLP_HIGH_OFF_RDCH_0,DMA Read Linked List Pointer High" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper Bits" group.long 0x400++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_1,DMA Write Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x408++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_1,DMA write transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." line.long 0x4 "DMA_SAR_LOW_OFF_WRCH_1,DMA Write SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_WRCH_1,DMA write SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_WRCH_1,DMA Write DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_1,DMA write DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_1,DMA write linked list pointer low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_1,DMA write linked list pointer high" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." group.long 0x500++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_1,DMA Read Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x508++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_1,DMA read transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." line.long 0x4 "DMA_SAR_LOW_OFF_RDCH_1,DMA Read SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_RDCH_1,DMA read SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_RDCH_1,DMA Read DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 Bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_RDCH_1,DMA read DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_RDCH_1,DMA Read Linked List Pointer Low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower Bits" line.long 0x18 "DMA_LLP_HIGH_OFF_RDCH_1,DMA Read Linked List Pointer High" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper Bits" group.long 0x600++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_2,DMA Write Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x608++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_2,DMA write transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." line.long 0x4 "DMA_SAR_LOW_OFF_WRCH_2,DMA Write SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_WRCH_2,DMA write SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_WRCH_2,DMA Write DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_2,DMA write DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_2,DMA write linked list pointer low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_2,DMA write linked list pointer high" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." group.long 0x700++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_2,DMA Read Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x708++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_2,DMA read transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." line.long 0x4 "DMA_SAR_LOW_OFF_RDCH_2,DMA Read SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_RDCH_2,DMA read SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_RDCH_2,DMA Read DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 Bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_RDCH_2,DMA read DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_RDCH_2,DMA Read Linked List Pointer Low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower Bits" line.long 0x18 "DMA_LLP_HIGH_OFF_RDCH_2,DMA Read Linked List Pointer High" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper Bits" group.long 0x800++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_3,DMA Write Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x808++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_3,DMA write transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." line.long 0x4 "DMA_SAR_LOW_OFF_WRCH_3,DMA Write SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_WRCH_3,DMA write SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_WRCH_3,DMA Write DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_WRCH_3,DMA write DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_WRCH_3,DMA write linked list pointer low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." line.long 0x18 "DMA_LLP_HIGH_OFF_WRCH_3,DMA write linked list pointer high" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." group.long 0x900++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_3,DMA Read Channel Control" bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline hexmask.long.byte 0x0 17.--22. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." newline bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: R/W" "0: Disable linked list operation,1: Enable linked list operation Note: The access.." newline bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: R/W" "0,1" newline rbitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "0: Reserved,1: Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" newline bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" newline bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" group.long 0x908++0x1B line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_3,DMA read transfer size" hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." line.long 0x4 "DMA_SAR_LOW_OFF_RDCH_3,DMA Read SAR Low" hexmask.long 0x4 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 Bits)" line.long 0x8 "DMA_SAR_HIGH_OFF_RDCH_3,DMA read SAR high" hexmask.long 0x8 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0xC "DMA_DAR_LOW_OFF_RDCH_3,DMA Read DAR Low" hexmask.long 0xC 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address (Lower 32 Bits)" line.long 0x10 "DMA_DAR_HIGH_OFF_RDCH_3,DMA read DAR high" hexmask.long 0x10 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W" line.long 0x14 "DMA_LLP_LOW_OFF_RDCH_3,DMA Read Linked List Pointer Low" hexmask.long 0x14 0.--31. 1. "LLP_LOW,Lower Bits" line.long 0x18 "DMA_LLP_HIGH_OFF_RDCH_3,DMA Read Linked List Pointer High" hexmask.long 0x18 0.--31. 1. "LLP_HIGH,Upper Bits" tree.end tree "SERDES_EP_PCIE_1" base ad:0x44100000 rgroup.long 0x0++0x3 line.long 0x0 "DEVICE_VENDOR_ID,Device ID And Vendor ID" hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID" newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID" group.long 0x4++0x3 line.long 0x0 "COMMAND,Command And Status" eventfld.long 0x0 31. "DETECTED_PARITY_ERR,Detected parity error" "0,1" newline eventfld.long 0x0 30. "SIGNALED_SYS_ERR,Signaled system error" "0,1" newline eventfld.long 0x0 29. "RCVD_MASTER_ABORT,Received master abort" "0,1" newline eventfld.long 0x0 28. "RCVD_TARGET_ABORT,Received target abort" "0,1" newline eventfld.long 0x0 27. "SIGNALED_TARGET_ABORT,Signaled target abort" "0,1" newline eventfld.long 0x0 24. "MASTER_DPE,Master data parity error" "0,1" newline rbitfld.long 0x0 19. "INT_STATUS,Emulation interrupt pending" "0: No INTx emulation interrupt is pending.,1: An INTX emulation interrupt is pending." newline bitfld.long 0x0 10. "INT_EN,Interrupt enable/disable" "0: PCIe allows Functions to assert INTx interrupts.,1: PCIe prevents Functions from asserting INTx.." newline bitfld.long 0x0 8. "SERREN,SERR# Enable" "0,1" newline bitfld.long 0x0 6. "PARITY_ERR_RESPONSE,Parity error response" "0,1" newline bitfld.long 0x0 2. "BUS_MASTER_EN,Bus_Master_Enable" "0,1" newline bitfld.long 0x0 1. "MEM_SPACE_EN,Memory_Space_Enable" "0,1" newline bitfld.long 0x0 0. "IO_SPACE_EN,I_O_Space_Enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CLASS_CODE_REVISION_ID,Class Code And Revision ID" hexmask.long.byte 0x0 24.--31. 1. "BASE_CLASS_CODE,Base class code" newline hexmask.long.byte 0x0 16.--23. 1. "SUBCLASS_CODE,Sub-class code" newline hexmask.long.byte 0x0 8.--15. 1. "PROGRAM_INTERFACE,Programming interface" newline hexmask.long.byte 0x0 0.--7. 1. "REVISION_ID,Revision ID" group.long 0xC++0x7 line.long 0x0 "BHTLCLS,BIST. Header Type. Latency Timer. And Cache Line Size" hexmask.long.byte 0x0 24.--31. 1. "BIST,BIST control and status" newline rbitfld.long 0x0 23. "MULTI_FUNC,Multi-function device" "0: Software must not probe for Functions other than..,1: The device may contain multiple Functions." newline hexmask.long.byte 0x0 16.--22. 1. "HEADER_TYPE,Header layout" newline hexmask.long.byte 0x0 0.--7. 1. "CACHE_LINE_SIZE,Cache line size" line.long 0x4 "BAR0,Base Address 0" hexmask.long 0x4 4.--31. 1. "ADDRESS,ADDRESS" newline rbitfld.long 0x4 3. "PREF,PREF" "0: Non-prefetchable,1: Prefetchable" newline bitfld.long 0x4 1.--2. "TYPE,TYPE" "0: = 32-bit BAR,?,2: = 64-bit BAR,?" newline rbitfld.long 0x4 0. "Mem_I_O,Mem_I_O" "0: = BAR 0 is a memory BAR,1: = BAR 0 is an I/O BAR" rgroup.long 0x14++0x3 line.long 0x0 "BAR1,Base Address 1" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x18++0x3 line.long 0x0 "BAR2,Base Address 2" hexmask.long 0x0 4.--31. 1. "ADDRESS,ADDRESS" newline rbitfld.long 0x0 3. "PREF,PREF" "0: Non-prefetchable,1: Prefetchable" newline bitfld.long 0x0 1.--2. "TYPE,TYPE" "0: = 32-bit BAR,?,2: = 64-bit BAR,?" newline rbitfld.long 0x0 0. "MEM_I_O,MEM_I_O" "0: BAR 2 is a memory BAR,1: BAR 2 is an I/O BAR" rgroup.long 0x1C++0x3 line.long 0x0 "BAR3,Base Address 3" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" group.long 0x20++0x3 line.long 0x0 "BAR4,Base Address 4" hexmask.long 0x0 4.--31. 1. "ADDRESS,ADDRESS" newline rbitfld.long 0x0 3. "PREF,PREF" "0: = Non-prefetchable,1: = Prefetchable" newline bitfld.long 0x0 1.--2. "TYPE,TYPE" "0: = 32-bit BAR,?,2: = 64-bit BAR,?" newline bitfld.long 0x0 0. "MEM_I_O,MEM_I_O" "0: = BAR 4 is a memory BAR,1: = BAR 4 is an I/O BAR" rgroup.long 0x24++0x3 line.long 0x0 "BAR5,Base Address 5" hexmask.long 0x0 0.--31. 1. "ADDRESS,ADDRESS" rgroup.long 0x2C++0x3 line.long 0x0 "SSID,Subsystem ID And Subsystem Vendor ID" hexmask.long.word 0x0 16.--31. 1. "SUBSYS_DEV_ID,Subsystem ID" newline hexmask.long.word 0x0 0.--15. 1. "SUBSYS_VENDOR_ID,Subsystem vendor ID" group.long 0x30++0x3 line.long 0x0 "EROMBAR,Expansion ROM Base Address" hexmask.long.tbyte 0x0 11.--31. 1. "ADDRESS,ADDRESS" newline bitfld.long 0x0 0. "ENABLE,ENABLE" "0,1" group.long 0x30++0x3 line.long 0x0 "EROMBARMASK,Expansion ROM BAR Mask" hexmask.long 0x0 1.--31. 1. "ROM_MASK,Expansion ROM Mask" newline rbitfld.long 0x0 0. "ROM_BAR_ENABLED,Expansion ROM Bar Mask Register Enabled" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "CAPPR,Capabilities Pointer" hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities pointer" group.long 0x3C++0x3 line.long 0x0 "MLMGIPIL,Max_Lat. Min_Gnt. Interrupt Pin. And Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. "INT_PIN,INT_PIN" newline hexmask.long.byte 0x0 0.--7. 1. "INT_LINE,Interrupt line" rgroup.long 0x40++0x3 line.long 0x0 "PMCAP,Power Management Capabilities" hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,Power Management Event Support" newline bitfld.long 0x0 26. "D2_SUPPORT,D2 State Support" "0: The Function does not support the D2 power..,1: The Function supports the D2 power management.." newline bitfld.long 0x0 25. "D1_SUPPORT,D1 State Support" "0: The Function does not support the D1 power..,1: The Function supports the D1 power management.." newline bitfld.long 0x0 22.--24. "AUX_CURR,Auxiliary Current Requirements" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device-Specific Initialization" "0: The Function does not require a device-specific..,1: The Function requires a device-specific.." newline bitfld.long 0x0 16.--18. "PM_SPEC_VER,Power management spec version" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next capability pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Power management capability ID" group.long 0x44++0x3 line.long 0x0 "PMCSR,Power Management Control And Status" hexmask.long.byte 0x0 24.--31. 1. "DATA,Power data information" newline rbitfld.long 0x0 23. "BPCC_EN,Bus power/clock control enable" "0: The bus power/clock control policies defined in..,1: The bus power/clock control policies defined in.." newline rbitfld.long 0x0 22. "B2_B3_SUPPORT,B2/B3 support" "0: B3,1: B2" newline eventfld.long 0x0 15. "PME_STATUS,PME status" "0,1" newline rbitfld.long 0x0 13.--14. "DATA_SCALE,Data scaling factor" "0,1,2,3" newline bitfld.long 0x0 8. "PME_ENABLE,PME# enable" "0: The Function cannot assert PME#.,1: The Function can assert PME#." newline bitfld.long 0x0 3. "NO_SOFT_RST,No Soft Reset" "0: Internal reset,1: No internal reset" newline bitfld.long 0x0 0.--1. "POWER_STATE,Power state" "0: D0,1: D1,2: D2,3: D3hot" group.long 0x50++0x13 line.long 0x0 "MSI_CIDNC,PCI Express MSI Message Capability ID" bitfld.long 0x0 26. "EXT_DATA_EN,Extended Message Data Enable" "0: Not configured,1: Configured" newline rbitfld.long 0x0 25. "EXT_DATA_CAP,Extended Message Data Capable" "0: The Function is incapable of providing..,1: The Function is capable of providing.." newline rbitfld.long 0x0 24. "PVM_SUPPORT,MSI per-vector masking capable" "0: The Function does not support MSI per-vector..,1: The Function supports MSI per-vector masking." newline rbitfld.long 0x0 23. "ADDR_CAP_64,MSI 64-bit address capable" "0: The Function is incapable of sending a 64-bit..,1: The Function is capable of sending a 64-bit.." newline bitfld.long 0x0 20.--22. "MULTI_MSG_EN,MSI multiple message enable" "0: 1 vector allocated.,1: 2 vectors allocated.,2: 4 vectors allocated.,3: 8 vectors allocated.,4: 16 vectors allocated.,5: 32 vectors allocated.,?,?" newline rbitfld.long 0x0 17.--19. "MULTI_MSG_CAP,MSI multiple message capable" "0: 1 vector requested.,1: 2 vectors requested.,2: 4 vectors requested.,3: 8 vectors requested.,4: 16 vectors requested.,5: 32 vectors requested.,?,?" newline bitfld.long 0x0 16. "ENABLE,MSI enable" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "CAP_NEXT_PTR,MSI capability next pointer" newline hexmask.long.byte 0x0 0.--7. 1. "CAP_ID,MSI capability ID" line.long 0x4 "MSI_MLADDR,MSI message lower address" hexmask.long 0x4 2.--31. 1. "MSG_LOWER_ADDR,System-specified message lower address" line.long 0x8 "MSI_MUADDR_DATA,MSI message upper address or data" hexmask.long.word 0x8 16.--31. 1. "EMDATA_UADDRU,Extended MSI data or upper 16 bits of the upper address" newline hexmask.long.word 0x8 0.--15. 1. "DATA_UADDRL,Data or lower 16 bits of the upper address" line.long 0xC "MSI_DATA_MASK,MSI data or mask bits" hexmask.long.word 0xC 16.--31. 1. "DATA_UMB,Data or upper mask bits" newline hexmask.long.word 0xC 0.--15. 1. "DATA_LMB,Data or lower mask bits" line.long 0x10 "MSI_PEND_MASK_BITS,MSI pending or mask bits" hexmask.long 0x10 0.--31. 1. "PEND_MASK_BITS,Pending or mask bits" rgroup.long 0x64++0x3 line.long 0x0 "MSI_PEND_BITS,MSI pending bits" hexmask.long 0x0 0.--31. 1. "PEND_BITS,Pending bits" rgroup.long 0x70++0x7 line.long 0x0 "CINCPCR,Capabilities ID and next pointer" hexmask.long.byte 0x0 25.--29. 1. "INT_MSG_NUM,PCIe Interrupt Message Number" newline bitfld.long 0x0 24. "SLOT_IMP,PCIe Slot Implemented Valid" "0: The link associated with this port is either..,1: The link associated with this port is connected.." newline hexmask.long.byte 0x0 20.--23. 1. "DEV_PORT_TYPE,PCIe device/port type" newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,PCIe capability version number" newline hexmask.long.byte 0x0 8.--15. 1. "CAP_NEXT_PTR,PCIe Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "CAP_ID,PCIe capability ID" line.long 0x4 "DEV_CAPABILITIES,Device capabilities" bitfld.long 0x4 28. "FLR_CAP,Function-level reset (FLR) capability" "0: The Function does not support FLR.,1: The Function supports FLR." newline bitfld.long 0x4 26.--27. "CSPLS,Captured slot power limit scale" "0,1,2,3" newline hexmask.long.byte 0x4 18.--25. 1. "CSPLV,Captured slot power limit value" newline bitfld.long 0x4 15. "ROLE_BASED_ERR_REPORT,Role-based error reporting" "?,1: Role-based error reporting is implemented." newline bitfld.long 0x4 9.--11. "EP_L1_ACCPT_LAT,EP L1 acceptable latency" "0: Maximum of 1 us.,1: Maximum of 2 us.,2: Maximum of 4 us.,3: Maximum of 8 us.,4: Maximum of 16 us.,5: Maximum of 32 us.,6: Maximum of 64 us.,7: No limit." newline bitfld.long 0x4 6.--8. "EP_L0S_ACCPT_LAT,EP L0s acceptable latency" "0: Maximum of 64 ns.,1: Maximum of 128 ns.,2: Maximum of 256 ns.,3: Maximum of 512 ns.,4: Maximum of 1 us.,5: Maximum of 2 us.,6: Maximum of 4 us.,7: No limit." newline bitfld.long 0x4 5. "EXT_TAG_SUP,Extended Tag Field Supported" "0: 5-bit Tag field supported.,1: 8-bit Tag field supported." newline bitfld.long 0x4 3.--4. "PHAN_FUNC_SUP,Phantom Functions Supported" "0,1,2,3" newline bitfld.long 0x4 0.--2. "MAX_PL_SIZE_SUP,Max Payload Size Supported" "0: Max payload size is 128 bytes.,1: Max payload size is 256 bytes.,2: Max payload size is 512 bytes.,3: Max payload size is 1024 bytes.,4: Max payload size is 2048 bytes.,5: Max payload size is 4096 bytes.,?,?" group.long 0x78++0x3 line.long 0x0 "DEV_CONTROL_STATUS,Device control and status" rbitfld.long 0x0 21. "TRANS_PENDING,TP" "0: All outstanding non-posted requests have..,1: The Function has issued non-posted requests that.." newline rbitfld.long 0x0 20. "APD,Aux power detected status" "0,1" newline eventfld.long 0x0 19. "URD,Unsupported request detected status" "0,1" newline eventfld.long 0x0 18. "FED,Fatal error detected status" "0,1" newline eventfld.long 0x0 17. "NFED,Non-fatal error detected status" "0,1" newline eventfld.long 0x0 16. "CED,Correctable error detected status" "0,1" newline bitfld.long 0x0 15. "INITIATE_FLR,Initiate FLR" "0,1" newline bitfld.long 0x0 12.--14. "MAX_READ_REQ_SIZE,Max read request size" "0: Maximum read request size is 128 bytes.,1: Maximum read request size is 256 bytes.,2: Maximum read request size is 512 bytes.,3: Maximum read request size is 1024 bytes.,4: Maximum read request size is 2048 bytes.,5: Maximum read request size is 4096 bytes.,?,?" newline rbitfld.long 0x0 11. "EN_NO_SNOOP,Enable no snoop" "0,1" newline bitfld.long 0x0 10. "APE,Aux power PM enable" "0,1" newline bitfld.long 0x0 9. "PHANTOM_FUNC_EN,Phantom Functions enable" "0: The Function cannot use Phantom functions.,1: The Function is allowed to use Phantom functions." newline bitfld.long 0x0 8. "EXT_TAG_EN,Extended Tag field enable" "0: The Function is restricted to using a 5-bit Tag..,1: The Function is allowed to use an 8-bit Tag field." newline bitfld.long 0x0 5.--7. "MAX_PAYLOAD_SIZE,Max payload size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "EN_REL_ORDER,Enable relaxed ordering" "0,1" newline bitfld.long 0x0 3. "URR,Unsupported request reporting enable" "0,1" newline bitfld.long 0x0 2. "FER,Fatal error reporting" "0,1" newline bitfld.long 0x0 1. "NFER,Non-fatal error reporting enable" "0,1" newline bitfld.long 0x0 0. "CER,Correctable error reporting enable" "0,1" rgroup.long 0x7C++0x3 line.long 0x0 "LINK_CAPABILITIES,Link Capabilities" hexmask.long.byte 0x0 24.--31. 1. "PORT_NUM,Port number" newline bitfld.long 0x0 18. "CLOCK_POWER_MAN,Clock power management" "0,1" newline bitfld.long 0x0 15.--17. "L1_EXIT_LATENCY,L1 exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "L0S_EXIT_LATENCY,L0s exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10.--11. "ASPM_SUPPORT,Active State Power Management (ASPM) support" "0: No ASPM support,1: L0s supported,2: L1 supported,3: L0s and L1 supported" newline hexmask.long.byte 0x0 4.--9. 1. "MAX_LINK_WIDTH,Maximum link width" newline hexmask.long.byte 0x0 0.--3. 1. "MAX_LINK_SPEED,Max link speed" group.long 0x80++0x3 line.long 0x0 "LINK_CONTROL_STATUS,Link Control And Status" rbitfld.long 0x0 29. "DLL_ACTIVE,Data link layer active" "0,1" newline rbitfld.long 0x0 28. "SLOT_CLK_CONFIG,Slot Clock Configuration" "0,1" newline hexmask.long.byte 0x0 20.--25. 1. "NEGO_LINK_WIDTH,Current link speed" newline hexmask.long.byte 0x0 16.--19. 1. "LINK_SPEED,Current link speed" newline bitfld.long 0x0 9. "HW_AUTO_WIDTH_DISABLE,Hardware autonomous width disable" "0,1" newline bitfld.long 0x0 8. "EN_CLK_POWER_MAN,Enable clock power management" "0,1" newline bitfld.long 0x0 7. "EXTENDED_SYNCH,Extended synch" "0,1" newline bitfld.long 0x0 6. "COMMON_CLK_CONFIG,Common clock configuration" "0,1" newline bitfld.long 0x0 3. "RCB,Read Completion Boundary (RCB)" "0: 64 byte,1: 128 byte" newline bitfld.long 0x0 0.--1. "ASPM_CONTROL,Active State Power Management (ASPM) control" "0: Disabled,1: L0s entry enabled,2: L1 entry enabled,3: L0s and L1 entry enabled" rgroup.long 0x94++0x3 line.long 0x0 "DEVICE_CAPABILITIES2_REG,Device capabilities 2" bitfld.long 0x0 18.--19. "PCIE_CAP_OBFF_SUPPORT,(OBFF) Optimized Buffer Flush/fill Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" newline bitfld.long 0x0 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1" newline bitfld.long 0x0 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1" newline bitfld.long 0x0 14.--15. "PCIE_CAP2_LN_SYS_CLS,LN System CLS. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No Relaxed Ordering Enabled PR-PR Passing. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 9. "PCIE_CAP_128_CAS_CPL_SUPP,128 Bit CAS Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64 Bit AtomicOp Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32 Bit AtomicOp Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,Atomic Operation Routing Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x98++0x3 line.long 0x0 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device control 2 and status 2" rbitfld.long 0x0 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable" "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable" "0: Enable completion timeout,1: Disable completion timeout" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value" rgroup.long 0x9C++0x3 line.long 0x0 "LINK_CAPABILITIES_2,Link capabilities 2" bitfld.long 0x0 8. "CROSSLINK_SUPPORTED,Crosslink supported" "0: The meaning depends on the port speed as..,1: The associated port supports crosslinks." newline hexmask.long.byte 0x0 1.--7. 1. "SUPPORT_LINK_SPEED_VECTOR,Support_Link_Speed_Vector" group.long 0xA0++0x3 line.long 0x0 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 And Status 2" rbitfld.long 0x0 31. "DRS_MESSAGE_RECEIVED,DRS Message Received" "0,1" newline rbitfld.long 0x0 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence" "0,1,2,3,4,5,6,7" newline eventfld.long 0x0 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0GT/s" "0,1" newline rbitfld.long 0x0 20. "PCIE_CAP_EQ_CPL_P3,Equalization 8.0GT/s Phase 3 Successful" "0,1" newline rbitfld.long 0x0 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0GT/s Phase 2 Successful" "0,1" newline rbitfld.long 0x0 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0GT/s Phase 1 Successful" "0,1" newline rbitfld.long 0x0 17. "PCIE_CAP_EQ_CPL,Equalization 8.0GT/s Complete" "0,1" newline rbitfld.long 0x0 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s" newline bitfld.long 0x0 11. "PCIE_CAP_COMPLIANCE_SOS,Sets Compliance Skip Ordered Sets transmission." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance" "0,1" newline bitfld.long 0x0 7.--9. "PCIE_CAP_TX_MARGIN,Controls Transmit Margin for Debug or Compliance" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis For 5 GT/s" "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance Mode" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed" group.long 0xB0++0x3 line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control" bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable" "0,1" newline bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size" newline hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID" rgroup.long 0xB4++0x7 line.long 0x0 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset And BIR" hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table Bar Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is.." "0,1,2,3,4,5,6,7" line.long 0x4 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset And BIR" hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline bitfld.long 0x4 0.--2. "PCI_MSIX_PBA,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." "0,1,2,3,4,5,6,7" rgroup.long 0x100++0x3 line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header" hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." group.long 0x104++0x17 line.long 0x0 "UNCORR_ERR_STATUS_OFF,Uncorrectable error status" eventfld.long 0x0 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" newline eventfld.long 0x0 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status" "0,1" newline eventfld.long 0x0 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "UNCORR_ERR_MASK_OFF,Uncorrectable error mask" rbitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note:.." "0,1" newline rbitfld.long 0x4 24. "ATOMIC_EGRESS_BLOCKED_ERR_MASK,AtomicOp Egress Block Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This register field is sticky." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x4 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x8 "UNCORR_ERR_SEV_OFF,Uncorrectable error severity" rbitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" newline rbitfld.long 0x8 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R/W (sticky).." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This register field is sticky." "0,1" newline bitfld.long 0x8 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0xC "CORR_ERR_STATUS_OFF,Correctable error status" eventfld.long 0xC 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory non-fatal error status" "0,1" newline eventfld.long 0xC 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x10 "CORR_ERR_MASK_OFF,Correctable error mask" bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x14 "ADV_ERR_CAP_CTRL_OFF,Advanced error capabilities and control" rbitfld.long 0x14 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long 0x11C++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long 0x138++0x17 line.long 0x0 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1." hexmask.long.byte 0x0 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header." hexmask.long.word 0x10 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.byte 0x10 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.word 0x10 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register.." line.long 0x14 "LINK_CONTROL3_REG,Link control 3" bitfld.long 0x14 1. "EQ_REQ_INT_EN,Link equalization request interrupt enable" "0,1" newline bitfld.long 0x14 0. "PERFORM_EQ,Perform equalization" "0,1" group.long 0x150++0x3 line.long 0x0 "LANE_ERR_STATUS_REG,Lane error status" eventfld.long 0x0 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" rgroup.long 0x154++0xB line.long 0x0 "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control For Lanes 1 And 0" bitfld.long 0x0 28.--30. "USP_RX_PRESET_HINT1,Upstream port 8.0 GT/s receiver preset hint 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "USP_TX_PRESET1,Upstream port 8.0 GT/s transmitter preset 1" newline bitfld.long 0x0 20.--22. "DSP_RX_PRESET_HINT1,Downstream port 8.0 GT/s receiver preset hint 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "DSP_TX_PRESET1,Downstream port 8.0 GT/s transmitter preset 1" newline bitfld.long 0x0 12.--14. "USP_RX_PRESET_HINT0,Upstream port 8.0 GT/s receiver preset hint 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "USP_TX_PRESET0,Upstream port 8.0 GT/s transmitter preset 0" newline bitfld.long 0x0 4.--6. "DSP_RX_PRESET_HINT0,Downstream port 8.0 GT/s receiver preset hint 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "DSP_TX_PRESET0,Downstream port 8.0 GT/s transmitter preset 0" line.long 0x4 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header." hexmask.long.word 0x4 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." line.long 0x8 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header." hexmask.long.word 0x8 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x8 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x8 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x160++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control" hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select" newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "0: no change,1: per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "0: no change,1: per clear,?,?" rgroup.long 0x164++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event counter data" hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long 0x168++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control" hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select" newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select" newline bitfld.long 0x0 0. "TIMER_START,Timer Start" "0: Stop,1: Start/restart" rgroup.long 0x16C++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-Based Analysis Data" hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time-Based Analysis Data" group.long 0x188++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable" bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error)." hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error)" hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error)." bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error)" bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error Injection Count" line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error)." hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error)." bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "0: Generates duplicate TLPs by handling ACK DLLP as..,1: Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0)." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1)." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2)." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3)." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0)." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1)." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2)." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3)." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0)." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1)." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2)." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3)." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0)." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1)." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2)." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3)." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error)." bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "0: TLP Header,1: TLP Prefix 1st 4-DWORDs,2: TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long 0x1F8++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1" bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0: 40ns,1: 160ns,2: 320ns,3: 640ns Note: This register field is sticky" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification." "0: 2,1: 8,2: 16,3: 32 Note: This register field is sticky" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2" bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long 0x208++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status (Layer1 Per-lane)" hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status (Layer1 LTSSM)" hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline eventfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer" line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status (PM)" hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline eventfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long 0x214++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status (Layer2)" bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long 0x218++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon debug status (layer3 FC)" hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit data1" newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit data0" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit select(header data)" "0: Header credit,1: Data credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit select (TLP type)" "0: Posted,1: Non-posted,2: Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit select (credit type)" "0: Rx,1: Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit select (VC)" "0,1,2,3,4,5,6,7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status (Layer3)" eventfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long 0x228++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1" hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0: 500ns,1: 1us,?,?" newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0: 32ms,1: 56ms,?,?" newline bitfld.long 0x0 4. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed -.." "0: 8,1: 16" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2" bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. Note: This register field is sticky." newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3" bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." rgroup.long 0x238++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1" bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "0: Equalization is not attempted,1: Equalization finished successfully,2: Equalization finished unsuccessfully,3: Reserved This bit is automatically cleared when.." newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2" hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3" hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." rgroup.long 0x258++0x7 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended Capability ID. Capability Version. And Next Capability Offset" hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." line.long 0x4 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header." hexmask.long.word 0x4 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long 0x260++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control." bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control" hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "0: counters are frozen The counters are enabled by..,1: counters increment when the controller detects a.." newline eventfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long 0x268++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long 0x26C++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "0: counters are frozen The counters are enabled by..,1: enables the counters to increment on detected.." newline eventfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long 0x270++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long 0x274++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "0: none,1: 1-bit,2: 2-bit,?" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long 0x278++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations" hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations" hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." group.long 0x280++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable" bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode" eventfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long 0x288++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected" hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected" hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." group.long 0x700++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack latency timer and replay timer" hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor-specific DLLP" hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type -.." line.long 0x8 "PORT_FORCE_OFF,Port force link" hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline eventfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control" bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "0: Core enters ASPM L1 only after idle period..,1: Core enters ASPM L1 after a period in which it.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used .." "0: 1 us,1: 2 us,?,?,?,?,?,?" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us Note: This register field is sticky." "0: 1 us,1: 2 us,?,?,?,?,?,?" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS" newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature is turned off. The controller schedules a low-priority ACK DLLP.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control" bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link mode enable" newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline eventfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew" bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "GEN34_ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode in Gen3 or Gen4 rate: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode This register bit only affects Gen3 or Gen4 operating rate. For Gen1 or Gen2 operating rate the.." "0: Nominal Half Full Buffer mode,1: Nominal Empty Buffer Mode This register bit only.." newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer control and max function number" bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling.." "0: Scaling Factor is 1024,1: Scaling Factor is 256,2: Scaling Factor is 64,3: Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack latency timer modifier" newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay timer limit modifier" newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request" line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer and Filter Mask 1" hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1" newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2" hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2" line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control" bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. You.." "0,1" rgroup.long 0x728++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,Debug Field 0" line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,Debug Field 1" line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0 .." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long 0x73C++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline eventfld.long 0x0 15. "RX_SERIALIZATION_Q_READ_ERR,Receive Serialization Read Error. Indicates the serialization queue has attempted to read an incorrectly formatted TLP." "0,1" newline eventfld.long 0x0 14. "RX_SERIALIZATION_Q_WRITE_ERR,Receive Serialization Queue Write Error. Indicates insufficient buffer space available to write to the serialization queue." "0,1" newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline eventfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long 0x740++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: R" group.long 0x748++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "0: Round robin Note: This register field is sticky,1: Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "0: Strict ordering: posted,1: PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register.." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This.." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register.." group.long 0x80C++0x3 line.long 0x0 "GEN2_CTRL_OFF,Link Width And Speed Change Control" bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "0: Use RxElecIdle signal to infer Electrical Idle,1: Use RxValid signal to infer Electrical Idle.." newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This.." "0: -6 dB,1: -3" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing Note: The access attributes of this field are as.." "0: Full Swing,1: Low Swing Note: The access attributes of this.." newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto Flipping Of The Lanes" "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane For Auto Flip" "0: Connect logical Lane0 to physical lane 0 or 1..,1: Connect logical Lane0 to physical lane 1,2: Connect logical Lane0 to physical lane 3,3: Connect logical Lane0 to physical lane 7,4: Connect logical Lane0 to physical lane 15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long 0x810++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY status" hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY status" group.long 0x814++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY control" hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long 0x81C++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable target map control" hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: RSVDP" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: RSVDP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) address" hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,iMRM address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register; and.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,iMRM Upper Address" hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,iMRM upper address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,iMRM Interrupt #0 Enable" hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt #0 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,iMRM Interrupt #0 Mask" hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt #0 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,iMRM Interrupt #0 Status" hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt #0 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,iMRM Interrupt #1 Enable" hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt #1 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,iMRM Interrupt #1 Mask" hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt #1 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,iMRM Interrupt #1 Status" hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt #1 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,iMRM Interrupt #2 Enable" hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt #2 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,iMRM Interrupt #2 Mask" hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt #2 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,iMRM Interrupt #2 Status" hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt #2 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,iMRM Interrupt #3 Enable" hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt #3 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,iMRM Interrupt #3 Mask" hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt #3 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,iMRM Interrupt #3 Status" hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt #3 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,iMRM Interrupt #4 Enable" hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt #4 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,iMRM Interrupt #4 Mask" hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt #4 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,iMRM Interrupt #4 Status" hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt #4 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,iMRM Interrupt #5 Enable" hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt #5 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,iMRM Interrupt #5 Mask" hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt #5 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,iMRM Interrupt #5 Status" hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt #5 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,iMRM Interrupt #6 Enable" hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt #6 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,iMRM Interrupt #6 Mask" hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt #6 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,iMRM Interrupt #6 Status" hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt #6 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,iMRM Interrupt #7 Enable" hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt #7 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,iMRM Interrupt #7 Mask" hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt #7 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,iMRM Interrupt #7 Status" hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt #7 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,iMRM general-purpose IO" hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,RADM clock gating enable control" bitfld.long 0x70 0. "RADM_CLK_GATING_EN,Enable Radm clock gating feature. - 0: Disable - 1: Enable(default)" "0: Disable,1: Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 control" bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable." "0,1" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable" "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable" "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable" "0,1" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,Assert RxEqEval" "0: mac_phy_rxeqeval asserts after 1us and 2 TS1..,1: mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable" "0,1" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable" "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable" "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 And Phase 3 Disable" "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler For Gen3 and Gen4 Data Rate" "0,1" newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant" "0: The receiver complies with the ZRX-DC parameter..,1: The receiver does not comply with the ZRX-DC.." group.long 0x8A8++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control" bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "0: Do not request,1: request Note: Gen3 and Gen4 share the same.." newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM" "0: Do not include,1: Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "0: not support,1: support Note: Gen3 and Gen4 share the same.." newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable" "0: Abort the current evaluation stop any attempt to..,1: ignore the 2ms timeout and continue as normal." newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (When Optimal Settings Are Not Found)" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode" line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control" hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture For C+1" newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture For C-1" newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth" newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase" group.long 0x8B4++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order rule control" hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE loopback control" bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable" bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4)" "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,Suppress" "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status will be generated for.." "0: The controller drops all incoming I/O or MEM..,1: The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write To Read-Only Fields Using DBI" "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,Up-configure multi-lane control" bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY interoperability control" bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1. Note: This register field is sticky." "0: Controller requests aux_clk switch and core_clk..,1: Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access attributes of this field are as.." "0: Core waits for the PHY to acknowledge transition..,1: Core does not wait for PHY to acknowledge.." newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS and.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control" eventfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link reset request flush control" hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response" hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping" "0: OKAY,1: OKAY with all FFFF_FFFF data for all CRS..,2: OKAY with FFFF_0001 data for CRS completions to..,3: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping" "0: OKAY (with FFFF data),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping" "0: OKAY (with FFFF data for non-posted requests),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout" bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control" bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward To The Application" "0: The zero-length read terminates at the PCIe AXI..,1: The zero-length read is forwarded to the.." newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector" "0: B'last event: wait for the all of the write..,1: AW'last event: wait until the complete Posted..,?,?" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable" "0,1" group.long 0x8E0++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "0: lower = Peripheral,1: lower = Memory type" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline bitfld.long 0x8 24.--25. "CFG_MSTR_AWDOMAIN_VALUE,Master Write DOMAIN Signal Value. Value of the individual bits in mstr_awdomain when CFG_MSTR_AWDOMAIN_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awdomain is always '11' Note:.." "0,1,2,3" newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline bitfld.long 0x8 16.--17. "CFG_MSTR_ARDOMAIN_VALUE,Master Read DOMAIN Signal Value. Value of the individual bits in mstr_ardomain when CFG_MSTR_ARDOMAIN_MODE is '1' Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline bitfld.long 0x8 8.--9. "CFG_MSTR_AWDOMAIN_MODE,Master Write DOMAIN Signal Behavior. Defines how the individual bits in mstr_awdomain[1:0] are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWDOMAIN_VALUE field.." "0: set automatically by the AXI master,1: set by the value of the corresponding bit of the..,?,?" newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." newline bitfld.long 0x8 0.--1. "CFG_MSTR_ARDOMAIN_MODE,Master Read DOMAIN Signal Behavior. Defines how the individual bits in mstr_ardomain[1:0] are controlled: - 0: set automatically by the AXI master - 1: set the value of the corresponding bit of the CFG_MSTR_ARDOMAIN_VALUE field.." "0: set automatically by the AXI master,1: set the value of the corresponding bit of the..,?,?" group.long 0x8F0++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long 0x8F8++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long 0x930++0xB line.long 0x0 "INTERFACE_TIMER_CONTROL_OFF,Interface Timer Control" bitfld.long 0x0 4. "FORCE_PENDING,Writing to this bit forces the value of the pending flags. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2.--3. "INTERFACE_TIMER_SCALING,Interface timer scaling. This field can be used to reduce the timer duration for verification purpose. This field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 1. "INTERFACE_TIMER_AER_EN,Interface timer AER generation enable. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "INTERFACE_TIMER_EN,Interface timer enable. Note: This register field is sticky." "0,1" line.long 0x4 "INTERFACE_TIMER_TARGET_OFF,Interface Timer Target" hexmask.long.word 0x4 0.--15. 1. "INTERFACE_TIMER_TARGET,Interface timer target value. This field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register field is sticky." line.long 0x8 "INTERFACE_TIMER_STATUS_OFF,Interface Timer Status Register." eventfld.long 0x8 11. "SLAVE_RD_ADD_TIMEOUT,Slave read address channel timeout." "0,1" newline eventfld.long 0x8 10. "SLAVE_WR_DATA_TIMEOUT,Slave write data channel timeout." "0,1" newline eventfld.long 0x8 9. "SLAVE_WR_ADD_TIMEOUT,Slave write address channel timeout." "0,1" newline eventfld.long 0x8 6. "MASTER_RD_DATA_TIMEOUT,Master read data channel timeout." "0,1" newline eventfld.long 0x8 5. "MASTER_WR_RES_TIMEOUT,Master write response channel timeout." "0,1" newline eventfld.long 0x8 4. "CLIENT2_INTERFACE_TIMEOUT,Client2 interface timeout." "0,1" newline eventfld.long 0x8 3. "CLIENT1_INTERFACE_TIMEOUT,Client1 interface timeout." "0,1" newline eventfld.long 0x8 1. "CPL_INTERFACE_TIMEOUT,CPL interface timeout." "0,1" newline eventfld.long 0x8 0. "MESSAGE_INTERFACE_TIMEOUT,Message interface timeout." "0,1" group.long 0x940++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low" hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High" hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long 0x948++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell" bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long 0x94C++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM Power Mode And Debug Control" hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long 0x960++0x7 line.long 0x0 "SAFETY_MASK_OFF,Masks for functional safety interrupt events." bitfld.long 0x0 5. "SAFETY_INT_MASK_5,Mask for functional safety interrupt event 5 (RASDP correctable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "SAFETY_INT_MASK_4,Mask for functional safety interrupt event 4 (PCIe correctable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "SAFETY_INT_MASK_3,Mask for functional safety interrupt event 3 (PCIe uncorrectable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "SAFETY_INT_MASK_2,Mask for functional safety interrupt event 2 (Interface timers). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "SAFETY_INT_MASK_1,Mask for functional safety interrupt event 1 (CDM register checker). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "SAFETY_INT_MASK_0,Mask for functional safety interrupt event 0 (RASDP). Note: This register field is sticky." "0,1" line.long 0x4 "SAFETY_STATUS_OFF,Status for functional safety interrupt events." eventfld.long 0x4 5. "SAFETY_INT_STATUS_5,Status for functional safety interrupt event 5 (RASDP correctable)." "0,1" newline eventfld.long 0x4 4. "SAFETY_INT_STATUS_4,Status for functional safety interrupt event 4 (PCIe correctable)." "0,1" newline eventfld.long 0x4 3. "SAFETY_INT_STATUS_3,Status for functional safety interrupt event 3 (PCIe uncorrectable)." "0,1" newline eventfld.long 0x4 2. "SAFETY_INT_STATUS_2,Status for functional safety interrupt event 2 (Interface timers)." "0,1" newline eventfld.long 0x4 1. "SAFETY_INT_STATUS_1,Status for functional safety interrupt event 1 (CDM register checker)." "0,1" newline eventfld.long 0x4 0. "SAFETY_INT_STATUS_0,Status for functional safety interrupt event 0 (RASDP)." "0,1" group.long 0xB20++0x7 line.long 0x0 "PL_CHK_REG_CONTROL_STATUS_OFF,CDM Register Checking Control and Status" eventfld.long 0x0 18. "CHK_REG_COMPLETE,The system has completed a checking cycle." "0,1" newline eventfld.long 0x0 17. "CHK_REG_LOGIC_ERROR,The system has detected an error in its own checking logic." "0,1" newline eventfld.long 0x0 16. "CHK_REG_COMPARISON_ERROR,The system has detected that there is a bit error in the CDM Register Data." "0,1" newline bitfld.long 0x0 1. "CHK_REG_CONTINUOUS,Set Continuous Checking Sequence. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "CHK_REG_START,Begins a checking sequence. Note: This register field is sticky." "0,1" line.long 0x4 "PL_CHK_REG_START_END_OFF,CDM Register Checking First and Last address to check." hexmask.long.word 0x4 16.--31. 1. "CHK_REG_END_ADDR,The last address that is checked by the system. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "CHK_REG_START_ADDR,The first address that is checked by the system. Note: This register field is sticky." rgroup.long 0xB28++0x7 line.long 0x0 "PL_CHK_REG_ERR_ADDR_OFF,CDM Register Checking Error Address." hexmask.long 0x0 0.--31. 1. "CHK_REG_ERR_ADDR,The address at which an error has been detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." line.long 0x4 "PL_CHK_REG_ERR_PF_VF_OFF,CDM Register Checking error PF and VF Numbers." hexmask.long.word 0x4 16.--27. 1. "CHK_REG_VF_ERR_NUMBER,The VF number at which the error was detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--4. 1. "CHK_REG_PF_ERR_NUMBER,The PF number at which the error was detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." group.long 0xB40++0x3 line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control" hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x20010)++0x3 line.long 0x0 "BAR_MASK[$1],BARn Mask" hexmask.long 0x0 1.--31. 1. "PCI_TYPE0_BAR0_MASK,BAR0 Mask" newline bitfld.long 0x0 0. "PCI_TYPE0_BAR0_ENABLED,BAR0 Mask Enabled" "0: Disabled,1: Enabled" repeat.end group.long 0x60000++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60020++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60100++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_0,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Start Address High" newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Start Address Low" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60120++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60200++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_1,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60220++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60300++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_1,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_1,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Start Address High" newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Start Address Low" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_1,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60320++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60400++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_2,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60420++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60500++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_2,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_2,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Start Address High" newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Start Address Low" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_2,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60520++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60600++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_3,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60620++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60700++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_3,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_3,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Start Address High" newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Start Address Low" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_3,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60720++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60800++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_4,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_4,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60820++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60A00++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_5,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_5,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,Lower Target Outbound" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60A20++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." tree.end tree "SERDES_PHY" base ad:0x40483000 group.word 0xC++0x1 saveindex 0x8 0xF 0xF line.word 0x0 "SUP_DIG_LVL_OVRD_IN,Override Values For Level Settings" bitfld.word 0x0 9. "TX_VBOOST_LVL_EN,Enable Override Value For tx_vboost_lvl" "0,1" bitfld.word 0x0 6.--8. "TX_VBOOST_LVL,Override Value For tx_vboost_lvl" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5. "RX_VREF_CTRL_EN,Enable Override Value For rx_vref_ctrl" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "RX_VREF_CTRL,Override Value For rx_vref_ctrl" rgroup.word 0xC++0x1 saveindex 0x8 0x19 0x19 line.word 0x0 "SUP_DIG_ASIC_IN,Current values for incoming SUP control signals from ASIC" bitfld.word 0x0 15. "TEST_TX_REF_CLK_EN,Value From ASIC For test_tx_refclk_en" "0,1" bitfld.word 0x0 14. "MPLLB_STATE,Value To ASIC For mpllb_state_i" "0,1" bitfld.word 0x0 13. "MPLLA_STATE,Value To ASIC For mplla_state_i" "0,1" newline bitfld.word 0x0 12. "RES_ACK_OUT,Value To ASIC For res_ack_out_i" "0,1" bitfld.word 0x0 11. "RES_ACK_IN,Value From ASIC For res_req_in" "0,1" bitfld.word 0x0 10. "RES_REQ_OUT,Value To ASIC For res_ack_out_i" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value From ASIC For res_req_in" "0,1" bitfld.word 0x0 8. "RTUNE_ACK,Value To ASIC For rtune_ack_i" "0,1" bitfld.word 0x0 7. "RTUNE_REQ,Value From ASIC For rtune_req" "0,1" newline bitfld.word 0x0 6. "TEST_POWERDOWN,Value From ASIC For test_powerdown" "0,1" bitfld.word 0x0 5. "TEST_BURNIN,Value From ASIC For test_burnin" "0,1" bitfld.word 0x0 4. "REF_USE_PAD,Value From ASIC For ref_use_pad" "0,1" newline bitfld.word 0x0 3. "REF_REPEAT_CLK_EN,Value From ASIC For ref_repeat_clk_en" "0,1" bitfld.word 0x0 2. "REF_CLK_DIV2_EN,Value From ASIC For ref_clk_div2_en" "0,1" bitfld.word 0x0 1. "REF_CLK_EN,Value From ASIC For ref_clk_en" "0,1" newline bitfld.word 0x0 0. "PHY_RESET,Value From ASIC For phy_reset" "0,1" group.word 0xC++0x1 saveindex 0x8 0x61 0x61 line.word 0x0 "SUP_DIG_RTUNE_CONFIG,Configure Rtune Operation" bitfld.word 0x0 3.--5. "SUP_ANA_TERM_CTRL,Set The Reference Resistor In The Analog" "0: 54,1: 52,2: 50 (default),3: 48,4: 46,5: 44,6: 42,7: 40" bitfld.word 0x0 2. "TX_CAL_EN,Enable Calibration Of TX Resistor" "0,1" bitfld.word 0x0 1. "FAST_RTUNE,Enable Fast Resitor Tuning (Simulation Only)" "0,1" newline bitfld.word 0x0 0. "RX_CAL_EN,Enable Calibration Of RX Resistor" "0,1" rgroup.word 0xC++0x1 saveindex 0x8 0x67 0x67 line.word 0x0 "SUP_DIG_RTUNE_TXDN_STAT,TX-DN Resistor Tuning Register Status" hexmask.word 0x0 0.--9. 1. "TXDN_STAT,Current Value Of The TX-DN Resistor Tuning Register" rgroup.word 0xC++0x1 saveindex 0x8 0x68 0x68 line.word 0x0 "SUP_DIG_RTUNE_TXUP_STAT,TX-UP Resistor Tuning Register Status" hexmask.word 0x0 0.--9. 1. "TXUP_STAT,Current Value Of The TX-UP Resistor Tuning Register" group.word 0xC++0x1 saveindex 0x8 0x2001 0x2001 line.word 0x0 "RAWCMN_DIG_MPLLA_OVRD_IN,Override values for incoming MPLLA signals" bitfld.word 0x0 10. "MPLLA_BW_OVRD_EN,Override enable for mplla_bandwidth[15:0]" "0,1" bitfld.word 0x0 9. "MPLLA_DIV8_CLK_EN_OVRD_EN,Override enable for mplla_div8_clk_en" "0,1" bitfld.word 0x0 8. "MPLLA_DIV8_CLK_EN_OVRD_VAL,Override value for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 7. "MPLLA_DIV10_CLK_EN_OVRD_EN,Override enable for mplla_div10_clk_en" "0,1" bitfld.word 0x0 6. "MPLLA_DIV10_CLK_EN_OVRD_VAL,Override value for mplla_div10_clk_en" "0,1" bitfld.word 0x0 5. "MPLLA_TX_CLK_DIV_OVRD_EN,Override enable for mplla_tx_clk_div[2:0]" "0,1" newline bitfld.word 0x0 2.--4. "MPLLA_TX_CLK_DIV_OVRD_VAL,Override value for mplla_tx_clk_div[2:0]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 1. "MPLLA_WORD_DIV2_EN_OVRD_EN,Override enable for mplla_word_div2_en" "0,1" bitfld.word 0x0 0. "MPLLA_WORD_DIV2_EN_OVRD_VAL,Override value for mplla_word_div2_en" "0,1" group.word 0xC++0x1 saveindex 0x8 0x2002 0x2002 line.word 0x0 "RAWCMN_DIG_MPLLA_BW_OVRD_IN,Override values for incoming MPLLA bandwidth" hexmask.word 0x0 0.--15. 1. "MPLLA_BW_OVRD_VAL,Override value for mplla_bandwidth[15:0]" group.word 0xC++0x1 saveindex 0x8 0x2004 0x2004 line.word 0x0 "RAWCMN_DIG_MPLLB_OVRD_IN,Override values for incoming MPLLB signals" bitfld.word 0x0 10. "MPLLB_BW_OVRD_EN,Override enable for mpllb_bandwidth[15:0]" "0,1" bitfld.word 0x0 9. "MPLLB_DIV8_CLK_EN_OVRD_EN,Override enable for mpllb_div8_clk_en" "0,1" bitfld.word 0x0 8. "MPLLB_DIV8_CLK_EN_OVRD_VAL,Override value for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 7. "MPLLB_DIV10_CLK_EN_OVRD_EN,Override enable for mpllb_div10_clk_en" "0,1" bitfld.word 0x0 6. "MPLLB_DIV10_CLK_EN_OVRD_VAL,Override value for mpllb_div10_clk_en" "0,1" bitfld.word 0x0 5. "MPLLB_TX_CLK_DIV_OVRD_EN,Override enable for mpllb_tx_clk_div[2:0]" "0,1" newline bitfld.word 0x0 2.--4. "MPLLB_TX_CLK_DIV_OVRD_VAL,Override value for mpllb_tx_clk_div[2:0]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 1. "MPLLB_WORD_DIV2_EN_OVRD_EN,Override enable for mpllb_word_div2_en" "0,1" bitfld.word 0x0 0. "MPLLB_WORD_DIV2_EN_OVRD_VAL,Override value for mpllb_word_div2_en" "0,1" group.word 0xC++0x1 saveindex 0x8 0x2005 0x2005 line.word 0x0 "RAWCMN_DIG_MPLLB_BW_OVRD_IN,Override values for incoming MPLLB bandwidth" hexmask.word 0x0 0.--15. 1. "MPLLB_BW_OVRD_VAL,Override value for mpllb_bandwidth[15:0]" group.word 0xC++0x1 saveindex 0x8 0x200A 0x200A line.word 0x0 "RAWCMN_DIG_CMN_CTL_1,Common Control 1" bitfld.word 0x0 5. "RTUNE_REQ_OVRD_EN,Override enable for rtune_req" "0,1" bitfld.word 0x0 4. "RTUNE_REQ_OVRD_VAL,Override value for rtune_req" "0,1" bitfld.word 0x0 3. "MPLLB_INIT_CAL_DISABLE_OVRD_EN,Override enable for mpllb_init_cal_disable" "0,1" newline bitfld.word 0x0 2. "MPLLB_INIT_CAL_DISABLE_OVRD_VAL,Override value for mpllb_init_cal_disable" "0,1" bitfld.word 0x0 1. "MPLLA_INIT_CAL_DISABLE_OVRD_EN,Override enable for mplla_init_cal_disable" "0,1" bitfld.word 0x0 0. "MPLLA_INIT_CAL_DISABLE_OVRD_VAL,Override value for mplla_init_cal_disable" "0,1" group.word 0xC++0x1 saveindex 0x8 0x3019 0x3019 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN,Override incoming values for rx_eq_delta_iq" bitfld.word 0x0 4. "RX_EQ_DELTA_IQ_OVRD_EN,Enable override value for rx_eq_delta_iq" "0,1" hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_DELTA_IQ_OVRD_VAL,Override value for rx_eq_delta_iq" group.word 0xC++0x1 saveindex 0x8 0x3119 0x3119 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN,Override Incoming Values For rx_eq_delta_iq" bitfld.word 0x0 4. "RX_EQ_DELTA_IQ_OVRD_EN,Enable override value for rx_eq_delta_iq" "0,1" hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_DELTA_IQ_OVRD_VAL,Override value for rx_eq_delta_iq" tree.end tree "SERDES_PHY_PCIE_1" base ad:0x44183000 group.word 0xC++0x1 saveindex 0x8 0xF 0xF line.word 0x0 "SUP_DIG_LVL_OVRD_IN,Override Values For Level Settings" bitfld.word 0x0 9. "TX_VBOOST_LVL_EN,Enable Override Value For tx_vboost_lvl" "0,1" bitfld.word 0x0 6.--8. "TX_VBOOST_LVL,Override Value For tx_vboost_lvl" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5. "RX_VREF_CTRL_EN,Enable Override Value For rx_vref_ctrl" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "RX_VREF_CTRL,Override Value For rx_vref_ctrl" rgroup.word 0xC++0x1 saveindex 0x8 0x19 0x19 line.word 0x0 "SUP_DIG_ASIC_IN,Current values for incoming SUP control signals from ASIC" bitfld.word 0x0 15. "TEST_TX_REF_CLK_EN,Value From ASIC For test_tx_refclk_en" "0,1" bitfld.word 0x0 14. "MPLLB_STATE,Value To ASIC For mpllb_state_i" "0,1" bitfld.word 0x0 13. "MPLLA_STATE,Value To ASIC For mplla_state_i" "0,1" newline bitfld.word 0x0 12. "RES_ACK_OUT,Value To ASIC For res_ack_out_i" "0,1" bitfld.word 0x0 11. "RES_ACK_IN,Value From ASIC For res_req_in" "0,1" bitfld.word 0x0 10. "RES_REQ_OUT,Value To ASIC For res_ack_out_i" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value From ASIC For res_req_in" "0,1" bitfld.word 0x0 8. "RTUNE_ACK,Value To ASIC For rtune_ack_i" "0,1" bitfld.word 0x0 7. "RTUNE_REQ,Value From ASIC For rtune_req" "0,1" newline bitfld.word 0x0 6. "TEST_POWERDOWN,Value From ASIC For test_powerdown" "0,1" bitfld.word 0x0 5. "TEST_BURNIN,Value From ASIC For test_burnin" "0,1" bitfld.word 0x0 4. "REF_USE_PAD,Value From ASIC For ref_use_pad" "0,1" newline bitfld.word 0x0 3. "REF_REPEAT_CLK_EN,Value From ASIC For ref_repeat_clk_en" "0,1" bitfld.word 0x0 2. "REF_CLK_DIV2_EN,Value From ASIC For ref_clk_div2_en" "0,1" bitfld.word 0x0 1. "REF_CLK_EN,Value From ASIC For ref_clk_en" "0,1" newline bitfld.word 0x0 0. "PHY_RESET,Value From ASIC For phy_reset" "0,1" group.word 0xC++0x1 saveindex 0x8 0x61 0x61 line.word 0x0 "SUP_DIG_RTUNE_CONFIG,Configure Rtune Operation" bitfld.word 0x0 3.--5. "SUP_ANA_TERM_CTRL,Set The Reference Resistor In The Analog" "0: 54,1: 52,2: 50 (default),3: 48,4: 46,5: 44,6: 42,7: 40" bitfld.word 0x0 2. "TX_CAL_EN,Enable Calibration Of TX Resistor" "0,1" bitfld.word 0x0 1. "FAST_RTUNE,Enable Fast Resitor Tuning (Simulation Only)" "0,1" newline bitfld.word 0x0 0. "RX_CAL_EN,Enable Calibration Of RX Resistor" "0,1" rgroup.word 0xC++0x1 saveindex 0x8 0x67 0x67 line.word 0x0 "SUP_DIG_RTUNE_TXDN_STAT,TX-DN Resistor Tuning Register Status" hexmask.word 0x0 0.--9. 1. "TXDN_STAT,Current Value Of The TX-DN Resistor Tuning Register" rgroup.word 0xC++0x1 saveindex 0x8 0x68 0x68 line.word 0x0 "SUP_DIG_RTUNE_TXUP_STAT,TX-UP Resistor Tuning Register Status" hexmask.word 0x0 0.--9. 1. "TXUP_STAT,Current Value Of The TX-UP Resistor Tuning Register" group.word 0xC++0x1 saveindex 0x8 0x2001 0x2001 line.word 0x0 "RAWCMN_DIG_MPLLA_OVRD_IN,Override values for incoming MPLLA signals" bitfld.word 0x0 10. "MPLLA_BW_OVRD_EN,Override enable for mplla_bandwidth[15:0]" "0,1" bitfld.word 0x0 9. "MPLLA_DIV8_CLK_EN_OVRD_EN,Override enable for mplla_div8_clk_en" "0,1" bitfld.word 0x0 8. "MPLLA_DIV8_CLK_EN_OVRD_VAL,Override value for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 7. "MPLLA_DIV10_CLK_EN_OVRD_EN,Override enable for mplla_div10_clk_en" "0,1" bitfld.word 0x0 6. "MPLLA_DIV10_CLK_EN_OVRD_VAL,Override value for mplla_div10_clk_en" "0,1" bitfld.word 0x0 5. "MPLLA_TX_CLK_DIV_OVRD_EN,Override enable for mplla_tx_clk_div[2:0]" "0,1" newline bitfld.word 0x0 2.--4. "MPLLA_TX_CLK_DIV_OVRD_VAL,Override value for mplla_tx_clk_div[2:0]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 1. "MPLLA_WORD_DIV2_EN_OVRD_EN,Override enable for mplla_word_div2_en" "0,1" bitfld.word 0x0 0. "MPLLA_WORD_DIV2_EN_OVRD_VAL,Override value for mplla_word_div2_en" "0,1" group.word 0xC++0x1 saveindex 0x8 0x2002 0x2002 line.word 0x0 "RAWCMN_DIG_MPLLA_BW_OVRD_IN,Override values for incoming MPLLA bandwidth" hexmask.word 0x0 0.--15. 1. "MPLLA_BW_OVRD_VAL,Override value for mplla_bandwidth[15:0]" group.word 0xC++0x1 saveindex 0x8 0x2004 0x2004 line.word 0x0 "RAWCMN_DIG_MPLLB_OVRD_IN,Override values for incoming MPLLB signals" bitfld.word 0x0 10. "MPLLB_BW_OVRD_EN,Override enable for mpllb_bandwidth[15:0]" "0,1" bitfld.word 0x0 9. "MPLLB_DIV8_CLK_EN_OVRD_EN,Override enable for mpllb_div8_clk_en" "0,1" bitfld.word 0x0 8. "MPLLB_DIV8_CLK_EN_OVRD_VAL,Override value for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 7. "MPLLB_DIV10_CLK_EN_OVRD_EN,Override enable for mpllb_div10_clk_en" "0,1" bitfld.word 0x0 6. "MPLLB_DIV10_CLK_EN_OVRD_VAL,Override value for mpllb_div10_clk_en" "0,1" bitfld.word 0x0 5. "MPLLB_TX_CLK_DIV_OVRD_EN,Override enable for mpllb_tx_clk_div[2:0]" "0,1" newline bitfld.word 0x0 2.--4. "MPLLB_TX_CLK_DIV_OVRD_VAL,Override value for mpllb_tx_clk_div[2:0]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 1. "MPLLB_WORD_DIV2_EN_OVRD_EN,Override enable for mpllb_word_div2_en" "0,1" bitfld.word 0x0 0. "MPLLB_WORD_DIV2_EN_OVRD_VAL,Override value for mpllb_word_div2_en" "0,1" group.word 0xC++0x1 saveindex 0x8 0x2005 0x2005 line.word 0x0 "RAWCMN_DIG_MPLLB_BW_OVRD_IN,Override values for incoming MPLLB bandwidth" hexmask.word 0x0 0.--15. 1. "MPLLB_BW_OVRD_VAL,Override value for mpllb_bandwidth[15:0]" group.word 0xC++0x1 saveindex 0x8 0x200A 0x200A line.word 0x0 "RAWCMN_DIG_CMN_CTL_1,Common Control 1" bitfld.word 0x0 5. "RTUNE_REQ_OVRD_EN,Override enable for rtune_req" "0,1" bitfld.word 0x0 4. "RTUNE_REQ_OVRD_VAL,Override value for rtune_req" "0,1" bitfld.word 0x0 3. "MPLLB_INIT_CAL_DISABLE_OVRD_EN,Override enable for mpllb_init_cal_disable" "0,1" newline bitfld.word 0x0 2. "MPLLB_INIT_CAL_DISABLE_OVRD_VAL,Override value for mpllb_init_cal_disable" "0,1" bitfld.word 0x0 1. "MPLLA_INIT_CAL_DISABLE_OVRD_EN,Override enable for mplla_init_cal_disable" "0,1" bitfld.word 0x0 0. "MPLLA_INIT_CAL_DISABLE_OVRD_VAL,Override value for mplla_init_cal_disable" "0,1" group.word 0xC++0x1 saveindex 0x8 0x3019 0x3019 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN,Override incoming values for rx_eq_delta_iq" bitfld.word 0x0 4. "RX_EQ_DELTA_IQ_OVRD_EN,Enable override value for rx_eq_delta_iq" "0,1" hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_DELTA_IQ_OVRD_VAL,Override value for rx_eq_delta_iq" group.word 0xC++0x1 saveindex 0x8 0x3119 0x3119 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN,Override Incoming Values For rx_eq_delta_iq" bitfld.word 0x0 4. "RX_EQ_DELTA_IQ_OVRD_EN,Enable override value for rx_eq_delta_iq" "0,1" hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_DELTA_IQ_OVRD_VAL,Override value for rx_eq_delta_iq" tree.end tree "SERDES_RC_PCIE_1" base ad:0x44100000 rgroup.long 0x0++0x3 line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID And Vendor ID" hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID" newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID" group.long 0x4++0x3 line.long 0x0 "TYPE1_STATUS_COMMAND_REG,Status and Command" eventfld.long 0x0 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline eventfld.long 0x0 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline eventfld.long 0x0 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline eventfld.long 0x0 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline eventfld.long 0x0 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x0 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline eventfld.long 0x0 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x0 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x0 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x0 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x0 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x0 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline bitfld.long 0x0 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x0 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x0 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Specification." "0,1" newline rbitfld.long 0x0 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x0 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x0 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x0 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x0 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x0 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code And Revision ID" hexmask.long.byte 0x0 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x0 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x0 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x0 0.--7. 1. "REVISION_ID,Revision ID" group.long 0xC++0x3 line.long 0x0 "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size" hexmask.long.byte 0x0 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0x0 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0x0 16.--22. 1. "HEADER_TYPE,Header Layout" newline hexmask.long.byte 0x0 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0x0 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." group.long 0x18++0xF line.long 0x0 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number" hexmask.long.byte 0x0 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x0 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x0 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x0 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x4 "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. I/O Limit. And Base" eventfld.long 0x4 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline eventfld.long 0x4 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline eventfld.long 0x4 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline eventfld.long 0x4 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline eventfld.long 0x4 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline eventfld.long 0x4 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline hexmask.long.byte 0x4 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x4 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x4 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 8. "IO_DECODE_BIT8,I/O Addressing Encode (I/O Limit Address)" "0: The bridge supports only 16-bit I/O addressing..,1: The bridge supports 32-bit I/O address decoding." newline hexmask.long.byte 0x4 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x4 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 0. "IO_DECODE,I/O addressing encode (I/O base address)" "0: The bridge supports only 16-bit I/O addressing..,1: The bridge supports 32-bit I/O address decoding.." line.long 0x8 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base" hexmask.long.word 0x8 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x8 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x8 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x8 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0xC "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit And Base" hexmask.long.word 0xC 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0xC 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. The value of PREF_MEM_LIMIT_DECODE indicates the following: - 0b: Indicates that the bridge supports only 32 bit addresses - 1b:.." "0,1" newline hexmask.long.word 0xC 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0xC 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode" "0: The bridge supports only 32-bit addresses.,1: The bridge supports 64 bit addresses;.." rgroup.long 0x28++0xF line.long 0x0 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits" hexmask.long 0x0 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit" line.long 0x4 "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits" hexmask.long 0x4 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit" line.long 0x8 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit And Base Upper 16 Bits" hexmask.long.word 0x8 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x8 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." line.long 0xC "TYPE1_CAP_PTR_REG,Capabilities Pointer" hexmask.long.byte 0xC 0.--7. 1. "CAP_POINTER,Capabilities Pointer" group.long 0x38++0x7 line.long 0x0 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address" hexmask.long.tbyte 0x0 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline bitfld.long 0x0 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x4 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. And Interrupt Line" hexmask.long.word 0x4 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x4 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x4 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x4 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x4 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely .." "0,1" newline bitfld.long 0x4 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "0,1" newline bitfld.long 0x4 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x4 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "INT_PIN,Interrupt PIN" newline hexmask.long.byte 0x4 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." rgroup.long 0x40++0x3 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities" hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,Power Management Event Support" newline bitfld.long 0x0 26. "D2_SUPPORT,D2 State Support" "0,1" newline bitfld.long 0x0 25. "D1_SUPPORT,D1 State Support" "0,1" newline bitfld.long 0x0 22.--24. "AUX_CURR,Auxiliary Current Requirements" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization" "0,1" newline bitfld.long 0x0 19. "PME_CLK,PCI Clock Requirement" "0,1" newline bitfld.long 0x0 16.--18. "PM_SPEC_VER,Power Management Spec Version" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Power Management Capability ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x44++0x3 line.long 0x0 "CON_STATUS_REG,Power Management Control And Status" hexmask.long.byte 0x0 24.--31. 1. "DATA_REG_ADD_INFO,Power data information" newline rbitfld.long 0x0 23. "BUS_PWR_CLK_CON_EN,Bus power/clock control enable" "0,1" newline rbitfld.long 0x0 22. "B2_B3_SUPPORT,B2B3 support for D3hot" "0,1" newline eventfld.long 0x0 15. "PME_STATUS,PME status" "0,1" newline rbitfld.long 0x0 13.--14. "DATA_SCALE,Data scaling factor" "0,1,2,3" newline hexmask.long.byte 0x0 9.--12. 1. "DATA_SELECT,Data select" newline bitfld.long 0x0 8. "PME_ENABLE,PME enable" "0,1" newline rbitfld.long 0x0 3. "NO_SOFT_RST,No Soft Reset" "0,1" newline bitfld.long 0x0 0.--1. "POWER_STATE,Power State" "0,1,2,3" group.long 0x50++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability ID. Next Pointer. Capability And Control" rbitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended message data enable" "0,1" newline rbitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable" "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,MSI Per Vector Masking Capable" "0,1" newline rbitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,MSI 64-bit Address Capable" "0,1" newline bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,MSI Multiple Message Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,MSI Multiple Message Capable" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,MSI Capability Next Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,MSI Capability ID. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x4 "MSI_CAP_OFF_04H_REG,MSI message lower address" hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,MSI Message Lower Address Field. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x8 "MSI_CAP_OFF_08H_REG,Data or upper address" hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a 32 bit MSI Message this field contains Ext MSI Data. For 64-bit it contains upper 16 bits of the Upper Address. For a description of this standard PCIe register field see the PCI Express Specification Note: The access.." newline hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a 32-bit MSI Message this field contains Data. For 64-bit it contains lower 16 bits of the Upper Address. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of.." line.long 0xC "MSI_CAP_OFF_0CH_REG,Data or mask bits" hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a 64-bit MSI Message this field contains Data. For 32-bit it contains the upper Mask Bits if PVM is enabled. For a description of this standard PCIe register field see the PCI Express Specification Note: The access attributes.." newline hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a 64-bit MSI Message this field contains Data. For 32-bit it contains the lower Mask Bits if PVM is enabled. For a description of this standard PCIe register field see the PCI Express Specification Note: The access attributes.." line.long 0x10 "MSI_CAP_OFF_10H_REG,Pending or Mask Bits" hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when Vector Masking Capable. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this.." rgroup.long 0x64++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits" hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Used for MSI 64-bit messaging when Vector Masking Capable. Contains Pending Bits. For a description of this standard PCIe register field see the PCI Express Specification." rgroup.long 0x70++0x7 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer" bitfld.long 0x0 30. "RSVD,Reserved. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIe Interrupt Message Number" newline bitfld.long 0x0 24. "PCIE_SLOT_IMP,PCIe Slot Implemented Valid" "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,PCIe device/port type" newline hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,PCIE Capability Version Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,PCIE Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,PCIE Capability ID. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities" bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-based Error Reporting Implemented. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field.." "0,1,2,3" newline bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max Payload Size Supported. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is.." "0,1,2,3,4,5,6,7" group.long 0x78++0x3 line.long 0x0 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Status" rbitfld.long 0x0 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 20. "PCIE_CAP_AUX_POWER_DETECTED,Aux Power Detected Status. For a description of this standard PCIe register field see the PCI Express Specification. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" newline eventfld.long 0x0 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (for endpoints). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max Read Request Size. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux power PM enable" "0,1" newline rbitfld.long 0x0 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom functions enable" "0,1" newline rbitfld.long 0x0 8. "PCIE_CAP_EXT_TAG_EN,Extended tag field enable" "0,1" newline bitfld.long 0x0 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long 0x7C++0x3 line.long 0x0 "LINK_CAPABILITIES_REG,Link Capabilities" hexmask.long.byte 0x0 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." "0,1" newline bitfld.long 0x0 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x0 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock power management" "0,1" newline bitfld.long 0x0 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,LOs exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Level of ASPM (Active State Power Management) Support. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No.." "0,1,2,3" newline hexmask.long.byte 0x0 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum link width" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Maximum link speed" group.long 0x80++0x3 line.long 0x0 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Status" eventfld.long 0x0 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. For a description of this standard PCIe register field see the PCI Express Specification. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG." "0,1" newline eventfld.long 0x0 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. For a description of this standard PCIe register field see the PCI Express Specification. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG." "0,1" newline rbitfld.long 0x0 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Active. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration" "0,1" newline rbitfld.long 0x0 27. "PCIE_CAP_LINK_TRAINING,LTSSM is in Configuration or Recovery State. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. For a description of this standard PCIe register field see the PCI Express Specification." newline rbitfld.long 0x0 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS signaling control" "0,1,2,3" newline rbitfld.long 0x0 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link autonomous bandwidth management interrupt enable" "0,1" newline rbitfld.long 0x0 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link bandwidth management interrupt enable" "0,1" newline bitfld.long 0x0 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline rbitfld.long 0x0 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. For a description of this standard PCIe register field see the PCI Express Specification. The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The.." "0,1" newline bitfld.long 0x0 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 5. "PCIE_CAP_RETRAIN_LINK,Initiate link retrain" "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_LINK_DISABLE,Initiate link disable" "0,1" newline rbitfld.long 0x0 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB)" "0,1" newline bitfld.long 0x0 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. Software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s; otherwise the result is undefined. For a.." "0,1,2,3" rgroup.long 0x84++0x3 line.long 0x0 "SLOT_CAPABILITIES_REG,Slot Capabilities" hexmask.long.word 0x0 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1,2,3" newline hexmask.long.byte 0x0 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot Plug Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot Plug Surprise possible. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 2. "PCIE_CAP_MRL_SENSOR,MRL Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" group.long 0x88++0xB line.long 0x0 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status" eventfld.long 0x0 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline rbitfld.long 0x0 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 20. "PCIE_CAP_CMD_CPLD,Command Completed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" newline bitfld.long 0x0 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" newline bitfld.long 0x0 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot Plug Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Write value is gated with PCIE_CAP_NO_CMD_CPL_SUPPORT field in SLOT_CAPABILITIES_REG. Note: The access.." "0,1" newline bitfld.long 0x0 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities" rbitfld.long 0x4 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable" "0,1" newline rbitfld.long 0x4 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,Configuration request retry status (CRS) software visibility enable" "0,1" newline bitfld.long 0x4 3. "PCIE_CAP_PME_INT_EN,PME interrupt enable" "0,1" newline bitfld.long 0x4 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System error on fatal error enable" "0,1" newline bitfld.long 0x4 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System error on non-fatal error enable" "0,1" newline bitfld.long 0x4 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System error on correctable error enable" "0,1" line.long 0x8 "ROOT_STATUS_REG,Root Status" rbitfld.long 0x8 17. "PCIE_CAP_PME_PENDING,PME Pending. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x8 16. "PCIE_CAP_PME_STATUS,PME Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.word 0x8 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. For a description of this standard PCIe register field see the PCI Express Specification." rgroup.long 0x94++0x3 line.long 0x0 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2" bitfld.long 0x0 18.--19. "PCIE_CAP_OBFF_SUPPORT,(OBFF) Optimized Buffer Flush/fill Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" newline bitfld.long 0x0 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1" newline bitfld.long 0x0 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1" newline bitfld.long 0x0 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No Relaxed Ordering Enabled PR-PR Passing. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 9. "PCIE_CAP_128_CAS_CPL_SUPP,128 Bit CAS Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64 Bit AtomicOp Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32 Bit AtomicOp Completer Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,Atomic Operation Routing Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x98++0x3 line.long 0x0 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2" rbitfld.long 0x0 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable" "0: Enable completion timeout,1: Disable completion timeout" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." rgroup.long 0x9C++0x3 line.long 0x0 "LINK_CAPABILITIES2_REG,Link Capabilities 2" bitfld.long 0x0 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Cross Link Supported. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. For a description of this standard PCIe register field see the PCI Express Specification. This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED.." group.long 0xA0++0x3 line.long 0x0 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2" rbitfld.long 0x0 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline rbitfld.long 0x0 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. For a description of this standard PCIe register field see the PCI Express Base Specification 4.0." "0,1,2,3,4,5,6,7" newline eventfld.long 0x0 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0GT/s. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x0 20. "PCIE_CAP_EQ_CPL_P3,Equalization 8.0GT/s Phase 3 Successful. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0GT/s Phase 2 Successful. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0GT/s Phase 1 Successful. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PCIE_CAP_EQ_CPL,Equalization 8.0GT/s Complete. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. For a description of this standard PCIe register field see the PCI Express Specification. In C-PCIe mode its contents are derived by sampling the PIPE" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 11. "PCIE_CAP_COMPLIANCE_SOS,Sets Compliance Skip Ordered Sets transmission. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x0 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." "0,1" newline bitfld.long 0x0 7.--9. "PCIE_CAP_TX_MARGIN,Controls Transmit Margin for Debug or Compliance. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 6. "PCIE_CAP_SEL_DEEMPHASIS,Controls Selectable De-emphasis for 5 GT/s" "0,1" newline bitfld.long 0x0 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." "0,1" newline bitfld.long 0x0 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance Mode. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long 0xB0++0x3 line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control" bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size" newline hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer" newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Specification." rgroup.long 0xB4++0x7 line.long 0x0 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR" hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table Bar Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is.." "0,1,2,3,4,5,6,7" line.long 0x4 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR" hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline bitfld.long 0x4 0.--2. "PCI_MSIX_PBA,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." "0,1,2,3,4,5,6,7" rgroup.long 0x100++0x3 line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header" hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." group.long 0x104++0x17 line.long 0x0 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status" eventfld.long 0x0 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" newline eventfld.long 0x0 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" newline eventfld.long 0x0 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x0 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask" rbitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. Note:.." "0,1" newline rbitfld.long 0x4 24. "ATOMIC_EGRESS_BLOCKED_ERR_MASK,AtomicOp Egress Block Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x4 5. "SURPRISE_DOWN_ERR_MASK,Surprise down error mask" "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x8 "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity" rbitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" newline rbitfld.long 0x8 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note:.." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise down error severity (optional)" "0,1" newline bitfld.long 0x8 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0xC "CORR_ERR_STATUS_OFF,Correctable Error Status" eventfld.long 0xC 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0xC 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x10 "CORR_ERR_MASK_OFF,Correctable Error Mask" bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x14 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control" rbitfld.long 0x14 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x14 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long 0x11C++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0" hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1" hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2" hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3" hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long 0x12C++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command" bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status" hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number" newline eventfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline eventfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long 0x134++0x17 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification" hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1" hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2" hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3" hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4" hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x14 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header" hexmask.long.word 0x14 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.byte 0x14 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.word 0x14 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." group.long 0x14C++0x7 line.long 0x0 "LINK_CONTROL3_REG,Link control 3" bitfld.long 0x0 1. "EQ_REQ_INT_EN,Link equalization request interrupt enable" "0,1" newline bitfld.long 0x0 0. "PERFORM_EQ,Perform equalization" "0,1" line.long 0x4 "LANE_ERR_STATUS_REG,Lane Error Status" eventfld.long 0x4 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" rgroup.long 0x154++0xB line.long 0x0 "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register For Lanes 1 And 0" bitfld.long 0x0 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." newline bitfld.long 0x0 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." newline bitfld.long 0x0 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." newline bitfld.long 0x0 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header" hexmask.long.word 0x4 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." line.long 0x8 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header" hexmask.long.word 0x8 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x8 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x8 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long 0x160++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control" hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select" newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "0: no change,1: per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "0: no change,1: per clear,?,?" rgroup.long 0x164++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data" hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long 0x168++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control" hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select" newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select" newline bitfld.long 0x0 0. "TIMER_START,Timer Start" "0: Stop,1: Start/restart" rgroup.long 0x16C++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-Based Analysis Data" hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time-Based Analysis Data" group.long 0x188++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable" bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error)" hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error)" hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error)" bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error)" bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error Injection Count" line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error)" hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error)" bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "0: Generates duplicate TLPs by handling ACK DLLP as..,1: Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0)" hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1)" hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2)" hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3)" hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0)" hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1)" hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2)" hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3)" hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0)" hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1)" hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2)" hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3)" hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0)" hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1)" hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2)" hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3)" hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error)" bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "0: TLP Header,1: TLP Prefix 1st 4-DWORDs,2: TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long 0x1F8++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1" bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0: 40ns,1: 160ns,2: 320ns,3: 640ns Note: This register field is sticky" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification." "0: 2,1: 8,2: 16,3: 32 Note: This register field is sticky" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2" bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long 0x208++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status (Layer1 Per-lane)" hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status (Layer1 LTSSM)" hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline eventfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer" line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status (PM)" hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline eventfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long 0x214++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status (Layer2)" bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long 0x218++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status (Layer3 FC)" hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "0: Header Credit,1: Data Credit Note: This register field is sticky" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "0: Posted,1: Non-Posted,2: Completion Note: This register field is sticky,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "0: Rx,1: Tx Note: This register field is sticky" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "0: VC0,1: VC1,2: VC2,?,?,?,?,7: VC7 Note: This register field is sticky" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status (Layer3)" eventfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long 0x228++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1" hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0: 500ns,1: 1us,?,?" newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0: 32ms,1: 56ms,?,?" newline bitfld.long 0x0 4. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed -.." "0: 8,1: 16" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2" bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. Note: This register field is sticky." newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3" bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from link partner. Note: This register field is sticky." rgroup.long 0x238++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1" bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event" "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation" "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation" "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info" "0,1,2,3" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence" "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2" hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3" hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." rgroup.long 0x258++0x7 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended Capability ID. Capability Version And Next Capability Offset" hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." line.long 0x4 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header" hexmask.long.word 0x4 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long 0x260++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control" bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control" hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "0: counters are frozen The counters are enabled by..,1: counters increment when the controller detects a.." newline eventfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long 0x268++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data" hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long 0x26C++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control" hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "0: counters are frozen The counters are enabled by..,1: enables the counters to increment on detected.." newline eventfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long 0x270++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data" hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long 0x274++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control" hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "0: none,1: 1-bit,2: 2-bit,?" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long 0x278++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations" hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations" hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." group.long 0x280++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable" bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode" eventfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long 0x288++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected" hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected" hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." group.long 0x700++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer" hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP" hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link" bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew for SRIS instead of using received SKP OS if DO_DESKEW_FOR_SRIS is set to 1. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline eventfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control" bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "0: Core enters ASPM L1 only after idle period..,1: Core enters ASPM L1 after a period in which it.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used .." "0: 1 us,1: 2 us,?,?,?,?,?,?" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us Note: This register field is sticky." "0: 1 us,1: 2 us,?,?,?,?,?,?" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS" newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature is turned off. The controller schedules a low-priority ACK DLLP.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control" bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable" newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline eventfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew" bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "GEN34_ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode in Gen3 or Gen4 rate: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode This register bit only affects Gen3 or Gen4 operating rate. For Gen1 or Gen2 operating rate the.." "0: Nominal Half Full Buffer mode,1: Nominal Empty Buffer Mode This register bit only.." newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number" bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling.." "0: Scaling Factor is 1024,1: Scaling Factor is 256,2: Scaling Factor is 64,3: Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay timer limit modifier" newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer and Filter Mask 1" hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1" newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2" hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2" line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control" bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests" "0,1" rgroup.long 0x728++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The bits in this field have the following meaning: Bits 31:26: Reserved Bit 25: Receiver is receiving logical idle Bit 24: 2n symbol is also idle (16bit PHY interface only) Bits 23:8: PIPE transmit data Bits 7:6: PIPE transmit K indication Bits.." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The bits in this field have the following meaning: Bit 31: Scrambling disabled for the link Bit 30: TSSM in DISABLE state; link inoperable Bit 29: LTSSM performing link training Bit 28: LTSSM is in Polling" line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0 .." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long 0x73C++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline eventfld.long 0x0 15. "RX_SERIALIZATION_Q_READ_ERR,Receive Serialization Read Error. Indicates the serialization queue has attempted to read an incorrectly formatted TLP." "0,1" newline eventfld.long 0x0 14. "RX_SERIALIZATION_Q_WRITE_ERR,Receive Serialization Queue Write Error. Indicates insufficient buffer space available to write to the serialization queue." "0,1" newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline eventfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long 0x740++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access." group.long 0x748++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control" bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "0: Round robin Note: This register field is sticky,1: Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "0: Strict ordering: posted,1: PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is sticky." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control" hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control" hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." group.long 0x80C++0x3 line.long 0x0 "GEN2_CTRL_OFF,Link Width And Speed Change Control" bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "0: Use RxElecIdle signal to infer Electrical Idle,1: Use RxValid signal to infer Electrical Idle.." newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB Note: The access attributes of this field are as follows: - Wire: No access. Note: This register.." "0: -6 dB,1: -3" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). Note: The access attributes of this field are as follows: - Wire: No access. Note: This.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing Note: The access attributes of this field are as.." "0: Full Swing,1: Low Swing Note: The access attributes of this.." newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto Flipping Of The Lanes" "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane For Auto Flip" "0: Connect logical Lane0 to physical lane 0 or 1..,1: Connect logical Lane0 to physical lane 1,2: Connect logical Lane0 to physical lane 3,3: Connect logical Lane0 to physical lane 7,4: Connect logical Lane0 to physical lane 15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long 0x810++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status" hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY status" group.long 0x814++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control" hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long 0x81C++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control" hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access." newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address" hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address" hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt #0 Enable" hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt #0 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt #0 Mask" hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt #0 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt #0 Status" hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt #0 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt #1 Enable" hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt #1 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt #1 Mask" hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt #1 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt #1 Status" hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt #1 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt #2 Enable" hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt #2 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt #2 Mask" hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt #2 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt #2 Status" hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt #2 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt #3 Enable" hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt #3 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt #3 Mask" hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt #3 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt #3 Status" hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt #3 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt #4 Enable" hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt #4 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt #4 Mask" hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt #4 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt #4 Status" hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt #4 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt #5 Enable" hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt #5 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt #5 Mask" hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt #5 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt #5 Status" hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt #5 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt #6 Enable" hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt #6 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt #6 Mask" hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt #6 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt #6 Status" hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt #6 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt #7 Enable" hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt #7 Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt #7 Mask" hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt #7 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt #7 Status" hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt #7 Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO" hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,RADM clock gating enable control" bitfld.long 0x70 0. "RADM_CLK_GATING_EN,Enable Radm clock gating feature. - 0: Disable - 1: Enable(default)" "0: Disable,1: Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control" bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable." "0,1" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable" "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable" "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable" "0,1" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request" "0: mac_phy_rxeqeval asserts after 1us and 2 TS1..,1: mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable" "0,1" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable" "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable" "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 And Phase 3 Disable" "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler For Gen3 and Gen4 Data Rate" "0,1" newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant" "0: The receiver complies with the ZRX-DC parameter..,1: The receiver does not comply with the ZRX-DC.." group.long 0x8A8++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control" bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "0: Do not request,1: request Note: Gen3 and Gen4 share the same.." newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM" "0: Do not include,1: Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "0: not support,1: support Note: Gen3 and Gen4 share the same.." newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable" "0: Abort the current evaluation stop any attempt to..,1: ignore the 2ms timeout and continue as normal." newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (When Optimal Settings Are Not Found)" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode" line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control" hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture For C+1" newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture For C-1" newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth" newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase" group.long 0x8B4++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control" hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control" bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable" bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). Simplified Replay Timer Values are: - A value from 24 000 to 31 000 Symbol Times when Extended Synch is 0b. - A value from 80 000 to 100 000 Symbol Times when Extended Synch is 1b. Must not.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,This field only applies to request TLPs (with UR filtering status) that you have chosen to forward to the application (when you set DEFAULT_TARGET in this register)" "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status will be generated for.." "0: The controller drops all incoming I/O or MEM..,1: The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write To Read-Only Fields Using DBI" "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control" bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control" bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1. Note: This register field is sticky." "0: Controller requests aux_clk switch and core_clk..,1: Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access attributes of this field are as.." "0: Core waits for the PHY to acknowledge transition..,1: Core does not wait for PHY to acknowledge.." newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS and.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control" eventfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control" hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response" hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping" "0: OKAY,1: OKAY with all FFFF_FFFF data for all CRS..,2: OKAY with FFFF_0001 data for CRS completions to..,3: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping" "0: OKAY (with FFFF data),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping" "0: OKAY (with FFFF data for non-posted requests),1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field.." line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout" bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control" bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward To The Application" "0: The zero-length read terminates at the PCIe AXI..,1: The zero-length read is forwarded to the.." newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector" "0: B'last event: wait for the all of the write..,1: AW'last event: wait until the complete Posted..,?,?" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable" "0,1" group.long 0x8E0++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "0: lower = Peripheral,1: lower = Memory type" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline bitfld.long 0x8 24.--25. "CFG_MSTR_AWDOMAIN_VALUE,Master Write DOMAIN Signal Value. Value of the individual bits in mstr_awdomain when CFG_MSTR_AWDOMAIN_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awdomain is always '11' Note:.." "0,1,2,3" newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline bitfld.long 0x8 16.--17. "CFG_MSTR_ARDOMAIN_VALUE,Master Read DOMAIN Signal Value. Value of the individual bits in mstr_ardomain when CFG_MSTR_ARDOMAIN_MODE is '1' Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline bitfld.long 0x8 8.--9. "CFG_MSTR_AWDOMAIN_MODE,Master Write DOMAIN Signal Behavior. Defines how the individual bits in mstr_awdomain[1:0] are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWDOMAIN_VALUE field.." "0: set automatically by the AXI master,1: set by the value of the corresponding bit of the..,?,?" newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." newline bitfld.long 0x8 0.--1. "CFG_MSTR_ARDOMAIN_MODE,Master Read DOMAIN Signal Behavior. Defines how the individual bits in mstr_ardomain[1:0] are controlled: - 0: set automatically by the AXI master - 1: set the value of the corresponding bit of the CFG_MSTR_ARDOMAIN_VALUE field.." "0: set automatically by the AXI master,1: set the value of the corresponding bit of the..,?,?" group.long 0x8F0++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to" hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to" hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long 0x8F8++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number" hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type" hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long 0x930++0xB line.long 0x0 "INTERFACE_TIMER_CONTROL_OFF,Interface Timer Control" bitfld.long 0x0 4. "FORCE_PENDING,Writing to this bit forces the value of the pending flags. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2.--3. "INTERFACE_TIMER_SCALING,Interface timer scaling. This field can be used to reduce the timer duration for verification purpose. This field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 1. "INTERFACE_TIMER_AER_EN,Interface timer AER generation enable. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "INTERFACE_TIMER_EN,Interface timer enable. Note: This register field is sticky." "0,1" line.long 0x4 "INTERFACE_TIMER_TARGET_OFF,Interface Timer Target" hexmask.long.word 0x4 0.--15. 1. "INTERFACE_TIMER_TARGET,Interface timer target value. This field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register field is sticky." line.long 0x8 "INTERFACE_TIMER_STATUS_OFF,Interface Timer Status" eventfld.long 0x8 11. "SLAVE_RD_ADD_TIMEOUT,Slave read address channel timeout." "0,1" newline eventfld.long 0x8 10. "SLAVE_WR_DATA_TIMEOUT,Slave write data channel timeout." "0,1" newline eventfld.long 0x8 9. "SLAVE_WR_ADD_TIMEOUT,Slave write address channel timeout." "0,1" newline eventfld.long 0x8 6. "MASTER_RD_DATA_TIMEOUT,Master read data channel timeout." "0,1" newline eventfld.long 0x8 5. "MASTER_WR_RES_TIMEOUT,Master write response channel timeout." "0,1" newline eventfld.long 0x8 4. "CLIENT2_INTERFACE_TIMEOUT,Client2 interface timeout." "0,1" newline eventfld.long 0x8 3. "CLIENT1_INTERFACE_TIMEOUT,Client1 interface timeout." "0,1" newline eventfld.long 0x8 1. "CPL_INTERFACE_TIMEOUT,CPL interface timeout." "0,1" newline eventfld.long 0x8 0. "MESSAGE_INTERFACE_TIMEOUT,Message interface timeout." "0,1" group.long 0x940++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low" hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High" hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long 0x948++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell" bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long 0x94C++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM Power Mode And Debug Control" hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long 0x960++0x7 line.long 0x0 "SAFETY_MASK_OFF,Masks for functional safety interrupt events" bitfld.long 0x0 5. "SAFETY_INT_MASK_5,Mask for functional safety interrupt event 5 (RASDP correctable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "SAFETY_INT_MASK_4,Mask for functional safety interrupt event 4 (PCIe correctable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "SAFETY_INT_MASK_3,Mask for functional safety interrupt event 3 (PCIe uncorrectable). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "SAFETY_INT_MASK_2,Mask for functional safety interrupt event 2 (Interface timers). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "SAFETY_INT_MASK_1,Mask for functional safety interrupt event 1 (CDM register checker). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "SAFETY_INT_MASK_0,Mask for functional safety interrupt event 0 (RASDP). Note: This register field is sticky." "0,1" line.long 0x4 "SAFETY_STATUS_OFF,Status for functional safety interrupt events." eventfld.long 0x4 5. "SAFETY_INT_STATUS_5,Status for functional safety interrupt event 5 (RASDP correctable)." "0,1" newline eventfld.long 0x4 4. "SAFETY_INT_STATUS_4,Status for functional safety interrupt event 4 (PCIe correctable)." "0,1" newline eventfld.long 0x4 3. "SAFETY_INT_STATUS_3,Status for functional safety interrupt event 3 (PCIe uncorrectable)." "0,1" newline eventfld.long 0x4 2. "SAFETY_INT_STATUS_2,Status for functional safety interrupt event 2 (Interface timers)." "0,1" newline eventfld.long 0x4 1. "SAFETY_INT_STATUS_1,Status for functional safety interrupt event 1 (CDM register checker)." "0,1" newline eventfld.long 0x4 0. "SAFETY_INT_STATUS_0,Status for functional safety interrupt event 0 (RASDP)." "0,1" group.long 0xB20++0x7 line.long 0x0 "PL_CHK_REG_CONTROL_STATUS_OFF,CDM Register Checking Control and Status" eventfld.long 0x0 18. "CHK_REG_COMPLETE,The system has completed a checking cycle." "0,1" newline eventfld.long 0x0 17. "CHK_REG_LOGIC_ERROR,The system has detected an error in its own checking logic." "0,1" newline eventfld.long 0x0 16. "CHK_REG_COMPARISON_ERROR,The system has detected that there is a bit error in the CDM Register Data." "0,1" newline bitfld.long 0x0 1. "CHK_REG_CONTINUOUS,Set Continuous Checking Sequence. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "CHK_REG_START,Begins a checking sequence. Note: This register field is sticky." "0,1" line.long 0x4 "PL_CHK_REG_START_END_OFF,CDM Register Checking First and Last address to check" hexmask.long.word 0x4 16.--31. 1. "CHK_REG_END_ADDR,The last address that is checked by the system. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "CHK_REG_START_ADDR,The first address that is checked by the system. Note: This register field is sticky." rgroup.long 0xB28++0x7 line.long 0x0 "PL_CHK_REG_ERR_ADDR_OFF,CDM Register Checking Error Address." hexmask.long 0x0 0.--31. 1. "CHK_REG_ERR_ADDR,The address at which an error has been detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." line.long 0x4 "PL_CHK_REG_ERR_PF_VF_OFF,CDM Register Checking error PF and VF Numbers" hexmask.long.word 0x4 16.--27. 1. "CHK_REG_VF_ERR_NUMBER,The VF number at which the error was detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--4. 1. "CHK_REG_PF_ERR_NUMBER,The PF number at which the error was detected. Valid only when the CDM Register Checker Comparison Error bit is set in the status register. Note: This register field is sticky." group.long 0xB40++0x3 line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control" hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x20010)++0x3 line.long 0x0 "BAR_MASK[$1],BARn Mask" hexmask.long 0x0 1.--31. 1. "PCI_TYPE1_BAR0_MASK,BAR0 Mask" newline bitfld.long 0x0 0. "PCI_TYPE1_BAR0_ENABLED,BAR0 Mask Enabled" "0: Disabled,1: Enabled" repeat.end group.long 0x60000++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60020++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60100++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_0,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_0,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated. This field is sticky." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60120++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60200++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_1,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_1,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60220++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60300++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_1,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_1,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_1,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated. This field is sticky." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_1,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_1,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_1,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60320++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60400++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_2,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_2,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60420++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60500++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_2,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_2,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_2,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated. This field is sticky." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_2,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_2,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_2,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60520++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60600++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_3,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_3,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60620++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60700++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_3,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU Region size is 4 GB,1: Maximum ATU Region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_INBOUND_3,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "0: Address Match Mode,1: Vendor ID Match Mode" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x4 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x4 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "0,1,2,3" newline bitfld.long 0x4 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x4 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x4 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x4 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_INBOUND_3,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated. This field is sticky." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated" line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_INBOUND_3,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_3,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_3,iATU Lower Target Address" hexmask.long.tbyte 0x14 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region." newline hexmask.long.word 0x14 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region." line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." group.long 0x60720++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky." group.long 0x60800++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_4,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_4,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60820++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." group.long 0x60A00++0x1B line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_5,iATU Region Control 1" bitfld.long 0x0 20.--22. "CTRL_1_FUNC_NUM,Function Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase Maximum ATU Region Size" "0: Maximum ATU region size is 4 GB,1: Maximum ATU region size is 1 TB" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." line.long 0x4 "IATU_REGION_CTRL_2_OFF_OUTBOUND_5,iATU Region Control 2" bitfld.long 0x4 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "CFG_SHIFT_MODE,CFG Shift Mode" "0,1" newline bitfld.long 0x4 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "0: LWR_TARGET_RW in the..,1: LWR_TARGET_RW in the.." newline bitfld.long 0x4 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0 .." "0: Fmt[1] =0/1 so that TLPs with or without data..,1: Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x4 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x4 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." line.long 0x8 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5,iATU Lower Base Address" hexmask.long.tbyte 0x8 12.--31. 1. "LWR_BASE_RW,Forms bits 31:12 of the start address of the address region to be translated." newline hexmask.long.word 0x8 0.--11. 1. "LWR_BASE_HW,Forms bits 11:0 of the start address of the address region to be translated." line.long 0xC "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5,iATU Upper Base Address" hexmask.long 0xC 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Limit Address" hexmask.long.tbyte 0x10 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated." newline hexmask.long.word 0x10 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated." line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5,iATU Lower Target Address" hexmask.long 0x14 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the translated region LWR_TARGET_RW[11:0] are not used" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5,iATU Upper Target Address" hexmask.long 0x18 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." group.long 0x60A20++0x3 line.long 0x0 "IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5,iATU Upper Limit Address" hexmask.long.tbyte 0x0 8.--31. 1. "UPPR_LIMIT_ADDR_HW,Forms MSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'. These bits are always '0'." newline hexmask.long.byte 0x0 0.--7. 1. "UPPR_LIMIT_ADDR_RW,Forms the LSB's of the Upper Limit part of the region 'end address' to be translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky." tree.end tree "SERDES_SS" base ad:0x40480000 group.long 0x0++0xB line.long 0x0 "PCIE_PHY_GEN_CTRL,PCIe PHY General Control" rbitfld.long 0x0 25. "PHY_RTUNE_STS,Resistor Tune Status" "0: Tuning has not started or completed,1: Tuning completed" newline bitfld.long 0x0 24. "PHY_RTUNE_REQ,Resistor Tune Request" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 17. "REF_USE_PAD,Reference Is From External Pad" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 16. "REF_REPEAT_CLK_EN,Repeat Reference Clock Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 11. "RX1_TERM_ACDC,Receiver Termination Control For Rx1" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 10. "RX0_TERM_ACDC,Receiver Termination Control For Rx0" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 9. "RX_SRIS_MODE,SRIS Enable As Defined In PCIe ECN" "0: Disables,1: Enables" newline bitfld.long 0x0 2. "CR_PARA_CLK_DIV2_EN,CR Parallel Clock Divider Control" "0: Same as PHY ref_dig_fr_clk,1: Half of ref_dig_fr_clk" newline bitfld.long 0x0 0. "EXT_PCLK_REQ,pipeP_pclk Required By External Logic" "0: Driven to 0,1: Driven to 1" line.long 0x4 "PCIE_PHY_LPBK_CTRL,PCIe PHY Loopback Control" bitfld.long 0x4 3. "LANE1_RX2TX_PAR_LB_EN,Lane1 Parallel (RX To TX) Loopback Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x4 2. "LANE1_TX2RX_LOOPBK,Lane1 Analog Serial Loopback Control" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x4 1. "LANE0_RX2TX_PAR_LB_EN,Lane0 Parallel (RX to TX) Loopback Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x4 0. "LANE0_TX2RX_LOOPBK,Lane0 Analog Serial Loopback Control" "0: Driven to 0,1: Driven to 1" line.long 0x8 "PCIE_PHY_SRAM_CSR,PCIe PHY SRAM Control And Status" rbitfld.long 0x8 2. "SRAM_INIT_DONE,SRAM Initialization Done" "0: 0,1: 1" newline bitfld.long 0x8 1. "SRAM_EXT_LD_DONE,SRAM External Load Done" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x8 0. "SRAM_BYPASS,SRAM Bypass" "0: Driven to 0,1: Driven to 1" group.long 0x10++0x13 line.long 0x0 "PCIE_PHY_MPLLA_CTRL,PCIe PHY MPLLA Control" rbitfld.long 0x0 31. "MPLLA_STATE,MPLLA State Indicator" "0: 0,1: 1" newline rbitfld.long 0x0 30. "MPLL_STATE,MPLLA or MPLLB State Indicator" "0: phy0_mplla_state and phy0_mpllb_state are 0,1: phy0_mplla_state or phy0_mpllb_state is 1" newline bitfld.long 0x0 0. "MPLLA_FORCE_EN,MPLLA Force Enable" "0: Driven to 0,1: Driven to 1" line.long 0x4 "PCIE_PHY_MPLLB_CTRL,PCIe PHY MPLLB Control" rbitfld.long 0x4 31. "MPLLB_STATE,MPLLB State Indicator" "0: 0,1: 1" newline rbitfld.long 0x4 30. "MPLL_STATE,MPLLA or MPLLB State Indicator" "0: phy0_mplla_state and phy0_mpllb_state are 0,1: phy0_mplla_state or phy0_mpllb_state is 1" newline bitfld.long 0x4 0. "MPLLB_FORCE_EN,MPLLB Force Enable" "0: Driven to 0,1: Driven to 1" line.long 0x8 "PCIE_PHY_EXT_CTRL_SEL,PCIe PHY Setting External Control" bitfld.long 0x8 0. "EXT_PHY_CTRL_SEL,External Control Of PHY Setting" "0: Driven to 0,1: Driven to 1" line.long 0xC "PCIE_PHY_EXT_BS_CTRL,PCIe PHY Boundary Scan Control" bitfld.long 0xC 6. "EXT_BS_TX_LOWSWING,TX Boundary Scan Low Swing" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0xC 5. "EXT_BS_RX_BIGSWING,RX Boundary Scan Big Swing" "0: Driven to 0,1: Driven to 1" newline hexmask.long.byte 0xC 0.--4. 1. "EXT_BS_RX_LEVEL,ACJTAG Receiver Sensitivity Level Control" line.long 0x10 "PCIE_PHY_REF_CLK_CTRL,PCIe Reference Clock Control" bitfld.long 0x10 3.--5. "REF_RANGE,Input Reference Clock frequency Range" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 2. "REF_CLK_DIV2_EN,Input Reference Clock Divider Control" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x10 1. "REF_CLK_MPLLB_DIV2_EN,MPLLB Reference Clock Divider Control" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x10 0. "REF_CLK_MPLLA_DIV2_EN,MPLLA Reference Clock Divider Control" "0: Driven to 0,1: Driven to 1" group.long 0x30++0xB line.long 0x0 "PCIE_PHY_EXT_MPLLA_CTRL_1,PCIe PHY MPLLA Control 1" hexmask.long.byte 0x0 24.--31. 1. "EXT_MPLLA_DIV_MULTIPLIER,MPLLA Output Frequency Multiplier Control" newline bitfld.long 0x0 19. "EXT_MPLLA_DIV_CLK_EN,MPLLA Divide Clock Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 18. "EXT_MPLLA_DIV8_CLK_EN,MPLLA Divide by 8 Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 17. "EXT_MPLLA_DIV16P5_CLK_EN,MPLLA Divide by 16.5 Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 16. "EXT_MPLLA_DIV10_CLK_EN,MPLLA Divide by 10 Enable" "0: Driven to 0,1: Driven to 1" newline hexmask.long.word 0x0 0.--15. 1. "EXT_MPLLA_BANDWIDTH,MPLLA Bandwidth Control" line.long 0x4 "PCIE_PHY_EXT_MPLLA_CTRL_2,PCIe PHY MPLLA Control 2" hexmask.long.word 0x4 12.--22. 1. "EXT_MPLLA_FRACN_CTRL,MPLLA Fractional Control" newline hexmask.long.byte 0x4 0.--7. 1. "EXT_MPLLA_MULTIPLIER,MPLLA Frequency Multiplier Control" line.long 0x8 "PCIE_PHY_EXT_MPLLA_CTRL_3,PCIe PHY MPLLA Control 3" bitfld.long 0x8 31. "EXT_MPLLA_WORD_DIV2_EN,MPLLA Word Clock Divide by 2" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x8 28.--30. "EXT_MPLLA_TX_CLK_DIV,MPLLA Tx Clock Divide" "0,1,2,3,4,5,6,7" group.long 0x40++0xB line.long 0x0 "PCIE_PHY_EXT_MPLLB_CTRL_1,PCIe PHY MPLLB Control 1" hexmask.long.byte 0x0 24.--31. 1. "EXT_MPLLB_DIV_MULTIPLIER,MPLLB Output Frequency Multiplier Control" newline bitfld.long 0x0 19. "EXT_MPLLB_DIV_CLK_EN,MPLLB Divide Clock Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 18. "EXT_MPLLB_DIV8_CLK_EN,MPLLB Divide by 8 Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 16. "EXT_MPLLB_DIV10_CLK_EN,MPLLB Divide by 10 Enable" "0: Driven to 0,1: Driven to 1" newline hexmask.long.word 0x0 0.--15. 1. "EXT_MPLLB_BANDWIDTH,MPLLB Bandwidth Control" line.long 0x4 "PCIE_PHY_EXT_MPLLB_CTRL_2,PCIe PHY MPLLB Control 2" hexmask.long.word 0x4 12.--22. 1. "EXT_MPLLB_FRACN_CTRL,MPLLB Fractional Control" newline hexmask.long.byte 0x4 0.--7. 1. "EXT_MPLLB_MULTIPLIER,MPLLB Frequency Multiplier Control" line.long 0x8 "PCIE_PHY_EXT_MPLLB_CTRL_3,PCIe PHY MPLLB Control 3" bitfld.long 0x8 31. "EXT_MPLLB_WORD_DIV2_EN,MPLLB Word Clock Divide by 2" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x8 28.--30. "EXT_MPLLB_TX_CLK_DIV,MPLLB Tx Clock Divide" "0,1,2,3,4,5,6,7" group.long 0x50++0xB line.long 0x0 "PCIE_PHY_EXT_RX_EQ_CTRL_1A,PCIe PHY RX Equalization Control 1 For Gen1 Speed" hexmask.long.byte 0x0 26.--31. 1. "EXT_RX_EQ_CTLE_POLE_G1,RX Equalization CTLE Pole" newline hexmask.long.word 0x0 16.--25. 1. "EXT_RX_EQ_CTLE_BOOST_G1,RX Equalization CTLE Boost" newline hexmask.long.byte 0x0 4.--9. 1. "EXT_RX_EQ_ATT_LVL_G1,RX Equalization Attenuation Level" newline bitfld.long 0x0 2.--3. "EXT_RX_ADAPT_DFE_EN_G1,RX DFE Enable" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EXT_RX_ADAPT_AFE_EN_G1,RX Adaptation Enable" "0,1,2,3" line.long 0x4 "PCIE_PHY_EXT_RX_EQ_CTRL_1B,PCIe PHY RX Equalization Control 2 For Gen1 Speed" hexmask.long.byte 0x4 24.--31. 1. "EXT_RX_EQ_VGA2_GAIN_G1,RX Equalization VGA Gain 2" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_RX_EQ_VGA1_GAIN_G1,RX Equalization VGA Gain 1" newline hexmask.long.word 0x4 0.--15. 1. "EXT_RX_EQ_DFE_TAP1_G1,RX Equalization DFE Tap1" line.long 0x8 "PCIE_PHY_EXT_RX_EQ_CTRL_1C,PCIe PHY RX Equalization Control 3 For Gen1 Speed" hexmask.long.byte 0x8 0.--7. 1. "EXT_RX_EQ_DELTA_IQ_G1,RX Equalization DELTA IQ" group.long 0x60++0xB line.long 0x0 "PCIE_PHY_EXT_RX_EQ_CTRL_2A,PCIe PHY RX Equalization Control 1 For Gen2 Speed" hexmask.long.byte 0x0 26.--31. 1. "EXT_RX_EQ_CTLE_POLE_G2,RX Equalization CTLE Pole" newline hexmask.long.word 0x0 16.--25. 1. "EXT_RX_EQ_CTLE_BOOST_G2,RX Equalization CTLE Boost" newline hexmask.long.byte 0x0 4.--9. 1. "EXT_RX_EQ_ATT_LVL_G2,RX Equalization Attenuation Level" newline bitfld.long 0x0 2.--3. "EXT_RX_ADAPT_DFE_EN_G2,RX DFE Enable" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EXT_RX_ADAPT_AFE_EN_G2,RX Adaptation Enable" "0,1,2,3" line.long 0x4 "PCIE_PHY_EXT_RX_EQ_CTRL_2B,PCIe PHY RX Equalization Control 2 For Gen2 Speed" hexmask.long.byte 0x4 24.--31. 1. "EXT_RX_EQ_VGA2_GAIN_G2,RX Equalization VGA Gain 2" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_RX_EQ_VGA1_GAIN_G2,RX Equalization VGA Gain 1" newline hexmask.long.word 0x4 0.--15. 1. "EXT_RX_EQ_DFE_TAP1_G2,RX Equalization DFE Tap1" line.long 0x8 "PCIE_PHY_EXT_RX_EQ_CTRL_2C,PCIe PHY RX Equalization Control 3 For Gen2 Speed" hexmask.long.byte 0x8 0.--7. 1. "EXT_RX_EQ_DELTA_IQ_G2,RX Equalization DELTA IQ" group.long 0x70++0xB line.long 0x0 "PCIE_PHY_EXT_RX_EQ_CTRL_3A,PCIe PHY RX Equalization Control 1 For Gen3 Speed" hexmask.long.byte 0x0 26.--31. 1. "EXT_RX_EQ_CTLE_POLE_G3,RX Equalization CTLE Pole" newline hexmask.long.word 0x0 16.--25. 1. "EXT_RX_EQ_CTLE_BOOST_G3,RX Equalization CTLE Boost" newline hexmask.long.byte 0x0 4.--9. 1. "EXT_RX_EQ_ATT_LVL_G3,RX Equalization Attenuation Level" newline bitfld.long 0x0 2.--3. "EXT_RX_ADAPT_DFE_EN_G3,RX DFE Enable" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EXT_RX_ADAPT_AFE_EN_G3,RX Adaptation Enable" "0,1,2,3" line.long 0x4 "PCIE_PHY_EXT_RX_EQ_CTRL_3B,PCIe PHY RX Equalization Control 2 For Gen3 Speed" hexmask.long.byte 0x4 24.--31. 1. "EXT_RX_EQ_VGA2_GAIN_G3,RX Equalization VGA Gain 2" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_RX_EQ_VGA1_GAIN_G3,RX Equalization VGA Gain 1" newline hexmask.long.word 0x4 0.--15. 1. "EXT_RX_EQ_DFE_TAP1_G3,RX Equalization DFE Tap1" line.long 0x8 "PCIE_PHY_EXT_RX_EQ_CTRL_3C,PCIe PHY RX Equalization Control 3 For Gen3 Speed" hexmask.long.byte 0x8 0.--7. 1. "EXT_RX_EQ_DELTA_IQ_G3,RX Equalization DELTA IQ" group.long 0x80++0xB line.long 0x0 "PCIE_PHY_EXT_RX_EQ_CTRL_4A,PCIe PHY RX Equalization Control 1 For Gen4 Speed" hexmask.long.byte 0x0 26.--31. 1. "EXT_RX_EQ_CTLE_POLE_G4,RX Equalization CTLE Pole" newline hexmask.long.word 0x0 16.--25. 1. "EXT_RX_EQ_CTLE_BOOST_G4,RX Equalization CTLE Boost" newline hexmask.long.byte 0x0 4.--9. 1. "EXT_RX_EQ_ATT_LVL_G4,RX Equalization Attenuation Level" newline bitfld.long 0x0 2.--3. "EXT_RX_ADAPT_DFE_EN_G4,RX DFE Enable" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EXT_RX_ADAPT_AFE_EN_G4,RX Adaptation Enable" "0,1,2,3" line.long 0x4 "PCIE_PHY_EXT_RX_EQ_CTRL_4B,PCIe PHY RX Equalization Control 2 For Gen4 Speed" hexmask.long.byte 0x4 24.--31. 1. "EXT_RX_EQ_VGA2_GAIN_G4,RX Equalization VGA Gain 2" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_RX_EQ_VGA1_GAIN_G4,RX Equalization VGA Gain 1" newline hexmask.long.word 0x4 0.--15. 1. "EXT_RX_EQ_DFE_TAP1_G4,RX Equalization DFE Tap1" line.long 0x8 "PCIE_PHY_EXT_RX_EQ_CTRL_4C,PCIe PHY RX Equalization Control 3 For Gen4 Speed" hexmask.long.byte 0x8 0.--7. 1. "EXT_RX_EQ_DELTA_IQ_G4,RX Equalization DELTA IQ" group.long 0x90++0x17 line.long 0x0 "PCIE_PHY_EXT_CALI_CTRL_1,PCIe PHY Calibration Control For Gen1 Speed" hexmask.long.byte 0x0 16.--21. 1. "EXT_RX_REF_LD_VAL_G1,RX VCO Calibration Reference Load Value" newline hexmask.long.word 0x0 0.--12. 1. "EXT_RX_VCO_LD_VAL_G1,RX VCO Calibration Load Value" line.long 0x4 "PCIE_PHY_EXT_CALI_CTRL_2,PCIe PHY Calibration Control For Gen2 Speed" hexmask.long.byte 0x4 16.--21. 1. "EXT_RX_REF_LD_VAL_G2,RX VCO Calibration Reference Load Value" newline hexmask.long.word 0x4 0.--12. 1. "EXT_RX_VCO_LD_VAL_G2,RX VCO Calibration Load Value" line.long 0x8 "PCIE_PHY_EXT_CALI_CTRL_3,PCIe PHY Calibration Control For Gen3 Speed" hexmask.long.byte 0x8 16.--21. 1. "EXT_RX_REF_LD_VAL_G3,RX VCO Calibration Reference Load Value" newline hexmask.long.word 0x8 0.--12. 1. "EXT_RX_VCO_LD_VAL_G3,RX VCO Calibration Load Value" line.long 0xC "PCIE_PHY_EXT_CALI_CTRL_4,PCIe PHY Calibration Control For Gen4 Speed" hexmask.long.byte 0xC 16.--21. 1. "EXT_RX_REF_LD_VAL_G4,RX VCO Calibration Reference Load Value" newline hexmask.long.word 0xC 0.--12. 1. "EXT_RX_VCO_LD_VAL_G4,RX VCO Calibration Load Value" line.long 0x10 "PCIE_PHY_EXT_MISC_CTRL_1,PCIe PHY Miscellaneous Control 1" bitfld.long 0x10 29.--31. "EXT_RX_TERM_CTRL,RX Term Control" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--28. 1. "EXT_RX_VREF_CTRL,RX Biasing Current Control" newline hexmask.long.word 0x10 8.--18. 1. "EXT_RX_LOS_PWR_UP_CNT,Receiver LOS Power Up Counter" newline hexmask.long.byte 0x10 1.--6. 1. "EXT_RX_LOS_THRESHOLD,Receiver LOS Threshold" newline bitfld.long 0x10 0. "EXT_RX_LOS_LFPS_EN,Receiver LOS LFPS Enable" "0: Driven to 0,1: Driven to 1" line.long 0x14 "PCIE_PHY_EXT_MISC_CTRL_2,PCIe PHY Miscellaneous Control 2" bitfld.long 0x14 24.--26. "EXT_TX_TERM_CTRL,Tx Term Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 16.--18. "EXT_TX_VBOOST_LVL,TX Voltage Boost Maximum Level" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EXT_TX_IBOOST_LVL,Transmitter Current Boost Level" group.long 0xB0++0xB line.long 0x0 "PCIE_PHY_EXT_TX_EQ_CTRL_1,PCIe PHY TX Equalization Control For Gen1 Speed" bitfld.long 0x0 28.--29. "EXT_TX_EQ_OVRD_G1,TX Equalization Override Enable" "0,1,2,3" newline hexmask.long.word 0x0 16.--25. 1. "EXT_TX_EQ_MAIN_G1,TX Equalization Amplitude Adjustment Control" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_TX_EQ_PRE_G1,TX Equalization Pre-Emphasis Level Adjustment Control" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_TX_EQ_POST_G1,TX Equalization Post-Emphasis Level Adjustment Control" line.long 0x4 "PCIE_PHY_EXT_TX_EQ_CTRL_2,PCIe PHY TX Equalization Control For Gen2 Speed" bitfld.long 0x4 28.--29. "EXT_TX_EQ_OVRD_G2,TX Equalization Override Enable" "0,1,2,3" newline hexmask.long.word 0x4 16.--25. 1. "EXT_TX_EQ_MAIN_G2,TX Equalization Amplitude Adjustment Control" newline hexmask.long.byte 0x4 8.--15. 1. "EXT_TX_EQ_PRE_G2,TX Equalization Pre-Emphasis Level Adjustment Control" newline hexmask.long.byte 0x4 0.--7. 1. "EXT_TX_EQ_POST_G2,TX Equalization Post-Emphasis Level Adjustment Control" line.long 0x8 "PCIE_PHY_EXT_TX_EQ_CTRL_3,PCIe PHY TX Equalization Control For Gen3 Speed" bitfld.long 0x8 28.--29. "EXT_TX_EQ_OVRD_G3,TX Equalization Override Enable" "0,1,2,3" newline hexmask.long.word 0x8 16.--25. 1. "EXT_TX_EQ_MAIN_G3,TX Equalization Amplitude Adjustment Control" newline hexmask.long.byte 0x8 8.--15. 1. "EXT_TX_EQ_PRE_G3,TX Equalization Pre-Emphasis Level Adjustment Control" newline hexmask.long.byte 0x8 0.--7. 1. "EXT_TX_EQ_POST_G3,TX Equalization Post-Emphasis Level Adjustment Control" group.long 0xC0++0x3 line.long 0x0 "PCIE_PHY_XPCS0_RX_OVRD_CTRL,PCIe PHY XPCS_0 Rx Override Control" hexmask.long.word 0x0 16.--28. 1. "XPCS0_RX_VCO_LD_VAL,Override Control for xpcs0_rx0_vco_ld_val" newline hexmask.long.byte 0x0 8.--13. 1. "XPCS0_RX_REF_LD_VAL,Override Control For xpcs0_rx0_ref_ld_val" newline bitfld.long 0x0 0. "XPCS0_RX_OVRD,XPCS_0 RX Override Control" "0: Does not override,1: Overrides" group.long 0xD0++0x3 line.long 0x0 "PCIE_PHY_XPCS1_RX_OVRD_CTRL,PCIe PHY XPCS_1 Rx Override Control" hexmask.long.word 0x0 16.--28. 1. "XPCS1_RX_VCO_LD_VAL,Override Control for xpcs1_rx0_vco_ld_val" newline hexmask.long.byte 0x0 8.--13. 1. "XPCS1_RX_REF_LD_VAL,Override Control For xpcs1_rx0_ref_ld_val" newline bitfld.long 0x0 0. "XPCS1_RX_OVRD,XPCS_1 RX Override Control" "0: Does not override,1: Overrides" rgroup.long 0xE0++0xF line.long 0x0 "SS_RO_REG_0,Subsystem Read-Only Register 0" hexmask.long.byte 0x0 26.--31. 1. "MSTR_ARMISC_INFO_DMA,DMA Bits Of The AXI Read Master Transaction" newline bitfld.long 0x0 25. "PCS1_LINK_STATUS,XPCS_1 Receive Link Status" "0: Link down,1: Link up" newline bitfld.long 0x0 24. "PCS1_SGMII_FULL_DUPLEX,SGMII Full Duplex Of XPCS_1" "0: Half duplex,1: Full duplex" newline bitfld.long 0x0 23. "PCS1_SGMII_LINK_STS,SGMII Link Status Of XPCS_1" "0: Link down,1: Link up" newline bitfld.long 0x0 22. "PCS0_LINK_STATUS,XPCS_0 Receive Link Status" "0: Link down,1: Link up" newline bitfld.long 0x0 21. "PCS0_SGMII_FULL_DUPLEX,SGMII Full Duplex Of XPCS_0" "0: Half duplex,1: Full duplex" newline bitfld.long 0x0 20. "PCS0_SGMII_LINK_STS,SGMII Link Status Of XPCS_0" "0: Link down,1: Link up" newline bitfld.long 0x0 19. "CDM_REG_CHK_CMPLT,Register Checking Complete" "0: Not completed,1: Completed" newline bitfld.long 0x0 18. "CDM_REG_CHK_CMP_ERR,CDM Comparison Error" "0: The values are not matched.,1: The values are matched." newline bitfld.long 0x0 17. "CDM_REG_CHK_LOGIC_ERR,Error In Register-Checking Logic" "0: No error,1: Error" newline bitfld.long 0x0 15.--16. "PCS1_LINK_SPEED,SGMII MAC Speed Control" "0: 10 Mbps,1: 100 Mbps,2: 100 Mbps,?" newline bitfld.long 0x0 13.--14. "PCS0_LINK_SPEED,SGMII MAC Speed Control" "0: 10 Mbps,1: 100 Mbps,2: 1000 Mbps,?" newline hexmask.long.byte 0x0 5.--12. 1. "MSI_CTRL_INT_VEC,DSP AXI MSI Interrupt Vector" newline bitfld.long 0x0 4. "MSTR_ARMISC_INFO_LAST_DCMP_TLP,Last TLP Of The PCIe Controller's AXI Master Read Request" "0: The TLP in the transaction is not the last TLP..,1: The TLP in the transaction is the last TLP of.." newline bitfld.long 0x0 3. "MSTR_AWMISC_INFO_LAST_DCMP_TLP,Last TLP Of The PCIe controller's AXI Master Write Request" "0: The TLP in the transaction is not the last TLP..,1: The TLP in the transaction is the last TLP of.." newline bitfld.long 0x0 2. "PHY_RX1_LOS,Receive Loss Of Signal (LOS) Output 1" "0: The receiver has not lost the signal.,1: The receiver has lost the signal." newline bitfld.long 0x0 1. "PHY_RX0_LOS,Receive Loss Of Signal (LOS) Output 0" "0: The receiver has not lost the signal.,1: The receiver has lost the signal." line.long 0x4 "SS_RO_REG_1,Subsystem Read-Only Register 1" hexmask.long.word 0x4 17.--27. 1. "SLV_RMISC_INFO,Miscellaneous Read Information" newline hexmask.long.word 0x4 6.--16. 1. "SLV_BMISC_INFO,Miscellaneous Write Information" newline hexmask.long.byte 0x4 0.--5. 1. "MSTR_AWMISC_INFO_DMA,DMA Bits Of The AXI Write Master Transaction" line.long 0x8 "SS_RO_REG_2,Subsystem Read-Only Register 2" hexmask.long 0x8 0.--31. 1. "REG2,Subsystem Read Only Register 2" line.long 0xC "SS_RO_REG_3,Subsystem Read-Only Register 3" hexmask.long 0xC 0.--31. 1. "REG3,Subsystem Read Only Register 3" group.long 0xF0++0x17 line.long 0x0 "SS_RW_REG_0,Subsystem Read/Write Register 0" bitfld.long 0x0 31. "MSTR_RMISC_INFO,Miscellaneous Information Related To AXI Master Read-Response Transactions" "0: The controller operates normally.,1: The controller sets the Poisoned TLP (EP) bit in.." newline bitfld.long 0x0 30. "MDR,Memory Data Retention" "0: The subsystem retains data stored in memory and..,1: The subsystem does not retain data stored in.." newline bitfld.long 0x0 29. "PHY_TEST_TX_REF_CLK_EN,TX Reference Clock Output Enable" "0: Normal functional operation,1: The reference clock inputs (ref_pad_clk_{p m} or.." newline bitfld.long 0x0 27. "PHY_TEST_POWERDOWN,All Circuits Power-Down Control" "0: The PHY circuitry operates normally.,1: The PHY deactivates all its circuitry for IDDQ.." newline bitfld.long 0x0 25. "SLV_AWMISC_INFO_ATU_BYPASS,AXI Slave Write Request iATU Bypass" "0: The iATU must process this request.,1: The iATU must not process this request." newline bitfld.long 0x0 24. "SLV_ARMISC_INFO_ATU_BYPASS,AXI Slave Read Request iATU Bypass" "0: The iATU must process this request.,1: The iATU must not process this request." newline bitfld.long 0x0 23. "CLKEN,PCIe Reference Clock Enable" "0: External clock (phy0_ref_pad_clk_m..,1: Internal clock (PCIE_REF_CLK) is the reference.." newline hexmask.long.byte 0x0 15.--22. 1. "SLV_AWMISC_INFO_P_TAG,AXI Slave Write Request Tag" newline bitfld.long 0x0 14. "SLV_WMISC_INFO,Miscellaneous Information Related To AXI Slave Write-Data Transactions" "0: The controller operates normally.,1: The controller sets the Poisoned TLP (EP) bit in.." newline bitfld.long 0x0 12.--13. "MSTR_RMISC_INFO_CPL_STAT,AXI Master Read Response Selection Bus" "0: Successful completion,1: Completer abort,2: Unsupported request,3: Successful completion" newline bitfld.long 0x0 10.--11. "MSTR_BMISC_INFO_CPL_STAT,AXI Master Write Response Selection Bus" "0: Successful completion,1: Completer abort,2: Unsupported request,3: Successful completion" newline bitfld.long 0x0 9. "PHY0_CR_PARA_SEL,Control Register (CR) Parallel Interface Select" "0: Select the JTAG interface.,1: Select the CR interface." newline bitfld.long 0x0 7. "APP_XFER_PENDING,Application Transfer Pending" "0: No transactions exist outside the core,1: Transactions exist outside the core and the core.." newline bitfld.long 0x0 6. "SYS_INT,System Interrupt" "0,1" newline bitfld.long 0x0 5. "SYS_EML_INTERLOCK_ENGAGED,System Electromechanical Interlock Engaged" "0: Electromechanical interlock is not engaged,1: Electromechanical interlock is engaged" newline bitfld.long 0x0 4. "SYS_CMD_CPLED_INT,Command Completed Interrupt" "0: Command not completed,1: Command completed" newline bitfld.long 0x0 3. "SYS_ATTEN_BUTTON_PRESSED,Attention Button Pressed" "0,1" newline bitfld.long 0x0 0.--2. "SUBSYS_MODE,Subsystem Mode Selection" "0: PCIe Gen3x2 mode,1: PCIe Gen3x1 and SGMII 1G bifurcation mode (lane..,2: PCIe Gen3x1 and SGMII 1G bifurcation mode (lane..,3: Two SGMII 1G/2.5G bifurcation mode XPCS_0..,4: Two SGMII 1G/2.5G bifurcation mode XPCS_1..,?,?,?" line.long 0x4 "SS_RW_REG_1,Subsystem Read/Write Register 1" bitfld.long 0x4 7. "PARITY_MODE_SLV_RD_DATA,Parity Error Injection In AXI Slave Read Data Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 6. "PARITY_MODE_MSTR_WR_DATA,Parity Error Injection In AXI Master Write Data Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 5. "PARITY_MODE_MSTR_WR_ADDR,Parity Error Injection In AXI Master Write Address Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 4. "PARITY_MODE_MSTR_RD_ADDR,Parity Error Injection In AXI Master Read Address Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 3. "PARITY_MODE_SLV_WR_DATA,Parity Error Injection In AXI Slave Write Data Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 2. "PARITY_MODE_SLV_WR_ADDR,Parity Error Injection In AXI Slave Write Address Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 1. "PARITY_MODE_SLV_RD_ADDR,Parity Error Injection In AXI Slave Read Address Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 0. "PARITY_MODE_MSTR_RD_DATA,Parity Error Injection In AXI Master Read Data Bus" "0: No error injected,1: Error injected" line.long 0x8 "SS_RW_REG_2,Subsystem Read/Write Register 2" hexmask.long.tbyte 0x8 0.--21. 1. "SLV_ARMISC_INFO,Miscellaneous Information Associated With The AXI Slave Read Transaction" line.long 0xC "SS_RW_REG_3,Subsystem Read/Write Register 3" hexmask.long.tbyte 0xC 0.--21. 1. "SLV_AWMISC_INFO,Miscellaneous Information Associated With The AXI Slave Write Transaction" line.long 0x10 "SS_RW_REG_4,Subsystem Read/Write Register 4" hexmask.long 0x10 0.--31. 1. "SLV_AWMISC_INFO_HDR_3DW,AXI Slave Third Header DWs" line.long 0x14 "SS_RW_REG_5,Subsystem Read/Write Register 5" hexmask.long 0x14 0.--31. 1. "SLV_AWMISC_INFO_HDR_4DW,AXI Slave Fourth Header DWs" rgroup.long 0x1000++0x3 line.long 0x0 "PCIE_SUBSYSTEM_VERSION,PCIe Subsystem Version" hexmask.long 0x0 0.--31. 1. "VERSION,PCIe Subsystem Version" group.long 0x1040++0x3 line.long 0x0 "LINK_INT_CTRL_STS,Link Interrupt Control And Status" rbitfld.long 0x0 6. "LTSSM_STATE_RCVRY_EQ,Recovery Equalization State Status" "0: Not in Recovery Equalization state,1: In Recovery Equalization state" newline bitfld.long 0x0 5. "PHY_LINK_UP_INT_EN,PHY Link Up Interrupt Enable Control" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "PHY_LINK_DOWN_INT_EN,PHY Link Down Interrupt Enable Control" "0: Disable,1: Enable" newline eventfld.long 0x0 2. "LINK_REQ_RST_NOT_CLR,Clear Link Request Reset Status" "0: Do not change LINK_REQ_RST_NOT_STS,1: Change LINK_REQ_RST_NOT_STS to 0" newline bitfld.long 0x0 1. "LINK_REQ_RST_NOT_INT_EN,Link Request Reset Interrupt Enable Control" "0: Disable,1: Enable" newline rbitfld.long 0x0 0. "LINK_REQ_RST_NOT_STS,Link Request Reset Status" "0: Not set,1: Set" group.long 0x1050++0x17 line.long 0x0 "PE0_GEN_CTRL_1,PCIe Controller 0 General Control 1" bitfld.long 0x0 30. "TX_LANE_FLIP_EN,Manual Lane Reversal For Transmit Lanes In C-PCIe Mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "RX_LANE_FLIP_EN,Manual Lane Reversal For Receive Lanes In C-PCIe Mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "SRIS_MODE,SRIS Operation Mode" "0: Non-SRIS,1: SRIS" newline bitfld.long 0x0 4. "DEVICE_TYPE_OVERRIDE,Override Device Type" "0: You cannot override the device type.,1: You can override the device type." newline hexmask.long.byte 0x0 0.--3. 1. "DEVICE_TYPE,Device Type" line.long 0x4 "PE0_GEN_CTRL_2,PCIe Controller 0 General Control 2" bitfld.long 0x4 9. "SLV_ACLK_UNGATE,AXI Slave Clock Gating Control" "0: Gate,1: Do not gate" newline bitfld.long 0x4 8. "MSTR_ACLK_UNGATE,AXI Master Clock Gating Control" "0: Gate,1: Do not gate" line.long 0x8 "PE0_GEN_CTRL_3,PCIe Controller 0 General Control 3" bitfld.long 0x8 13.--15. "DIAG_CTRL_BUS,Diagnostic Control Bus" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3. "RAS_DES_SD_HOLD_LTSSM,Hold And Release LTSSM In Silicon Debug" "0: LTSSM not held in current state and might change..,1: LTSSM held in current state and does not change" newline bitfld.long 0x8 2. "HOT_RESET,Hot Reset" "?,1: Trigger a hot reset" newline bitfld.long 0x8 1. "CRS_EN,Configuration Request Retry Status (CRS) Enable" "0: PCIe controller does not complete incoming..,1: PCIe controller completes incoming configuration.." newline bitfld.long 0x8 0. "LTSSM_EN,LTSSM Enable" "0: Hold LTSSM in the Detect state until your..,1: Allow LTSSM to continue link establishment and.." line.long 0xC "PE0_GEN_CTRL_4,PCIe Controller 0 General Control 4" bitfld.long 0xC 31. "CRS_EN_CLR_MASK,CRS_EN Clear Mask" "0: CRS_EN does not change,1: CRS_EN goes to its reset value" newline bitfld.long 0xC 30. "LTSSM_EN_CLR_MASK,LTSSM_EN Clear Mask" "0: LTSSM_EN does not change,1: LTSSM_EN goes to its reset value" newline bitfld.long 0xC 28.--29. "CFG_RAS_DES_TBA_CTRL,Start And End Of Time-Based Analysis" "0: No actions,1: Start,2: End,?" line.long 0x10 "PE0_PM_CTRL,PCIe Controller 0 PM Control" bitfld.long 0x10 31. "BEACON_INT_EN,Beacon Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 21. "APP_CLK_PM_EN,Clock PM Feature Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 20. "APP_CLK_REQ,Wake Up Reference Clock" "0: No request to wake up,1: Explicit request to wake up" newline bitfld.long 0x10 19. "READY_ENTER_L23,Ready To Enter L23" "0: Not ready,1: Ready" newline bitfld.long 0x10 18. "EXIT_ASPM_L1,Request To Exit ASPM State L1" "0: No request to exit,1: Explicit request to exit" newline bitfld.long 0x10 17. "ENTER_ASPM_L1,Request To Enter ASPM State L1" "0: No request to enter,1: Explicit request to enter" newline bitfld.long 0x10 16. "PM_PME_REQ,PM_PME Message Request" "0,1" newline hexmask.long.byte 0x10 0.--4. 1. "PME_PF_INDEX,PF Index Of PM_PME Request And PM Status" line.long 0x14 "PE0_PM_STS,PCIe Controller 0 PM Status" eventfld.long 0x14 31. "BEACON_INT_STS,Beacon Interrupt Status" "0,1" newline rbitfld.long 0x14 15. "PM_LINKST_L2_EXIT,Power Management Is Exiting L2 State" "0: Not in L2 exit,1: In L2 exit" newline rbitfld.long 0x14 14. "PM_LINKST_IN_L2,Power Management In L2 State" "0: Not in L2,1: In L2" newline rbitfld.long 0x14 12. "PM_LINKST_IN_L1,Power Management In L1 State" "0: Not in L1,1: In L1" newline rbitfld.long 0x14 11. "PM_LINKST_IN_L0S,Power Management In L0s State" "0: Not in L0s,1: In L0s" newline rbitfld.long 0x14 8.--10. "PM_CURNT_STATE,PM Controller's Current Power State" "0: L0 and others,1: L0S,2: L1,3: L2,4: L3,?,?,?" newline rbitfld.long 0x14 4. "PM_STATUS,PME Status Mirror" "0,1" newline rbitfld.long 0x14 3. "PM_PME_EN,PME Enable Mirror" "0,1" newline rbitfld.long 0x14 0.--2. "PM_DSTATE,Current Power Management D-State" "0: D0,1: D1,2: D2,3: D3,4: Uninitialized,?,?,?" group.long 0x1070++0x13 line.long 0x0 "PE0_TX_MSG_HDR_1,PCIe Controller 0 Transmit Message Header 1" bitfld.long 0x0 29.--30. "MSG_HDR_FM,Format Field" "0,1,2,3" newline hexmask.long.byte 0x0 24.--28. 1. "MSG_HDR_TYPE,Type Field" newline bitfld.long 0x0 20.--22. "MSG_HDR_TC,Traffic Class" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "MSG_HDR_TD,TLP Digest (TD)" "0,1" newline bitfld.long 0x0 14. "MSG_HDR_EP,Poisoned TLP (EP)" "0,1" newline bitfld.long 0x0 12.--13. "MSG_HDR_ATTR,Attribute[1:0] Relaxing Ordering And No Snoop" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "MSG_HDR_LENGTH,Tied to 0." line.long 0x4 "PE0_TX_MSG_HDR_2,PCIe Controller 0 Transmit Message Header 2" hexmask.long.byte 0x4 24.--31. 1. "MSG_HDR_BYTE4,Requeser ID[15:8] Byte 4" newline hexmask.long.byte 0x4 16.--23. 1. "MSG_HDR_BYTE5,Requester ID[7:0] Byte 5" newline hexmask.long.byte 0x4 8.--15. 1. "MSG_HDR_BYTE6,Message Tag Byte 6" newline hexmask.long.byte 0x4 0.--7. 1. "MSG_HDR_BYTE7,Message Code Byte 7" line.long 0x8 "PE0_TX_MSG_HDR_3,PCIe Controller 0 Transmit Message Header 3" hexmask.long.byte 0x8 24.--31. 1. "MSG_HDR_BYTE8,Byte 8" newline hexmask.long.byte 0x8 16.--23. 1. "MSG_HDR_BYTE9,Byte 9" newline hexmask.long.byte 0x8 8.--15. 1. "MSG_HDR_BYTE10,Byte 10" newline hexmask.long.byte 0x8 0.--7. 1. "MSG_HDR_BYTE11,Byte 11" line.long 0xC "PE0_TX_MSG_HDR_4,PCIe controller 0 transmit message header 4" hexmask.long.byte 0xC 24.--31. 1. "MSG_HDR_BYTE12,Byte 12" newline hexmask.long.byte 0xC 16.--23. 1. "MSG_HDR_BYTE13,Byte 13" newline hexmask.long.byte 0xC 8.--15. 1. "MSG_HDR_BYTE14,Byte 14" newline hexmask.long.byte 0xC 0.--7. 1. "MSG_HDR_BYTE15,Byte 15" line.long 0x10 "PE0_TX_MSG_REQ,PCIe Controller 0 Transmit Message Request" bitfld.long 0x10 20. "UNLOCK_REQ,Unlock message" "0,1" newline bitfld.long 0x10 19. "PME_TURN_OFF_REQ,PME_Turn_Off Message Request" "0,1" newline bitfld.long 0x10 17. "VEN_MSG_REQ,Vendor-Defined Message Request" "0: Normal operation,1: Trigger a vendor-defined message request" newline hexmask.long.byte 0x10 0.--4. 1. "TX_MSG_PF_NUM,PF Number Of Message Requester" rgroup.long 0x1090++0xF line.long 0x0 "PE0_RX_MSG_HDR_1,PCIe Controller 0 Receive Message Header 1" hexmask.long.byte 0x0 24.--31. 1. "MSG_HDR_BYTE0,Byte 0" newline hexmask.long.byte 0x0 16.--23. 1. "MSG_HDR_BYTE1,Byte 1" newline hexmask.long.byte 0x0 8.--15. 1. "MSG_HDR_BYTE2,Byte 2" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_HDR_BYTE3,Byte 3" line.long 0x4 "PE0_RX_MSG_HDR_2,PCIe Controller 0 Receive Message Header 2" hexmask.long.byte 0x4 24.--31. 1. "MSG_HDR_BYTE4,Byte 4" newline hexmask.long.byte 0x4 16.--23. 1. "MSG_HDR_BYTE5,Byte 5" newline hexmask.long.byte 0x4 8.--15. 1. "MSG_HDR_BYTE6,Byte 6" newline hexmask.long.byte 0x4 0.--7. 1. "MSG_HDR_BYTE7,Byte 7" line.long 0x8 "PE0_RX_MSG_HDR_3,PCIe Controller 0 Receive Message Header 3" hexmask.long.byte 0x8 24.--31. 1. "MSG_HDR_BYTE8,Byte 8" newline hexmask.long.byte 0x8 16.--23. 1. "MSG_HDR_BYTE9,Byte 9" newline hexmask.long.byte 0x8 8.--15. 1. "MSG_HDR_BYTE10,Byte 10" newline hexmask.long.byte 0x8 0.--7. 1. "MSG_HDR_BYTE11,Byte 11" line.long 0xC "PE0_RX_MSG_HDR_4,PCIe Controller 0 Receive Message Header 4" hexmask.long.byte 0xC 24.--31. 1. "MSG_HDR_BYTE12,Byte 12" newline hexmask.long.byte 0xC 16.--23. 1. "MSG_HDR_BYTE13,Byte 13" newline hexmask.long.byte 0xC 8.--15. 1. "MSG_HDR_BYTE14,Byte 14" newline hexmask.long.byte 0xC 0.--7. 1. "MSG_HDR_BYTE15,Byte 15" group.long 0x10A0++0xB line.long 0x0 "PE0_RX_MSG_STS,PCIe Controller 0 Receive Message Status" eventfld.long 0x0 31. "MSGQ_OVERFLOW,Receive Message Queue Overflow Status" "0,1" newline eventfld.long 0x0 20. "UNLOCK_STS,Unlock Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 19. "PME_TURN_OFF_STS,PME_Turn_Off Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 18. "VDM_TYPE1_STS,Vendor-Defined Type 1 Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 17. "VDM_TYPE0_STS,Vendor-Defined Type 0 Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 12. "PM_PME_STS,PM_PME Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 11. "PME_TO_ACK_STS,PME_TO_Ack message status" "0: Not captured,1: Captured" line.long 0x4 "PE0_RX_MSG_CAP_CTRL,PCIe Controller 0 Receive Message Capture Control" bitfld.long 0x4 20. "CAP_UNLOCK,Capture Unlock message in received Message Header register." "0: Disable,1: Enable" newline bitfld.long 0x4 19. "CAP_PME_TURN_OFF,Capture PME_Turn_Off Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x4 18. "CAP_VDM_TYPE1,Capture Vendor-Defined Type 1 Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x4 17. "CAP_VDM_TYPE0,Capture Vendor-Defined Type 0 Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x4 12. "CAP_PM_PME,Capture PM_PME Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x4 11. "CAP_PME_TO_ACK,Capture PME_TO_Ack Message In Received Message Header Register" "0: Disable,1: Enable" line.long 0x8 "PE0_RX_MSG_INT_CTRL,PCIe Controller 0 Receive Message Interrupt Control" bitfld.long 0x8 31. "MSGQ_OVERFLOW_INT_EN,Interrupt Enable When Message Queue Overflows" "0: Disable,1: Enable" newline bitfld.long 0x8 20. "UNLOCK_INT_EN,Interrupt Enable When Unlock Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 19. "PME_TURN_OFF_INT_EN,Interrupt Enable When PME_Turn_Off Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 18. "VDM_TYPE1_INT_EN,Interrupt Enable When Vendor-Defined Type 1 Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 17. "VDM_TYPE0_INT_EN,Interrupt Enable When Vendor-Defined Type 0 Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 12. "PM_PME_INT_EN,Interrupt Enable When PM_PME Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "PME_TO_ACK_INT_EN,Interrupt Enable When PME_TO_Ack Message In Received Message Header Register" "0: Disable,1: Enable" rgroup.long 0x10B0++0x7 line.long 0x0 "PE0_LINK_DBG_1,PCIe Controller 0 Link Debug 1" bitfld.long 0x0 16.--17. "SYMBOL_LOCK,Symbol Lock" "0,1,2,3" newline bitfld.long 0x0 0.--1. "RECEIVER_DETECTED,Receiver Detected On Lanes" "0,1,2,3" line.long 0x4 "PE0_LINK_DBG_2,PCIe Controller 0 Link Debug 2" bitfld.long 0x4 24. "CDM_IN_RESET,CDM Register In Reset" "0: Not in reset or will not be reset,1: In reset or will be reset" newline bitfld.long 0x4 23. "BRDG_SLV_XFER_PENDING,AXI Slave Non-DBI Transfer Pending Status" "0: No pending request,1: Pending request exists" newline bitfld.long 0x4 22. "BRDG_DBI_XFER_PENDING,AXI Slave DBI Transfer Pending Status" "0: No pending request,1: Pending request exists" newline bitfld.long 0x4 21. "EDMA_XFER_PENDING,eDMA Transfer Pending Status" "0: No pending request,1: Pending request exists" newline bitfld.long 0x4 20. "RADM_XFER_PENDING,Receive Request Pending Status" "0: No pending request,1: Pending request exists" newline bitfld.long 0x4 16. "VC0_Q_NOT_EMPTY,VC0 Queue Not Empty" "0: Empty,1: Not empty" newline bitfld.long 0x4 10.--12. "PHY_POWRDOWN,PHY Power State" "0: P0 (L0): Normal,1: P0s (L0s): Low recovery time power saving,2: P1 (L1): Longer recovery time additional power..,3: P2 (L2): Lowest power state,?,?,?,?" newline bitfld.long 0x4 8.--9. "RATE,Link Signaling Rate" "0: 2.5 GT/s,1: 5.0 GT/s,2: 8.0 GT/s,3: 16.0 GT/s" newline bitfld.long 0x4 7. "RDLH_LINK_UP,Data Link Layer Up Or Down Indicator" "0,1" newline bitfld.long 0x4 6. "SMLH_LINK_UP,PHY Link Up Or Down Indicator" "0: Down,1: Up" newline hexmask.long.byte 0x4 0.--5. 1. "SMLH_LTSSM_STATE,LTSSM State" rgroup.long 0x10C0++0x7 line.long 0x0 "PE0_AXI_MSTR_DBG_1,PCIe Controller 0 AXI Master Debug 1" hexmask.long.byte 0x0 24.--31. 1. "MSTR_WR_ERR,AXI Master Write Response Error Counter" newline hexmask.long.byte 0x0 16.--23. 1. "MSTR_WR_REQ_PEND,AXI Master Write Pending Request Counter" newline hexmask.long.word 0x0 0.--15. 1. "MSTR_WR_REQ,AXI Master Write Request Counter" line.long 0x4 "PE0_AXI_MSTR_DBG_2,PCIe Controller 0 AXI Master Debug 2" hexmask.long.byte 0x4 24.--31. 1. "MSTR_RD_ERR,AXI Master Read Response Error Counter" newline hexmask.long.byte 0x4 16.--23. 1. "MSTR_RD_REQ_PEND,AXI Master Read Pending Request Counter" newline hexmask.long.word 0x4 0.--15. 1. "MSTR_RD_REQ,AXI Master Read Request Counter" rgroup.long 0x10D0++0x7 line.long 0x0 "PE0_AXI_SLV_DBG_1,PCIe Controller 0 AXI Slave Debug 1" hexmask.long.byte 0x0 24.--31. 1. "SLV_WR_ERR,AXI Slave Write Response Error Counter" newline hexmask.long.byte 0x0 16.--23. 1. "SLV_WR_REQ_PEND,AXI Slave Write Pending Request Counter" newline hexmask.long.word 0x0 0.--15. 1. "SLV_WR_REQ,AXI Slave Write Request Counter" line.long 0x4 "PE0_AXI_SLV_DBG_2,PCIe Controller 0 AXI Slave Debug 2" hexmask.long.byte 0x4 24.--31. 1. "SLV_RD_ERR,AXI Slave Read Response Error Counter" newline hexmask.long.byte 0x4 16.--23. 1. "SLV_RD_REQ_PEND,AXI Slave Read Pending Request Counter" newline hexmask.long.word 0x4 0.--15. 1. "SLV_RD_REQ,AXI Slave Read Request Counter" group.long 0x10E0++0x13 line.long 0x0 "PE0_ERR_STS,PCIe Controller 0 Error Status" eventfld.long 0x0 31. "APBSLV_TIMEOUT_STS,APB Slave Timeout Error" "0: No timeout error detected,1: Timeout error detected" newline eventfld.long 0x0 30. "LINK_DOWN_STS,Link Down Event" "0: No link down error detected,1: Link down error detected" newline eventfld.long 0x0 26. "RETRYSOTRAM_PARERR_STS,Retry SOT RAM Parity Error" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 25. "RETRYRAM_PARERR_STS,Retry RAM Parity Error" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 16. "VC_QOVERFLOW,RADM Queue Overflow Error" "0: No overflow error detected,1: Overflow error detected" newline eventfld.long 0x0 12. "P_DATAQ_PARERR_STS_0,Receive Data Queue 0 Parity Error" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 8. "P_HDRQ_PARERR_STS_0,Receive Header Queue 0 Parity Error" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 7. "RXDATA_PERR,Parity Error Receive Datapath" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 6. "TXDATA_PERR_BACK,Parity Error Back" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 5. "TXDATA_PERR_FRONT,Parity Error Front" "0: No parity error detected,1: Parity error detected" line.long 0x4 "PE0_ERR_INT_CTRL,PCIe Controller 0 Error Interrupt Control" bitfld.long 0x4 31. "APBSLV_TIMEOUT_INT_EN,Interrupt Enable For APB Slave Timeout Error" "0: Disable,1: Enable" newline bitfld.long 0x4 30. "LINK_DOWN_INT_EN,Interrupt Enable For Link Down Event" "0: Disable,1: Enable" newline bitfld.long 0x4 26. "RETRYSOTRAM_PARERR_INT_EN,Interrupt Enable For Retry SOT RAM Parity Error" "0: Disable,1: Enable" newline bitfld.long 0x4 25. "RETRYRAM_PARERR_INT_EN,Interrupt Enable For Retry RAM Parity Error" "0: Disable,1: Enable" newline bitfld.long 0x4 16. "VC_QOVERFLOW_INT_EN,Interrupt Enable For RADM Queue Overflow Error" "0: Disable,1: Enable" newline bitfld.long 0x4 12. "P_DATAQ_PARERR_INT_EN_0,Interrupt Enable For Receive Data Queue 0 Parity Error" "0: Disable,1: Enable" newline bitfld.long 0x4 8. "P_HDRQ_PARERR_INT_EN_0,Interrupt Enable For Receive Header Queue 0 Parity Error" "0: Disable,1: Enable" newline bitfld.long 0x4 7. "RXDATA_PERR_INT_EN,Interrupt Enable For Parity Error In The Receive Datapath" "0: Disable,1: Enable" newline bitfld.long 0x4 6. "TXDATA_PERR_BACK_INT_EN,Interrupt Enable For Parity Error At Back End Of The Transmit Datapath" "0: Disable,1: Enable" newline bitfld.long 0x4 5. "TXDATA_PERR_FRONT_INT_EN,Interrupt Enable For Parity Error At Front End Of The Transmit Datapath" "0: Disable,1: Enable" line.long 0x8 "PE0_INT_STS,PCIe Controller 0 Interrupt Status" eventfld.long 0x8 13. "BW_MGT_MSI_STS,Link Bandwidth Management MSI Status" "0: The conditions in the field description are not..,1: The conditions in the field description are met" newline eventfld.long 0x8 12. "LINK_AUTO_BW_MSI_STS,Link Autonomous Bandwidth MSI Status" "0: The conditions in the field description are not..,1: The conditions in the field description are met" newline eventfld.long 0x8 10. "LINK_EQ_REQ_INT_STS,Link Equalization Request Interrupt Status" "0: LINK_CONTROL2_LINK_STATUS2_REG[PCIE_CAP_LINK_EQ_REQ] = 0 or LINK_CONTROL3_REG[EQ_REQ_INT_EN] = 0..,1: LINK_CONTROL2_LINK_STATUS2_REG[PCIE_CAP_LINK_EQ_REQ] = LINK_CONTROL3_REG[EQ_REQ_INT_EN] = 1.." newline eventfld.long 0x8 9. "BW_MGT_INT_STS,Link Bandwidth Management Interrupt Status" "0: The conditions in the field description are not..,1: The conditions in the field description are met" newline eventfld.long 0x8 8. "LINK_AUTO_BW_INT_STS,Link Autonomous Bandwidth Interrupt Status" "0: The conditions in the field description are not..,1: The conditions in the field description are met" newline eventfld.long 0x8 7. "SYS_ERR_RC_STS,System Error Status" "0: No device reports any system error or the..,1: A device reports a system error and the.." newline eventfld.long 0x8 6. "HP_INT_STS,Hot-Plug Status" "0,1" newline eventfld.long 0x8 5. "PME_INT_STS,PME Interrupt Status" "0: ROOT_CONTROL_ROOT_CAPABILITIES_REG[PCIE_CAP_PME_INT_EN] = 0 or ROOT_STATUS_REG[PCIE_CAP_PME_STATUS] = 0..,1: ROOT_CONTROL_ROOT_CAPABILITIES_REG[PCIE_CAP_PME_INT_EN] = ROOT_STATUS_REG[PCIE_CAP_PME_STATUS] = 1.." newline eventfld.long 0x8 4. "AER_RC_ERR_INT_STS,Root Complex Advanced Error Reporting Status" "0: Fields in ROOT_ERR_STATUS_OFF are 0 or fields in..,1: A field in ROOT_ERR_STATUS_OFF is 1 and its.." newline rbitfld.long 0x8 2. "ERR_INT_STS,Internal Error Interrupt Status" "0,1" newline rbitfld.long 0x8 1. "RX_MSG_INT_STS,Receive Message Interrupt Status" "0,1" newline rbitfld.long 0x8 0. "BEACON_INT_STS,Beacon Interrupt Status" "0: Not detected,1: Detected" line.long 0xC "PE0_MSI_GEN_CTRL,PCIe Controller 0 MSI Generation Control" hexmask.long 0xC 0.--31. 1. "MSI_INT,MSI Vector" line.long 0x10 "PE0_FSM_TRACK_1,PCIe Controller 0 FSM Track 1" rbitfld.long 0x10 31. "EVENT_B_3,TS2 Status In FSM State 3" "0: Not received,1: Received" newline rbitfld.long 0x10 30. "EVENT_A_3,TS1 Status In FSM State 3" "0: Not received,1: Received" newline hexmask.long.byte 0x10 24.--29. 1. "FSM_3,FSM State 3" newline rbitfld.long 0x10 23. "EVENT_B_2,TS2 Status In FSM State 2" "0: Not received,1: Received" newline rbitfld.long 0x10 22. "EVENT_A_2,TS1 Status In FSM State 2" "0: Not received,1: Received" newline hexmask.long.byte 0x10 16.--21. 1. "FSM_2,FSM State 2" newline rbitfld.long 0x10 15. "EVENT_B_1,TS2 Status In FSM State 1" "0: Not received,1: Received" newline rbitfld.long 0x10 14. "EVENT_A_1,TS1 Status In FSM State 1" "0: Not received,1: Received" newline hexmask.long.byte 0x10 8.--13. 1. "FSM_1,FSM State 1" newline bitfld.long 0x10 6. "FSM_MON_EN,FSM Track Enable" "0: Disable,1: Enable" newline hexmask.long.byte 0x10 0.--5. 1. "FSM_TRIG,Trigger State Of FSM Track" rgroup.long 0x10F4++0x3 line.long 0x0 "PE0_FSM_TRACK_2,PCIe Controller 0 FSM Track 2" bitfld.long 0x0 31. "EVENT_B_7,TS2 Status In FSM State 7" "0: Not received,1: Received" newline bitfld.long 0x0 30. "EVENT_A_7,TS1 Status In FSM State 7" "0: Not received,1: Received" newline hexmask.long.byte 0x0 24.--29. 1. "FSM_7,FSM State 7" newline bitfld.long 0x0 23. "EVENT_B_6,TS2 Status In FSM State 6" "0: Not received,1: Received" newline bitfld.long 0x0 22. "EVENT_A_6,TS1 Status In FSM State 6" "0: Not received,1: Received" newline hexmask.long.byte 0x0 16.--21. 1. "FSM_6,FSM State 6" newline bitfld.long 0x0 15. "EVENT_B_5,TS2 Status In FSM State 5" "0: Not received,1: Received" newline bitfld.long 0x0 14. "EVENT_A_5,TS1 Status In FSM State 5" "0: Not received,1: Received" newline hexmask.long.byte 0x0 8.--13. 1. "FSM_5,FSM State 5" newline bitfld.long 0x0 7. "EVENT_B_4,TS2 Status In FSM State 4" "0: Not received,1: Received" newline bitfld.long 0x0 6. "EVENT_A_4,TS1 Status In FSM State 4" "0: Not received,1: Received" newline hexmask.long.byte 0x0 0.--5. 1. "FSM_4,FSM State 4" group.long 0x3000++0x3 line.long 0x0 "APB_BRIDGE_TO_CTRL,APB Bridge Timeout Control" hexmask.long.word 0x0 16.--31. 1. "APB_TIMER_LIMT,APB Watchdog Timeout Threshold (us)" newline bitfld.long 0x0 10. "APB_TIMEOUT_DIS,APB Timeout Control Disable" "0: Enable,1: Disable" newline hexmask.long.word 0x0 0.--9. 1. "APBCLK_FREQ,APB Clock Frequency (MHz)" group.long 0x3008++0xB line.long 0x0 "PHY_REG_ADDR,PHY Register Address" bitfld.long 0x0 31. "PHY_REG_EN,Indirect PHY Register Access Enable" "0: Disable,1: Enable" newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indirect PHY Register Access Address" line.long 0x4 "PHY_REG_DATA,PHY Register Data" hexmask.long.word 0x4 0.--15. 1. "DATA,Indirect PHY Register Access Data" line.long 0x8 "RST_CTRL,Reset Control" bitfld.long 0x8 1. "WARM_RST,Warm Reset Control" "0: Deassert,1: Assert" newline bitfld.long 0x8 0. "COLD_RST,Cold Reset Control" "0: Deassert,1: Assert" tree.end tree "SERDES_SS_PCIE_1" base ad:0x44180000 group.long 0x0++0xB line.long 0x0 "PCIE_PHY_GEN_CTRL,PCIe PHY General Control" rbitfld.long 0x0 25. "PHY_RTUNE_STS,Resistor Tune Status" "0: Tuning has not started or completed,1: Tuning completed" newline bitfld.long 0x0 24. "PHY_RTUNE_REQ,Resistor Tune Request" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 17. "REF_USE_PAD,Reference Is From External Pad" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 16. "REF_REPEAT_CLK_EN,Repeat Reference Clock Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 11. "RX1_TERM_ACDC,Receiver Termination Control For Rx1" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 10. "RX0_TERM_ACDC,Receiver Termination Control For Rx0" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 9. "RX_SRIS_MODE,SRIS Enable As Defined In PCIe ECN" "0: Disables,1: Enables" newline bitfld.long 0x0 2. "CR_PARA_CLK_DIV2_EN,CR Parallel Clock Divider Control" "0: Same as PHY ref_dig_fr_clk,1: Half of ref_dig_fr_clk" newline bitfld.long 0x0 0. "EXT_PCLK_REQ,pipeP_pclk Required By External Logic" "0: Driven to 0,1: Driven to 1" line.long 0x4 "PCIE_PHY_LPBK_CTRL,PCIe PHY Loopback Control" bitfld.long 0x4 3. "LANE1_RX2TX_PAR_LB_EN,Lane1 Parallel (RX To TX) Loopback Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x4 2. "LANE1_TX2RX_LOOPBK,Lane1 Analog Serial Loopback Control" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x4 1. "LANE0_RX2TX_PAR_LB_EN,Lane0 Parallel (RX to TX) Loopback Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x4 0. "LANE0_TX2RX_LOOPBK,Lane0 Analog Serial Loopback Control" "0: Driven to 0,1: Driven to 1" line.long 0x8 "PCIE_PHY_SRAM_CSR,PCIe PHY SRAM Control And Status" rbitfld.long 0x8 2. "SRAM_INIT_DONE,SRAM Initialization Done" "0: 0,1: 1" newline bitfld.long 0x8 1. "SRAM_EXT_LD_DONE,SRAM External Load Done" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x8 0. "SRAM_BYPASS,SRAM Bypass" "0: Driven to 0,1: Driven to 1" group.long 0x10++0x13 line.long 0x0 "PCIE_PHY_MPLLA_CTRL,PCIe PHY MPLLA Control" rbitfld.long 0x0 31. "MPLLA_STATE,MPLLA State Indicator" "0: 0,1: 1" newline rbitfld.long 0x0 30. "MPLL_STATE,MPLLA or MPLLB State Indicator" "0: phy0_mplla_state and phy0_mpllb_state are 0,1: phy0_mplla_state or phy0_mpllb_state is 1" newline bitfld.long 0x0 0. "MPLLA_FORCE_EN,MPLLA Force Enable" "0: Driven to 0,1: Driven to 1" line.long 0x4 "PCIE_PHY_MPLLB_CTRL,PCIe PHY MPLLB Control" rbitfld.long 0x4 31. "MPLLB_STATE,MPLLB State Indicator" "0: 0,1: 1" newline rbitfld.long 0x4 30. "MPLL_STATE,MPLLA or MPLLB State Indicator" "0: phy0_mplla_state and phy0_mpllb_state are 0,1: phy0_mplla_state or phy0_mpllb_state is 1" newline bitfld.long 0x4 0. "MPLLB_FORCE_EN,MPLLB Force Enable" "0: Driven to 0,1: Driven to 1" line.long 0x8 "PCIE_PHY_EXT_CTRL_SEL,PCIe PHY Setting External Control" bitfld.long 0x8 0. "EXT_PHY_CTRL_SEL,External Control Of PHY Setting" "0: Driven to 0,1: Driven to 1" line.long 0xC "PCIE_PHY_EXT_BS_CTRL,PCIe PHY Boundary Scan Control" bitfld.long 0xC 6. "EXT_BS_TX_LOWSWING,TX Boundary Scan Low Swing" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0xC 5. "EXT_BS_RX_BIGSWING,RX Boundary Scan Big Swing" "0: Driven to 0,1: Driven to 1" newline hexmask.long.byte 0xC 0.--4. 1. "EXT_BS_RX_LEVEL,ACJTAG Receiver Sensitivity Level Control" line.long 0x10 "PCIE_PHY_REF_CLK_CTRL,PCIe Reference Clock Control" bitfld.long 0x10 3.--5. "REF_RANGE,Input Reference Clock frequency Range" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 2. "REF_CLK_DIV2_EN,Input Reference Clock Divider Control" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x10 1. "REF_CLK_MPLLB_DIV2_EN,MPLLB Reference Clock Divider Control" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x10 0. "REF_CLK_MPLLA_DIV2_EN,MPLLA Reference Clock Divider Control" "0: Driven to 0,1: Driven to 1" group.long 0x30++0xB line.long 0x0 "PCIE_PHY_EXT_MPLLA_CTRL_1,PCIe PHY MPLLA Control 1" hexmask.long.byte 0x0 24.--31. 1. "EXT_MPLLA_DIV_MULTIPLIER,MPLLA Output Frequency Multiplier Control" newline bitfld.long 0x0 19. "EXT_MPLLA_DIV_CLK_EN,MPLLA Divide Clock Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 18. "EXT_MPLLA_DIV8_CLK_EN,MPLLA Divide by 8 Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 17. "EXT_MPLLA_DIV16P5_CLK_EN,MPLLA Divide by 16.5 Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 16. "EXT_MPLLA_DIV10_CLK_EN,MPLLA Divide by 10 Enable" "0: Driven to 0,1: Driven to 1" newline hexmask.long.word 0x0 0.--15. 1. "EXT_MPLLA_BANDWIDTH,MPLLA Bandwidth Control" line.long 0x4 "PCIE_PHY_EXT_MPLLA_CTRL_2,PCIe PHY MPLLA Control 2" hexmask.long.word 0x4 12.--22. 1. "EXT_MPLLA_FRACN_CTRL,MPLLA Fractional Control" newline hexmask.long.byte 0x4 0.--7. 1. "EXT_MPLLA_MULTIPLIER,MPLLA Frequency Multiplier Control" line.long 0x8 "PCIE_PHY_EXT_MPLLA_CTRL_3,PCIe PHY MPLLA Control 3" bitfld.long 0x8 31. "EXT_MPLLA_WORD_DIV2_EN,MPLLA Word Clock Divide by 2" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x8 28.--30. "EXT_MPLLA_TX_CLK_DIV,MPLLA Tx Clock Divide" "0,1,2,3,4,5,6,7" group.long 0x40++0xB line.long 0x0 "PCIE_PHY_EXT_MPLLB_CTRL_1,PCIe PHY MPLLB Control 1" hexmask.long.byte 0x0 24.--31. 1. "EXT_MPLLB_DIV_MULTIPLIER,MPLLB Output Frequency Multiplier Control" newline bitfld.long 0x0 19. "EXT_MPLLB_DIV_CLK_EN,MPLLB Divide Clock Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 18. "EXT_MPLLB_DIV8_CLK_EN,MPLLB Divide by 8 Enable" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x0 16. "EXT_MPLLB_DIV10_CLK_EN,MPLLB Divide by 10 Enable" "0: Driven to 0,1: Driven to 1" newline hexmask.long.word 0x0 0.--15. 1. "EXT_MPLLB_BANDWIDTH,MPLLB Bandwidth Control" line.long 0x4 "PCIE_PHY_EXT_MPLLB_CTRL_2,PCIe PHY MPLLB Control 2" hexmask.long.word 0x4 12.--22. 1. "EXT_MPLLB_FRACN_CTRL,MPLLB Fractional Control" newline hexmask.long.byte 0x4 0.--7. 1. "EXT_MPLLB_MULTIPLIER,MPLLB Frequency Multiplier Control" line.long 0x8 "PCIE_PHY_EXT_MPLLB_CTRL_3,PCIe PHY MPLLB Control 3" bitfld.long 0x8 31. "EXT_MPLLB_WORD_DIV2_EN,MPLLB Word Clock Divide by 2" "0: Driven to 0,1: Driven to 1" newline bitfld.long 0x8 28.--30. "EXT_MPLLB_TX_CLK_DIV,MPLLB Tx Clock Divide" "0,1,2,3,4,5,6,7" group.long 0x50++0xB line.long 0x0 "PCIE_PHY_EXT_RX_EQ_CTRL_1A,PCIe PHY RX Equalization Control 1 For Gen1 Speed" hexmask.long.byte 0x0 26.--31. 1. "EXT_RX_EQ_CTLE_POLE_G1,RX Equalization CTLE Pole" newline hexmask.long.word 0x0 16.--25. 1. "EXT_RX_EQ_CTLE_BOOST_G1,RX Equalization CTLE Boost" newline hexmask.long.byte 0x0 4.--9. 1. "EXT_RX_EQ_ATT_LVL_G1,RX Equalization Attenuation Level" newline bitfld.long 0x0 2.--3. "EXT_RX_ADAPT_DFE_EN_G1,RX DFE Enable" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EXT_RX_ADAPT_AFE_EN_G1,RX Adaptation Enable" "0,1,2,3" line.long 0x4 "PCIE_PHY_EXT_RX_EQ_CTRL_1B,PCIe PHY RX Equalization Control 2 For Gen1 Speed" hexmask.long.byte 0x4 24.--31. 1. "EXT_RX_EQ_VGA2_GAIN_G1,RX Equalization VGA Gain 2" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_RX_EQ_VGA1_GAIN_G1,RX Equalization VGA Gain 1" newline hexmask.long.word 0x4 0.--15. 1. "EXT_RX_EQ_DFE_TAP1_G1,RX Equalization DFE Tap1" line.long 0x8 "PCIE_PHY_EXT_RX_EQ_CTRL_1C,PCIe PHY RX Equalization Control 3 For Gen1 Speed" hexmask.long.byte 0x8 0.--7. 1. "EXT_RX_EQ_DELTA_IQ_G1,RX Equalization DELTA IQ" group.long 0x60++0xB line.long 0x0 "PCIE_PHY_EXT_RX_EQ_CTRL_2A,PCIe PHY RX Equalization Control 1 For Gen2 Speed" hexmask.long.byte 0x0 26.--31. 1. "EXT_RX_EQ_CTLE_POLE_G2,RX Equalization CTLE Pole" newline hexmask.long.word 0x0 16.--25. 1. "EXT_RX_EQ_CTLE_BOOST_G2,RX Equalization CTLE Boost" newline hexmask.long.byte 0x0 4.--9. 1. "EXT_RX_EQ_ATT_LVL_G2,RX Equalization Attenuation Level" newline bitfld.long 0x0 2.--3. "EXT_RX_ADAPT_DFE_EN_G2,RX DFE Enable" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EXT_RX_ADAPT_AFE_EN_G2,RX Adaptation Enable" "0,1,2,3" line.long 0x4 "PCIE_PHY_EXT_RX_EQ_CTRL_2B,PCIe PHY RX Equalization Control 2 For Gen2 Speed" hexmask.long.byte 0x4 24.--31. 1. "EXT_RX_EQ_VGA2_GAIN_G2,RX Equalization VGA Gain 2" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_RX_EQ_VGA1_GAIN_G2,RX Equalization VGA Gain 1" newline hexmask.long.word 0x4 0.--15. 1. "EXT_RX_EQ_DFE_TAP1_G2,RX Equalization DFE Tap1" line.long 0x8 "PCIE_PHY_EXT_RX_EQ_CTRL_2C,PCIe PHY RX Equalization Control 3 For Gen2 Speed" hexmask.long.byte 0x8 0.--7. 1. "EXT_RX_EQ_DELTA_IQ_G2,RX Equalization DELTA IQ" group.long 0x70++0xB line.long 0x0 "PCIE_PHY_EXT_RX_EQ_CTRL_3A,PCIe PHY RX Equalization Control 1 For Gen3 Speed" hexmask.long.byte 0x0 26.--31. 1. "EXT_RX_EQ_CTLE_POLE_G3,RX Equalization CTLE Pole" newline hexmask.long.word 0x0 16.--25. 1. "EXT_RX_EQ_CTLE_BOOST_G3,RX Equalization CTLE Boost" newline hexmask.long.byte 0x0 4.--9. 1. "EXT_RX_EQ_ATT_LVL_G3,RX Equalization Attenuation Level" newline bitfld.long 0x0 2.--3. "EXT_RX_ADAPT_DFE_EN_G3,RX DFE Enable" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EXT_RX_ADAPT_AFE_EN_G3,RX Adaptation Enable" "0,1,2,3" line.long 0x4 "PCIE_PHY_EXT_RX_EQ_CTRL_3B,PCIe PHY RX Equalization Control 2 For Gen3 Speed" hexmask.long.byte 0x4 24.--31. 1. "EXT_RX_EQ_VGA2_GAIN_G3,RX Equalization VGA Gain 2" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_RX_EQ_VGA1_GAIN_G3,RX Equalization VGA Gain 1" newline hexmask.long.word 0x4 0.--15. 1. "EXT_RX_EQ_DFE_TAP1_G3,RX Equalization DFE Tap1" line.long 0x8 "PCIE_PHY_EXT_RX_EQ_CTRL_3C,PCIe PHY RX Equalization Control 3 For Gen3 Speed" hexmask.long.byte 0x8 0.--7. 1. "EXT_RX_EQ_DELTA_IQ_G3,RX Equalization DELTA IQ" group.long 0x80++0xB line.long 0x0 "PCIE_PHY_EXT_RX_EQ_CTRL_4A,PCIe PHY RX Equalization Control 1 For Gen4 Speed" hexmask.long.byte 0x0 26.--31. 1. "EXT_RX_EQ_CTLE_POLE_G4,RX Equalization CTLE Pole" newline hexmask.long.word 0x0 16.--25. 1. "EXT_RX_EQ_CTLE_BOOST_G4,RX Equalization CTLE Boost" newline hexmask.long.byte 0x0 4.--9. 1. "EXT_RX_EQ_ATT_LVL_G4,RX Equalization Attenuation Level" newline bitfld.long 0x0 2.--3. "EXT_RX_ADAPT_DFE_EN_G4,RX DFE Enable" "0,1,2,3" newline bitfld.long 0x0 0.--1. "EXT_RX_ADAPT_AFE_EN_G4,RX Adaptation Enable" "0,1,2,3" line.long 0x4 "PCIE_PHY_EXT_RX_EQ_CTRL_4B,PCIe PHY RX Equalization Control 2 For Gen4 Speed" hexmask.long.byte 0x4 24.--31. 1. "EXT_RX_EQ_VGA2_GAIN_G4,RX Equalization VGA Gain 2" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_RX_EQ_VGA1_GAIN_G4,RX Equalization VGA Gain 1" newline hexmask.long.word 0x4 0.--15. 1. "EXT_RX_EQ_DFE_TAP1_G4,RX Equalization DFE Tap1" line.long 0x8 "PCIE_PHY_EXT_RX_EQ_CTRL_4C,PCIe PHY RX Equalization Control 3 For Gen4 Speed" hexmask.long.byte 0x8 0.--7. 1. "EXT_RX_EQ_DELTA_IQ_G4,RX Equalization DELTA IQ" group.long 0x90++0x17 line.long 0x0 "PCIE_PHY_EXT_CALI_CTRL_1,PCIe PHY Calibration Control For Gen1 Speed" hexmask.long.byte 0x0 16.--21. 1. "EXT_RX_REF_LD_VAL_G1,RX VCO Calibration Reference Load Value" newline hexmask.long.word 0x0 0.--12. 1. "EXT_RX_VCO_LD_VAL_G1,RX VCO Calibration Load Value" line.long 0x4 "PCIE_PHY_EXT_CALI_CTRL_2,PCIe PHY Calibration Control For Gen2 Speed" hexmask.long.byte 0x4 16.--21. 1. "EXT_RX_REF_LD_VAL_G2,RX VCO Calibration Reference Load Value" newline hexmask.long.word 0x4 0.--12. 1. "EXT_RX_VCO_LD_VAL_G2,RX VCO Calibration Load Value" line.long 0x8 "PCIE_PHY_EXT_CALI_CTRL_3,PCIe PHY Calibration Control For Gen3 Speed" hexmask.long.byte 0x8 16.--21. 1. "EXT_RX_REF_LD_VAL_G3,RX VCO Calibration Reference Load Value" newline hexmask.long.word 0x8 0.--12. 1. "EXT_RX_VCO_LD_VAL_G3,RX VCO Calibration Load Value" line.long 0xC "PCIE_PHY_EXT_CALI_CTRL_4,PCIe PHY Calibration Control For Gen4 Speed" hexmask.long.byte 0xC 16.--21. 1. "EXT_RX_REF_LD_VAL_G4,RX VCO Calibration Reference Load Value" newline hexmask.long.word 0xC 0.--12. 1. "EXT_RX_VCO_LD_VAL_G4,RX VCO Calibration Load Value" line.long 0x10 "PCIE_PHY_EXT_MISC_CTRL_1,PCIe PHY Miscellaneous Control 1" bitfld.long 0x10 29.--31. "EXT_RX_TERM_CTRL,RX Term Control" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--28. 1. "EXT_RX_VREF_CTRL,RX Biasing Current Control" newline hexmask.long.word 0x10 8.--18. 1. "EXT_RX_LOS_PWR_UP_CNT,Receiver LOS Power Up Counter" newline hexmask.long.byte 0x10 1.--6. 1. "EXT_RX_LOS_THRESHOLD,Receiver LOS Threshold" newline bitfld.long 0x10 0. "EXT_RX_LOS_LFPS_EN,Receiver LOS LFPS Enable" "0: Driven to 0,1: Driven to 1" line.long 0x14 "PCIE_PHY_EXT_MISC_CTRL_2,PCIe PHY Miscellaneous Control 2" bitfld.long 0x14 24.--26. "EXT_TX_TERM_CTRL,Tx Term Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 16.--18. "EXT_TX_VBOOST_LVL,TX Voltage Boost Maximum Level" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EXT_TX_IBOOST_LVL,Transmitter Current Boost Level" group.long 0xB0++0xB line.long 0x0 "PCIE_PHY_EXT_TX_EQ_CTRL_1,PCIe PHY TX Equalization Control For Gen1 Speed" bitfld.long 0x0 28.--29. "EXT_TX_EQ_OVRD_G1,TX Equalization Override Enable" "0,1,2,3" newline hexmask.long.word 0x0 16.--25. 1. "EXT_TX_EQ_MAIN_G1,TX Equalization Amplitude Adjustment Control" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_TX_EQ_PRE_G1,TX Equalization Pre-Emphasis Level Adjustment Control" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_TX_EQ_POST_G1,TX Equalization Post-Emphasis Level Adjustment Control" line.long 0x4 "PCIE_PHY_EXT_TX_EQ_CTRL_2,PCIe PHY TX Equalization Control For Gen2 Speed" bitfld.long 0x4 28.--29. "EXT_TX_EQ_OVRD_G2,TX Equalization Override Enable" "0,1,2,3" newline hexmask.long.word 0x4 16.--25. 1. "EXT_TX_EQ_MAIN_G2,TX Equalization Amplitude Adjustment Control" newline hexmask.long.byte 0x4 8.--15. 1. "EXT_TX_EQ_PRE_G2,TX Equalization Pre-Emphasis Level Adjustment Control" newline hexmask.long.byte 0x4 0.--7. 1. "EXT_TX_EQ_POST_G2,TX Equalization Post-Emphasis Level Adjustment Control" line.long 0x8 "PCIE_PHY_EXT_TX_EQ_CTRL_3,PCIe PHY TX Equalization Control For Gen3 Speed" bitfld.long 0x8 28.--29. "EXT_TX_EQ_OVRD_G3,TX Equalization Override Enable" "0,1,2,3" newline hexmask.long.word 0x8 16.--25. 1. "EXT_TX_EQ_MAIN_G3,TX Equalization Amplitude Adjustment Control" newline hexmask.long.byte 0x8 8.--15. 1. "EXT_TX_EQ_PRE_G3,TX Equalization Pre-Emphasis Level Adjustment Control" newline hexmask.long.byte 0x8 0.--7. 1. "EXT_TX_EQ_POST_G3,TX Equalization Post-Emphasis Level Adjustment Control" group.long 0xC0++0x3 line.long 0x0 "PCIE_PHY_XPCS0_RX_OVRD_CTRL,PCIe PHY XPCS_0 Rx Override Control" hexmask.long.word 0x0 16.--28. 1. "XPCS0_RX_VCO_LD_VAL,Override Control for xpcs0_rx0_vco_ld_val" newline hexmask.long.byte 0x0 8.--13. 1. "XPCS0_RX_REF_LD_VAL,Override Control For xpcs0_rx0_ref_ld_val" newline bitfld.long 0x0 0. "XPCS0_RX_OVRD,XPCS_0 RX Override Control" "0: Does not override,1: Overrides" group.long 0xD0++0x3 line.long 0x0 "PCIE_PHY_XPCS1_RX_OVRD_CTRL,PCIe PHY XPCS_1 Rx Override Control" hexmask.long.word 0x0 16.--28. 1. "XPCS1_RX_VCO_LD_VAL,Override Control for xpcs1_rx0_vco_ld_val" newline hexmask.long.byte 0x0 8.--13. 1. "XPCS1_RX_REF_LD_VAL,Override Control For xpcs1_rx0_ref_ld_val" newline bitfld.long 0x0 0. "XPCS1_RX_OVRD,XPCS_1 RX Override Control" "0: Does not override,1: Overrides" rgroup.long 0xE0++0xF line.long 0x0 "SS_RO_REG_0,Subsystem Read-Only Register 0" hexmask.long.byte 0x0 26.--31. 1. "MSTR_ARMISC_INFO_DMA,DMA Bits Of The AXI Read Master Transaction" newline bitfld.long 0x0 25. "PCS1_LINK_STATUS,XPCS_1 Receive Link Status" "0: Link down,1: Link up" newline bitfld.long 0x0 24. "PCS1_SGMII_FULL_DUPLEX,SGMII Full Duplex Of XPCS_1" "0: Half duplex,1: Full duplex" newline bitfld.long 0x0 23. "PCS1_SGMII_LINK_STS,SGMII Link Status Of XPCS_1" "0: Link down,1: Link up" newline bitfld.long 0x0 22. "PCS0_LINK_STATUS,XPCS_0 Receive Link Status" "0: Link down,1: Link up" newline bitfld.long 0x0 21. "PCS0_SGMII_FULL_DUPLEX,SGMII Full Duplex Of XPCS_0" "0: Half duplex,1: Full duplex" newline bitfld.long 0x0 20. "PCS0_SGMII_LINK_STS,SGMII Link Status Of XPCS_0" "0: Link down,1: Link up" newline bitfld.long 0x0 19. "CDM_REG_CHK_CMPLT,Register Checking Complete" "0: Not completed,1: Completed" newline bitfld.long 0x0 18. "CDM_REG_CHK_CMP_ERR,CDM Comparison Error" "0: The values are not matched.,1: The values are matched." newline bitfld.long 0x0 17. "CDM_REG_CHK_LOGIC_ERR,Error In Register-Checking Logic" "0: No error,1: Error" newline bitfld.long 0x0 15.--16. "PCS1_LINK_SPEED,SGMII MAC Speed Control" "0: 10 Mbps,1: 100 Mbps,2: 100 Mbps,?" newline bitfld.long 0x0 13.--14. "PCS0_LINK_SPEED,SGMII MAC Speed Control" "0: 10 Mbps,1: 100 Mbps,2: 1000 Mbps,?" newline hexmask.long.byte 0x0 5.--12. 1. "MSI_CTRL_INT_VEC,DSP AXI MSI Interrupt Vector" newline bitfld.long 0x0 4. "MSTR_ARMISC_INFO_LAST_DCMP_TLP,Last TLP Of The PCIe Controller's AXI Master Read Request" "0: The TLP in the transaction is not the last TLP..,1: The TLP in the transaction is the last TLP of.." newline bitfld.long 0x0 3. "MSTR_AWMISC_INFO_LAST_DCMP_TLP,Last TLP Of The PCIe controller's AXI Master Write Request" "0: The TLP in the transaction is not the last TLP..,1: The TLP in the transaction is the last TLP of.." newline bitfld.long 0x0 2. "PHY_RX1_LOS,Receive Loss Of Signal (LOS) Output 1" "0: The receiver has not lost the signal.,1: The receiver has lost the signal." newline bitfld.long 0x0 1. "PHY_RX0_LOS,Receive Loss Of Signal (LOS) Output 0" "0: The receiver has not lost the signal.,1: The receiver has lost the signal." line.long 0x4 "SS_RO_REG_1,Subsystem Read-Only Register 1" hexmask.long.word 0x4 17.--27. 1. "SLV_RMISC_INFO,Miscellaneous Read Information" newline hexmask.long.word 0x4 6.--16. 1. "SLV_BMISC_INFO,Miscellaneous Write Information" newline hexmask.long.byte 0x4 0.--5. 1. "MSTR_AWMISC_INFO_DMA,DMA Bits Of The AXI Write Master Transaction" line.long 0x8 "SS_RO_REG_2,Subsystem Read-Only Register 2" hexmask.long 0x8 0.--31. 1. "REG2,Subsystem Read Only Register 2" line.long 0xC "SS_RO_REG_3,Subsystem Read-Only Register 3" hexmask.long 0xC 0.--31. 1. "REG3,Subsystem Read Only Register 3" group.long 0xF0++0x17 line.long 0x0 "SS_RW_REG_0,Subsystem Read/Write Register 0" bitfld.long 0x0 31. "MSTR_RMISC_INFO,Miscellaneous Information Related To AXI Master Read-Response Transactions" "0: The controller operates normally.,1: The controller sets the Poisoned TLP (EP) bit in.." newline bitfld.long 0x0 30. "MDR,Memory Data Retention" "0: The subsystem retains data stored in memory and..,1: The subsystem does not retain data stored in.." newline bitfld.long 0x0 29. "PHY_TEST_TX_REF_CLK_EN,TX Reference Clock Output Enable" "0: Normal functional operation,1: The reference clock inputs (ref_pad_clk_{p m} or.." newline bitfld.long 0x0 27. "PHY_TEST_POWERDOWN,All Circuits Power-Down Control" "0: The PHY circuitry operates normally.,1: The PHY deactivates all its circuitry for IDDQ.." newline bitfld.long 0x0 25. "SLV_AWMISC_INFO_ATU_BYPASS,AXI Slave Write Request iATU Bypass" "0: The iATU must process this request.,1: The iATU must not process this request." newline bitfld.long 0x0 24. "SLV_ARMISC_INFO_ATU_BYPASS,AXI Slave Read Request iATU Bypass" "0: The iATU must process this request.,1: The iATU must not process this request." newline bitfld.long 0x0 23. "CLKEN,PCIe Reference Clock Enable" "0: External clock (phy0_ref_pad_clk_m..,1: Internal clock (PCIE_REF_CLK) is the reference.." newline hexmask.long.byte 0x0 15.--22. 1. "SLV_AWMISC_INFO_P_TAG,AXI Slave Write Request Tag" newline bitfld.long 0x0 14. "SLV_WMISC_INFO,Miscellaneous Information Related To AXI Slave Write-Data Transactions" "0: The controller operates normally.,1: The controller sets the Poisoned TLP (EP) bit in.." newline bitfld.long 0x0 12.--13. "MSTR_RMISC_INFO_CPL_STAT,AXI Master Read Response Selection Bus" "0: Successful completion,1: Completer abort,2: Unsupported request,3: Successful completion" newline bitfld.long 0x0 10.--11. "MSTR_BMISC_INFO_CPL_STAT,AXI Master Write Response Selection Bus" "0: Successful completion,1: Completer abort,2: Unsupported request,3: Successful completion" newline bitfld.long 0x0 9. "PHY0_CR_PARA_SEL,Control Register (CR) Parallel Interface Select" "0: Select the JTAG interface.,1: Select the CR interface." newline bitfld.long 0x0 7. "APP_XFER_PENDING,Application Transfer Pending" "0: No transactions exist outside the core,1: Transactions exist outside the core and the core.." newline bitfld.long 0x0 6. "SYS_INT,System Interrupt" "0,1" newline bitfld.long 0x0 5. "SYS_EML_INTERLOCK_ENGAGED,System Electromechanical Interlock Engaged" "0: Electromechanical interlock is not engaged,1: Electromechanical interlock is engaged" newline bitfld.long 0x0 4. "SYS_CMD_CPLED_INT,Command Completed Interrupt" "0: Command not completed,1: Command completed" newline bitfld.long 0x0 3. "SYS_ATTEN_BUTTON_PRESSED,Attention Button Pressed" "0,1" newline bitfld.long 0x0 0.--2. "SUBSYS_MODE,Subsystem Mode Selection" "0: PCIe Gen3x2 mode,1: PCIe Gen3x1 and SGMII 1G bifurcation mode (lane..,2: PCIe Gen3x1 and SGMII 1G bifurcation mode (lane..,3: Two SGMII 1G/2.5G bifurcation mode XPCS_0..,4: Two SGMII 1G/2.5G bifurcation mode XPCS_1..,?,?,?" line.long 0x4 "SS_RW_REG_1,Subsystem Read/Write Register 1" bitfld.long 0x4 7. "PARITY_MODE_SLV_RD_DATA,Parity Error Injection In AXI Slave Read Data Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 6. "PARITY_MODE_MSTR_WR_DATA,Parity Error Injection In AXI Master Write Data Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 5. "PARITY_MODE_MSTR_WR_ADDR,Parity Error Injection In AXI Master Write Address Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 4. "PARITY_MODE_MSTR_RD_ADDR,Parity Error Injection In AXI Master Read Address Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 3. "PARITY_MODE_SLV_WR_DATA,Parity Error Injection In AXI Slave Write Data Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 2. "PARITY_MODE_SLV_WR_ADDR,Parity Error Injection In AXI Slave Write Address Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 1. "PARITY_MODE_SLV_RD_ADDR,Parity Error Injection In AXI Slave Read Address Bus" "0: No error injected,1: Error injected" newline bitfld.long 0x4 0. "PARITY_MODE_MSTR_RD_DATA,Parity Error Injection In AXI Master Read Data Bus" "0: No error injected,1: Error injected" line.long 0x8 "SS_RW_REG_2,Subsystem Read/Write Register 2" hexmask.long.tbyte 0x8 0.--21. 1. "SLV_ARMISC_INFO,Miscellaneous Information Associated With The AXI Slave Read Transaction" line.long 0xC "SS_RW_REG_3,Subsystem Read/Write Register 3" hexmask.long.tbyte 0xC 0.--21. 1. "SLV_AWMISC_INFO,Miscellaneous Information Associated With The AXI Slave Write Transaction" line.long 0x10 "SS_RW_REG_4,Subsystem Read/Write Register 4" hexmask.long 0x10 0.--31. 1. "SLV_AWMISC_INFO_HDR_3DW,AXI Slave Third Header DWs" line.long 0x14 "SS_RW_REG_5,Subsystem Read/Write Register 5" hexmask.long 0x14 0.--31. 1. "SLV_AWMISC_INFO_HDR_4DW,AXI Slave Fourth Header DWs" rgroup.long 0x1000++0x3 line.long 0x0 "PCIE_SUBSYSTEM_VERSION,PCIe Subsystem Version" hexmask.long 0x0 0.--31. 1. "VERSION,PCIe Subsystem Version" group.long 0x1040++0x3 line.long 0x0 "LINK_INT_CTRL_STS,Link Interrupt Control And Status" rbitfld.long 0x0 6. "LTSSM_STATE_RCVRY_EQ,Recovery Equalization State Status" "0: Not in Recovery Equalization state,1: In Recovery Equalization state" newline bitfld.long 0x0 5. "PHY_LINK_UP_INT_EN,PHY Link Up Interrupt Enable Control" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "PHY_LINK_DOWN_INT_EN,PHY Link Down Interrupt Enable Control" "0: Disable,1: Enable" newline eventfld.long 0x0 2. "LINK_REQ_RST_NOT_CLR,Clear Link Request Reset Status" "0: Do not change LINK_REQ_RST_NOT_STS,1: Change LINK_REQ_RST_NOT_STS to 0" newline bitfld.long 0x0 1. "LINK_REQ_RST_NOT_INT_EN,Link Request Reset Interrupt Enable Control" "0: Disable,1: Enable" newline rbitfld.long 0x0 0. "LINK_REQ_RST_NOT_STS,Link Request Reset Status" "0: Not set,1: Set" group.long 0x1050++0x17 line.long 0x0 "PE0_GEN_CTRL_1,PCIe Controller 0 General Control 1" bitfld.long 0x0 30. "TX_LANE_FLIP_EN,Manual Lane Reversal For Transmit Lanes In C-PCIe Mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "RX_LANE_FLIP_EN,Manual Lane Reversal For Receive Lanes In C-PCIe Mode" "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "SRIS_MODE,SRIS Operation Mode" "0: Non-SRIS,1: SRIS" newline bitfld.long 0x0 4. "DEVICE_TYPE_OVERRIDE,Override Device Type" "0: You cannot override the device type.,1: You can override the device type." newline hexmask.long.byte 0x0 0.--3. 1. "DEVICE_TYPE,Device Type" line.long 0x4 "PE0_GEN_CTRL_2,PCIe Controller 0 General Control 2" bitfld.long 0x4 9. "SLV_ACLK_UNGATE,AXI Slave Clock Gating Control" "0: Gate,1: Do not gate" newline bitfld.long 0x4 8. "MSTR_ACLK_UNGATE,AXI Master Clock Gating Control" "0: Gate,1: Do not gate" line.long 0x8 "PE0_GEN_CTRL_3,PCIe Controller 0 General Control 3" bitfld.long 0x8 13.--15. "DIAG_CTRL_BUS,Diagnostic Control Bus" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3. "RAS_DES_SD_HOLD_LTSSM,Hold And Release LTSSM In Silicon Debug" "0: LTSSM not held in current state and might change..,1: LTSSM held in current state and does not change" newline bitfld.long 0x8 2. "HOT_RESET,Hot Reset" "?,1: Trigger a hot reset" newline bitfld.long 0x8 1. "CRS_EN,Configuration Request Retry Status (CRS) Enable" "0: PCIe controller does not complete incoming..,1: PCIe controller completes incoming configuration.." newline bitfld.long 0x8 0. "LTSSM_EN,LTSSM Enable" "0: Hold LTSSM in the Detect state until your..,1: Allow LTSSM to continue link establishment and.." line.long 0xC "PE0_GEN_CTRL_4,PCIe Controller 0 General Control 4" bitfld.long 0xC 31. "CRS_EN_CLR_MASK,CRS_EN Clear Mask" "0: CRS_EN does not change,1: CRS_EN goes to its reset value" newline bitfld.long 0xC 30. "LTSSM_EN_CLR_MASK,LTSSM_EN Clear Mask" "0: LTSSM_EN does not change,1: LTSSM_EN goes to its reset value" newline bitfld.long 0xC 28.--29. "CFG_RAS_DES_TBA_CTRL,Start And End Of Time-Based Analysis" "0: No actions,1: Start,2: End,?" line.long 0x10 "PE0_PM_CTRL,PCIe Controller 0 PM Control" bitfld.long 0x10 31. "BEACON_INT_EN,Beacon Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 21. "APP_CLK_PM_EN,Clock PM Feature Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 20. "APP_CLK_REQ,Wake Up Reference Clock" "0: No request to wake up,1: Explicit request to wake up" newline bitfld.long 0x10 19. "READY_ENTER_L23,Ready To Enter L23" "0: Not ready,1: Ready" newline bitfld.long 0x10 18. "EXIT_ASPM_L1,Request To Exit ASPM State L1" "0: No request to exit,1: Explicit request to exit" newline bitfld.long 0x10 17. "ENTER_ASPM_L1,Request To Enter ASPM State L1" "0: No request to enter,1: Explicit request to enter" newline bitfld.long 0x10 16. "PM_PME_REQ,PM_PME Message Request" "0,1" newline hexmask.long.byte 0x10 0.--4. 1. "PME_PF_INDEX,PF Index Of PM_PME Request And PM Status" line.long 0x14 "PE0_PM_STS,PCIe Controller 0 PM Status" eventfld.long 0x14 31. "BEACON_INT_STS,Beacon Interrupt Status" "0,1" newline rbitfld.long 0x14 15. "PM_LINKST_L2_EXIT,Power Management Is Exiting L2 State" "0: Not in L2 exit,1: In L2 exit" newline rbitfld.long 0x14 14. "PM_LINKST_IN_L2,Power Management In L2 State" "0: Not in L2,1: In L2" newline rbitfld.long 0x14 12. "PM_LINKST_IN_L1,Power Management In L1 State" "0: Not in L1,1: In L1" newline rbitfld.long 0x14 11. "PM_LINKST_IN_L0S,Power Management In L0s State" "0: Not in L0s,1: In L0s" newline rbitfld.long 0x14 8.--10. "PM_CURNT_STATE,PM Controller's Current Power State" "0: L0 and others,1: L0S,2: L1,3: L2,4: L3,?,?,?" newline rbitfld.long 0x14 4. "PM_STATUS,PME Status Mirror" "0,1" newline rbitfld.long 0x14 3. "PM_PME_EN,PME Enable Mirror" "0,1" newline rbitfld.long 0x14 0.--2. "PM_DSTATE,Current Power Management D-State" "0: D0,1: D1,2: D2,3: D3,4: Uninitialized,?,?,?" group.long 0x1070++0x13 line.long 0x0 "PE0_TX_MSG_HDR_1,PCIe Controller 0 Transmit Message Header 1" bitfld.long 0x0 29.--30. "MSG_HDR_FM,Format Field" "0,1,2,3" newline hexmask.long.byte 0x0 24.--28. 1. "MSG_HDR_TYPE,Type Field" newline bitfld.long 0x0 20.--22. "MSG_HDR_TC,Traffic Class" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "MSG_HDR_TD,TLP Digest (TD)" "0,1" newline bitfld.long 0x0 14. "MSG_HDR_EP,Poisoned TLP (EP)" "0,1" newline bitfld.long 0x0 12.--13. "MSG_HDR_ATTR,Attribute[1:0] Relaxing Ordering And No Snoop" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "MSG_HDR_LENGTH,Tied to 0." line.long 0x4 "PE0_TX_MSG_HDR_2,PCIe Controller 0 Transmit Message Header 2" hexmask.long.byte 0x4 24.--31. 1. "MSG_HDR_BYTE4,Requeser ID[15:8] Byte 4" newline hexmask.long.byte 0x4 16.--23. 1. "MSG_HDR_BYTE5,Requester ID[7:0] Byte 5" newline hexmask.long.byte 0x4 8.--15. 1. "MSG_HDR_BYTE6,Message Tag Byte 6" newline hexmask.long.byte 0x4 0.--7. 1. "MSG_HDR_BYTE7,Message Code Byte 7" line.long 0x8 "PE0_TX_MSG_HDR_3,PCIe Controller 0 Transmit Message Header 3" hexmask.long.byte 0x8 24.--31. 1. "MSG_HDR_BYTE8,Byte 8" newline hexmask.long.byte 0x8 16.--23. 1. "MSG_HDR_BYTE9,Byte 9" newline hexmask.long.byte 0x8 8.--15. 1. "MSG_HDR_BYTE10,Byte 10" newline hexmask.long.byte 0x8 0.--7. 1. "MSG_HDR_BYTE11,Byte 11" line.long 0xC "PE0_TX_MSG_HDR_4,PCIe controller 0 transmit message header 4" hexmask.long.byte 0xC 24.--31. 1. "MSG_HDR_BYTE12,Byte 12" newline hexmask.long.byte 0xC 16.--23. 1. "MSG_HDR_BYTE13,Byte 13" newline hexmask.long.byte 0xC 8.--15. 1. "MSG_HDR_BYTE14,Byte 14" newline hexmask.long.byte 0xC 0.--7. 1. "MSG_HDR_BYTE15,Byte 15" line.long 0x10 "PE0_TX_MSG_REQ,PCIe Controller 0 Transmit Message Request" bitfld.long 0x10 20. "UNLOCK_REQ,Unlock message" "0,1" newline bitfld.long 0x10 19. "PME_TURN_OFF_REQ,PME_Turn_Off Message Request" "0,1" newline bitfld.long 0x10 17. "VEN_MSG_REQ,Vendor-Defined Message Request" "0: Normal operation,1: Trigger a vendor-defined message request" newline hexmask.long.byte 0x10 0.--4. 1. "TX_MSG_PF_NUM,PF Number Of Message Requester" rgroup.long 0x1090++0xF line.long 0x0 "PE0_RX_MSG_HDR_1,PCIe Controller 0 Receive Message Header 1" hexmask.long.byte 0x0 24.--31. 1. "MSG_HDR_BYTE0,Byte 0" newline hexmask.long.byte 0x0 16.--23. 1. "MSG_HDR_BYTE1,Byte 1" newline hexmask.long.byte 0x0 8.--15. 1. "MSG_HDR_BYTE2,Byte 2" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_HDR_BYTE3,Byte 3" line.long 0x4 "PE0_RX_MSG_HDR_2,PCIe Controller 0 Receive Message Header 2" hexmask.long.byte 0x4 24.--31. 1. "MSG_HDR_BYTE4,Byte 4" newline hexmask.long.byte 0x4 16.--23. 1. "MSG_HDR_BYTE5,Byte 5" newline hexmask.long.byte 0x4 8.--15. 1. "MSG_HDR_BYTE6,Byte 6" newline hexmask.long.byte 0x4 0.--7. 1. "MSG_HDR_BYTE7,Byte 7" line.long 0x8 "PE0_RX_MSG_HDR_3,PCIe Controller 0 Receive Message Header 3" hexmask.long.byte 0x8 24.--31. 1. "MSG_HDR_BYTE8,Byte 8" newline hexmask.long.byte 0x8 16.--23. 1. "MSG_HDR_BYTE9,Byte 9" newline hexmask.long.byte 0x8 8.--15. 1. "MSG_HDR_BYTE10,Byte 10" newline hexmask.long.byte 0x8 0.--7. 1. "MSG_HDR_BYTE11,Byte 11" line.long 0xC "PE0_RX_MSG_HDR_4,PCIe Controller 0 Receive Message Header 4" hexmask.long.byte 0xC 24.--31. 1. "MSG_HDR_BYTE12,Byte 12" newline hexmask.long.byte 0xC 16.--23. 1. "MSG_HDR_BYTE13,Byte 13" newline hexmask.long.byte 0xC 8.--15. 1. "MSG_HDR_BYTE14,Byte 14" newline hexmask.long.byte 0xC 0.--7. 1. "MSG_HDR_BYTE15,Byte 15" group.long 0x10A0++0xB line.long 0x0 "PE0_RX_MSG_STS,PCIe Controller 0 Receive Message Status" eventfld.long 0x0 31. "MSGQ_OVERFLOW,Receive Message Queue Overflow Status" "0,1" newline eventfld.long 0x0 20. "UNLOCK_STS,Unlock Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 19. "PME_TURN_OFF_STS,PME_Turn_Off Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 18. "VDM_TYPE1_STS,Vendor-Defined Type 1 Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 17. "VDM_TYPE0_STS,Vendor-Defined Type 0 Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 12. "PM_PME_STS,PM_PME Message Status" "0: Not captured,1: Captured" newline eventfld.long 0x0 11. "PME_TO_ACK_STS,PME_TO_Ack message status" "0: Not captured,1: Captured" line.long 0x4 "PE0_RX_MSG_CAP_CTRL,PCIe Controller 0 Receive Message Capture Control" bitfld.long 0x4 20. "CAP_UNLOCK,Capture Unlock message in received Message Header register." "0: Disable,1: Enable" newline bitfld.long 0x4 19. "CAP_PME_TURN_OFF,Capture PME_Turn_Off Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x4 18. "CAP_VDM_TYPE1,Capture Vendor-Defined Type 1 Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x4 17. "CAP_VDM_TYPE0,Capture Vendor-Defined Type 0 Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x4 12. "CAP_PM_PME,Capture PM_PME Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x4 11. "CAP_PME_TO_ACK,Capture PME_TO_Ack Message In Received Message Header Register" "0: Disable,1: Enable" line.long 0x8 "PE0_RX_MSG_INT_CTRL,PCIe Controller 0 Receive Message Interrupt Control" bitfld.long 0x8 31. "MSGQ_OVERFLOW_INT_EN,Interrupt Enable When Message Queue Overflows" "0: Disable,1: Enable" newline bitfld.long 0x8 20. "UNLOCK_INT_EN,Interrupt Enable When Unlock Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 19. "PME_TURN_OFF_INT_EN,Interrupt Enable When PME_Turn_Off Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 18. "VDM_TYPE1_INT_EN,Interrupt Enable When Vendor-Defined Type 1 Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 17. "VDM_TYPE0_INT_EN,Interrupt Enable When Vendor-Defined Type 0 Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 12. "PM_PME_INT_EN,Interrupt Enable When PM_PME Message In Received Message Header Register" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "PME_TO_ACK_INT_EN,Interrupt Enable When PME_TO_Ack Message In Received Message Header Register" "0: Disable,1: Enable" rgroup.long 0x10B0++0x7 line.long 0x0 "PE0_LINK_DBG_1,PCIe Controller 0 Link Debug 1" bitfld.long 0x0 16.--17. "SYMBOL_LOCK,Symbol Lock" "0,1,2,3" newline bitfld.long 0x0 0.--1. "RECEIVER_DETECTED,Receiver Detected On Lanes" "0,1,2,3" line.long 0x4 "PE0_LINK_DBG_2,PCIe Controller 0 Link Debug 2" bitfld.long 0x4 24. "CDM_IN_RESET,CDM Register In Reset" "0: Not in reset or will not be reset,1: In reset or will be reset" newline bitfld.long 0x4 23. "BRDG_SLV_XFER_PENDING,AXI Slave Non-DBI Transfer Pending Status" "0: No pending request,1: Pending request exists" newline bitfld.long 0x4 22. "BRDG_DBI_XFER_PENDING,AXI Slave DBI Transfer Pending Status" "0: No pending request,1: Pending request exists" newline bitfld.long 0x4 21. "EDMA_XFER_PENDING,eDMA Transfer Pending Status" "0: No pending request,1: Pending request exists" newline bitfld.long 0x4 20. "RADM_XFER_PENDING,Receive Request Pending Status" "0: No pending request,1: Pending request exists" newline bitfld.long 0x4 16. "VC0_Q_NOT_EMPTY,VC0 Queue Not Empty" "0: Empty,1: Not empty" newline bitfld.long 0x4 10.--12. "PHY_POWRDOWN,PHY Power State" "0: P0 (L0): Normal,1: P0s (L0s): Low recovery time power saving,2: P1 (L1): Longer recovery time additional power..,3: P2 (L2): Lowest power state,?,?,?,?" newline bitfld.long 0x4 8.--9. "RATE,Link Signaling Rate" "0: 2.5 GT/s,1: 5.0 GT/s,2: 8.0 GT/s,3: 16.0 GT/s" newline bitfld.long 0x4 7. "RDLH_LINK_UP,Data Link Layer Up Or Down Indicator" "0,1" newline bitfld.long 0x4 6. "SMLH_LINK_UP,PHY Link Up Or Down Indicator" "0: Down,1: Up" newline hexmask.long.byte 0x4 0.--5. 1. "SMLH_LTSSM_STATE,LTSSM State" rgroup.long 0x10C0++0x7 line.long 0x0 "PE0_AXI_MSTR_DBG_1,PCIe Controller 0 AXI Master Debug 1" hexmask.long.byte 0x0 24.--31. 1. "MSTR_WR_ERR,AXI Master Write Response Error Counter" newline hexmask.long.byte 0x0 16.--23. 1. "MSTR_WR_REQ_PEND,AXI Master Write Pending Request Counter" newline hexmask.long.word 0x0 0.--15. 1. "MSTR_WR_REQ,AXI Master Write Request Counter" line.long 0x4 "PE0_AXI_MSTR_DBG_2,PCIe Controller 0 AXI Master Debug 2" hexmask.long.byte 0x4 24.--31. 1. "MSTR_RD_ERR,AXI Master Read Response Error Counter" newline hexmask.long.byte 0x4 16.--23. 1. "MSTR_RD_REQ_PEND,AXI Master Read Pending Request Counter" newline hexmask.long.word 0x4 0.--15. 1. "MSTR_RD_REQ,AXI Master Read Request Counter" rgroup.long 0x10D0++0x7 line.long 0x0 "PE0_AXI_SLV_DBG_1,PCIe Controller 0 AXI Slave Debug 1" hexmask.long.byte 0x0 24.--31. 1. "SLV_WR_ERR,AXI Slave Write Response Error Counter" newline hexmask.long.byte 0x0 16.--23. 1. "SLV_WR_REQ_PEND,AXI Slave Write Pending Request Counter" newline hexmask.long.word 0x0 0.--15. 1. "SLV_WR_REQ,AXI Slave Write Request Counter" line.long 0x4 "PE0_AXI_SLV_DBG_2,PCIe Controller 0 AXI Slave Debug 2" hexmask.long.byte 0x4 24.--31. 1. "SLV_RD_ERR,AXI Slave Read Response Error Counter" newline hexmask.long.byte 0x4 16.--23. 1. "SLV_RD_REQ_PEND,AXI Slave Read Pending Request Counter" newline hexmask.long.word 0x4 0.--15. 1. "SLV_RD_REQ,AXI Slave Read Request Counter" group.long 0x10E0++0x13 line.long 0x0 "PE0_ERR_STS,PCIe Controller 0 Error Status" eventfld.long 0x0 31. "APBSLV_TIMEOUT_STS,APB Slave Timeout Error" "0: No timeout error detected,1: Timeout error detected" newline eventfld.long 0x0 30. "LINK_DOWN_STS,Link Down Event" "0: No link down error detected,1: Link down error detected" newline eventfld.long 0x0 26. "RETRYSOTRAM_PARERR_STS,Retry SOT RAM Parity Error" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 25. "RETRYRAM_PARERR_STS,Retry RAM Parity Error" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 16. "VC_QOVERFLOW,RADM Queue Overflow Error" "0: No overflow error detected,1: Overflow error detected" newline eventfld.long 0x0 12. "P_DATAQ_PARERR_STS_0,Receive Data Queue 0 Parity Error" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 8. "P_HDRQ_PARERR_STS_0,Receive Header Queue 0 Parity Error" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 7. "RXDATA_PERR,Parity Error Receive Datapath" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 6. "TXDATA_PERR_BACK,Parity Error Back" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0x0 5. "TXDATA_PERR_FRONT,Parity Error Front" "0: No parity error detected,1: Parity error detected" line.long 0x4 "PE0_ERR_INT_CTRL,PCIe Controller 0 Error Interrupt Control" bitfld.long 0x4 31. "APBSLV_TIMEOUT_INT_EN,Interrupt Enable For APB Slave Timeout Error" "0: Disable,1: Enable" newline bitfld.long 0x4 30. "LINK_DOWN_INT_EN,Interrupt Enable For Link Down Event" "0: Disable,1: Enable" newline bitfld.long 0x4 26. "RETRYSOTRAM_PARERR_INT_EN,Interrupt Enable For Retry SOT RAM Parity Error" "0: Disable,1: Enable" newline bitfld.long 0x4 25. "RETRYRAM_PARERR_INT_EN,Interrupt Enable For Retry RAM Parity Error" "0: Disable,1: Enable" newline bitfld.long 0x4 16. "VC_QOVERFLOW_INT_EN,Interrupt Enable For RADM Queue Overflow Error" "0: Disable,1: Enable" newline bitfld.long 0x4 12. "P_DATAQ_PARERR_INT_EN_0,Interrupt Enable For Receive Data Queue 0 Parity Error" "0: Disable,1: Enable" newline bitfld.long 0x4 8. "P_HDRQ_PARERR_INT_EN_0,Interrupt Enable For Receive Header Queue 0 Parity Error" "0: Disable,1: Enable" newline bitfld.long 0x4 7. "RXDATA_PERR_INT_EN,Interrupt Enable For Parity Error In The Receive Datapath" "0: Disable,1: Enable" newline bitfld.long 0x4 6. "TXDATA_PERR_BACK_INT_EN,Interrupt Enable For Parity Error At Back End Of The Transmit Datapath" "0: Disable,1: Enable" newline bitfld.long 0x4 5. "TXDATA_PERR_FRONT_INT_EN,Interrupt Enable For Parity Error At Front End Of The Transmit Datapath" "0: Disable,1: Enable" line.long 0x8 "PE0_INT_STS,PCIe Controller 0 Interrupt Status" eventfld.long 0x8 13. "BW_MGT_MSI_STS,Link Bandwidth Management MSI Status" "0: The conditions in the field description are not..,1: The conditions in the field description are met" newline eventfld.long 0x8 12. "LINK_AUTO_BW_MSI_STS,Link Autonomous Bandwidth MSI Status" "0: The conditions in the field description are not..,1: The conditions in the field description are met" newline eventfld.long 0x8 10. "LINK_EQ_REQ_INT_STS,Link Equalization Request Interrupt Status" "0: LINK_CONTROL2_LINK_STATUS2_REG[PCIE_CAP_LINK_EQ_REQ] = 0 or LINK_CONTROL3_REG[EQ_REQ_INT_EN] = 0..,1: LINK_CONTROL2_LINK_STATUS2_REG[PCIE_CAP_LINK_EQ_REQ] = LINK_CONTROL3_REG[EQ_REQ_INT_EN] = 1.." newline eventfld.long 0x8 9. "BW_MGT_INT_STS,Link Bandwidth Management Interrupt Status" "0: The conditions in the field description are not..,1: The conditions in the field description are met" newline eventfld.long 0x8 8. "LINK_AUTO_BW_INT_STS,Link Autonomous Bandwidth Interrupt Status" "0: The conditions in the field description are not..,1: The conditions in the field description are met" newline eventfld.long 0x8 7. "SYS_ERR_RC_STS,System Error Status" "0: No device reports any system error or the..,1: A device reports a system error and the.." newline eventfld.long 0x8 6. "HP_INT_STS,Hot-Plug Status" "0,1" newline eventfld.long 0x8 5. "PME_INT_STS,PME Interrupt Status" "0: ROOT_CONTROL_ROOT_CAPABILITIES_REG[PCIE_CAP_PME_INT_EN] = 0 or ROOT_STATUS_REG[PCIE_CAP_PME_STATUS] = 0..,1: ROOT_CONTROL_ROOT_CAPABILITIES_REG[PCIE_CAP_PME_INT_EN] = ROOT_STATUS_REG[PCIE_CAP_PME_STATUS] = 1.." newline eventfld.long 0x8 4. "AER_RC_ERR_INT_STS,Root Complex Advanced Error Reporting Status" "0: Fields in ROOT_ERR_STATUS_OFF are 0 or fields in..,1: A field in ROOT_ERR_STATUS_OFF is 1 and its.." newline rbitfld.long 0x8 2. "ERR_INT_STS,Internal Error Interrupt Status" "0,1" newline rbitfld.long 0x8 1. "RX_MSG_INT_STS,Receive Message Interrupt Status" "0,1" newline rbitfld.long 0x8 0. "BEACON_INT_STS,Beacon Interrupt Status" "0: Not detected,1: Detected" line.long 0xC "PE0_MSI_GEN_CTRL,PCIe Controller 0 MSI Generation Control" hexmask.long 0xC 0.--31. 1. "MSI_INT,MSI Vector" line.long 0x10 "PE0_FSM_TRACK_1,PCIe Controller 0 FSM Track 1" rbitfld.long 0x10 31. "EVENT_B_3,TS2 Status In FSM State 3" "0: Not received,1: Received" newline rbitfld.long 0x10 30. "EVENT_A_3,TS1 Status In FSM State 3" "0: Not received,1: Received" newline hexmask.long.byte 0x10 24.--29. 1. "FSM_3,FSM State 3" newline rbitfld.long 0x10 23. "EVENT_B_2,TS2 Status In FSM State 2" "0: Not received,1: Received" newline rbitfld.long 0x10 22. "EVENT_A_2,TS1 Status In FSM State 2" "0: Not received,1: Received" newline hexmask.long.byte 0x10 16.--21. 1. "FSM_2,FSM State 2" newline rbitfld.long 0x10 15. "EVENT_B_1,TS2 Status In FSM State 1" "0: Not received,1: Received" newline rbitfld.long 0x10 14. "EVENT_A_1,TS1 Status In FSM State 1" "0: Not received,1: Received" newline hexmask.long.byte 0x10 8.--13. 1. "FSM_1,FSM State 1" newline bitfld.long 0x10 6. "FSM_MON_EN,FSM Track Enable" "0: Disable,1: Enable" newline hexmask.long.byte 0x10 0.--5. 1. "FSM_TRIG,Trigger State Of FSM Track" rgroup.long 0x10F4++0x3 line.long 0x0 "PE0_FSM_TRACK_2,PCIe Controller 0 FSM Track 2" bitfld.long 0x0 31. "EVENT_B_7,TS2 Status In FSM State 7" "0: Not received,1: Received" newline bitfld.long 0x0 30. "EVENT_A_7,TS1 Status In FSM State 7" "0: Not received,1: Received" newline hexmask.long.byte 0x0 24.--29. 1. "FSM_7,FSM State 7" newline bitfld.long 0x0 23. "EVENT_B_6,TS2 Status In FSM State 6" "0: Not received,1: Received" newline bitfld.long 0x0 22. "EVENT_A_6,TS1 Status In FSM State 6" "0: Not received,1: Received" newline hexmask.long.byte 0x0 16.--21. 1. "FSM_6,FSM State 6" newline bitfld.long 0x0 15. "EVENT_B_5,TS2 Status In FSM State 5" "0: Not received,1: Received" newline bitfld.long 0x0 14. "EVENT_A_5,TS1 Status In FSM State 5" "0: Not received,1: Received" newline hexmask.long.byte 0x0 8.--13. 1. "FSM_5,FSM State 5" newline bitfld.long 0x0 7. "EVENT_B_4,TS2 Status In FSM State 4" "0: Not received,1: Received" newline bitfld.long 0x0 6. "EVENT_A_4,TS1 Status In FSM State 4" "0: Not received,1: Received" newline hexmask.long.byte 0x0 0.--5. 1. "FSM_4,FSM State 4" group.long 0x3000++0x3 line.long 0x0 "APB_BRIDGE_TO_CTRL,APB Bridge Timeout Control" hexmask.long.word 0x0 16.--31. 1. "APB_TIMER_LIMT,APB Watchdog Timeout Threshold (us)" newline bitfld.long 0x0 10. "APB_TIMEOUT_DIS,APB Timeout Control Disable" "0: Enable,1: Disable" newline hexmask.long.word 0x0 0.--9. 1. "APBCLK_FREQ,APB Clock Frequency (MHz)" group.long 0x3008++0xB line.long 0x0 "PHY_REG_ADDR,PHY Register Address" bitfld.long 0x0 31. "PHY_REG_EN,Indirect PHY Register Access Enable" "0: Disable,1: Enable" newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indirect PHY Register Access Address" line.long 0x4 "PHY_REG_DATA,PHY Register Data" hexmask.long.word 0x4 0.--15. 1. "DATA,Indirect PHY Register Access Data" line.long 0x8 "RST_CTRL,Reset Control" bitfld.long 0x8 1. "WARM_RST,Warm Reset Control" "0: Deassert,1: Assert" newline bitfld.long 0x8 0. "COLD_RST,Cold Reset Control" "0: Deassert,1: Assert" tree.end tree "SERDES_XPCS_0" base ad:0x40482000 group.word 0x1F0000++0x1 line.word 0x0 "SR_MII_CTRL,SR MII MMD Control" bitfld.word 0x0 15. "RST,Soft reset (RW SC type)" "0,1" newline bitfld.word 0x0 14. "LBE,Loopback enable" "0,1" newline bitfld.word 0x0 13. "SS13,Speed selection (LSB)" "0,1" newline bitfld.word 0x0 12. "AN_ENABLE,Enable auto-negotiation" "0,1" newline bitfld.word 0x0 11. "LPM,Power-down mode" "0: Normal operation,1: The XPCS and the PHY enter Power-down mode. To.." newline bitfld.word 0x0 9. "RESTART_AN,Restart auto-negotiation (RW SC type)" "0,1" newline bitfld.word 0x0 8. "DUPLEX_MODE,Duplex mode" "0: Half duplex,1: Full duplex" newline bitfld.word 0x0 6. "SS6,Speed selection" "0,1" newline rbitfld.word 0x0 5. "SS5,Reserved" "0,1" rgroup.word 0x1F0001++0x5 line.word 0x0 "SR_MII_STS,SR MII MMD Status" bitfld.word 0x0 15. "ABL100T4,100BASE-T4 ability" "0,1" newline bitfld.word 0x0 14. "FD100ABL,100BASE-X full-duplex ability" "0,1" newline bitfld.word 0x0 13. "HD100ABL,100BASE-X half-duplex ability" "0,1" newline bitfld.word 0x0 12. "FD10ABL,10 Mbps full-duplex ability" "0,1" newline bitfld.word 0x0 11. "HD10ABL,10 Mbps half-duplex ability" "0,1" newline bitfld.word 0x0 10. "FD100T,100BASE-T2 full-duplex ability" "0,1" newline bitfld.word 0x0 9. "HD100T,100BASE-T2 half-duplex ability" "0,1" newline bitfld.word 0x0 8. "EXT_STS_ABL,Extended status information" "0: No extended status information is present at..,1: Extended Status information is present at.." newline bitfld.word 0x0 7. "UN_DIR_ABL,Unidirectional ability" "0: The XPCS is able to transmit GMII only when the..,1: The XPCS is able to transmit GMII irrespective.." newline bitfld.word 0x0 6. "MF_PRE_SUP,MF preamble suppression" "0: The XPCS does not accept the MDIO frames with..,1: The XPCS accepts the MDIO frames with preamble.." newline bitfld.word 0x0 5. "AN_CMPL,Auto-negotiation complete" "0: The AN process is not complete.,1: The AN process is complete." newline bitfld.word 0x0 4. "RF,Remote fault (RO LH type)" "0: The XPCS did not detect a remote fault.,1: The XPCS detected a remote fault." newline bitfld.word 0x0 3. "AN_ABL,Auto-negotiation ability" "0: The XPCS is unable to perform auto-negotiation.,1: The XPCS is able to perform auto-negotiation." newline bitfld.word 0x0 2. "LINK_STS,Link status (RO LL type)" "0: Link down,1: Link up" newline bitfld.word 0x0 0. "EXT_REG_CAP,Extended register capability" "0: Extended register capability does not exist,1: Extended Register capability exists" line.word 0x1 "SR_MII_DEV_ID1,SR MII MMD Device Identifier 1" hexmask.word 0x1 0.--15. 1. "VS_MII_DEV_OUI_3_18,Organizationally Unique Identifier[3:18]" line.word 0x2 "SR_MII_DEV_ID2,SR MII MMD Device Identifier 2" hexmask.word.byte 0x2 10.--15. 1. "VS_MMD_DEV_OUI_19_24,Organizationally unique identifier [19:24]" newline hexmask.word.byte 0x2 4.--9. 1. "VS_MMD_DEV_MMN_5_0,Model number" newline hexmask.word.byte 0x2 0.--3. 1. "VS_MMD_DEV_RN_3_0,Revision number" group.word 0x1F0004++0x1 line.word 0x0 "SR_MII_AN_ADV,SR MII MMD AN Advertisement" rbitfld.word 0x0 15. "NP,Next page" "0,1" newline bitfld.word 0x0 12.--13. "RF,Remote fault" "0: No error,1: Offline,2: Link failure,3: Auto-negotiation error" newline bitfld.word 0x0 7.--8. "PAUSE,Pause ability" "0: No pause,1: Asymmetric pause towards the link partner,2: Symmetric pause,3: Symmetric pause and asymmetric pause towards the.." newline bitfld.word 0x0 6. "HD,Half duplex" "0,1" newline bitfld.word 0x0 5. "FD,Full duplex" "0,1" rgroup.word 0x1F0005++0x3 line.word 0x0 "SR_MII_LP_BABL,SR MII MMD AN Link Partner Base Ability" bitfld.word 0x0 15. "LP_NP,Next page" "0,1" newline bitfld.word 0x0 14. "LP_ACK,ACK bit from the link partner" "0,1" newline bitfld.word 0x0 12.--13. "LP_RF,Remote fault" "0: No error,1: Offline,2: Link failure,3: Auto-negotiation error" newline bitfld.word 0x0 7.--8. "LP_PAUSE,Pause ability" "0: No pause,1: Asymmetric pause towards the link partner,2: Symmetric pause,3: Both symmetric pause and asymmetric pause.." newline bitfld.word 0x0 6. "LP_HD,Half duplex" "0,1" newline bitfld.word 0x0 5. "LP_FD,Full duplex" "0,1" line.word 0x1 "SR_MII_EXPN,SR MII MMD AN Expansion" bitfld.word 0x1 2. "LD_NP_ABL,Local device next page able" "0: The local device does not have the next-page..,1: The local device has the next-page ability" newline bitfld.word 0x1 1. "PG_RCVD,Page received (RO LH type)" "0: The local device did not receive a new page,1: The local device received a new page" rgroup.word 0x1F000F++0x1 line.word 0x0 "SR_MII_EXT_STS,SR MII MMD Extended Status" bitfld.word 0x0 15. "CAP_1G_X_FD,1000BASE-X full-duplex capable" "0: Not capable of 1000BASE-X full-duplex,1: Capable of 1000BASE-X full-duplex" newline bitfld.word 0x0 14. "CAP_1G_X_HD,1000BASE-X half-duplex capable" "0: Not capable of 1000BASE-X half-duplex,1: Capable of 1000BASE-X half-duplex" newline bitfld.word 0x0 13. "CAP_1G_T_FD,1000BASE-T full-duplex capable" "0: Not capable of 1000BASE-T full-duplex,1: Capable of 1000BASE-T full-duplex" newline bitfld.word 0x0 12. "CAP_1G_T_HD,1000BASE-T half-duplex capable" "0: Not capable of 1000BASE-T half-duplex,1: Capable of 1000BASE-T half-duplex" rgroup.word 0x1F0708++0x11 line.word 0x0 "SR_MII_TIME_SYNC_ABL,SR MII MMD Time Sync Capability" bitfld.word 0x0 1. "MII_TX_DLY_ABL,XPCS transmit path data delay information available" "0,1" newline bitfld.word 0x0 0. "MII_RX_DLY_ABL,XPCS receive path data delay information available" "0,1" line.word 0x1 "SR_MII_TIME_SYNC_TX_MAX_DLY_LWR,SR MII MMD Time Sync Tx Max Delay Lower" hexmask.word 0x1 0.--15. 1. "MII_TX_MAX_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS transmit path." line.word 0x2 "SR_MII_TIME_SYNC_TX_MAX_DLY_UPR,SR MII MMD Time Sync Tx Max Delay Upper" hexmask.word 0x2 0.--15. 1. "MII_TX_MAX_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS transmit path." line.word 0x3 "SR_MII_TIME_SYNC_TX_MIN_DLY_LWR,SR MII MMD Time Sync Tx Min Delay Lower" hexmask.word 0x3 0.--15. 1. "MII_TX_MIN_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS transmit path." line.word 0x4 "SR_MII_TIME_SYNC_TX_MIN_DLY_UPR,SR MII MMD Time Sync Tx Min Delay Upper" hexmask.word 0x4 0.--15. 1. "MII_TX_MIN_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS transmit path." line.word 0x5 "SR_MII_TIME_SYNC_RX_MAX_DLY_LWR,SR MII MMD Time Sync Rx Max Delay Lower" hexmask.word 0x5 0.--15. 1. "MII_RX_MAX_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS receive path." line.word 0x6 "SR_MII_TIME_SYNC_RX_MAX_DLY_UPR,SR MII MMD Time Sync Rx Max Delay Upper" hexmask.word 0x6 0.--15. 1. "MII_RX_MAX_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS receive path." line.word 0x7 "SR_MII_TIME_SYNC_RX_MIN_DLY_LWR,SR MII MMD Time Sync Rx Min Delay Lower" hexmask.word 0x7 0.--15. 1. "MII_RX_MIN_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS receive path." line.word 0x8 "SR_MII_TIME_SYNC_RX_MIN_DLY_UPR,SR MII MMD Time Sync Rx Min Delay Upper" hexmask.word 0x8 0.--15. 1. "MII_RX_MIN_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS receive path." group.word 0x1F8000++0x9 line.word 0x0 "VR_MII_DIG_CTRL1,VR MII MMD Digital Control 1" bitfld.word 0x0 15. "VR_RST,Vendor-specific soft reset (RW SC type)" "0,1" newline bitfld.word 0x0 14. "R2TLBE,Rx to Tx loopback enable" "0: Loopback path is disabled,1: Loopback path is enabled" newline rbitfld.word 0x0 13. "EN_VSMMD1,Enable vendor-specific MMD1" "0,1" newline bitfld.word 0x0 11. "PWRSV,Power save" "0: Normal operation,1: XPCS and the PHY enter the power-save mode" newline rbitfld.word 0x0 10. "CS_EN,Reserved" "0,1" newline bitfld.word 0x0 9. "MAC_AUTO_SW,Automatic Speed Mode Change after CL37 AN" "0,1" newline bitfld.word 0x0 8. "INIT,Datapath initialization control" "0,1" newline rbitfld.word 0x0 7. "MSK_RD_ERR,Mask running disparity error" "0,1" newline bitfld.word 0x0 6. "PRE_EMP,Pre-emption packet enable" "0,1" newline bitfld.word 0x0 4. "DTXLANED_0,Tx lane 0 disable" "0,1" newline bitfld.word 0x0 3. "CL37_TMR_OVR_RIDE,Override control for CL37 link timer" "0,1" newline bitfld.word 0x0 2. "EN_2_5G_MODE,Enable 2.5G GMII mode" "0,1" newline bitfld.word 0x0 1. "BYP_PWRUP,Bypass power-up sequence" "0: The XPCS waits for the MPLL Tx or Rx PLL status..,1: The XPCS bypasses the normal flow of the.." newline rbitfld.word 0x0 0. "PHY_MODE_CTRL,When SGMII_PHY_AN_AUTO_RESTART=Enabled or QSGMII_PHY_AN_AUTO_RESTART=Enabled: PHY mode control" "0: SGMII/QSGMII(Port0) autonegotiation advertises..,1: XPCS advertises the values of input ports.." line.word 0x1 "VR_MII_AN_CTRL,VR MII MMD AN Control" bitfld.word 0x1 8. "MII_CTRL,MII Control This bit controls the width of the MAC interface when operating at SGMII/QSGMII/USXGMII speed modes of 10 Mbps or 100 Mbps - 0: 4-bit MII - 1: 8-bit MII This bit also controls the xpcs_mii_ctrl_o signal which is used for external.." "0: 4-bit MII,1: 8-bit MII This bit also controls the.." newline bitfld.word 0x1 4. "SGMII_LINK_STS,SGMII Link Status/ USXGMII Link Status /QSGMII Port0 Link Status" "0,1" newline bitfld.word 0x1 3. "TX_CONFIG,Transmit configuration" "0: Configures the XPCS as the MAC side..,1: Configures the XPCS as the PHY side.." newline bitfld.word 0x1 1.--2. "PCS_MODE,PCS mode" "0: 1000BASE-X mode (clause 37 auto-negotiation is..,?,2: SGMII mode (clause 37 auto-negotiation is as per..,3: QSGMII mode (clause 37 auto-negotiation conforms.." newline bitfld.word 0x1 0. "MII_AN_INTR_EN,Clause 37 AN complete interrupt enable" "0: The Clause 37 auto-negotiation complete..,1: The Clause 37 auto-negotiation complete.." line.word 0x2 "VR_MII_AN_INTR_STS,VR MII MMD AN Interrupt And Status" hexmask.word.byte 0x2 8.--14. 1. "USXG_AN_STS,Reserved" newline rbitfld.word 0x2 6. "LP_CK_STP,Link Partner EEE Clock Stop Capability This field indicates the EEE clock stop capability (or clock-stop enabe - in case far-end is acting as QSGMII MAC) advertised by the far-end device. This field is valid only when PCS_MODE[1:0] is set to.." "0,1" newline rbitfld.word 0x2 5. "LP_EEE_CAP,Link Partner EEE Capability This field indicates the EEE capability advertised by the far-end device (Port 0 QSGMII PHY). This field is valid only when PCS_MODE[1:0] is set to the QSGMII mode and the auto-negotiation is complete along port 0." "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "CL37_ANSGM_STS,Clause 37 AN SGMII Status/QSGMII Port 0 Status This field is valid only when the PCS_MODE[1:0] is set to the SGMII/QSGMII mode and the auto-negotiation is complete. It indicates the status received from remote link after the SGMII/QSGMII.." newline bitfld.word 0x2 0. "CL37_ANCMPLT_INTR,Clause 37 AN Complete Interrupt (SS WC Type) The XPCS sets this bit when Clause 37 auto-negotiation is complete. The host must clear this bit by writing 0 to it." "0,1" line.word 0x3 "VR_MII_TC,VR MII MMD Test Control" bitfld.word 0x3 2. "TPE,Test Pattern Enable Lanes" "0,1" newline bitfld.word 0x3 0.--1. "TP,Test Pattern Select" "0,1,2,3" line.word 0x5 "VR_MII_DBG_CTRL,VR MII MMD Debug Control" bitfld.word 0x5 6. "RX_DT_EN_CTL,Rx Data Enable Control" "0,1" newline rbitfld.word 0x5 5. "SUPRESS_EEE_LOS_DET,Reserved" "0,1" newline bitfld.word 0x5 4. "SUPRESS_LOS_DET,Suppress Loss of Signal Detection" "0,1" newline bitfld.word 0x5 0. "RESTAR_SYNC_0,Restart Synchronization" "0,1" group.word 0x1F800A++0x1 line.word 0x0 "VR_MII_LINK_TIMER_CTRL,VR MII MMD Link Timer Control" hexmask.word 0x0 0.--15. 1. "CL37_LINK_TIME,Programmable Link Timer Value for Clause 37 autonegotiation. This field can be programmed to any desired value if application wishes to over-ride the standard specified values for Link Timer used during Clause 37 Auto negotiation. Link.." rgroup.word 0x1F8010++0x3 line.word 0x0 "VR_MII_DIG_STS,VR MII MMD Digital Status" bitfld.word 0x0 13.--15. "LTX_STATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "LRX_STATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "RXFIFO_OVF,Rx FIFO Overflow (RO LH Type) This bit indicates the clock rate compensation FIFO overflow. - 0: Normal operation - 1: FIFO overflow" "0: Normal operation,1: FIFO overflow" newline bitfld.word 0x0 5. "RXFIFO_UNDF,Rx FIFO Underflow (RO LH Type) This bit indicates the clock rate compensation FIFO underflow. - 0: Normal operation - 1: FIFO underflow" "0: Normal operation,1: FIFO underflow" newline bitfld.word 0x0 2.--4. "PSEQ_STATE,Power Up Sequence State" "0: Wait for ACK High 0,1: Wait for ACK Low 0,2: Wait for ACK High 1,3: Wait for ACK Low 1,4: Tx/Rx stable (Power_Good state),5: Power Save state,6: Power Down state,?" newline bitfld.word 0x0 1. "LB_ACTIVE,Reserved" "0,1" line.word 0x1 "VR_MII_ICG_ERRCNT1,VR MII MMD Invalid Code Group Error Count 1" hexmask.word.byte 0x1 0.--7. 1. "EC0,Invalid Code Group Count Lane 0 (RO LH Type) This field gives the invalid code group count in Lane 0 when Bit 4 of VR MII MMD Digital Error Count Select Register is set to 1." group.word 0x1F8012++0x1 line.word 0x0 "VR_MII_DIG_ERRCNT_SEL,VR MII MMD Digital Error Count Select" bitfld.word 0x0 4. "INV_EC_EN,Invalid Code Group Error Counter Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 0. "COR,Clear on Read" "0: Normal operation,1: Clear any error counter that is read" group.word 0x1F8015++0x1 line.word 0x0 "VR_MII_GPIO,VR MII MMD GPIO" hexmask.word.byte 0x0 8.--15. 1. "GPIO_OUT,GPIO Output The content written on this field is driven to the xpcs_gpo_o[7:0] output port. Dependency: This field is valid only when GPIO_EN = Enabled." newline hexmask.word.byte 0x0 0.--7. 1. "GPIO_IN,GPIO Input This field indicates the content of the xpcs_gpo_i[7:0] port. Dependency: This field is valid only when GPIO_EN = Enabled." rgroup.word 0x1F8018++0x1 line.word 0x0 "VR_MII_MISC_STS,VR MII MMD Miscellaneous Status" hexmask.word.byte 0x0 0.--3. 1. "BIT_SFT,Bit Shift This field indicates the number of bit-shifts carried-out by comma-detect logic so as to align the incoming 10-bit XGXS Rx data Default Value: The default value of this field can be any value depending on the status of comma-detect.." rgroup.word 0x1F8020++0x1 line.word 0x0 "VR_MII_RX_LSTS,VR MII PHY Rx Lane Status" bitfld.word 0x0 13.--15. "RX_VALID_3_1,DPLL Lock Status for Lanes[3:1]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "RX_VALID_0,DPLL Lock Status for Lane 0" "0,1" newline bitfld.word 0x0 9.--11. "RX_PLL_STATE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "RX_PLL_STATE_0,Reserved" "0,1" newline bitfld.word 0x0 5.--7. "SIG_DET_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "SIG_DET_0,Rx Signal Detect for Lane 0" "0,1" group.word 0x1F8030++0xF line.word 0x0 "VR_MII_Gen5_12G_16G_TX_GENCTRL0,VR MII PHY Tx General Control 0" rbitfld.word 0x0 13.--15. "TX_DT_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "TX_DT_EN_0,Tx Data Enable on PHY lane 0" "0,1" newline rbitfld.word 0x0 9.--11. "TX_RST_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "TX_RST_0,Tx Reset on PHY lane 0" "0,1" newline rbitfld.word 0x0 5.--7. "TX_INV_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "TX_INV_0,Tx Invert on PHY lane 0" "0,1" newline rbitfld.word 0x0 1.--3. "TXBCN_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TXBCN_EN_0,Tx Beaconing Enable on PHY lane 0" "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_TX_GENCTRL1,VR MII PHY Tx General Control 1" rbitfld.word 0x1 13.--15. "TX_CLK_RDY_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 12. "TX_CLK_RDY_0,Transmitter Input clock ready on lane 0" "0,1" newline bitfld.word 0x1 8.--10. "VBOOST_LVL,Tx Voltage Boost Maximum Level" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x1 5.--7. "VBOOST_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "VBOOST_EN_0,Tx voltage Boost Enable on PHY lane 0" "0,1" newline rbitfld.word 0x1 1.--3. "DET_RX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "DET_RX_REQ_0,Transmitter Rx-Detection request on PHY lane 0." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_TX_GENCTRL2,VR MII PHY Tx General Control 2" rbitfld.word 0x2 14.--15. "TX3_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 12.--13. "TX2_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 10.--11. "TX1_WIDTH,Reserved" "0,1,2,3" newline bitfld.word 0x2 8.--9. "TX0_WIDTH,Tx Datapath Width on lane 0 of the PHY This field controls the width of input transmit data on lane 0. The encoding of the width is as follows : - 2'b00 : 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit This field drives the output port.." "0: 8-bit,1: 10-bit,2: 16-bit,3: 20-bit This field drives the output port.." newline rbitfld.word 0x2 5.--7. "TX_LPD_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "TX_LPD_0,Transmitter Lane Power Down on PHY lane 0. This field drives the output 'xpcs_tx_lpd_o[3:1]'. This field can be asserted to put the phy transmitter to a power state equivalent to that of P1." "0,1" newline rbitfld.word 0x2 1.--3. "TX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 0. "TX_REQ_0,Transmitter operation request on PHY lane 0 (RW SC Type)" "0,1" line.word 0x3 "VR_MII_Gen5_12G_16G_TX_BOOST_CTRL,VR MII PHY Tx Boost Control" hexmask.word.byte 0x3 12.--15. 1. "TX3_IBOOST,Reserved" newline hexmask.word.byte 0x3 8.--11. 1. "TX2_IBOOST,Reserved" newline hexmask.word.byte 0x3 4.--7. 1. "TX1_IBOOST,Reserved" newline hexmask.word.byte 0x3 0.--3. 1. "TX0_IBOOST,Tx current boost level on lane 0 of the PHY. This bit drives the output port xpcs_tx0_iboost_lvl_o[3:0]." line.word 0x4 "VR_MII_Gen5_12G_16G_TX_RATE_CTRL,VR MII PHY Tx Rate Control" rbitfld.word 0x4 12.--14. "TX3_RATE,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x4 8.--10. "TX2_RATE,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x4 4.--6. "TX1_RATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x4 0.--2. "TX0_RATE,Tx date rate on PHY lane 0." "0,1,2,3,4,5,6,7" line.word 0x5 "VR_MII_Gen5_12G_16G_TX_POWER_STATE_CTRL,VR MII PHY Tx Power State" rbitfld.word 0x5 9.--11. "TX_DISABLE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x5 8. "TX_DISABLE_0,Transmitter Disable on lane 0 This field drives the output port 'xpcs_tx_disable_o[0]'." "0,1" newline rbitfld.word 0x5 6.--7. "TX3_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 4.--5. "TX2_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 2.--3. "TX1_PSTATE,Reserved" "0,1,2,3" newline bitfld.word 0x5 0.--1. "TX0_PSTATE,Tx power state control for PHY lane 0." "0,1,2,3" line.word 0x6 "VR_MII_Gen5_12G_16G_TX_EQ_CTRL0,VR MII PHY Tx Equalization Control 0" hexmask.word.byte 0x6 8.--13. 1. "TX_EQ_MAIN,Control for setting Tx driver output amplitude" newline hexmask.word.byte 0x6 0.--5. 1. "TX_EQ_PRE,Tx Pre-Emphasis level adjustment Control" line.word 0x7 "VR_MII_Gen5_12G_16G_TX_EQ_CTRL1,VR MII PHY Tx Equalization Control 1" rbitfld.word 0x7 8. "CA_TX_EQ,Reserved" "0,1" newline rbitfld.word 0x7 7. "TX_EQ_DEF_CTRL,Reserved" "0,1" newline rbitfld.word 0x7 6. "TX_EQ_OVR_RIDE,Reserved" "0,1" newline hexmask.word.byte 0x7 0.--5. 1. "TX_EQ_POST,Tx Post-Emphasis level adjustment Control This field controls the transmitter driver output pre-emphasis (pre-shoot coefficient). This field drives the output port 'rpcs_ktx_post_o' if 'TX_EQ_OVR_RIDE' bit is set or in configurations with.." group.word 0x1F803C++0x1 line.word 0x0 "VR_MII_Consumer_10G_TX_TERM_CTRL,VR MII PHY Transmit Termination Control" bitfld.word 0x0 0.--2. "TX0_TERM,Transmit Termination Control for lane 0" "0,1,2,3,4,5,6,7" rgroup.word 0x1F8040++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_TX_STS,VR MII PHY Tx Status" bitfld.word 0x0 5.--7. "DETRX_RSLT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "DETRX_RSLT_0,Receiver Detection Result on PHY lane 0. This field captures the value of the input port 'xpcs_tx_detrx_result_o[0]'. The value of this field is valid when 'TX_ACK_0' is high. - 1'b0: Receiver not detected - 1'b1: Receiver detected" "0: Receiver not detected,1: Receiver detected" newline bitfld.word 0x0 1.--3. "TX_ACK_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TX_ACK_0,Tx Acknowledge on PHY lane 0. This bit captures the value of the input port 'xpcs_tx_ack_i[0]'. Whenever this bit is read as high it indicates that the requested transmitter setting is complete or the requested RX-detection operation is.." "0,1" group.word 0x1F8050++0x11 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_GENCTRL0,VR MII PHY Rx General Control 0" rbitfld.word 0x0 13.--15. "RX_CLKSFT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "RX_CLKSFT_0,Rx clock shift on PHY lane 0. When this bit is set a 1-bit shift of receive data happens relate to receive clock. This operation works only if alignment enable is disabled. This bit drives the output port 'xpcs_rx_clk_shift_o[0]'." "0,1" newline rbitfld.word 0x0 9.--11. "RX_DT_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "RX_DT_EN_0,Rx Data Enable on PHY lane 0. This bit should be set to enable the PHY receiver data output on lane 0. This bit drives the output port 'xgxs_rx_data_en_o[0]'." "0,1" newline rbitfld.word 0x0 5.--7. "RX_ALIGN_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "RX_ALIGN_EN_0,Rx Data Alignment Enable on PHY lane 0. This bit can be set to enable word alignment (based on k28.5 character) in the PHY. This field drives the output port 'xgxs_rx_align_en_o[0]'." "0,1" newline rbitfld.word 0x0 1.--3. "RX_TERM_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "RX_TERM_EN_0,Rx Termination Enable on PHY lane 0. When this bit is set PHY Rx is terminated with a nominal 50 ohm resistance. Otherwise the termination is in high impedance. This field drives the output port 'xpcs_rx_term_en_o[0]'." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_RX_GENCTRL1,VR MII PHY Rx General Control 1" rbitfld.word 0x1 9.--11. "RX_TERM_ACDC_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 8. "RX_TERM_ACDC_0,Rx Termination control on PHY lane 0. - 0: DC Termination (Floating Rx) - 1: AC Termination (Grounded Rx) This field drives the output port xpcs_rx_term_acdc_o[0]." "0: DC Termination,1: AC Termination" newline rbitfld.word 0x1 5.--7. "RX_RST_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "RX_RST_0,Rx reset on PHY lane 0. When this bit is set RX data path all the receiver settings and state machines of the PHY are reset This field drives the output port xgxs_rx_reset_o[0] when XPCS is in POWER_GOOD state." "0,1" newline rbitfld.word 0x1 1.--3. "RX_INV_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "RX_INV_0,Rx Data Invert on PHY lane 0. When this bit is set the data on PHY Rx serial lines are logically inverted. This signal drives the output port xgxs_rx_invert_o[0]." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_RX_GENCTRL2,VR MII PHY Rx General Control 2" rbitfld.word 0x2 14.--15. "RX3_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 12.--13. "RX2_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 10.--11. "RX1_WIDTH,Reserved" "0,1,2,3" newline bitfld.word 0x2 8.--9. "RX0_WIDTH,Rx Datapath Width on lane 0 of the PHY This field controls the width of output receive data from PHY on lane 3. The encoding of the width is as follows : - 2'b00: 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit This field drives the.." "0: 8-bit,1: 10-bit,2: 16-bit,3: 20-bit This field drives the output port.." newline rbitfld.word 0x2 5.--7. "RX_LPD_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "RX_LPD_0,Receiver Lane Power Down on PHY lane 0. This bit can be set to power down the receiver to a power state equivalent to that of P1. This bit drives the output port 'xpcs_rx_lpd_o[0]'." "0,1" newline rbitfld.word 0x2 1.--3. "RX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 0. "RX_REQ_0,Receiver operation request on PHY lane 0 (RW SC Type). This bit can be set to 1 by application.This bit is self-cleared when 'xpcs_tx_ack_i[0]' is asserted. When this bit is set a new receiver setting request is made towards the PHY.This bit.." "0,1" line.word 0x3 "VR_MII_Gen5_12G_16G_RX_GENCTRL3,VR MII PHY Rx General Control 3" rbitfld.word 0x3 13.--15. "LOS_LFPS_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 12. "LOS_LFPS_EN_0,Rx LOS LFPS Enable on lane 0 of the PHY This field drives the output port xpcs_rx_los_lfps_en_o[0] to enable the LFPS filter on lane 0 of the PHY." "0,1" newline rbitfld.word 0x3 9.--11. "LOS_TRSHLD_3,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x3 6.--8. "LOS_TRSHLD_2,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x3 3.--5. "LOS_TRSHLD_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 0.--2. "LOS_TRSHLD_0,Loss of signal threshold on PHY lane 0. This field drives the output port xpcs_rx0_los_threshold_o[2:0]. Threshold voltages for various values are as follows : - 3'b000: Reserved - 3'b001: 90 mVpp - 3'b010: 120 mVpp - 3'b011: 150 mVpp -.." "0: Reserved,1: 90 mVpp,2: 120 mVpp,3: 150 mVpp,4: 180 mVpp,5: 210 mVpp,6: 240 mVpp,7: 270 mVpp" line.word 0x4 "VR_MII_Gen5_12G_16G_RX_RATE_CTRL,VR MII PHY Rx Rate Control" rbitfld.word 0x4 12.--13. "RX3_RATE,Reserved" "0,1,2,3" newline rbitfld.word 0x4 8.--9. "RX2_RATE,Reserved" "0,1,2,3" newline rbitfld.word 0x4 4.--5. "RX1_RATE,Reserved" "0,1,2,3" newline bitfld.word 0x4 0.--1. "RX0_RATE,Rx date rate on lane 0 of the PHY Data Rate Encoding is as follows : - 2'b00: baud - 2'b01: baud/2 - 2'b10: baud/4 - 2'b11: baud/8" "0: baud,1: baud/2,2: baud/4,3: baud/8" line.word 0x5 "VR_MII_Gen5_12G_16G_RX_POWER_STATE_CTRL,VR MII PHY Rx Power State" rbitfld.word 0x5 12. "EEE_OVR_RIDE,Reserved" "0,1" newline rbitfld.word 0x5 9.--11. "RX_DISABLE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x5 8. "RX_DISABLE_0,Receiver Disable on lane 0 This bit can be set in P1 power state to put the receiver in a low power mode. This field drives the output port 'xpcs_rx_disable_o[0]'." "0,1" newline rbitfld.word 0x5 6.--7. "RX3_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 4.--5. "RX2_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 2.--3. "RX1_PSTATE,Reserved" "0,1,2,3" newline bitfld.word 0x5 0.--1. "RX0_PSTATE,Rx power state control for PHY lane 0. Power state encoding is as follows : - 2'b00: P0 - 2'b01: P0s - 2'b10: P1 - 2'b11: P2" "0: P0,1: P0s,2: P1,3: P2" line.word 0x6 "VR_MII_Gen5_12G_16G_RX_CDR_CTRL,VR MII PHY Rx CDR Control" rbitfld.word 0x6 9.--11. "VCO_LOW_FREQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 8. "VCO_LOW_FREQ_0,Rx VCO lower frequency band mode on lane 0 of the PHY This field controls the frequency of the Rx VCO to a lower-frequency operating band. This field drives the output port xpcs_rx_cdr_vco_lowfreq_o[0]." "0,1" newline rbitfld.word 0x6 5.--7. "CDR_SSC_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 4. "CDR_SSC_EN_0,Rx CDR SSC Mode Enable on lane 0 of the PHY This field controls the CDR tracking gains and duration. This bit should be set to 1 when receive data has a spread spectrum clock and should be cleared if receive data does not have SSC. This bit.." "0,1" newline rbitfld.word 0x6 1.--3. "CDR_TRACK_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 0. "CDR_TRACK_EN_0,Rx CDR Tracking Enable on lane 0 of the PHY This bit should be set to enable CDR tracking of receive data on lane 0 of the PHY. This bit drives the output port 'xpcs_rx_cdr_track_en_o[0]'." "0,1" line.word 0x7 "VR_MII_Gen5_12G_16G_RX_ATTN_CTRL,VR MII PHY Rx Attenuation Control" rbitfld.word 0x7 12.--14. "RX3_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x7 8.--10. "RX2_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x7 4.--6. "RX1_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x7 0.--2. "RX0_EQ_ATT_LVL,Rx Equalization Attenuation level for lane 0 of the PHY This field drives the output port xpcs_rx0_eq_att_lvl_o[2:0]. This field controls the AFE attenuation level of the PHY." "0,1,2,3,4,5,6,7" line.word 0x8 "VR_MII_Gen5_12G_RX_EQ_CTRL0,VR MII PHY Rx Equalization Control 0" hexmask.word.byte 0x8 12.--15. 1. "AFE_GAIN_0,Rx Equalization AFE Gain on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_afe_gain_o[3:0]." newline hexmask.word.byte 0x8 0.--4. 1. "CTLE_BOOST_0,Rx Equalization CTLE Boost value on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_ctle_boost_o[4:0].This field controls the CTLE boost level." group.word 0x1F805C++0x5 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_EQ_CTRL4,VR MII PHY Rx Equalization Control 4" rbitfld.word 0x0 12. "RX_AD_REQ,Reserved" "0,1" newline rbitfld.word 0x0 11. "RX_EQ_STRT_CTRL,Reserved" "0,1" newline rbitfld.word 0x0 10. "SELF_MAIN_EN,Reserved" "0,1" newline rbitfld.word 0x0 9. "PING_PONG_EN,Reserved" "0,1" newline rbitfld.word 0x0 8. "SEQ_EQ_EN,Reserved" "0,1" newline rbitfld.word 0x0 5.--7. "CONT_OFF_CAN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "CONT_OFF_CAN_0,Receiver offset cancellation continuous operation on lane 0 This bit can be set if continuous receiver offset cancellation is required. If this bit is 0 offset cancellation runs when receiver exits P2 power state. This bit drives the.." "0,1" newline rbitfld.word 0x0 1.--3. "CONT_ADAPT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "CONT_ADAPT_0,Receiver Adaptation Continuous Operation on lane 0 This bit can be set to enable continuous receiver adaptation in the PHY. This bit drives the output port 'xpcs_rx_offcan_cont_o'." "0,1" line.word 0x1 "VR_MII_Gen5_12G_AFE_DFE_EN_CTRL,VR MII PHY AFE-DFE Enable" rbitfld.word 0x1 5.--7. "DFE_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "DFE_EN_0,Rx DFE Enable on lane 0 of the PHY This bit drives the output port xpcs_rx_adapt_dfe_en_o[0]. This bit can be set to enable Rx adaption and decision feedback equalization (DFE) circuitry and applies the input setting of DFE Tap1:.." "0,1" newline rbitfld.word 0x1 1.--3. "AFE_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "AFE_EN_0,Rx Adaptation AFE Enable on lane 0 of the PHY This bit drives the output port xpcs_rx_adapt_afe_en_o[0]. This bit can be set to enable Rx adaption circuitry and applies the following input receiver equalization settings to the PHY: -.." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_DFE_TAP_CTRL0,VR MII PHY DFE Tap Control 0" hexmask.word.byte 0x2 8.--15. 1. "DFE_TAP1_1,Reserved" newline hexmask.word.byte 0x2 0.--7. 1. "DFE_TAP1_0,Rx Equalization DFE Tap1 value on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_dfe_tap1_o[7:0]" rgroup.word 0x1F8060++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_STS,VR MII PHY Rx Status" bitfld.word 0x0 1.--3. "RX_ACK_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "RX_ACK_0,Rx Acknowledge on PHY lane 0. This bit captures the value of the input port xpcs_rx_ack_i[0]. If this bit is set it indicates that the requested receiver setting is complete. This bit forms a hand-shake with 'RX_REQ_0' bit. Once this bit is.." "0,1" group.word 0x1F8064++0x1 line.word 0x0 "VR_MII_Consumer_10G_RX_TERM_CTRL,VR MII PHY Receive Termination Control" bitfld.word 0x0 0.--2. "RX0_TERM,Receive Termination Control for lane 0" "0,1,2,3,4,5,6,7" group.word 0x1F806B++0x1 line.word 0x0 "VR_MII_Consumer_10G_RX_IQ_CTRL0,VR MII PHY RX IQ Control 0" hexmask.word.byte 0x0 8.--11. 1. "RX0_DELTA_IQ,RX IQ Offset Value for lane0. This field drives the output port xpcs_rx0_delta_iq_o[3:0]." group.word 0x1F8070++0x11 line.word 0x0 "VR_MII_Gen5_12G_16G_MPLL_CMN_CTRL,VR MII PHY MPLL Common Control" rbitfld.word 0x0 5.--7. "MPLLB_SEL_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "MPLLB_SEL_0,Tx MPLLB Select-lane 0 When this bit is set PHY selects MPLLB to generate Tx analog clocks on lane 0" "0,1" newline rbitfld.word 0x0 1.--3. "MPLL_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLL_EN_0,Tx MPLL Enable-lane 0 This bit should be set to power-up the MPLL.This bit should be 1 for normal operation." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_MPLLA_CTRL0,VR MII PHY MPLLA Control 0" bitfld.word 0x1 15. "MPLLA_CAL_DISABLE,MPLLA Calibration Disable This field can be programmed to 1 to disable calibration of MPLLA by PHY firmware." "0,1" newline hexmask.word.byte 0x1 0.--7. 1. "MPLLA_MULTIPLIER,MPLLA frequency Multiplier Control This field controls the multiplication of reference clock to a frequency suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset to ensure that PHY is.." line.word 0x2 "VR_MII_Gen5_12G_MPLLA_CTRL1,VR MII PHY MPLLA Control 1" hexmask.word 0x2 5.--15. 1. "MPLLA_FRACN_CTRL,MPLLA Fractional Control This field drives the output port xpcs_mplla_fracn_ctrl_o." line.word 0x3 "VR_MII_Gen5_12G_16G_MPLLA_CTRL2,VR MII PHY MPLLA Control 2" bitfld.word 0x3 11.--13. "MPLLA_TX_CLK_DIV,MPLLA Tx Clock Divider. This field drives the output port 'xpcs_mplla_tx_clk_div_o[1:0]'." "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 10. "MPLLA_DIV_CLK_EN,Enable mplla_div_clk from PHY. When asserted the frequency of mplla_div_clk from PHY is the MPLLA frequency divided by 'mplla_div_multiplier'" "0,1" newline bitfld.word 0x3 9. "MPLLA_DIV10_CLK_EN,MPLLA Divide by 10 Enable When this bit is set the frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 10." "0,1" newline bitfld.word 0x3 8. "MPLLA_DIV8_CLK_EN,MPLLA Divide by 8 Enable When this bit is set the frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 8." "0,1" newline hexmask.word.byte 0x3 0.--7. 1. "MPLLA_DIV_MULT,MPLLA Output Frequency Multiplier Control This field controls the frequency multiplication factor used to generate MPLLA clock output from the reference clock input as seen by the MPLL." line.word 0x4 "VR_MII_Gen5_12G_16G_MPLLB_CTRL0,VR MII PHY MPLLB Control 0" bitfld.word 0x4 15. "MPLLB_CAL_DISABLE,MPLLB Calibration Disable This field can be programmed to 1 to disable calibration of MPLLB by PHY firmware." "0,1" newline hexmask.word.byte 0x4 0.--7. 1. "MPLLB_MULTIPLIER,MPLLB frequency Multiplier Control This field controls the multiplication of reference clock to a frequency suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset to ensure that PHY is.." line.word 0x5 "VR_MII_Gen5_12G_MPLLB_CTRL1,VR MII PHY MPLLB Control 1" hexmask.word 0x5 5.--15. 1. "MPLLB_FRACN_CTRL,MPLLB Fractional Control This field drives the output port 'xpcs_mpllb_fracn_ctrl_o'." line.word 0x6 "VR_MII_Gen5_12G_16G_MPLLB_CTRL2,VR MII PHY MPLLB Control 2" bitfld.word 0x6 11.--13. "MPLLB_TX_CLK_DIV,MPLLB Tx Clock Divider. This field drives the output port 'xpcs_mpllb_tx_clk_div_o[1:0]'." "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 10. "MPLLB_DIV_CLK_EN,Enable mpllb_div_clk from PHY When asserted the frequency of mpllb_div_clk output from PHY is MPLLB frequency divided by 'mpllb_div_multiplier'" "0,1" newline bitfld.word 0x6 9. "MPLLB_DIV10_CLK_EN,MPLLB Divide by 10 Enable When this bit is set the frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 10." "0,1" newline bitfld.word 0x6 8. "MPLLB_DIV8_CLK_EN,MPLLB Divide by 8 Enable When this bit is set the frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 8." "0,1" newline hexmask.word.byte 0x6 0.--7. 1. "MPLLB_DIV_MULT,MPLLB Output Frequency Multiplier Control This field controls the frequency multiplication factor used to generate MPLLB clock output from the reference clock input as seen by the MPLL." line.word 0x7 "VR_MII_Gen5_12G_MPLLA_CTRL3,VR MII PHY MPLLA Control 3" hexmask.word 0x7 0.--15. 1. "MPLLA_BANDWIDTH,MPLLA Bandwidth Control This field controls the bandwidth of MPLLA present in the PHY. This field drives the output port 'xpcs_mplla_bandwidth_o'." line.word 0x8 "VR_MII_Gen5_12G_MPLLB_CTRL3,VR MII PHY MPLLB Control 3" hexmask.word 0x8 0.--15. 1. "MPLLB_BANDWIDTH,MPLLB Bandwidth Control This field controls the bandwidth of MPLLB present in the PHY. This field drives the output port 'xpcs_mpllb_bandwidth_o'." group.word 0x1F8090++0x5 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_CTRL0,VR MII PHY Miscellaneous Control 0" bitfld.word 0x0 15. "PLL_CTRL,PLL Reinitialization Control" "0,1" newline bitfld.word 0x0 14. "CR_PARA_SEL,Select CR Para Port This bit select the interface for accessing PHY registers * 0 -JTAG * 1 -CR parallel port This bit should be changed only after disabling 'jtag_tck'to PHY." "0,1" newline bitfld.word 0x0 13. "RTUNE_REQ,Resistor Tuning Request This bit can be set to trigger a resistor tune request to the PHY. This bit controls the 'xgxs_rtune_req_o' output port." "0,1" newline hexmask.word.byte 0x0 8.--12. 1. "RX_VREF_CTRL,Rx Biasing Current Control" newline rbitfld.word 0x0 5.--7. "RX2TX_LB_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "RX2TX_LB_EN_0,Enable Parallel Rx-to-Tx Loopback on lane 0 When this bit is set recovered parallel data from PHY receiver is looped back to the transmit serializer. This loop-back takes place internal to the PHY (not within XPCS)." "0,1" newline rbitfld.word 0x0 1.--3. "TX2RX_LB_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TX2RX_LB_EN_0,Enable Analog Tx-to-Rx Serial Loopback on lane 0 This bit can be set to enable serial loopback in the PHY from Tx pre-driver to Rx analog front-end." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_REF_CLK_CTRL,VR MII SPHY Reference Control" bitfld.word 0x1 8. "REF_RPT_CLK_EN,Repeat Reference Clock Enable If this bit is set ref_repeat_clk_{p m} clock from PHY is enabled." "0,1" newline bitfld.word 0x1 7. "REF_MPLLB_DIV2,MPLLB Reference Clock Divider Control" "0,1" newline bitfld.word 0x1 6. "REF_MPLLA_DIV2,MPLLA Reference Clock Divider Control" "0,1" newline bitfld.word 0x1 3.--5. "REF_RANGE,Input Reference Clock Range" "0: 20 - 26 MHz,1: 26.1 - 52 MHz,2: 52.1 - 78 MHz,3: 78.1 - 104 MHz,4: 104.1 - 130 MHz,5: 130.1 - 156 MHz,6: 156.1 - 182 MHz,7: 182.1 - 200 MHz" newline bitfld.word 0x1 2. "REF_CLK_DIV2,Reference Clock divide by 2" "0,1" newline bitfld.word 0x1 1. "REF_USE_PAD,Use Pad Clock As Reference Clock" "0: Internal PLL,1: External clock" newline bitfld.word 0x1 0. "REF_CLK_EN,Reference Clock Enable" "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_VCO_CAL_LD0,VR MII PHY VCO Calibration Load 0" hexmask.word 0x2 0.--12. 1. "VCO_LD_VAL_0,Rx VCO calibration load value on lane 0 of the PHY" group.word 0x1F8096++0x1 line.word 0x0 "VR_MII_Gen5_12G_VCO_CAL_REF0,VR MII PHY VCO Calibration Reference 0" hexmask.word.byte 0x0 8.--13. 1. "VCO_REF_LD_1,Reserved" newline hexmask.word.byte 0x0 0.--5. 1. "VCO_REF_LD_0,Rx VCO calibration reference load value -lane 0" rgroup.word 0x1F8098++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_STS,VR MII PHY Miscellaneous Status" bitfld.word 0x0 11. "REF_CLKDET_RESULT,Reserved" "0,1" newline bitfld.word 0x0 10. "MPLLB_STS,Status of MPLLB from PHY This bit denotes the value of xpcs_mpllb_state_i input." "0,1" newline bitfld.word 0x0 9. "MPLLA_STS,Status of MPLLA from PHY. This bit denotes the value of xpcs_mplla_state_i input" "0,1" newline bitfld.word 0x0 8. "RTUNE_ACK,Acknowledgment for Resistor Tune Request This bit denotes the value of 'xgxs_rtune_ack_i' input." "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "FOM,Reserved" group.word 0x1F8099++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_CTRL1,VR MII PHY Miscellaneous Control 1" hexmask.word 0x0 0.--15. 1. "RX_LNK_UP_TIME,Wait Time before PLL Re-initialization" group.word 0x1F80A0++0x5 line.word 0x0 "VR_MII_SNPS_CR_CTRL,VR MII PHY CR Control" bitfld.word 0x0 1. "WR_RDN,Write or Read Indicator This bit indicates whether a read or write operation is to be performed to the Synopsys PHY registers: - 0: Read - 1: Write" "0: Read,1: Write" newline bitfld.word 0x0 0. "START_BUSY,Start CR Port Access or Busy Indicator (WS SC Type)" "0,1" line.word 0x1 "VR_MII_SNPS_CR_ADDR,VR MII PHY CR Address" hexmask.word 0x1 0.--15. 1. "ADDRESS,CR Port Address" line.word 0x2 "VR_MII_SNPS_CR_DATA,VR MII CR Data" hexmask.word 0x2 0.--15. 1. "DATA,CR Port Data" group.word 0x1F80E1++0x1 line.word 0x0 "VR_MII_DIG_CTRL2,VR MII MMD Digital Control 2" bitfld.word 0x0 4. "TX_POL_INV_0,Tx Polarity Invert" "0: Not inverted,1: Inverted" newline bitfld.word 0x0 0. "RX_POL_INV_0,Rx Polarity Invert" "0: Not inverted,1: Inverted" tree.end tree "SERDES_XPCS_0_PCIE_1" base ad:0x44182000 group.word 0x1F0000++0x1 line.word 0x0 "SR_MII_CTRL,SR MII MMD Control" bitfld.word 0x0 15. "RST,Soft reset (RW SC type)" "0,1" newline bitfld.word 0x0 14. "LBE,Loopback enable" "0,1" newline bitfld.word 0x0 13. "SS13,Speed selection (LSB)" "0,1" newline bitfld.word 0x0 12. "AN_ENABLE,Enable auto-negotiation" "0,1" newline bitfld.word 0x0 11. "LPM,Power-down mode" "0: Normal operation,1: The XPCS and the PHY enter Power-down mode. To.." newline bitfld.word 0x0 9. "RESTART_AN,Restart auto-negotiation (RW SC type)" "0,1" newline bitfld.word 0x0 8. "DUPLEX_MODE,Duplex mode" "0: Half duplex,1: Full duplex" newline bitfld.word 0x0 6. "SS6,Speed selection" "0,1" newline rbitfld.word 0x0 5. "SS5,Reserved" "0,1" rgroup.word 0x1F0001++0x5 line.word 0x0 "SR_MII_STS,SR MII MMD Status" bitfld.word 0x0 15. "ABL100T4,100BASE-T4 ability" "0,1" newline bitfld.word 0x0 14. "FD100ABL,100BASE-X full-duplex ability" "0,1" newline bitfld.word 0x0 13. "HD100ABL,100BASE-X half-duplex ability" "0,1" newline bitfld.word 0x0 12. "FD10ABL,10 Mbps full-duplex ability" "0,1" newline bitfld.word 0x0 11. "HD10ABL,10 Mbps half-duplex ability" "0,1" newline bitfld.word 0x0 10. "FD100T,100BASE-T2 full-duplex ability" "0,1" newline bitfld.word 0x0 9. "HD100T,100BASE-T2 half-duplex ability" "0,1" newline bitfld.word 0x0 8. "EXT_STS_ABL,Extended status information" "0: No extended status information is present at..,1: Extended Status information is present at.." newline bitfld.word 0x0 7. "UN_DIR_ABL,Unidirectional ability" "0: The XPCS is able to transmit GMII only when the..,1: The XPCS is able to transmit GMII irrespective.." newline bitfld.word 0x0 6. "MF_PRE_SUP,MF preamble suppression" "0: The XPCS does not accept the MDIO frames with..,1: The XPCS accepts the MDIO frames with preamble.." newline bitfld.word 0x0 5. "AN_CMPL,Auto-negotiation complete" "0: The AN process is not complete.,1: The AN process is complete." newline bitfld.word 0x0 4. "RF,Remote fault (RO LH type)" "0: The XPCS did not detect a remote fault.,1: The XPCS detected a remote fault." newline bitfld.word 0x0 3. "AN_ABL,Auto-negotiation ability" "0: The XPCS is unable to perform auto-negotiation.,1: The XPCS is able to perform auto-negotiation." newline bitfld.word 0x0 2. "LINK_STS,Link status (RO LL type)" "0: Link down,1: Link up" newline bitfld.word 0x0 0. "EXT_REG_CAP,Extended register capability" "0: Extended register capability does not exist,1: Extended Register capability exists" line.word 0x1 "SR_MII_DEV_ID1,SR MII MMD Device Identifier 1" hexmask.word 0x1 0.--15. 1. "VS_MII_DEV_OUI_3_18,Organizationally Unique Identifier[3:18]" line.word 0x2 "SR_MII_DEV_ID2,SR MII MMD Device Identifier 2" hexmask.word.byte 0x2 10.--15. 1. "VS_MMD_DEV_OUI_19_24,Organizationally unique identifier [19:24]" newline hexmask.word.byte 0x2 4.--9. 1. "VS_MMD_DEV_MMN_5_0,Model number" newline hexmask.word.byte 0x2 0.--3. 1. "VS_MMD_DEV_RN_3_0,Revision number" group.word 0x1F0004++0x1 line.word 0x0 "SR_MII_AN_ADV,SR MII MMD AN Advertisement" rbitfld.word 0x0 15. "NP,Next page" "0,1" newline bitfld.word 0x0 12.--13. "RF,Remote fault" "0: No error,1: Offline,2: Link failure,3: Auto-negotiation error" newline bitfld.word 0x0 7.--8. "PAUSE,Pause ability" "0: No pause,1: Asymmetric pause towards the link partner,2: Symmetric pause,3: Symmetric pause and asymmetric pause towards the.." newline bitfld.word 0x0 6. "HD,Half duplex" "0,1" newline bitfld.word 0x0 5. "FD,Full duplex" "0,1" rgroup.word 0x1F0005++0x3 line.word 0x0 "SR_MII_LP_BABL,SR MII MMD AN Link Partner Base Ability" bitfld.word 0x0 15. "LP_NP,Next page" "0,1" newline bitfld.word 0x0 14. "LP_ACK,ACK bit from the link partner" "0,1" newline bitfld.word 0x0 12.--13. "LP_RF,Remote fault" "0: No error,1: Offline,2: Link failure,3: Auto-negotiation error" newline bitfld.word 0x0 7.--8. "LP_PAUSE,Pause ability" "0: No pause,1: Asymmetric pause towards the link partner,2: Symmetric pause,3: Both symmetric pause and asymmetric pause.." newline bitfld.word 0x0 6. "LP_HD,Half duplex" "0,1" newline bitfld.word 0x0 5. "LP_FD,Full duplex" "0,1" line.word 0x1 "SR_MII_EXPN,SR MII MMD AN Expansion" bitfld.word 0x1 2. "LD_NP_ABL,Local device next page able" "0: The local device does not have the next-page..,1: The local device has the next-page ability" newline bitfld.word 0x1 1. "PG_RCVD,Page received (RO LH type)" "0: The local device did not receive a new page,1: The local device received a new page" rgroup.word 0x1F000F++0x1 line.word 0x0 "SR_MII_EXT_STS,SR MII MMD Extended Status" bitfld.word 0x0 15. "CAP_1G_X_FD,1000BASE-X full-duplex capable" "0: Not capable of 1000BASE-X full-duplex,1: Capable of 1000BASE-X full-duplex" newline bitfld.word 0x0 14. "CAP_1G_X_HD,1000BASE-X half-duplex capable" "0: Not capable of 1000BASE-X half-duplex,1: Capable of 1000BASE-X half-duplex" newline bitfld.word 0x0 13. "CAP_1G_T_FD,1000BASE-T full-duplex capable" "0: Not capable of 1000BASE-T full-duplex,1: Capable of 1000BASE-T full-duplex" newline bitfld.word 0x0 12. "CAP_1G_T_HD,1000BASE-T half-duplex capable" "0: Not capable of 1000BASE-T half-duplex,1: Capable of 1000BASE-T half-duplex" rgroup.word 0x1F0708++0x11 line.word 0x0 "SR_MII_TIME_SYNC_ABL,SR MII MMD Time Sync Capability" bitfld.word 0x0 1. "MII_TX_DLY_ABL,XPCS transmit path data delay information available" "0,1" newline bitfld.word 0x0 0. "MII_RX_DLY_ABL,XPCS receive path data delay information available" "0,1" line.word 0x1 "SR_MII_TIME_SYNC_TX_MAX_DLY_LWR,SR MII MMD Time Sync Tx Max Delay Lower" hexmask.word 0x1 0.--15. 1. "MII_TX_MAX_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS transmit path." line.word 0x2 "SR_MII_TIME_SYNC_TX_MAX_DLY_UPR,SR MII MMD Time Sync Tx Max Delay Upper" hexmask.word 0x2 0.--15. 1. "MII_TX_MAX_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS transmit path." line.word 0x3 "SR_MII_TIME_SYNC_TX_MIN_DLY_LWR,SR MII MMD Time Sync Tx Min Delay Lower" hexmask.word 0x3 0.--15. 1. "MII_TX_MIN_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS transmit path." line.word 0x4 "SR_MII_TIME_SYNC_TX_MIN_DLY_UPR,SR MII MMD Time Sync Tx Min Delay Upper" hexmask.word 0x4 0.--15. 1. "MII_TX_MIN_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS transmit path." line.word 0x5 "SR_MII_TIME_SYNC_RX_MAX_DLY_LWR,SR MII MMD Time Sync Rx Max Delay Lower" hexmask.word 0x5 0.--15. 1. "MII_RX_MAX_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS receive path." line.word 0x6 "SR_MII_TIME_SYNC_RX_MAX_DLY_UPR,SR MII MMD Time Sync Rx Max Delay Upper" hexmask.word 0x6 0.--15. 1. "MII_RX_MAX_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS receive path." line.word 0x7 "SR_MII_TIME_SYNC_RX_MIN_DLY_LWR,SR MII MMD Time Sync Rx Min Delay Lower" hexmask.word 0x7 0.--15. 1. "MII_RX_MIN_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS receive path." line.word 0x8 "SR_MII_TIME_SYNC_RX_MIN_DLY_UPR,SR MII MMD Time Sync Rx Min Delay Upper" hexmask.word 0x8 0.--15. 1. "MII_RX_MIN_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS receive path." group.word 0x1F8000++0x9 line.word 0x0 "VR_MII_DIG_CTRL1,VR MII MMD Digital Control 1" bitfld.word 0x0 15. "VR_RST,Vendor-specific soft reset (RW SC type)" "0,1" newline bitfld.word 0x0 14. "R2TLBE,Rx to Tx loopback enable" "0: Loopback path is disabled,1: Loopback path is enabled" newline rbitfld.word 0x0 13. "EN_VSMMD1,Enable vendor-specific MMD1" "0,1" newline bitfld.word 0x0 11. "PWRSV,Power save" "0: Normal operation,1: XPCS and the PHY enter the power-save mode" newline rbitfld.word 0x0 10. "CS_EN,Reserved" "0,1" newline bitfld.word 0x0 9. "MAC_AUTO_SW,Automatic Speed Mode Change after CL37 AN" "0,1" newline bitfld.word 0x0 8. "INIT,Datapath initialization control" "0,1" newline rbitfld.word 0x0 7. "MSK_RD_ERR,Mask running disparity error" "0,1" newline bitfld.word 0x0 6. "PRE_EMP,Pre-emption packet enable" "0,1" newline bitfld.word 0x0 4. "DTXLANED_0,Tx lane 0 disable" "0,1" newline bitfld.word 0x0 3. "CL37_TMR_OVR_RIDE,Override control for CL37 link timer" "0,1" newline bitfld.word 0x0 2. "EN_2_5G_MODE,Enable 2.5G GMII mode" "0,1" newline bitfld.word 0x0 1. "BYP_PWRUP,Bypass power-up sequence" "0: The XPCS waits for the MPLL Tx or Rx PLL status..,1: The XPCS bypasses the normal flow of the.." newline rbitfld.word 0x0 0. "PHY_MODE_CTRL,When SGMII_PHY_AN_AUTO_RESTART=Enabled or QSGMII_PHY_AN_AUTO_RESTART=Enabled: PHY mode control" "0: SGMII/QSGMII(Port0) autonegotiation advertises..,1: XPCS advertises the values of input ports.." line.word 0x1 "VR_MII_AN_CTRL,VR MII MMD AN Control" bitfld.word 0x1 8. "MII_CTRL,MII Control This bit controls the width of the MAC interface when operating at SGMII/QSGMII/USXGMII speed modes of 10 Mbps or 100 Mbps - 0: 4-bit MII - 1: 8-bit MII This bit also controls the xpcs_mii_ctrl_o signal which is used for external.." "0: 4-bit MII,1: 8-bit MII This bit also controls the.." newline bitfld.word 0x1 4. "SGMII_LINK_STS,SGMII Link Status/ USXGMII Link Status /QSGMII Port0 Link Status" "0,1" newline bitfld.word 0x1 3. "TX_CONFIG,Transmit configuration" "0: Configures the XPCS as the MAC side..,1: Configures the XPCS as the PHY side.." newline bitfld.word 0x1 1.--2. "PCS_MODE,PCS mode" "0: 1000BASE-X mode (clause 37 auto-negotiation is..,?,2: SGMII mode (clause 37 auto-negotiation is as per..,3: QSGMII mode (clause 37 auto-negotiation conforms.." newline bitfld.word 0x1 0. "MII_AN_INTR_EN,Clause 37 AN complete interrupt enable" "0: The Clause 37 auto-negotiation complete..,1: The Clause 37 auto-negotiation complete.." line.word 0x2 "VR_MII_AN_INTR_STS,VR MII MMD AN Interrupt And Status" hexmask.word.byte 0x2 8.--14. 1. "USXG_AN_STS,Reserved" newline rbitfld.word 0x2 6. "LP_CK_STP,Link Partner EEE Clock Stop Capability This field indicates the EEE clock stop capability (or clock-stop enabe - in case far-end is acting as QSGMII MAC) advertised by the far-end device. This field is valid only when PCS_MODE[1:0] is set to.." "0,1" newline rbitfld.word 0x2 5. "LP_EEE_CAP,Link Partner EEE Capability This field indicates the EEE capability advertised by the far-end device (Port 0 QSGMII PHY). This field is valid only when PCS_MODE[1:0] is set to the QSGMII mode and the auto-negotiation is complete along port 0." "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "CL37_ANSGM_STS,Clause 37 AN SGMII Status/QSGMII Port 0 Status This field is valid only when the PCS_MODE[1:0] is set to the SGMII/QSGMII mode and the auto-negotiation is complete. It indicates the status received from remote link after the SGMII/QSGMII.." newline bitfld.word 0x2 0. "CL37_ANCMPLT_INTR,Clause 37 AN Complete Interrupt (SS WC Type) The XPCS sets this bit when Clause 37 auto-negotiation is complete. The host must clear this bit by writing 0 to it." "0,1" line.word 0x3 "VR_MII_TC,VR MII MMD Test Control" bitfld.word 0x3 2. "TPE,Test Pattern Enable Lanes" "0,1" newline bitfld.word 0x3 0.--1. "TP,Test Pattern Select" "0,1,2,3" line.word 0x5 "VR_MII_DBG_CTRL,VR MII MMD Debug Control" bitfld.word 0x5 6. "RX_DT_EN_CTL,Rx Data Enable Control" "0,1" newline rbitfld.word 0x5 5. "SUPRESS_EEE_LOS_DET,Reserved" "0,1" newline bitfld.word 0x5 4. "SUPRESS_LOS_DET,Suppress Loss of Signal Detection" "0,1" newline bitfld.word 0x5 0. "RESTAR_SYNC_0,Restart Synchronization" "0,1" group.word 0x1F800A++0x1 line.word 0x0 "VR_MII_LINK_TIMER_CTRL,VR MII MMD Link Timer Control" hexmask.word 0x0 0.--15. 1. "CL37_LINK_TIME,Programmable Link Timer Value for Clause 37 autonegotiation. This field can be programmed to any desired value if application wishes to over-ride the standard specified values for Link Timer used during Clause 37 Auto negotiation. Link.." rgroup.word 0x1F8010++0x3 line.word 0x0 "VR_MII_DIG_STS,VR MII MMD Digital Status" bitfld.word 0x0 13.--15. "LTX_STATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "LRX_STATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "RXFIFO_OVF,Rx FIFO Overflow (RO LH Type) This bit indicates the clock rate compensation FIFO overflow. - 0: Normal operation - 1: FIFO overflow" "0: Normal operation,1: FIFO overflow" newline bitfld.word 0x0 5. "RXFIFO_UNDF,Rx FIFO Underflow (RO LH Type) This bit indicates the clock rate compensation FIFO underflow. - 0: Normal operation - 1: FIFO underflow" "0: Normal operation,1: FIFO underflow" newline bitfld.word 0x0 2.--4. "PSEQ_STATE,Power Up Sequence State" "0: Wait for ACK High 0,1: Wait for ACK Low 0,2: Wait for ACK High 1,3: Wait for ACK Low 1,4: Tx/Rx stable (Power_Good state),5: Power Save state,6: Power Down state,?" newline bitfld.word 0x0 1. "LB_ACTIVE,Reserved" "0,1" line.word 0x1 "VR_MII_ICG_ERRCNT1,VR MII MMD Invalid Code Group Error Count 1" hexmask.word.byte 0x1 0.--7. 1. "EC0,Invalid Code Group Count Lane 0 (RO LH Type) This field gives the invalid code group count in Lane 0 when Bit 4 of VR MII MMD Digital Error Count Select Register is set to 1." group.word 0x1F8012++0x1 line.word 0x0 "VR_MII_DIG_ERRCNT_SEL,VR MII MMD Digital Error Count Select" bitfld.word 0x0 4. "INV_EC_EN,Invalid Code Group Error Counter Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 0. "COR,Clear on Read" "0: Normal operation,1: Clear any error counter that is read" group.word 0x1F8015++0x1 line.word 0x0 "VR_MII_GPIO,VR MII MMD GPIO" hexmask.word.byte 0x0 8.--15. 1. "GPIO_OUT,GPIO Output The content written on this field is driven to the xpcs_gpo_o[7:0] output port. Dependency: This field is valid only when GPIO_EN = Enabled." newline hexmask.word.byte 0x0 0.--7. 1. "GPIO_IN,GPIO Input This field indicates the content of the xpcs_gpo_i[7:0] port. Dependency: This field is valid only when GPIO_EN = Enabled." rgroup.word 0x1F8018++0x1 line.word 0x0 "VR_MII_MISC_STS,VR MII MMD Miscellaneous Status" hexmask.word.byte 0x0 0.--3. 1. "BIT_SFT,Bit Shift This field indicates the number of bit-shifts carried-out by comma-detect logic so as to align the incoming 10-bit XGXS Rx data Default Value: The default value of this field can be any value depending on the status of comma-detect.." rgroup.word 0x1F8020++0x1 line.word 0x0 "VR_MII_RX_LSTS,VR MII PHY Rx Lane Status" bitfld.word 0x0 13.--15. "RX_VALID_3_1,DPLL Lock Status for Lanes[3:1]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "RX_VALID_0,DPLL Lock Status for Lane 0" "0,1" newline bitfld.word 0x0 9.--11. "RX_PLL_STATE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "RX_PLL_STATE_0,Reserved" "0,1" newline bitfld.word 0x0 5.--7. "SIG_DET_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "SIG_DET_0,Rx Signal Detect for Lane 0" "0,1" group.word 0x1F8030++0xF line.word 0x0 "VR_MII_Gen5_12G_16G_TX_GENCTRL0,VR MII PHY Tx General Control 0" rbitfld.word 0x0 13.--15. "TX_DT_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "TX_DT_EN_0,Tx Data Enable on PHY lane 0" "0,1" newline rbitfld.word 0x0 9.--11. "TX_RST_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "TX_RST_0,Tx Reset on PHY lane 0" "0,1" newline rbitfld.word 0x0 5.--7. "TX_INV_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "TX_INV_0,Tx Invert on PHY lane 0" "0,1" newline rbitfld.word 0x0 1.--3. "TXBCN_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TXBCN_EN_0,Tx Beaconing Enable on PHY lane 0" "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_TX_GENCTRL1,VR MII PHY Tx General Control 1" rbitfld.word 0x1 13.--15. "TX_CLK_RDY_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 12. "TX_CLK_RDY_0,Transmitter Input clock ready on lane 0" "0,1" newline bitfld.word 0x1 8.--10. "VBOOST_LVL,Tx Voltage Boost Maximum Level" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x1 5.--7. "VBOOST_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "VBOOST_EN_0,Tx voltage Boost Enable on PHY lane 0" "0,1" newline rbitfld.word 0x1 1.--3. "DET_RX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "DET_RX_REQ_0,Transmitter Rx-Detection request on PHY lane 0." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_TX_GENCTRL2,VR MII PHY Tx General Control 2" rbitfld.word 0x2 14.--15. "TX3_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 12.--13. "TX2_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 10.--11. "TX1_WIDTH,Reserved" "0,1,2,3" newline bitfld.word 0x2 8.--9. "TX0_WIDTH,Tx Datapath Width on lane 0 of the PHY This field controls the width of input transmit data on lane 0. The encoding of the width is as follows : - 2'b00 : 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit This field drives the output port.." "0: 8-bit,1: 10-bit,2: 16-bit,3: 20-bit This field drives the output port.." newline rbitfld.word 0x2 5.--7. "TX_LPD_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "TX_LPD_0,Transmitter Lane Power Down on PHY lane 0. This field drives the output 'xpcs_tx_lpd_o[3:1]'. This field can be asserted to put the phy transmitter to a power state equivalent to that of P1." "0,1" newline rbitfld.word 0x2 1.--3. "TX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 0. "TX_REQ_0,Transmitter operation request on PHY lane 0 (RW SC Type)" "0,1" line.word 0x3 "VR_MII_Gen5_12G_16G_TX_BOOST_CTRL,VR MII PHY Tx Boost Control" hexmask.word.byte 0x3 12.--15. 1. "TX3_IBOOST,Reserved" newline hexmask.word.byte 0x3 8.--11. 1. "TX2_IBOOST,Reserved" newline hexmask.word.byte 0x3 4.--7. 1. "TX1_IBOOST,Reserved" newline hexmask.word.byte 0x3 0.--3. 1. "TX0_IBOOST,Tx current boost level on lane 0 of the PHY. This bit drives the output port xpcs_tx0_iboost_lvl_o[3:0]." line.word 0x4 "VR_MII_Gen5_12G_16G_TX_RATE_CTRL,VR MII PHY Tx Rate Control" rbitfld.word 0x4 12.--14. "TX3_RATE,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x4 8.--10. "TX2_RATE,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x4 4.--6. "TX1_RATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x4 0.--2. "TX0_RATE,Tx date rate on PHY lane 0." "0,1,2,3,4,5,6,7" line.word 0x5 "VR_MII_Gen5_12G_16G_TX_POWER_STATE_CTRL,VR MII PHY Tx Power State" rbitfld.word 0x5 9.--11. "TX_DISABLE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x5 8. "TX_DISABLE_0,Transmitter Disable on lane 0 This field drives the output port 'xpcs_tx_disable_o[0]'." "0,1" newline rbitfld.word 0x5 6.--7. "TX3_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 4.--5. "TX2_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 2.--3. "TX1_PSTATE,Reserved" "0,1,2,3" newline bitfld.word 0x5 0.--1. "TX0_PSTATE,Tx power state control for PHY lane 0." "0,1,2,3" line.word 0x6 "VR_MII_Gen5_12G_16G_TX_EQ_CTRL0,VR MII PHY Tx Equalization Control 0" hexmask.word.byte 0x6 8.--13. 1. "TX_EQ_MAIN,Control for setting Tx driver output amplitude" newline hexmask.word.byte 0x6 0.--5. 1. "TX_EQ_PRE,Tx Pre-Emphasis level adjustment Control" line.word 0x7 "VR_MII_Gen5_12G_16G_TX_EQ_CTRL1,VR MII PHY Tx Equalization Control 1" rbitfld.word 0x7 8. "CA_TX_EQ,Reserved" "0,1" newline rbitfld.word 0x7 7. "TX_EQ_DEF_CTRL,Reserved" "0,1" newline rbitfld.word 0x7 6. "TX_EQ_OVR_RIDE,Reserved" "0,1" newline hexmask.word.byte 0x7 0.--5. 1. "TX_EQ_POST,Tx Post-Emphasis level adjustment Control This field controls the transmitter driver output pre-emphasis (pre-shoot coefficient). This field drives the output port 'rpcs_ktx_post_o' if 'TX_EQ_OVR_RIDE' bit is set or in configurations with.." group.word 0x1F803C++0x1 line.word 0x0 "VR_MII_Consumer_10G_TX_TERM_CTRL,VR MII PHY Transmit Termination Control" bitfld.word 0x0 0.--2. "TX0_TERM,Transmit Termination Control for lane 0" "0,1,2,3,4,5,6,7" rgroup.word 0x1F8040++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_TX_STS,VR MII PHY Tx Status" bitfld.word 0x0 5.--7. "DETRX_RSLT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "DETRX_RSLT_0,Receiver Detection Result on PHY lane 0. This field captures the value of the input port 'xpcs_tx_detrx_result_o[0]'. The value of this field is valid when 'TX_ACK_0' is high. - 1'b0: Receiver not detected - 1'b1: Receiver detected" "0: Receiver not detected,1: Receiver detected" newline bitfld.word 0x0 1.--3. "TX_ACK_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TX_ACK_0,Tx Acknowledge on PHY lane 0. This bit captures the value of the input port 'xpcs_tx_ack_i[0]'. Whenever this bit is read as high it indicates that the requested transmitter setting is complete or the requested RX-detection operation is.." "0,1" group.word 0x1F8050++0x11 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_GENCTRL0,VR MII PHY Rx General Control 0" rbitfld.word 0x0 13.--15. "RX_CLKSFT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "RX_CLKSFT_0,Rx clock shift on PHY lane 0. When this bit is set a 1-bit shift of receive data happens relate to receive clock. This operation works only if alignment enable is disabled. This bit drives the output port 'xpcs_rx_clk_shift_o[0]'." "0,1" newline rbitfld.word 0x0 9.--11. "RX_DT_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "RX_DT_EN_0,Rx Data Enable on PHY lane 0. This bit should be set to enable the PHY receiver data output on lane 0. This bit drives the output port 'xgxs_rx_data_en_o[0]'." "0,1" newline rbitfld.word 0x0 5.--7. "RX_ALIGN_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "RX_ALIGN_EN_0,Rx Data Alignment Enable on PHY lane 0. This bit can be set to enable word alignment (based on k28.5 character) in the PHY. This field drives the output port 'xgxs_rx_align_en_o[0]'." "0,1" newline rbitfld.word 0x0 1.--3. "RX_TERM_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "RX_TERM_EN_0,Rx Termination Enable on PHY lane 0. When this bit is set PHY Rx is terminated with a nominal 50 ohm resistance. Otherwise the termination is in high impedance. This field drives the output port 'xpcs_rx_term_en_o[0]'." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_RX_GENCTRL1,VR MII PHY Rx General Control 1" rbitfld.word 0x1 9.--11. "RX_TERM_ACDC_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 8. "RX_TERM_ACDC_0,Rx Termination control on PHY lane 0. - 0: DC Termination (Floating Rx) - 1: AC Termination (Grounded Rx) This field drives the output port xpcs_rx_term_acdc_o[0]." "0: DC Termination,1: AC Termination" newline rbitfld.word 0x1 5.--7. "RX_RST_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "RX_RST_0,Rx reset on PHY lane 0. When this bit is set RX data path all the receiver settings and state machines of the PHY are reset This field drives the output port xgxs_rx_reset_o[0] when XPCS is in POWER_GOOD state." "0,1" newline rbitfld.word 0x1 1.--3. "RX_INV_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "RX_INV_0,Rx Data Invert on PHY lane 0. When this bit is set the data on PHY Rx serial lines are logically inverted. This signal drives the output port xgxs_rx_invert_o[0]." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_RX_GENCTRL2,VR MII PHY Rx General Control 2" rbitfld.word 0x2 14.--15. "RX3_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 12.--13. "RX2_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 10.--11. "RX1_WIDTH,Reserved" "0,1,2,3" newline bitfld.word 0x2 8.--9. "RX0_WIDTH,Rx Datapath Width on lane 0 of the PHY This field controls the width of output receive data from PHY on lane 3. The encoding of the width is as follows : - 2'b00: 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit This field drives the.." "0: 8-bit,1: 10-bit,2: 16-bit,3: 20-bit This field drives the output port.." newline rbitfld.word 0x2 5.--7. "RX_LPD_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "RX_LPD_0,Receiver Lane Power Down on PHY lane 0. This bit can be set to power down the receiver to a power state equivalent to that of P1. This bit drives the output port 'xpcs_rx_lpd_o[0]'." "0,1" newline rbitfld.word 0x2 1.--3. "RX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 0. "RX_REQ_0,Receiver operation request on PHY lane 0 (RW SC Type). This bit can be set to 1 by application.This bit is self-cleared when 'xpcs_tx_ack_i[0]' is asserted. When this bit is set a new receiver setting request is made towards the PHY.This bit.." "0,1" line.word 0x3 "VR_MII_Gen5_12G_16G_RX_GENCTRL3,VR MII PHY Rx General Control 3" rbitfld.word 0x3 13.--15. "LOS_LFPS_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 12. "LOS_LFPS_EN_0,Rx LOS LFPS Enable on lane 0 of the PHY This field drives the output port xpcs_rx_los_lfps_en_o[0] to enable the LFPS filter on lane 0 of the PHY." "0,1" newline rbitfld.word 0x3 9.--11. "LOS_TRSHLD_3,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x3 6.--8. "LOS_TRSHLD_2,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x3 3.--5. "LOS_TRSHLD_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 0.--2. "LOS_TRSHLD_0,Loss of signal threshold on PHY lane 0. This field drives the output port xpcs_rx0_los_threshold_o[2:0]. Threshold voltages for various values are as follows : - 3'b000: Reserved - 3'b001: 90 mVpp - 3'b010: 120 mVpp - 3'b011: 150 mVpp -.." "0: Reserved,1: 90 mVpp,2: 120 mVpp,3: 150 mVpp,4: 180 mVpp,5: 210 mVpp,6: 240 mVpp,7: 270 mVpp" line.word 0x4 "VR_MII_Gen5_12G_16G_RX_RATE_CTRL,VR MII PHY Rx Rate Control" rbitfld.word 0x4 12.--13. "RX3_RATE,Reserved" "0,1,2,3" newline rbitfld.word 0x4 8.--9. "RX2_RATE,Reserved" "0,1,2,3" newline rbitfld.word 0x4 4.--5. "RX1_RATE,Reserved" "0,1,2,3" newline bitfld.word 0x4 0.--1. "RX0_RATE,Rx date rate on lane 0 of the PHY Data Rate Encoding is as follows : - 2'b00: baud - 2'b01: baud/2 - 2'b10: baud/4 - 2'b11: baud/8" "0: baud,1: baud/2,2: baud/4,3: baud/8" line.word 0x5 "VR_MII_Gen5_12G_16G_RX_POWER_STATE_CTRL,VR MII PHY Rx Power State" rbitfld.word 0x5 12. "EEE_OVR_RIDE,Reserved" "0,1" newline rbitfld.word 0x5 9.--11. "RX_DISABLE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x5 8. "RX_DISABLE_0,Receiver Disable on lane 0 This bit can be set in P1 power state to put the receiver in a low power mode. This field drives the output port 'xpcs_rx_disable_o[0]'." "0,1" newline rbitfld.word 0x5 6.--7. "RX3_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 4.--5. "RX2_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 2.--3. "RX1_PSTATE,Reserved" "0,1,2,3" newline bitfld.word 0x5 0.--1. "RX0_PSTATE,Rx power state control for PHY lane 0. Power state encoding is as follows : - 2'b00: P0 - 2'b01: P0s - 2'b10: P1 - 2'b11: P2" "0: P0,1: P0s,2: P1,3: P2" line.word 0x6 "VR_MII_Gen5_12G_16G_RX_CDR_CTRL,VR MII PHY Rx CDR Control" rbitfld.word 0x6 9.--11. "VCO_LOW_FREQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 8. "VCO_LOW_FREQ_0,Rx VCO lower frequency band mode on lane 0 of the PHY This field controls the frequency of the Rx VCO to a lower-frequency operating band. This field drives the output port xpcs_rx_cdr_vco_lowfreq_o[0]." "0,1" newline rbitfld.word 0x6 5.--7. "CDR_SSC_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 4. "CDR_SSC_EN_0,Rx CDR SSC Mode Enable on lane 0 of the PHY This field controls the CDR tracking gains and duration. This bit should be set to 1 when receive data has a spread spectrum clock and should be cleared if receive data does not have SSC. This bit.." "0,1" newline rbitfld.word 0x6 1.--3. "CDR_TRACK_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 0. "CDR_TRACK_EN_0,Rx CDR Tracking Enable on lane 0 of the PHY This bit should be set to enable CDR tracking of receive data on lane 0 of the PHY. This bit drives the output port 'xpcs_rx_cdr_track_en_o[0]'." "0,1" line.word 0x7 "VR_MII_Gen5_12G_16G_RX_ATTN_CTRL,VR MII PHY Rx Attenuation Control" rbitfld.word 0x7 12.--14. "RX3_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x7 8.--10. "RX2_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x7 4.--6. "RX1_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x7 0.--2. "RX0_EQ_ATT_LVL,Rx Equalization Attenuation level for lane 0 of the PHY This field drives the output port xpcs_rx0_eq_att_lvl_o[2:0]. This field controls the AFE attenuation level of the PHY." "0,1,2,3,4,5,6,7" line.word 0x8 "VR_MII_Gen5_12G_RX_EQ_CTRL0,VR MII PHY Rx Equalization Control 0" hexmask.word.byte 0x8 12.--15. 1. "AFE_GAIN_0,Rx Equalization AFE Gain on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_afe_gain_o[3:0]." newline hexmask.word.byte 0x8 0.--4. 1. "CTLE_BOOST_0,Rx Equalization CTLE Boost value on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_ctle_boost_o[4:0].This field controls the CTLE boost level." group.word 0x1F805C++0x5 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_EQ_CTRL4,VR MII PHY Rx Equalization Control 4" rbitfld.word 0x0 12. "RX_AD_REQ,Reserved" "0,1" newline rbitfld.word 0x0 11. "RX_EQ_STRT_CTRL,Reserved" "0,1" newline rbitfld.word 0x0 10. "SELF_MAIN_EN,Reserved" "0,1" newline rbitfld.word 0x0 9. "PING_PONG_EN,Reserved" "0,1" newline rbitfld.word 0x0 8. "SEQ_EQ_EN,Reserved" "0,1" newline rbitfld.word 0x0 5.--7. "CONT_OFF_CAN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "CONT_OFF_CAN_0,Receiver offset cancellation continuous operation on lane 0 This bit can be set if continuous receiver offset cancellation is required. If this bit is 0 offset cancellation runs when receiver exits P2 power state. This bit drives the.." "0,1" newline rbitfld.word 0x0 1.--3. "CONT_ADAPT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "CONT_ADAPT_0,Receiver Adaptation Continuous Operation on lane 0 This bit can be set to enable continuous receiver adaptation in the PHY. This bit drives the output port 'xpcs_rx_offcan_cont_o'." "0,1" line.word 0x1 "VR_MII_Gen5_12G_AFE_DFE_EN_CTRL,VR MII PHY AFE-DFE Enable" rbitfld.word 0x1 5.--7. "DFE_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "DFE_EN_0,Rx DFE Enable on lane 0 of the PHY This bit drives the output port xpcs_rx_adapt_dfe_en_o[0]. This bit can be set to enable Rx adaption and decision feedback equalization (DFE) circuitry and applies the input setting of DFE Tap1:.." "0,1" newline rbitfld.word 0x1 1.--3. "AFE_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "AFE_EN_0,Rx Adaptation AFE Enable on lane 0 of the PHY This bit drives the output port xpcs_rx_adapt_afe_en_o[0]. This bit can be set to enable Rx adaption circuitry and applies the following input receiver equalization settings to the PHY: -.." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_DFE_TAP_CTRL0,VR MII PHY DFE Tap Control 0" hexmask.word.byte 0x2 8.--15. 1. "DFE_TAP1_1,Reserved" newline hexmask.word.byte 0x2 0.--7. 1. "DFE_TAP1_0,Rx Equalization DFE Tap1 value on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_dfe_tap1_o[7:0]" rgroup.word 0x1F8060++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_STS,VR MII PHY Rx Status" bitfld.word 0x0 1.--3. "RX_ACK_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "RX_ACK_0,Rx Acknowledge on PHY lane 0. This bit captures the value of the input port xpcs_rx_ack_i[0]. If this bit is set it indicates that the requested receiver setting is complete. This bit forms a hand-shake with 'RX_REQ_0' bit. Once this bit is.." "0,1" group.word 0x1F8064++0x1 line.word 0x0 "VR_MII_Consumer_10G_RX_TERM_CTRL,VR MII PHY Receive Termination Control" bitfld.word 0x0 0.--2. "RX0_TERM,Receive Termination Control for lane 0" "0,1,2,3,4,5,6,7" group.word 0x1F806B++0x1 line.word 0x0 "VR_MII_Consumer_10G_RX_IQ_CTRL0,VR MII PHY RX IQ Control 0" hexmask.word.byte 0x0 8.--11. 1. "RX0_DELTA_IQ,RX IQ Offset Value for lane0. This field drives the output port xpcs_rx0_delta_iq_o[3:0]." group.word 0x1F8070++0x11 line.word 0x0 "VR_MII_Gen5_12G_16G_MPLL_CMN_CTRL,VR MII PHY MPLL Common Control" rbitfld.word 0x0 5.--7. "MPLLB_SEL_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "MPLLB_SEL_0,Tx MPLLB Select-lane 0 When this bit is set PHY selects MPLLB to generate Tx analog clocks on lane 0" "0,1" newline rbitfld.word 0x0 1.--3. "MPLL_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLL_EN_0,Tx MPLL Enable-lane 0 This bit should be set to power-up the MPLL.This bit should be 1 for normal operation." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_MPLLA_CTRL0,VR MII PHY MPLLA Control 0" bitfld.word 0x1 15. "MPLLA_CAL_DISABLE,MPLLA Calibration Disable This field can be programmed to 1 to disable calibration of MPLLA by PHY firmware." "0,1" newline hexmask.word.byte 0x1 0.--7. 1. "MPLLA_MULTIPLIER,MPLLA frequency Multiplier Control This field controls the multiplication of reference clock to a frequency suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset to ensure that PHY is.." line.word 0x2 "VR_MII_Gen5_12G_MPLLA_CTRL1,VR MII PHY MPLLA Control 1" hexmask.word 0x2 5.--15. 1. "MPLLA_FRACN_CTRL,MPLLA Fractional Control This field drives the output port xpcs_mplla_fracn_ctrl_o." line.word 0x3 "VR_MII_Gen5_12G_16G_MPLLA_CTRL2,VR MII PHY MPLLA Control 2" bitfld.word 0x3 11.--13. "MPLLA_TX_CLK_DIV,MPLLA Tx Clock Divider. This field drives the output port 'xpcs_mplla_tx_clk_div_o[1:0]'." "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 10. "MPLLA_DIV_CLK_EN,Enable mplla_div_clk from PHY. When asserted the frequency of mplla_div_clk from PHY is the MPLLA frequency divided by 'mplla_div_multiplier'" "0,1" newline bitfld.word 0x3 9. "MPLLA_DIV10_CLK_EN,MPLLA Divide by 10 Enable When this bit is set the frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 10." "0,1" newline bitfld.word 0x3 8. "MPLLA_DIV8_CLK_EN,MPLLA Divide by 8 Enable When this bit is set the frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 8." "0,1" newline hexmask.word.byte 0x3 0.--7. 1. "MPLLA_DIV_MULT,MPLLA Output Frequency Multiplier Control This field controls the frequency multiplication factor used to generate MPLLA clock output from the reference clock input as seen by the MPLL." line.word 0x4 "VR_MII_Gen5_12G_16G_MPLLB_CTRL0,VR MII PHY MPLLB Control 0" bitfld.word 0x4 15. "MPLLB_CAL_DISABLE,MPLLB Calibration Disable This field can be programmed to 1 to disable calibration of MPLLB by PHY firmware." "0,1" newline hexmask.word.byte 0x4 0.--7. 1. "MPLLB_MULTIPLIER,MPLLB frequency Multiplier Control This field controls the multiplication of reference clock to a frequency suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset to ensure that PHY is.." line.word 0x5 "VR_MII_Gen5_12G_MPLLB_CTRL1,VR MII PHY MPLLB Control 1" hexmask.word 0x5 5.--15. 1. "MPLLB_FRACN_CTRL,MPLLB Fractional Control This field drives the output port 'xpcs_mpllb_fracn_ctrl_o'." line.word 0x6 "VR_MII_Gen5_12G_16G_MPLLB_CTRL2,VR MII PHY MPLLB Control 2" bitfld.word 0x6 11.--13. "MPLLB_TX_CLK_DIV,MPLLB Tx Clock Divider. This field drives the output port 'xpcs_mpllb_tx_clk_div_o[1:0]'." "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 10. "MPLLB_DIV_CLK_EN,Enable mpllb_div_clk from PHY When asserted the frequency of mpllb_div_clk output from PHY is MPLLB frequency divided by 'mpllb_div_multiplier'" "0,1" newline bitfld.word 0x6 9. "MPLLB_DIV10_CLK_EN,MPLLB Divide by 10 Enable When this bit is set the frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 10." "0,1" newline bitfld.word 0x6 8. "MPLLB_DIV8_CLK_EN,MPLLB Divide by 8 Enable When this bit is set the frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 8." "0,1" newline hexmask.word.byte 0x6 0.--7. 1. "MPLLB_DIV_MULT,MPLLB Output Frequency Multiplier Control This field controls the frequency multiplication factor used to generate MPLLB clock output from the reference clock input as seen by the MPLL." line.word 0x7 "VR_MII_Gen5_12G_MPLLA_CTRL3,VR MII PHY MPLLA Control 3" hexmask.word 0x7 0.--15. 1. "MPLLA_BANDWIDTH,MPLLA Bandwidth Control This field controls the bandwidth of MPLLA present in the PHY. This field drives the output port 'xpcs_mplla_bandwidth_o'." line.word 0x8 "VR_MII_Gen5_12G_MPLLB_CTRL3,VR MII PHY MPLLB Control 3" hexmask.word 0x8 0.--15. 1. "MPLLB_BANDWIDTH,MPLLB Bandwidth Control This field controls the bandwidth of MPLLB present in the PHY. This field drives the output port 'xpcs_mpllb_bandwidth_o'." group.word 0x1F8090++0x5 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_CTRL0,VR MII PHY Miscellaneous Control 0" bitfld.word 0x0 15. "PLL_CTRL,PLL Reinitialization Control" "0,1" newline bitfld.word 0x0 14. "CR_PARA_SEL,Select CR Para Port This bit select the interface for accessing PHY registers * 0 -JTAG * 1 -CR parallel port This bit should be changed only after disabling 'jtag_tck'to PHY." "0,1" newline bitfld.word 0x0 13. "RTUNE_REQ,Resistor Tuning Request This bit can be set to trigger a resistor tune request to the PHY. This bit controls the 'xgxs_rtune_req_o' output port." "0,1" newline hexmask.word.byte 0x0 8.--12. 1. "RX_VREF_CTRL,Rx Biasing Current Control" newline rbitfld.word 0x0 5.--7. "RX2TX_LB_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "RX2TX_LB_EN_0,Enable Parallel Rx-to-Tx Loopback on lane 0 When this bit is set recovered parallel data from PHY receiver is looped back to the transmit serializer. This loop-back takes place internal to the PHY (not within XPCS)." "0,1" newline rbitfld.word 0x0 1.--3. "TX2RX_LB_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TX2RX_LB_EN_0,Enable Analog Tx-to-Rx Serial Loopback on lane 0 This bit can be set to enable serial loopback in the PHY from Tx pre-driver to Rx analog front-end." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_REF_CLK_CTRL,VR MII SPHY Reference Control" bitfld.word 0x1 8. "REF_RPT_CLK_EN,Repeat Reference Clock Enable If this bit is set ref_repeat_clk_{p m} clock from PHY is enabled." "0,1" newline bitfld.word 0x1 7. "REF_MPLLB_DIV2,MPLLB Reference Clock Divider Control" "0,1" newline bitfld.word 0x1 6. "REF_MPLLA_DIV2,MPLLA Reference Clock Divider Control" "0,1" newline bitfld.word 0x1 3.--5. "REF_RANGE,Input Reference Clock Range" "0: 20 - 26 MHz,1: 26.1 - 52 MHz,2: 52.1 - 78 MHz,3: 78.1 - 104 MHz,4: 104.1 - 130 MHz,5: 130.1 - 156 MHz,6: 156.1 - 182 MHz,7: 182.1 - 200 MHz" newline bitfld.word 0x1 2. "REF_CLK_DIV2,Reference Clock divide by 2" "0,1" newline bitfld.word 0x1 1. "REF_USE_PAD,Use Pad Clock As Reference Clock" "0: Internal PLL,1: External clock" newline bitfld.word 0x1 0. "REF_CLK_EN,Reference Clock Enable" "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_VCO_CAL_LD0,VR MII PHY VCO Calibration Load 0" hexmask.word 0x2 0.--12. 1. "VCO_LD_VAL_0,Rx VCO calibration load value on lane 0 of the PHY" group.word 0x1F8096++0x1 line.word 0x0 "VR_MII_Gen5_12G_VCO_CAL_REF0,VR MII PHY VCO Calibration Reference 0" hexmask.word.byte 0x0 8.--13. 1. "VCO_REF_LD_1,Reserved" newline hexmask.word.byte 0x0 0.--5. 1. "VCO_REF_LD_0,Rx VCO calibration reference load value -lane 0" rgroup.word 0x1F8098++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_STS,VR MII PHY Miscellaneous Status" bitfld.word 0x0 11. "REF_CLKDET_RESULT,Reserved" "0,1" newline bitfld.word 0x0 10. "MPLLB_STS,Status of MPLLB from PHY This bit denotes the value of xpcs_mpllb_state_i input." "0,1" newline bitfld.word 0x0 9. "MPLLA_STS,Status of MPLLA from PHY. This bit denotes the value of xpcs_mplla_state_i input" "0,1" newline bitfld.word 0x0 8. "RTUNE_ACK,Acknowledgment for Resistor Tune Request This bit denotes the value of 'xgxs_rtune_ack_i' input." "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "FOM,Reserved" group.word 0x1F8099++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_CTRL1,VR MII PHY Miscellaneous Control 1" hexmask.word 0x0 0.--15. 1. "RX_LNK_UP_TIME,Wait Time before PLL Re-initialization" group.word 0x1F80A0++0x5 line.word 0x0 "VR_MII_SNPS_CR_CTRL,VR MII PHY CR Control" bitfld.word 0x0 1. "WR_RDN,Write or Read Indicator This bit indicates whether a read or write operation is to be performed to the Synopsys PHY registers: - 0: Read - 1: Write" "0: Read,1: Write" newline bitfld.word 0x0 0. "START_BUSY,Start CR Port Access or Busy Indicator (WS SC Type)" "0,1" line.word 0x1 "VR_MII_SNPS_CR_ADDR,VR MII PHY CR Address" hexmask.word 0x1 0.--15. 1. "ADDRESS,CR Port Address" line.word 0x2 "VR_MII_SNPS_CR_DATA,VR MII CR Data" hexmask.word 0x2 0.--15. 1. "DATA,CR Port Data" group.word 0x1F80E1++0x1 line.word 0x0 "VR_MII_DIG_CTRL2,VR MII MMD Digital Control 2" bitfld.word 0x0 4. "TX_POL_INV_0,Tx Polarity Invert" "0: Not inverted,1: Inverted" newline bitfld.word 0x0 0. "RX_POL_INV_0,Rx Polarity Invert" "0: Not inverted,1: Inverted" tree.end tree "SERDES_XPCS_1" base ad:0x40482800 group.word 0x1F0000++0x1 line.word 0x0 "SR_MII_CTRL,SR MII MMD Control" bitfld.word 0x0 15. "RST,Soft reset (RW SC type)" "0,1" newline bitfld.word 0x0 14. "LBE,Loopback enable" "0,1" newline bitfld.word 0x0 13. "SS13,Speed selection (LSB)" "0,1" newline bitfld.word 0x0 12. "AN_ENABLE,Enable auto-negotiation" "0,1" newline bitfld.word 0x0 11. "LPM,Power-down mode" "0: Normal operation,1: The XPCS and the PHY enter Power-down mode. To.." newline bitfld.word 0x0 9. "RESTART_AN,Restart auto-negotiation (RW SC type)" "0,1" newline bitfld.word 0x0 8. "DUPLEX_MODE,Duplex mode" "0: Half duplex,1: Full duplex" newline bitfld.word 0x0 6. "SS6,Speed selection" "0,1" newline rbitfld.word 0x0 5. "SS5,Reserved" "0,1" rgroup.word 0x1F0001++0x5 line.word 0x0 "SR_MII_STS,SR MII MMD Status" bitfld.word 0x0 15. "ABL100T4,100BASE-T4 ability" "0,1" newline bitfld.word 0x0 14. "FD100ABL,100BASE-X full-duplex ability" "0,1" newline bitfld.word 0x0 13. "HD100ABL,100BASE-X half-duplex ability" "0,1" newline bitfld.word 0x0 12. "FD10ABL,10 Mbps full-duplex ability" "0,1" newline bitfld.word 0x0 11. "HD10ABL,10 Mbps half-duplex ability" "0,1" newline bitfld.word 0x0 10. "FD100T,100BASE-T2 full-duplex ability" "0,1" newline bitfld.word 0x0 9. "HD100T,100BASE-T2 half-duplex ability" "0,1" newline bitfld.word 0x0 8. "EXT_STS_ABL,Extended status information" "0: No extended status information is present at..,1: Extended Status information is present at.." newline bitfld.word 0x0 7. "UN_DIR_ABL,Unidirectional ability" "0: The XPCS is able to transmit GMII only when the..,1: The XPCS is able to transmit GMII irrespective.." newline bitfld.word 0x0 6. "MF_PRE_SUP,MF preamble suppression" "0: The XPCS does not accept the MDIO frames with..,1: The XPCS accepts the MDIO frames with preamble.." newline bitfld.word 0x0 5. "AN_CMPL,Auto-negotiation complete" "0: The AN process is not complete.,1: The AN process is complete." newline bitfld.word 0x0 4. "RF,Remote fault (RO LH type)" "0: The XPCS did not detect a remote fault.,1: The XPCS detected a remote fault." newline bitfld.word 0x0 3. "AN_ABL,Auto-negotiation ability" "0: The XPCS is unable to perform auto-negotiation.,1: The XPCS is able to perform auto-negotiation." newline bitfld.word 0x0 2. "LINK_STS,Link status (RO LL type)" "0: Link down,1: Link up" newline bitfld.word 0x0 0. "EXT_REG_CAP,Extended register capability" "0: Extended register capability does not exist,1: Extended Register capability exists" line.word 0x1 "SR_MII_DEV_ID1,SR MII MMD Device Identifier 1" hexmask.word 0x1 0.--15. 1. "VS_MII_DEV_OUI_3_18,Organizationally Unique Identifier[3:18]" line.word 0x2 "SR_MII_DEV_ID2,SR MII MMD Device Identifier 2" hexmask.word.byte 0x2 10.--15. 1. "VS_MMD_DEV_OUI_19_24,Organizationally unique identifier [19:24]" newline hexmask.word.byte 0x2 4.--9. 1. "VS_MMD_DEV_MMN_5_0,Model number" newline hexmask.word.byte 0x2 0.--3. 1. "VS_MMD_DEV_RN_3_0,Revision number" group.word 0x1F0004++0x1 line.word 0x0 "SR_MII_AN_ADV,SR MII MMD AN Advertisement" rbitfld.word 0x0 15. "NP,Next page" "0,1" newline bitfld.word 0x0 12.--13. "RF,Remote fault" "0: No error,1: Offline,2: Link failure,3: Auto-negotiation error" newline bitfld.word 0x0 7.--8. "PAUSE,Pause ability" "0: No pause,1: Asymmetric pause towards the link partner,2: Symmetric pause,3: Symmetric pause and asymmetric pause towards the.." newline bitfld.word 0x0 6. "HD,Half duplex" "0,1" newline bitfld.word 0x0 5. "FD,Full duplex" "0,1" rgroup.word 0x1F0005++0x3 line.word 0x0 "SR_MII_LP_BABL,SR MII MMD AN Link Partner Base Ability" bitfld.word 0x0 15. "LP_NP,Next page" "0,1" newline bitfld.word 0x0 14. "LP_ACK,ACK bit from the link partner" "0,1" newline bitfld.word 0x0 12.--13. "LP_RF,Remote fault" "0: No error,1: Offline,2: Link failure,3: Auto-negotiation error" newline bitfld.word 0x0 7.--8. "LP_PAUSE,Pause ability" "0: No pause,1: Asymmetric pause towards the link partner,2: Symmetric pause,3: Both symmetric pause and asymmetric pause.." newline bitfld.word 0x0 6. "LP_HD,Half duplex" "0,1" newline bitfld.word 0x0 5. "LP_FD,Full duplex" "0,1" line.word 0x1 "SR_MII_EXPN,SR MII MMD AN Expansion" bitfld.word 0x1 2. "LD_NP_ABL,Local device next page able" "0: The local device does not have the next-page..,1: The local device has the next-page ability" newline bitfld.word 0x1 1. "PG_RCVD,Page received (RO LH type)" "0: The local device did not receive a new page,1: The local device received a new page" rgroup.word 0x1F000F++0x1 line.word 0x0 "SR_MII_EXT_STS,SR MII MMD Extended Status" bitfld.word 0x0 15. "CAP_1G_X_FD,1000BASE-X full-duplex capable" "0: Not capable of 1000BASE-X full-duplex,1: Capable of 1000BASE-X full-duplex" newline bitfld.word 0x0 14. "CAP_1G_X_HD,1000BASE-X half-duplex capable" "0: Not capable of 1000BASE-X half-duplex,1: Capable of 1000BASE-X half-duplex" newline bitfld.word 0x0 13. "CAP_1G_T_FD,1000BASE-T full-duplex capable" "0: Not capable of 1000BASE-T full-duplex,1: Capable of 1000BASE-T full-duplex" newline bitfld.word 0x0 12. "CAP_1G_T_HD,1000BASE-T half-duplex capable" "0: Not capable of 1000BASE-T half-duplex,1: Capable of 1000BASE-T half-duplex" rgroup.word 0x1F0708++0x11 line.word 0x0 "SR_MII_TIME_SYNC_ABL,SR MII MMD Time Sync Capability" bitfld.word 0x0 1. "MII_TX_DLY_ABL,XPCS transmit path data delay information available" "0,1" newline bitfld.word 0x0 0. "MII_RX_DLY_ABL,XPCS receive path data delay information available" "0,1" line.word 0x1 "SR_MII_TIME_SYNC_TX_MAX_DLY_LWR,SR MII MMD Time Sync Tx Max Delay Lower" hexmask.word 0x1 0.--15. 1. "MII_TX_MAX_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS transmit path." line.word 0x2 "SR_MII_TIME_SYNC_TX_MAX_DLY_UPR,SR MII MMD Time Sync Tx Max Delay Upper" hexmask.word 0x2 0.--15. 1. "MII_TX_MAX_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS transmit path." line.word 0x3 "SR_MII_TIME_SYNC_TX_MIN_DLY_LWR,SR MII MMD Time Sync Tx Min Delay Lower" hexmask.word 0x3 0.--15. 1. "MII_TX_MIN_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS transmit path." line.word 0x4 "SR_MII_TIME_SYNC_TX_MIN_DLY_UPR,SR MII MMD Time Sync Tx Min Delay Upper" hexmask.word 0x4 0.--15. 1. "MII_TX_MIN_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS transmit path." line.word 0x5 "SR_MII_TIME_SYNC_RX_MAX_DLY_LWR,SR MII MMD Time Sync Rx Max Delay Lower" hexmask.word 0x5 0.--15. 1. "MII_RX_MAX_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS receive path." line.word 0x6 "SR_MII_TIME_SYNC_RX_MAX_DLY_UPR,SR MII MMD Time Sync Rx Max Delay Upper" hexmask.word 0x6 0.--15. 1. "MII_RX_MAX_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS receive path." line.word 0x7 "SR_MII_TIME_SYNC_RX_MIN_DLY_LWR,SR MII MMD Time Sync Rx Min Delay Lower" hexmask.word 0x7 0.--15. 1. "MII_RX_MIN_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS receive path." line.word 0x8 "SR_MII_TIME_SYNC_RX_MIN_DLY_UPR,SR MII MMD Time Sync Rx Min Delay Upper" hexmask.word 0x8 0.--15. 1. "MII_RX_MIN_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS receive path." group.word 0x1F8000++0x9 line.word 0x0 "VR_MII_DIG_CTRL1,VR MII MMD Digital Control 1" bitfld.word 0x0 15. "VR_RST,Vendor-specific soft reset (RW SC type)" "0,1" newline bitfld.word 0x0 14. "R2TLBE,Rx to Tx loopback enable" "0: Loopback path is disabled,1: Loopback path is enabled" newline rbitfld.word 0x0 13. "EN_VSMMD1,Enable vendor-specific MMD1" "0,1" newline bitfld.word 0x0 11. "PWRSV,Power save" "0: Normal operation,1: XPCS and the PHY enter the power-save mode" newline rbitfld.word 0x0 10. "CS_EN,Reserved" "0,1" newline bitfld.word 0x0 9. "MAC_AUTO_SW,Automatic Speed Mode Change after CL37 AN" "0,1" newline bitfld.word 0x0 8. "INIT,Datapath initialization control" "0,1" newline rbitfld.word 0x0 7. "MSK_RD_ERR,Mask running disparity error" "0,1" newline bitfld.word 0x0 6. "PRE_EMP,Pre-emption packet enable" "0,1" newline bitfld.word 0x0 4. "DTXLANED_0,Tx lane 0 disable" "0,1" newline bitfld.word 0x0 3. "CL37_TMR_OVR_RIDE,Override control for CL37 link timer" "0,1" newline bitfld.word 0x0 2. "EN_2_5G_MODE,Enable 2.5G GMII mode" "0,1" newline bitfld.word 0x0 1. "BYP_PWRUP,Bypass power-up sequence" "0: The XPCS waits for the MPLL Tx or Rx PLL status..,1: The XPCS bypasses the normal flow of the.." newline rbitfld.word 0x0 0. "PHY_MODE_CTRL,When SGMII_PHY_AN_AUTO_RESTART=Enabled or QSGMII_PHY_AN_AUTO_RESTART=Enabled: PHY mode control" "0: SGMII/QSGMII(Port0) autonegotiation advertises..,1: XPCS advertises the values of input ports.." line.word 0x1 "VR_MII_AN_CTRL,VR MII MMD AN Control" bitfld.word 0x1 8. "MII_CTRL,MII Control This bit controls the width of the MAC interface when operating at SGMII/QSGMII/USXGMII speed modes of 10 Mbps or 100 Mbps - 0: 4-bit MII - 1: 8-bit MII This bit also controls the xpcs_mii_ctrl_o signal which is used for external.." "0: 4-bit MII,1: 8-bit MII This bit also controls the.." newline bitfld.word 0x1 4. "SGMII_LINK_STS,SGMII Link Status/ USXGMII Link Status /QSGMII Port0 Link Status" "0,1" newline bitfld.word 0x1 3. "TX_CONFIG,Transmit configuration" "0: Configures the XPCS as the MAC side..,1: Configures the XPCS as the PHY side.." newline bitfld.word 0x1 1.--2. "PCS_MODE,PCS mode" "0: 1000BASE-X mode (clause 37 auto-negotiation is..,?,2: SGMII mode (clause 37 auto-negotiation is as per..,3: QSGMII mode (clause 37 auto-negotiation conforms.." newline bitfld.word 0x1 0. "MII_AN_INTR_EN,Clause 37 AN complete interrupt enable" "0: The Clause 37 auto-negotiation complete..,1: The Clause 37 auto-negotiation complete.." line.word 0x2 "VR_MII_AN_INTR_STS,VR MII MMD AN Interrupt And Status" hexmask.word.byte 0x2 8.--14. 1. "USXG_AN_STS,Reserved" newline rbitfld.word 0x2 6. "LP_CK_STP,Link Partner EEE Clock Stop Capability This field indicates the EEE clock stop capability (or clock-stop enabe - in case far-end is acting as QSGMII MAC) advertised by the far-end device. This field is valid only when PCS_MODE[1:0] is set to.." "0,1" newline rbitfld.word 0x2 5. "LP_EEE_CAP,Link Partner EEE Capability This field indicates the EEE capability advertised by the far-end device (Port 0 QSGMII PHY). This field is valid only when PCS_MODE[1:0] is set to the QSGMII mode and the auto-negotiation is complete along port 0." "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "CL37_ANSGM_STS,Clause 37 AN SGMII Status/QSGMII Port 0 Status This field is valid only when the PCS_MODE[1:0] is set to the SGMII/QSGMII mode and the auto-negotiation is complete. It indicates the status received from remote link after the SGMII/QSGMII.." newline bitfld.word 0x2 0. "CL37_ANCMPLT_INTR,Clause 37 AN Complete Interrupt (SS WC Type) The XPCS sets this bit when Clause 37 auto-negotiation is complete. The host must clear this bit by writing 0 to it." "0,1" line.word 0x3 "VR_MII_TC,VR MII MMD Test Control" bitfld.word 0x3 2. "TPE,Test Pattern Enable Lanes" "0,1" newline bitfld.word 0x3 0.--1. "TP,Test Pattern Select" "0,1,2,3" line.word 0x5 "VR_MII_DBG_CTRL,VR MII MMD Debug Control" bitfld.word 0x5 6. "RX_DT_EN_CTL,Rx Data Enable Control" "0,1" newline rbitfld.word 0x5 5. "SUPRESS_EEE_LOS_DET,Reserved" "0,1" newline bitfld.word 0x5 4. "SUPRESS_LOS_DET,Suppress Loss of Signal Detection" "0,1" newline bitfld.word 0x5 0. "RESTAR_SYNC_0,Restart Synchronization" "0,1" group.word 0x1F800A++0x1 line.word 0x0 "VR_MII_LINK_TIMER_CTRL,VR MII MMD Link Timer Control" hexmask.word 0x0 0.--15. 1. "CL37_LINK_TIME,Programmable Link Timer Value for Clause 37 autonegotiation. This field can be programmed to any desired value if application wishes to over-ride the standard specified values for Link Timer used during Clause 37 Auto negotiation. Link.." rgroup.word 0x1F8010++0x3 line.word 0x0 "VR_MII_DIG_STS,VR MII MMD Digital Status" bitfld.word 0x0 13.--15. "LTX_STATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "LRX_STATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "RXFIFO_OVF,Rx FIFO Overflow (RO LH Type) This bit indicates the clock rate compensation FIFO overflow. - 0: Normal operation - 1: FIFO overflow" "0: Normal operation,1: FIFO overflow" newline bitfld.word 0x0 5. "RXFIFO_UNDF,Rx FIFO Underflow (RO LH Type) This bit indicates the clock rate compensation FIFO underflow. - 0: Normal operation - 1: FIFO underflow" "0: Normal operation,1: FIFO underflow" newline bitfld.word 0x0 2.--4. "PSEQ_STATE,Power Up Sequence State" "0: Wait for ACK High 0,1: Wait for ACK Low 0,2: Wait for ACK High 1,3: Wait for ACK Low 1,4: Tx/Rx stable (Power_Good state),5: Power Save state,6: Power Down state,?" newline bitfld.word 0x0 1. "LB_ACTIVE,Reserved" "0,1" line.word 0x1 "VR_MII_ICG_ERRCNT1,VR MII MMD Invalid Code Group Error Count 1" hexmask.word.byte 0x1 0.--7. 1. "EC0,Invalid Code Group Count Lane 0 (RO LH Type) This field gives the invalid code group count in Lane 0 when Bit 4 of VR MII MMD Digital Error Count Select Register is set to 1." group.word 0x1F8012++0x1 line.word 0x0 "VR_MII_DIG_ERRCNT_SEL,VR MII MMD Digital Error Count Select" bitfld.word 0x0 4. "INV_EC_EN,Invalid Code Group Error Counter Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 0. "COR,Clear on Read" "0: Normal operation,1: Clear any error counter that is read" group.word 0x1F8015++0x1 line.word 0x0 "VR_MII_GPIO,VR MII MMD GPIO" hexmask.word.byte 0x0 8.--15. 1. "GPIO_OUT,GPIO Output The content written on this field is driven to the xpcs_gpo_o[7:0] output port. Dependency: This field is valid only when GPIO_EN = Enabled." newline hexmask.word.byte 0x0 0.--7. 1. "GPIO_IN,GPIO Input This field indicates the content of the xpcs_gpo_i[7:0] port. Dependency: This field is valid only when GPIO_EN = Enabled." rgroup.word 0x1F8018++0x1 line.word 0x0 "VR_MII_MISC_STS,VR MII MMD Miscellaneous Status" hexmask.word.byte 0x0 0.--3. 1. "BIT_SFT,Bit Shift This field indicates the number of bit-shifts carried-out by comma-detect logic so as to align the incoming 10-bit XGXS Rx data Default Value: The default value of this field can be any value depending on the status of comma-detect.." rgroup.word 0x1F8020++0x1 line.word 0x0 "VR_MII_RX_LSTS,VR MII PHY Rx Lane Status" bitfld.word 0x0 13.--15. "RX_VALID_3_1,DPLL Lock Status for Lanes[3:1]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "RX_VALID_0,DPLL Lock Status for Lane 0" "0,1" newline bitfld.word 0x0 9.--11. "RX_PLL_STATE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "RX_PLL_STATE_0,Reserved" "0,1" newline bitfld.word 0x0 5.--7. "SIG_DET_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "SIG_DET_0,Rx Signal Detect for Lane 0" "0,1" group.word 0x1F8030++0xF line.word 0x0 "VR_MII_Gen5_12G_16G_TX_GENCTRL0,VR MII PHY Tx General Control 0" rbitfld.word 0x0 13.--15. "TX_DT_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "TX_DT_EN_0,Tx Data Enable on PHY lane 0" "0,1" newline rbitfld.word 0x0 9.--11. "TX_RST_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "TX_RST_0,Tx Reset on PHY lane 0" "0,1" newline rbitfld.word 0x0 5.--7. "TX_INV_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "TX_INV_0,Tx Invert on PHY lane 0" "0,1" newline rbitfld.word 0x0 1.--3. "TXBCN_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TXBCN_EN_0,Tx Beaconing Enable on PHY lane 0" "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_TX_GENCTRL1,VR MII PHY Tx General Control 1" rbitfld.word 0x1 13.--15. "TX_CLK_RDY_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 12. "TX_CLK_RDY_0,Transmitter Input clock ready on lane 0" "0,1" newline bitfld.word 0x1 8.--10. "VBOOST_LVL,Tx Voltage Boost Maximum Level" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x1 5.--7. "VBOOST_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "VBOOST_EN_0,Tx voltage Boost Enable on PHY lane 0" "0,1" newline rbitfld.word 0x1 1.--3. "DET_RX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "DET_RX_REQ_0,Transmitter Rx-Detection request on PHY lane 0." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_TX_GENCTRL2,VR MII PHY Tx General Control 2" rbitfld.word 0x2 14.--15. "TX3_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 12.--13. "TX2_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 10.--11. "TX1_WIDTH,Reserved" "0,1,2,3" newline bitfld.word 0x2 8.--9. "TX0_WIDTH,Tx Datapath Width on lane 0 of the PHY This field controls the width of input transmit data on lane 0. The encoding of the width is as follows : - 2'b00 : 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit This field drives the output port.." "0: 8-bit,1: 10-bit,2: 16-bit,3: 20-bit This field drives the output port.." newline rbitfld.word 0x2 5.--7. "TX_LPD_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "TX_LPD_0,Transmitter Lane Power Down on PHY lane 0. This field drives the output 'xpcs_tx_lpd_o[3:1]'. This field can be asserted to put the phy transmitter to a power state equivalent to that of P1." "0,1" newline rbitfld.word 0x2 1.--3. "TX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 0. "TX_REQ_0,Transmitter operation request on PHY lane 0 (RW SC Type)" "0,1" line.word 0x3 "VR_MII_Gen5_12G_16G_TX_BOOST_CTRL,VR MII PHY Tx Boost Control" hexmask.word.byte 0x3 12.--15. 1. "TX3_IBOOST,Reserved" newline hexmask.word.byte 0x3 8.--11. 1. "TX2_IBOOST,Reserved" newline hexmask.word.byte 0x3 4.--7. 1. "TX1_IBOOST,Reserved" newline hexmask.word.byte 0x3 0.--3. 1. "TX0_IBOOST,Tx current boost level on lane 0 of the PHY. This bit drives the output port xpcs_tx0_iboost_lvl_o[3:0]." line.word 0x4 "VR_MII_Gen5_12G_16G_TX_RATE_CTRL,VR MII PHY Tx Rate Control" rbitfld.word 0x4 12.--14. "TX3_RATE,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x4 8.--10. "TX2_RATE,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x4 4.--6. "TX1_RATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x4 0.--2. "TX0_RATE,Tx date rate on PHY lane 0." "0,1,2,3,4,5,6,7" line.word 0x5 "VR_MII_Gen5_12G_16G_TX_POWER_STATE_CTRL,VR MII PHY Tx Power State" rbitfld.word 0x5 9.--11. "TX_DISABLE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x5 8. "TX_DISABLE_0,Transmitter Disable on lane 0 This field drives the output port 'xpcs_tx_disable_o[0]'." "0,1" newline rbitfld.word 0x5 6.--7. "TX3_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 4.--5. "TX2_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 2.--3. "TX1_PSTATE,Reserved" "0,1,2,3" newline bitfld.word 0x5 0.--1. "TX0_PSTATE,Tx power state control for PHY lane 0." "0,1,2,3" line.word 0x6 "VR_MII_Gen5_12G_16G_TX_EQ_CTRL0,VR MII PHY Tx Equalization Control 0" hexmask.word.byte 0x6 8.--13. 1. "TX_EQ_MAIN,Control for setting Tx driver output amplitude" newline hexmask.word.byte 0x6 0.--5. 1. "TX_EQ_PRE,Tx Pre-Emphasis level adjustment Control" line.word 0x7 "VR_MII_Gen5_12G_16G_TX_EQ_CTRL1,VR MII PHY Tx Equalization Control 1" rbitfld.word 0x7 8. "CA_TX_EQ,Reserved" "0,1" newline rbitfld.word 0x7 7. "TX_EQ_DEF_CTRL,Reserved" "0,1" newline rbitfld.word 0x7 6. "TX_EQ_OVR_RIDE,Reserved" "0,1" newline hexmask.word.byte 0x7 0.--5. 1. "TX_EQ_POST,Tx Post-Emphasis level adjustment Control This field controls the transmitter driver output pre-emphasis (pre-shoot coefficient). This field drives the output port 'rpcs_ktx_post_o' if 'TX_EQ_OVR_RIDE' bit is set or in configurations with.." group.word 0x1F803C++0x1 line.word 0x0 "VR_MII_Consumer_10G_TX_TERM_CTRL,VR MII PHY Transmit Termination Control" bitfld.word 0x0 0.--2. "TX0_TERM,Transmit Termination Control for lane 0" "0,1,2,3,4,5,6,7" rgroup.word 0x1F8040++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_TX_STS,VR MII PHY Tx Status" bitfld.word 0x0 5.--7. "DETRX_RSLT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "DETRX_RSLT_0,Receiver Detection Result on PHY lane 0. This field captures the value of the input port 'xpcs_tx_detrx_result_o[0]'. The value of this field is valid when 'TX_ACK_0' is high. - 1'b0: Receiver not detected - 1'b1: Receiver detected" "0: Receiver not detected,1: Receiver detected" newline bitfld.word 0x0 1.--3. "TX_ACK_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TX_ACK_0,Tx Acknowledge on PHY lane 0. This bit captures the value of the input port 'xpcs_tx_ack_i[0]'. Whenever this bit is read as high it indicates that the requested transmitter setting is complete or the requested RX-detection operation is.." "0,1" group.word 0x1F8050++0x11 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_GENCTRL0,VR MII PHY Rx General Control 0" rbitfld.word 0x0 13.--15. "RX_CLKSFT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "RX_CLKSFT_0,Rx clock shift on PHY lane 0. When this bit is set a 1-bit shift of receive data happens relate to receive clock. This operation works only if alignment enable is disabled. This bit drives the output port 'xpcs_rx_clk_shift_o[0]'." "0,1" newline rbitfld.word 0x0 9.--11. "RX_DT_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "RX_DT_EN_0,Rx Data Enable on PHY lane 0. This bit should be set to enable the PHY receiver data output on lane 0. This bit drives the output port 'xgxs_rx_data_en_o[0]'." "0,1" newline rbitfld.word 0x0 5.--7. "RX_ALIGN_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "RX_ALIGN_EN_0,Rx Data Alignment Enable on PHY lane 0. This bit can be set to enable word alignment (based on k28.5 character) in the PHY. This field drives the output port 'xgxs_rx_align_en_o[0]'." "0,1" newline rbitfld.word 0x0 1.--3. "RX_TERM_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "RX_TERM_EN_0,Rx Termination Enable on PHY lane 0. When this bit is set PHY Rx is terminated with a nominal 50 ohm resistance. Otherwise the termination is in high impedance. This field drives the output port 'xpcs_rx_term_en_o[0]'." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_RX_GENCTRL1,VR MII PHY Rx General Control 1" rbitfld.word 0x1 9.--11. "RX_TERM_ACDC_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 8. "RX_TERM_ACDC_0,Rx Termination control on PHY lane 0. - 0: DC Termination (Floating Rx) - 1: AC Termination (Grounded Rx) This field drives the output port xpcs_rx_term_acdc_o[0]." "0: DC Termination,1: AC Termination" newline rbitfld.word 0x1 5.--7. "RX_RST_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "RX_RST_0,Rx reset on PHY lane 0. When this bit is set RX data path all the receiver settings and state machines of the PHY are reset This field drives the output port xgxs_rx_reset_o[0] when XPCS is in POWER_GOOD state." "0,1" newline rbitfld.word 0x1 1.--3. "RX_INV_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "RX_INV_0,Rx Data Invert on PHY lane 0. When this bit is set the data on PHY Rx serial lines are logically inverted. This signal drives the output port xgxs_rx_invert_o[0]." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_RX_GENCTRL2,VR MII PHY Rx General Control 2" rbitfld.word 0x2 14.--15. "RX3_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 12.--13. "RX2_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 10.--11. "RX1_WIDTH,Reserved" "0,1,2,3" newline bitfld.word 0x2 8.--9. "RX0_WIDTH,Rx Datapath Width on lane 0 of the PHY This field controls the width of output receive data from PHY on lane 3. The encoding of the width is as follows : - 2'b00: 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit This field drives the.." "0: 8-bit,1: 10-bit,2: 16-bit,3: 20-bit This field drives the output port.." newline rbitfld.word 0x2 5.--7. "RX_LPD_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "RX_LPD_0,Receiver Lane Power Down on PHY lane 0. This bit can be set to power down the receiver to a power state equivalent to that of P1. This bit drives the output port 'xpcs_rx_lpd_o[0]'." "0,1" newline rbitfld.word 0x2 1.--3. "RX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 0. "RX_REQ_0,Receiver operation request on PHY lane 0 (RW SC Type). This bit can be set to 1 by application.This bit is self-cleared when 'xpcs_tx_ack_i[0]' is asserted. When this bit is set a new receiver setting request is made towards the PHY.This bit.." "0,1" line.word 0x3 "VR_MII_Gen5_12G_16G_RX_GENCTRL3,VR MII PHY Rx General Control 3" rbitfld.word 0x3 13.--15. "LOS_LFPS_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 12. "LOS_LFPS_EN_0,Rx LOS LFPS Enable on lane 0 of the PHY This field drives the output port xpcs_rx_los_lfps_en_o[0] to enable the LFPS filter on lane 0 of the PHY." "0,1" newline rbitfld.word 0x3 9.--11. "LOS_TRSHLD_3,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x3 6.--8. "LOS_TRSHLD_2,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x3 3.--5. "LOS_TRSHLD_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 0.--2. "LOS_TRSHLD_0,Loss of signal threshold on PHY lane 0. This field drives the output port xpcs_rx0_los_threshold_o[2:0]. Threshold voltages for various values are as follows : - 3'b000: Reserved - 3'b001: 90 mVpp - 3'b010: 120 mVpp - 3'b011: 150 mVpp -.." "0: Reserved,1: 90 mVpp,2: 120 mVpp,3: 150 mVpp,4: 180 mVpp,5: 210 mVpp,6: 240 mVpp,7: 270 mVpp" line.word 0x4 "VR_MII_Gen5_12G_16G_RX_RATE_CTRL,VR MII PHY Rx Rate Control" rbitfld.word 0x4 12.--13. "RX3_RATE,Reserved" "0,1,2,3" newline rbitfld.word 0x4 8.--9. "RX2_RATE,Reserved" "0,1,2,3" newline rbitfld.word 0x4 4.--5. "RX1_RATE,Reserved" "0,1,2,3" newline bitfld.word 0x4 0.--1. "RX0_RATE,Rx date rate on lane 0 of the PHY Data Rate Encoding is as follows : - 2'b00: baud - 2'b01: baud/2 - 2'b10: baud/4 - 2'b11: baud/8" "0: baud,1: baud/2,2: baud/4,3: baud/8" line.word 0x5 "VR_MII_Gen5_12G_16G_RX_POWER_STATE_CTRL,VR MII PHY Rx Power State" rbitfld.word 0x5 12. "EEE_OVR_RIDE,Reserved" "0,1" newline rbitfld.word 0x5 9.--11. "RX_DISABLE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x5 8. "RX_DISABLE_0,Receiver Disable on lane 0 This bit can be set in P1 power state to put the receiver in a low power mode. This field drives the output port 'xpcs_rx_disable_o[0]'." "0,1" newline rbitfld.word 0x5 6.--7. "RX3_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 4.--5. "RX2_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 2.--3. "RX1_PSTATE,Reserved" "0,1,2,3" newline bitfld.word 0x5 0.--1. "RX0_PSTATE,Rx power state control for PHY lane 0. Power state encoding is as follows : - 2'b00: P0 - 2'b01: P0s - 2'b10: P1 - 2'b11: P2" "0: P0,1: P0s,2: P1,3: P2" line.word 0x6 "VR_MII_Gen5_12G_16G_RX_CDR_CTRL,VR MII PHY Rx CDR Control" rbitfld.word 0x6 9.--11. "VCO_LOW_FREQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 8. "VCO_LOW_FREQ_0,Rx VCO lower frequency band mode on lane 0 of the PHY This field controls the frequency of the Rx VCO to a lower-frequency operating band. This field drives the output port xpcs_rx_cdr_vco_lowfreq_o[0]." "0,1" newline rbitfld.word 0x6 5.--7. "CDR_SSC_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 4. "CDR_SSC_EN_0,Rx CDR SSC Mode Enable on lane 0 of the PHY This field controls the CDR tracking gains and duration. This bit should be set to 1 when receive data has a spread spectrum clock and should be cleared if receive data does not have SSC. This bit.." "0,1" newline rbitfld.word 0x6 1.--3. "CDR_TRACK_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 0. "CDR_TRACK_EN_0,Rx CDR Tracking Enable on lane 0 of the PHY This bit should be set to enable CDR tracking of receive data on lane 0 of the PHY. This bit drives the output port 'xpcs_rx_cdr_track_en_o[0]'." "0,1" line.word 0x7 "VR_MII_Gen5_12G_16G_RX_ATTN_CTRL,VR MII PHY Rx Attenuation Control" rbitfld.word 0x7 12.--14. "RX3_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x7 8.--10. "RX2_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x7 4.--6. "RX1_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x7 0.--2. "RX0_EQ_ATT_LVL,Rx Equalization Attenuation level for lane 0 of the PHY This field drives the output port xpcs_rx0_eq_att_lvl_o[2:0]. This field controls the AFE attenuation level of the PHY." "0,1,2,3,4,5,6,7" line.word 0x8 "VR_MII_Gen5_12G_RX_EQ_CTRL0,VR MII PHY Rx Equalization Control 0" hexmask.word.byte 0x8 12.--15. 1. "AFE_GAIN_0,Rx Equalization AFE Gain on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_afe_gain_o[3:0]." newline hexmask.word.byte 0x8 0.--4. 1. "CTLE_BOOST_0,Rx Equalization CTLE Boost value on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_ctle_boost_o[4:0].This field controls the CTLE boost level." group.word 0x1F805C++0x5 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_EQ_CTRL4,VR MII PHY Rx Equalization Control 4" rbitfld.word 0x0 12. "RX_AD_REQ,Reserved" "0,1" newline rbitfld.word 0x0 11. "RX_EQ_STRT_CTRL,Reserved" "0,1" newline rbitfld.word 0x0 10. "SELF_MAIN_EN,Reserved" "0,1" newline rbitfld.word 0x0 9. "PING_PONG_EN,Reserved" "0,1" newline rbitfld.word 0x0 8. "SEQ_EQ_EN,Reserved" "0,1" newline rbitfld.word 0x0 5.--7. "CONT_OFF_CAN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "CONT_OFF_CAN_0,Receiver offset cancellation continuous operation on lane 0 This bit can be set if continuous receiver offset cancellation is required. If this bit is 0 offset cancellation runs when receiver exits P2 power state. This bit drives the.." "0,1" newline rbitfld.word 0x0 1.--3. "CONT_ADAPT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "CONT_ADAPT_0,Receiver Adaptation Continuous Operation on lane 0 This bit can be set to enable continuous receiver adaptation in the PHY. This bit drives the output port 'xpcs_rx_offcan_cont_o'." "0,1" line.word 0x1 "VR_MII_Gen5_12G_AFE_DFE_EN_CTRL,VR MII PHY AFE-DFE Enable" rbitfld.word 0x1 5.--7. "DFE_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "DFE_EN_0,Rx DFE Enable on lane 0 of the PHY This bit drives the output port xpcs_rx_adapt_dfe_en_o[0]. This bit can be set to enable Rx adaption and decision feedback equalization (DFE) circuitry and applies the input setting of DFE Tap1:.." "0,1" newline rbitfld.word 0x1 1.--3. "AFE_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "AFE_EN_0,Rx Adaptation AFE Enable on lane 0 of the PHY This bit drives the output port xpcs_rx_adapt_afe_en_o[0]. This bit can be set to enable Rx adaption circuitry and applies the following input receiver equalization settings to the PHY: -.." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_DFE_TAP_CTRL0,VR MII PHY DFE Tap Control 0" hexmask.word.byte 0x2 8.--15. 1. "DFE_TAP1_1,Reserved" newline hexmask.word.byte 0x2 0.--7. 1. "DFE_TAP1_0,Rx Equalization DFE Tap1 value on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_dfe_tap1_o[7:0]" rgroup.word 0x1F8060++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_STS,VR MII PHY Rx Status" bitfld.word 0x0 1.--3. "RX_ACK_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "RX_ACK_0,Rx Acknowledge on PHY lane 0. This bit captures the value of the input port xpcs_rx_ack_i[0]. If this bit is set it indicates that the requested receiver setting is complete. This bit forms a hand-shake with 'RX_REQ_0' bit. Once this bit is.." "0,1" group.word 0x1F8064++0x1 line.word 0x0 "VR_MII_Consumer_10G_RX_TERM_CTRL,VR MII PHY Receive Termination Control" bitfld.word 0x0 0.--2. "RX0_TERM,Receive Termination Control for lane 0" "0,1,2,3,4,5,6,7" group.word 0x1F806B++0x1 line.word 0x0 "VR_MII_Consumer_10G_RX_IQ_CTRL0,VR MII PHY RX IQ Control 0" hexmask.word.byte 0x0 8.--11. 1. "RX0_DELTA_IQ,RX IQ Offset Value for lane0. This field drives the output port xpcs_rx0_delta_iq_o[3:0]." group.word 0x1F8070++0x11 line.word 0x0 "VR_MII_Gen5_12G_16G_MPLL_CMN_CTRL,VR MII PHY MPLL Common Control" rbitfld.word 0x0 5.--7. "MPLLB_SEL_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "MPLLB_SEL_0,Tx MPLLB Select-lane 0 When this bit is set PHY selects MPLLB to generate Tx analog clocks on lane 0" "0,1" newline rbitfld.word 0x0 1.--3. "MPLL_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLL_EN_0,Tx MPLL Enable-lane 0 This bit should be set to power-up the MPLL.This bit should be 1 for normal operation." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_MPLLA_CTRL0,VR MII PHY MPLLA Control 0" bitfld.word 0x1 15. "MPLLA_CAL_DISABLE,MPLLA Calibration Disable This field can be programmed to 1 to disable calibration of MPLLA by PHY firmware." "0,1" newline hexmask.word.byte 0x1 0.--7. 1. "MPLLA_MULTIPLIER,MPLLA frequency Multiplier Control This field controls the multiplication of reference clock to a frequency suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset to ensure that PHY is.." line.word 0x2 "VR_MII_Gen5_12G_MPLLA_CTRL1,VR MII PHY MPLLA Control 1" hexmask.word 0x2 5.--15. 1. "MPLLA_FRACN_CTRL,MPLLA Fractional Control This field drives the output port xpcs_mplla_fracn_ctrl_o." line.word 0x3 "VR_MII_Gen5_12G_16G_MPLLA_CTRL2,VR MII PHY MPLLA Control 2" bitfld.word 0x3 11.--13. "MPLLA_TX_CLK_DIV,MPLLA Tx Clock Divider. This field drives the output port 'xpcs_mplla_tx_clk_div_o[1:0]'." "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 10. "MPLLA_DIV_CLK_EN,Enable mplla_div_clk from PHY. When asserted the frequency of mplla_div_clk from PHY is the MPLLA frequency divided by 'mplla_div_multiplier'" "0,1" newline bitfld.word 0x3 9. "MPLLA_DIV10_CLK_EN,MPLLA Divide by 10 Enable When this bit is set the frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 10." "0,1" newline bitfld.word 0x3 8. "MPLLA_DIV8_CLK_EN,MPLLA Divide by 8 Enable When this bit is set the frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 8." "0,1" newline hexmask.word.byte 0x3 0.--7. 1. "MPLLA_DIV_MULT,MPLLA Output Frequency Multiplier Control This field controls the frequency multiplication factor used to generate MPLLA clock output from the reference clock input as seen by the MPLL." line.word 0x4 "VR_MII_Gen5_12G_16G_MPLLB_CTRL0,VR MII PHY MPLLB Control 0" bitfld.word 0x4 15. "MPLLB_CAL_DISABLE,MPLLB Calibration Disable This field can be programmed to 1 to disable calibration of MPLLB by PHY firmware." "0,1" newline hexmask.word.byte 0x4 0.--7. 1. "MPLLB_MULTIPLIER,MPLLB frequency Multiplier Control This field controls the multiplication of reference clock to a frequency suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset to ensure that PHY is.." line.word 0x5 "VR_MII_Gen5_12G_MPLLB_CTRL1,VR MII PHY MPLLB Control 1" hexmask.word 0x5 5.--15. 1. "MPLLB_FRACN_CTRL,MPLLB Fractional Control This field drives the output port 'xpcs_mpllb_fracn_ctrl_o'." line.word 0x6 "VR_MII_Gen5_12G_16G_MPLLB_CTRL2,VR MII PHY MPLLB Control 2" bitfld.word 0x6 11.--13. "MPLLB_TX_CLK_DIV,MPLLB Tx Clock Divider. This field drives the output port 'xpcs_mpllb_tx_clk_div_o[1:0]'." "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 10. "MPLLB_DIV_CLK_EN,Enable mpllb_div_clk from PHY When asserted the frequency of mpllb_div_clk output from PHY is MPLLB frequency divided by 'mpllb_div_multiplier'" "0,1" newline bitfld.word 0x6 9. "MPLLB_DIV10_CLK_EN,MPLLB Divide by 10 Enable When this bit is set the frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 10." "0,1" newline bitfld.word 0x6 8. "MPLLB_DIV8_CLK_EN,MPLLB Divide by 8 Enable When this bit is set the frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 8." "0,1" newline hexmask.word.byte 0x6 0.--7. 1. "MPLLB_DIV_MULT,MPLLB Output Frequency Multiplier Control This field controls the frequency multiplication factor used to generate MPLLB clock output from the reference clock input as seen by the MPLL." line.word 0x7 "VR_MII_Gen5_12G_MPLLA_CTRL3,VR MII PHY MPLLA Control 3" hexmask.word 0x7 0.--15. 1. "MPLLA_BANDWIDTH,MPLLA Bandwidth Control This field controls the bandwidth of MPLLA present in the PHY. This field drives the output port 'xpcs_mplla_bandwidth_o'." line.word 0x8 "VR_MII_Gen5_12G_MPLLB_CTRL3,VR MII PHY MPLLB Control 3" hexmask.word 0x8 0.--15. 1. "MPLLB_BANDWIDTH,MPLLB Bandwidth Control This field controls the bandwidth of MPLLB present in the PHY. This field drives the output port 'xpcs_mpllb_bandwidth_o'." group.word 0x1F8090++0x5 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_CTRL0,VR MII PHY Miscellaneous Control 0" bitfld.word 0x0 15. "PLL_CTRL,PLL Reinitialization Control" "0,1" newline bitfld.word 0x0 14. "CR_PARA_SEL,Select CR Para Port This bit select the interface for accessing PHY registers * 0 -JTAG * 1 -CR parallel port This bit should be changed only after disabling 'jtag_tck'to PHY." "0,1" newline bitfld.word 0x0 13. "RTUNE_REQ,Resistor Tuning Request This bit can be set to trigger a resistor tune request to the PHY. This bit controls the 'xgxs_rtune_req_o' output port." "0,1" newline hexmask.word.byte 0x0 8.--12. 1. "RX_VREF_CTRL,Rx Biasing Current Control" newline rbitfld.word 0x0 5.--7. "RX2TX_LB_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "RX2TX_LB_EN_0,Enable Parallel Rx-to-Tx Loopback on lane 0 When this bit is set recovered parallel data from PHY receiver is looped back to the transmit serializer. This loop-back takes place internal to the PHY (not within XPCS)." "0,1" newline rbitfld.word 0x0 1.--3. "TX2RX_LB_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TX2RX_LB_EN_0,Enable Analog Tx-to-Rx Serial Loopback on lane 0 This bit can be set to enable serial loopback in the PHY from Tx pre-driver to Rx analog front-end." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_REF_CLK_CTRL,VR MII SPHY Reference Control" bitfld.word 0x1 8. "REF_RPT_CLK_EN,Repeat Reference Clock Enable If this bit is set ref_repeat_clk_{p m} clock from PHY is enabled." "0,1" newline bitfld.word 0x1 7. "REF_MPLLB_DIV2,MPLLB Reference Clock Divider Control" "0,1" newline bitfld.word 0x1 6. "REF_MPLLA_DIV2,MPLLA Reference Clock Divider Control" "0,1" newline bitfld.word 0x1 3.--5. "REF_RANGE,Input Reference Clock Range" "0: 20 - 26 MHz,1: 26.1 - 52 MHz,2: 52.1 - 78 MHz,3: 78.1 - 104 MHz,4: 104.1 - 130 MHz,5: 130.1 - 156 MHz,6: 156.1 - 182 MHz,7: 182.1 - 200 MHz" newline bitfld.word 0x1 2. "REF_CLK_DIV2,Reference Clock divide by 2" "0,1" newline bitfld.word 0x1 1. "REF_USE_PAD,Use Pad Clock As Reference Clock" "0: Internal PLL,1: External clock" newline bitfld.word 0x1 0. "REF_CLK_EN,Reference Clock Enable" "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_VCO_CAL_LD0,VR MII PHY VCO Calibration Load 0" hexmask.word 0x2 0.--12. 1. "VCO_LD_VAL_0,Rx VCO calibration load value on lane 0 of the PHY" group.word 0x1F8096++0x1 line.word 0x0 "VR_MII_Gen5_12G_VCO_CAL_REF0,VR MII PHY VCO Calibration Reference 0" hexmask.word.byte 0x0 8.--13. 1. "VCO_REF_LD_1,Reserved" newline hexmask.word.byte 0x0 0.--5. 1. "VCO_REF_LD_0,Rx VCO calibration reference load value -lane 0" rgroup.word 0x1F8098++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_STS,VR MII PHY Miscellaneous Status" bitfld.word 0x0 11. "REF_CLKDET_RESULT,Reserved" "0,1" newline bitfld.word 0x0 10. "MPLLB_STS,Status of MPLLB from PHY This bit denotes the value of xpcs_mpllb_state_i input." "0,1" newline bitfld.word 0x0 9. "MPLLA_STS,Status of MPLLA from PHY. This bit denotes the value of xpcs_mplla_state_i input" "0,1" newline bitfld.word 0x0 8. "RTUNE_ACK,Acknowledgment for Resistor Tune Request This bit denotes the value of 'xgxs_rtune_ack_i' input." "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "FOM,Reserved" group.word 0x1F8099++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_CTRL1,VR MII PHY Miscellaneous Control 1" hexmask.word 0x0 0.--15. 1. "RX_LNK_UP_TIME,Wait Time before PLL Re-initialization" group.word 0x1F80A0++0x5 line.word 0x0 "VR_MII_SNPS_CR_CTRL,VR MII PHY CR Control" bitfld.word 0x0 1. "WR_RDN,Write or Read Indicator This bit indicates whether a read or write operation is to be performed to the Synopsys PHY registers: - 0: Read - 1: Write" "0: Read,1: Write" newline bitfld.word 0x0 0. "START_BUSY,Start CR Port Access or Busy Indicator (WS SC Type)" "0,1" line.word 0x1 "VR_MII_SNPS_CR_ADDR,VR MII PHY CR Address" hexmask.word 0x1 0.--15. 1. "ADDRESS,CR Port Address" line.word 0x2 "VR_MII_SNPS_CR_DATA,VR MII CR Data" hexmask.word 0x2 0.--15. 1. "DATA,CR Port Data" group.word 0x1F80E1++0x1 line.word 0x0 "VR_MII_DIG_CTRL2,VR MII MMD Digital Control 2" bitfld.word 0x0 4. "TX_POL_INV_0,Tx Polarity Invert" "0: Not inverted,1: Inverted" newline bitfld.word 0x0 0. "RX_POL_INV_0,Rx Polarity Invert" "0: Not inverted,1: Inverted" tree.end tree "SERDES_XPCS_1_PCIE_1" base ad:0x44182800 group.word 0x1F0000++0x1 line.word 0x0 "SR_MII_CTRL,SR MII MMD Control" bitfld.word 0x0 15. "RST,Soft reset (RW SC type)" "0,1" newline bitfld.word 0x0 14. "LBE,Loopback enable" "0,1" newline bitfld.word 0x0 13. "SS13,Speed selection (LSB)" "0,1" newline bitfld.word 0x0 12. "AN_ENABLE,Enable auto-negotiation" "0,1" newline bitfld.word 0x0 11. "LPM,Power-down mode" "0: Normal operation,1: The XPCS and the PHY enter Power-down mode. To.." newline bitfld.word 0x0 9. "RESTART_AN,Restart auto-negotiation (RW SC type)" "0,1" newline bitfld.word 0x0 8. "DUPLEX_MODE,Duplex mode" "0: Half duplex,1: Full duplex" newline bitfld.word 0x0 6. "SS6,Speed selection" "0,1" newline rbitfld.word 0x0 5. "SS5,Reserved" "0,1" rgroup.word 0x1F0001++0x5 line.word 0x0 "SR_MII_STS,SR MII MMD Status" bitfld.word 0x0 15. "ABL100T4,100BASE-T4 ability" "0,1" newline bitfld.word 0x0 14. "FD100ABL,100BASE-X full-duplex ability" "0,1" newline bitfld.word 0x0 13. "HD100ABL,100BASE-X half-duplex ability" "0,1" newline bitfld.word 0x0 12. "FD10ABL,10 Mbps full-duplex ability" "0,1" newline bitfld.word 0x0 11. "HD10ABL,10 Mbps half-duplex ability" "0,1" newline bitfld.word 0x0 10. "FD100T,100BASE-T2 full-duplex ability" "0,1" newline bitfld.word 0x0 9. "HD100T,100BASE-T2 half-duplex ability" "0,1" newline bitfld.word 0x0 8. "EXT_STS_ABL,Extended status information" "0: No extended status information is present at..,1: Extended Status information is present at.." newline bitfld.word 0x0 7. "UN_DIR_ABL,Unidirectional ability" "0: The XPCS is able to transmit GMII only when the..,1: The XPCS is able to transmit GMII irrespective.." newline bitfld.word 0x0 6. "MF_PRE_SUP,MF preamble suppression" "0: The XPCS does not accept the MDIO frames with..,1: The XPCS accepts the MDIO frames with preamble.." newline bitfld.word 0x0 5. "AN_CMPL,Auto-negotiation complete" "0: The AN process is not complete.,1: The AN process is complete." newline bitfld.word 0x0 4. "RF,Remote fault (RO LH type)" "0: The XPCS did not detect a remote fault.,1: The XPCS detected a remote fault." newline bitfld.word 0x0 3. "AN_ABL,Auto-negotiation ability" "0: The XPCS is unable to perform auto-negotiation.,1: The XPCS is able to perform auto-negotiation." newline bitfld.word 0x0 2. "LINK_STS,Link status (RO LL type)" "0: Link down,1: Link up" newline bitfld.word 0x0 0. "EXT_REG_CAP,Extended register capability" "0: Extended register capability does not exist,1: Extended Register capability exists" line.word 0x1 "SR_MII_DEV_ID1,SR MII MMD Device Identifier 1" hexmask.word 0x1 0.--15. 1. "VS_MII_DEV_OUI_3_18,Organizationally Unique Identifier[3:18]" line.word 0x2 "SR_MII_DEV_ID2,SR MII MMD Device Identifier 2" hexmask.word.byte 0x2 10.--15. 1. "VS_MMD_DEV_OUI_19_24,Organizationally unique identifier [19:24]" newline hexmask.word.byte 0x2 4.--9. 1. "VS_MMD_DEV_MMN_5_0,Model number" newline hexmask.word.byte 0x2 0.--3. 1. "VS_MMD_DEV_RN_3_0,Revision number" group.word 0x1F0004++0x1 line.word 0x0 "SR_MII_AN_ADV,SR MII MMD AN Advertisement" rbitfld.word 0x0 15. "NP,Next page" "0,1" newline bitfld.word 0x0 12.--13. "RF,Remote fault" "0: No error,1: Offline,2: Link failure,3: Auto-negotiation error" newline bitfld.word 0x0 7.--8. "PAUSE,Pause ability" "0: No pause,1: Asymmetric pause towards the link partner,2: Symmetric pause,3: Symmetric pause and asymmetric pause towards the.." newline bitfld.word 0x0 6. "HD,Half duplex" "0,1" newline bitfld.word 0x0 5. "FD,Full duplex" "0,1" rgroup.word 0x1F0005++0x3 line.word 0x0 "SR_MII_LP_BABL,SR MII MMD AN Link Partner Base Ability" bitfld.word 0x0 15. "LP_NP,Next page" "0,1" newline bitfld.word 0x0 14. "LP_ACK,ACK bit from the link partner" "0,1" newline bitfld.word 0x0 12.--13. "LP_RF,Remote fault" "0: No error,1: Offline,2: Link failure,3: Auto-negotiation error" newline bitfld.word 0x0 7.--8. "LP_PAUSE,Pause ability" "0: No pause,1: Asymmetric pause towards the link partner,2: Symmetric pause,3: Both symmetric pause and asymmetric pause.." newline bitfld.word 0x0 6. "LP_HD,Half duplex" "0,1" newline bitfld.word 0x0 5. "LP_FD,Full duplex" "0,1" line.word 0x1 "SR_MII_EXPN,SR MII MMD AN Expansion" bitfld.word 0x1 2. "LD_NP_ABL,Local device next page able" "0: The local device does not have the next-page..,1: The local device has the next-page ability" newline bitfld.word 0x1 1. "PG_RCVD,Page received (RO LH type)" "0: The local device did not receive a new page,1: The local device received a new page" rgroup.word 0x1F000F++0x1 line.word 0x0 "SR_MII_EXT_STS,SR MII MMD Extended Status" bitfld.word 0x0 15. "CAP_1G_X_FD,1000BASE-X full-duplex capable" "0: Not capable of 1000BASE-X full-duplex,1: Capable of 1000BASE-X full-duplex" newline bitfld.word 0x0 14. "CAP_1G_X_HD,1000BASE-X half-duplex capable" "0: Not capable of 1000BASE-X half-duplex,1: Capable of 1000BASE-X half-duplex" newline bitfld.word 0x0 13. "CAP_1G_T_FD,1000BASE-T full-duplex capable" "0: Not capable of 1000BASE-T full-duplex,1: Capable of 1000BASE-T full-duplex" newline bitfld.word 0x0 12. "CAP_1G_T_HD,1000BASE-T half-duplex capable" "0: Not capable of 1000BASE-T half-duplex,1: Capable of 1000BASE-T half-duplex" rgroup.word 0x1F0708++0x11 line.word 0x0 "SR_MII_TIME_SYNC_ABL,SR MII MMD Time Sync Capability" bitfld.word 0x0 1. "MII_TX_DLY_ABL,XPCS transmit path data delay information available" "0,1" newline bitfld.word 0x0 0. "MII_RX_DLY_ABL,XPCS receive path data delay information available" "0,1" line.word 0x1 "SR_MII_TIME_SYNC_TX_MAX_DLY_LWR,SR MII MMD Time Sync Tx Max Delay Lower" hexmask.word 0x1 0.--15. 1. "MII_TX_MAX_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS transmit path." line.word 0x2 "SR_MII_TIME_SYNC_TX_MAX_DLY_UPR,SR MII MMD Time Sync Tx Max Delay Upper" hexmask.word 0x2 0.--15. 1. "MII_TX_MAX_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS transmit path." line.word 0x3 "SR_MII_TIME_SYNC_TX_MIN_DLY_LWR,SR MII MMD Time Sync Tx Min Delay Lower" hexmask.word 0x3 0.--15. 1. "MII_TX_MIN_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS transmit path." line.word 0x4 "SR_MII_TIME_SYNC_TX_MIN_DLY_UPR,SR MII MMD Time Sync Tx Min Delay Upper" hexmask.word 0x4 0.--15. 1. "MII_TX_MIN_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS transmit path." line.word 0x5 "SR_MII_TIME_SYNC_RX_MAX_DLY_LWR,SR MII MMD Time Sync Rx Max Delay Lower" hexmask.word 0x5 0.--15. 1. "MII_RX_MAX_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS receive path." line.word 0x6 "SR_MII_TIME_SYNC_RX_MAX_DLY_UPR,SR MII MMD Time Sync Rx Max Delay Upper" hexmask.word 0x6 0.--15. 1. "MII_RX_MAX_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS receive path." line.word 0x7 "SR_MII_TIME_SYNC_RX_MIN_DLY_LWR,SR MII MMD Time Sync Rx Min Delay Lower" hexmask.word 0x7 0.--15. 1. "MII_RX_MIN_DLY_LWR,Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS receive path." line.word 0x8 "SR_MII_TIME_SYNC_RX_MIN_DLY_UPR,SR MII MMD Time Sync Rx Min Delay Upper" hexmask.word 0x8 0.--15. 1. "MII_RX_MIN_DLY_UPR,Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS receive path." group.word 0x1F8000++0x9 line.word 0x0 "VR_MII_DIG_CTRL1,VR MII MMD Digital Control 1" bitfld.word 0x0 15. "VR_RST,Vendor-specific soft reset (RW SC type)" "0,1" newline bitfld.word 0x0 14. "R2TLBE,Rx to Tx loopback enable" "0: Loopback path is disabled,1: Loopback path is enabled" newline rbitfld.word 0x0 13. "EN_VSMMD1,Enable vendor-specific MMD1" "0,1" newline bitfld.word 0x0 11. "PWRSV,Power save" "0: Normal operation,1: XPCS and the PHY enter the power-save mode" newline rbitfld.word 0x0 10. "CS_EN,Reserved" "0,1" newline bitfld.word 0x0 9. "MAC_AUTO_SW,Automatic Speed Mode Change after CL37 AN" "0,1" newline bitfld.word 0x0 8. "INIT,Datapath initialization control" "0,1" newline rbitfld.word 0x0 7. "MSK_RD_ERR,Mask running disparity error" "0,1" newline bitfld.word 0x0 6. "PRE_EMP,Pre-emption packet enable" "0,1" newline bitfld.word 0x0 4. "DTXLANED_0,Tx lane 0 disable" "0,1" newline bitfld.word 0x0 3. "CL37_TMR_OVR_RIDE,Override control for CL37 link timer" "0,1" newline bitfld.word 0x0 2. "EN_2_5G_MODE,Enable 2.5G GMII mode" "0,1" newline bitfld.word 0x0 1. "BYP_PWRUP,Bypass power-up sequence" "0: The XPCS waits for the MPLL Tx or Rx PLL status..,1: The XPCS bypasses the normal flow of the.." newline rbitfld.word 0x0 0. "PHY_MODE_CTRL,When SGMII_PHY_AN_AUTO_RESTART=Enabled or QSGMII_PHY_AN_AUTO_RESTART=Enabled: PHY mode control" "0: SGMII/QSGMII(Port0) autonegotiation advertises..,1: XPCS advertises the values of input ports.." line.word 0x1 "VR_MII_AN_CTRL,VR MII MMD AN Control" bitfld.word 0x1 8. "MII_CTRL,MII Control This bit controls the width of the MAC interface when operating at SGMII/QSGMII/USXGMII speed modes of 10 Mbps or 100 Mbps - 0: 4-bit MII - 1: 8-bit MII This bit also controls the xpcs_mii_ctrl_o signal which is used for external.." "0: 4-bit MII,1: 8-bit MII This bit also controls the.." newline bitfld.word 0x1 4. "SGMII_LINK_STS,SGMII Link Status/ USXGMII Link Status /QSGMII Port0 Link Status" "0,1" newline bitfld.word 0x1 3. "TX_CONFIG,Transmit configuration" "0: Configures the XPCS as the MAC side..,1: Configures the XPCS as the PHY side.." newline bitfld.word 0x1 1.--2. "PCS_MODE,PCS mode" "0: 1000BASE-X mode (clause 37 auto-negotiation is..,?,2: SGMII mode (clause 37 auto-negotiation is as per..,3: QSGMII mode (clause 37 auto-negotiation conforms.." newline bitfld.word 0x1 0. "MII_AN_INTR_EN,Clause 37 AN complete interrupt enable" "0: The Clause 37 auto-negotiation complete..,1: The Clause 37 auto-negotiation complete.." line.word 0x2 "VR_MII_AN_INTR_STS,VR MII MMD AN Interrupt And Status" hexmask.word.byte 0x2 8.--14. 1. "USXG_AN_STS,Reserved" newline rbitfld.word 0x2 6. "LP_CK_STP,Link Partner EEE Clock Stop Capability This field indicates the EEE clock stop capability (or clock-stop enabe - in case far-end is acting as QSGMII MAC) advertised by the far-end device. This field is valid only when PCS_MODE[1:0] is set to.." "0,1" newline rbitfld.word 0x2 5. "LP_EEE_CAP,Link Partner EEE Capability This field indicates the EEE capability advertised by the far-end device (Port 0 QSGMII PHY). This field is valid only when PCS_MODE[1:0] is set to the QSGMII mode and the auto-negotiation is complete along port 0." "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "CL37_ANSGM_STS,Clause 37 AN SGMII Status/QSGMII Port 0 Status This field is valid only when the PCS_MODE[1:0] is set to the SGMII/QSGMII mode and the auto-negotiation is complete. It indicates the status received from remote link after the SGMII/QSGMII.." newline bitfld.word 0x2 0. "CL37_ANCMPLT_INTR,Clause 37 AN Complete Interrupt (SS WC Type) The XPCS sets this bit when Clause 37 auto-negotiation is complete. The host must clear this bit by writing 0 to it." "0,1" line.word 0x3 "VR_MII_TC,VR MII MMD Test Control" bitfld.word 0x3 2. "TPE,Test Pattern Enable Lanes" "0,1" newline bitfld.word 0x3 0.--1. "TP,Test Pattern Select" "0,1,2,3" line.word 0x5 "VR_MII_DBG_CTRL,VR MII MMD Debug Control" bitfld.word 0x5 6. "RX_DT_EN_CTL,Rx Data Enable Control" "0,1" newline rbitfld.word 0x5 5. "SUPRESS_EEE_LOS_DET,Reserved" "0,1" newline bitfld.word 0x5 4. "SUPRESS_LOS_DET,Suppress Loss of Signal Detection" "0,1" newline bitfld.word 0x5 0. "RESTAR_SYNC_0,Restart Synchronization" "0,1" group.word 0x1F800A++0x1 line.word 0x0 "VR_MII_LINK_TIMER_CTRL,VR MII MMD Link Timer Control" hexmask.word 0x0 0.--15. 1. "CL37_LINK_TIME,Programmable Link Timer Value for Clause 37 autonegotiation. This field can be programmed to any desired value if application wishes to over-ride the standard specified values for Link Timer used during Clause 37 Auto negotiation. Link.." rgroup.word 0x1F8010++0x3 line.word 0x0 "VR_MII_DIG_STS,VR MII MMD Digital Status" bitfld.word 0x0 13.--15. "LTX_STATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "LRX_STATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "RXFIFO_OVF,Rx FIFO Overflow (RO LH Type) This bit indicates the clock rate compensation FIFO overflow. - 0: Normal operation - 1: FIFO overflow" "0: Normal operation,1: FIFO overflow" newline bitfld.word 0x0 5. "RXFIFO_UNDF,Rx FIFO Underflow (RO LH Type) This bit indicates the clock rate compensation FIFO underflow. - 0: Normal operation - 1: FIFO underflow" "0: Normal operation,1: FIFO underflow" newline bitfld.word 0x0 2.--4. "PSEQ_STATE,Power Up Sequence State" "0: Wait for ACK High 0,1: Wait for ACK Low 0,2: Wait for ACK High 1,3: Wait for ACK Low 1,4: Tx/Rx stable (Power_Good state),5: Power Save state,6: Power Down state,?" newline bitfld.word 0x0 1. "LB_ACTIVE,Reserved" "0,1" line.word 0x1 "VR_MII_ICG_ERRCNT1,VR MII MMD Invalid Code Group Error Count 1" hexmask.word.byte 0x1 0.--7. 1. "EC0,Invalid Code Group Count Lane 0 (RO LH Type) This field gives the invalid code group count in Lane 0 when Bit 4 of VR MII MMD Digital Error Count Select Register is set to 1." group.word 0x1F8012++0x1 line.word 0x0 "VR_MII_DIG_ERRCNT_SEL,VR MII MMD Digital Error Count Select" bitfld.word 0x0 4. "INV_EC_EN,Invalid Code Group Error Counter Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 0. "COR,Clear on Read" "0: Normal operation,1: Clear any error counter that is read" group.word 0x1F8015++0x1 line.word 0x0 "VR_MII_GPIO,VR MII MMD GPIO" hexmask.word.byte 0x0 8.--15. 1. "GPIO_OUT,GPIO Output The content written on this field is driven to the xpcs_gpo_o[7:0] output port. Dependency: This field is valid only when GPIO_EN = Enabled." newline hexmask.word.byte 0x0 0.--7. 1. "GPIO_IN,GPIO Input This field indicates the content of the xpcs_gpo_i[7:0] port. Dependency: This field is valid only when GPIO_EN = Enabled." rgroup.word 0x1F8018++0x1 line.word 0x0 "VR_MII_MISC_STS,VR MII MMD Miscellaneous Status" hexmask.word.byte 0x0 0.--3. 1. "BIT_SFT,Bit Shift This field indicates the number of bit-shifts carried-out by comma-detect logic so as to align the incoming 10-bit XGXS Rx data Default Value: The default value of this field can be any value depending on the status of comma-detect.." rgroup.word 0x1F8020++0x1 line.word 0x0 "VR_MII_RX_LSTS,VR MII PHY Rx Lane Status" bitfld.word 0x0 13.--15. "RX_VALID_3_1,DPLL Lock Status for Lanes[3:1]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "RX_VALID_0,DPLL Lock Status for Lane 0" "0,1" newline bitfld.word 0x0 9.--11. "RX_PLL_STATE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "RX_PLL_STATE_0,Reserved" "0,1" newline bitfld.word 0x0 5.--7. "SIG_DET_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "SIG_DET_0,Rx Signal Detect for Lane 0" "0,1" group.word 0x1F8030++0xF line.word 0x0 "VR_MII_Gen5_12G_16G_TX_GENCTRL0,VR MII PHY Tx General Control 0" rbitfld.word 0x0 13.--15. "TX_DT_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "TX_DT_EN_0,Tx Data Enable on PHY lane 0" "0,1" newline rbitfld.word 0x0 9.--11. "TX_RST_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "TX_RST_0,Tx Reset on PHY lane 0" "0,1" newline rbitfld.word 0x0 5.--7. "TX_INV_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "TX_INV_0,Tx Invert on PHY lane 0" "0,1" newline rbitfld.word 0x0 1.--3. "TXBCN_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TXBCN_EN_0,Tx Beaconing Enable on PHY lane 0" "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_TX_GENCTRL1,VR MII PHY Tx General Control 1" rbitfld.word 0x1 13.--15. "TX_CLK_RDY_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 12. "TX_CLK_RDY_0,Transmitter Input clock ready on lane 0" "0,1" newline bitfld.word 0x1 8.--10. "VBOOST_LVL,Tx Voltage Boost Maximum Level" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x1 5.--7. "VBOOST_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "VBOOST_EN_0,Tx voltage Boost Enable on PHY lane 0" "0,1" newline rbitfld.word 0x1 1.--3. "DET_RX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "DET_RX_REQ_0,Transmitter Rx-Detection request on PHY lane 0." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_TX_GENCTRL2,VR MII PHY Tx General Control 2" rbitfld.word 0x2 14.--15. "TX3_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 12.--13. "TX2_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 10.--11. "TX1_WIDTH,Reserved" "0,1,2,3" newline bitfld.word 0x2 8.--9. "TX0_WIDTH,Tx Datapath Width on lane 0 of the PHY This field controls the width of input transmit data on lane 0. The encoding of the width is as follows : - 2'b00 : 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit This field drives the output port.." "0: 8-bit,1: 10-bit,2: 16-bit,3: 20-bit This field drives the output port.." newline rbitfld.word 0x2 5.--7. "TX_LPD_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "TX_LPD_0,Transmitter Lane Power Down on PHY lane 0. This field drives the output 'xpcs_tx_lpd_o[3:1]'. This field can be asserted to put the phy transmitter to a power state equivalent to that of P1." "0,1" newline rbitfld.word 0x2 1.--3. "TX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 0. "TX_REQ_0,Transmitter operation request on PHY lane 0 (RW SC Type)" "0,1" line.word 0x3 "VR_MII_Gen5_12G_16G_TX_BOOST_CTRL,VR MII PHY Tx Boost Control" hexmask.word.byte 0x3 12.--15. 1. "TX3_IBOOST,Reserved" newline hexmask.word.byte 0x3 8.--11. 1. "TX2_IBOOST,Reserved" newline hexmask.word.byte 0x3 4.--7. 1. "TX1_IBOOST,Reserved" newline hexmask.word.byte 0x3 0.--3. 1. "TX0_IBOOST,Tx current boost level on lane 0 of the PHY. This bit drives the output port xpcs_tx0_iboost_lvl_o[3:0]." line.word 0x4 "VR_MII_Gen5_12G_16G_TX_RATE_CTRL,VR MII PHY Tx Rate Control" rbitfld.word 0x4 12.--14. "TX3_RATE,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x4 8.--10. "TX2_RATE,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x4 4.--6. "TX1_RATE,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x4 0.--2. "TX0_RATE,Tx date rate on PHY lane 0." "0,1,2,3,4,5,6,7" line.word 0x5 "VR_MII_Gen5_12G_16G_TX_POWER_STATE_CTRL,VR MII PHY Tx Power State" rbitfld.word 0x5 9.--11. "TX_DISABLE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x5 8. "TX_DISABLE_0,Transmitter Disable on lane 0 This field drives the output port 'xpcs_tx_disable_o[0]'." "0,1" newline rbitfld.word 0x5 6.--7. "TX3_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 4.--5. "TX2_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 2.--3. "TX1_PSTATE,Reserved" "0,1,2,3" newline bitfld.word 0x5 0.--1. "TX0_PSTATE,Tx power state control for PHY lane 0." "0,1,2,3" line.word 0x6 "VR_MII_Gen5_12G_16G_TX_EQ_CTRL0,VR MII PHY Tx Equalization Control 0" hexmask.word.byte 0x6 8.--13. 1. "TX_EQ_MAIN,Control for setting Tx driver output amplitude" newline hexmask.word.byte 0x6 0.--5. 1. "TX_EQ_PRE,Tx Pre-Emphasis level adjustment Control" line.word 0x7 "VR_MII_Gen5_12G_16G_TX_EQ_CTRL1,VR MII PHY Tx Equalization Control 1" rbitfld.word 0x7 8. "CA_TX_EQ,Reserved" "0,1" newline rbitfld.word 0x7 7. "TX_EQ_DEF_CTRL,Reserved" "0,1" newline rbitfld.word 0x7 6. "TX_EQ_OVR_RIDE,Reserved" "0,1" newline hexmask.word.byte 0x7 0.--5. 1. "TX_EQ_POST,Tx Post-Emphasis level adjustment Control This field controls the transmitter driver output pre-emphasis (pre-shoot coefficient). This field drives the output port 'rpcs_ktx_post_o' if 'TX_EQ_OVR_RIDE' bit is set or in configurations with.." group.word 0x1F803C++0x1 line.word 0x0 "VR_MII_Consumer_10G_TX_TERM_CTRL,VR MII PHY Transmit Termination Control" bitfld.word 0x0 0.--2. "TX0_TERM,Transmit Termination Control for lane 0" "0,1,2,3,4,5,6,7" rgroup.word 0x1F8040++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_TX_STS,VR MII PHY Tx Status" bitfld.word 0x0 5.--7. "DETRX_RSLT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "DETRX_RSLT_0,Receiver Detection Result on PHY lane 0. This field captures the value of the input port 'xpcs_tx_detrx_result_o[0]'. The value of this field is valid when 'TX_ACK_0' is high. - 1'b0: Receiver not detected - 1'b1: Receiver detected" "0: Receiver not detected,1: Receiver detected" newline bitfld.word 0x0 1.--3. "TX_ACK_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TX_ACK_0,Tx Acknowledge on PHY lane 0. This bit captures the value of the input port 'xpcs_tx_ack_i[0]'. Whenever this bit is read as high it indicates that the requested transmitter setting is complete or the requested RX-detection operation is.." "0,1" group.word 0x1F8050++0x11 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_GENCTRL0,VR MII PHY Rx General Control 0" rbitfld.word 0x0 13.--15. "RX_CLKSFT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "RX_CLKSFT_0,Rx clock shift on PHY lane 0. When this bit is set a 1-bit shift of receive data happens relate to receive clock. This operation works only if alignment enable is disabled. This bit drives the output port 'xpcs_rx_clk_shift_o[0]'." "0,1" newline rbitfld.word 0x0 9.--11. "RX_DT_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "RX_DT_EN_0,Rx Data Enable on PHY lane 0. This bit should be set to enable the PHY receiver data output on lane 0. This bit drives the output port 'xgxs_rx_data_en_o[0]'." "0,1" newline rbitfld.word 0x0 5.--7. "RX_ALIGN_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "RX_ALIGN_EN_0,Rx Data Alignment Enable on PHY lane 0. This bit can be set to enable word alignment (based on k28.5 character) in the PHY. This field drives the output port 'xgxs_rx_align_en_o[0]'." "0,1" newline rbitfld.word 0x0 1.--3. "RX_TERM_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "RX_TERM_EN_0,Rx Termination Enable on PHY lane 0. When this bit is set PHY Rx is terminated with a nominal 50 ohm resistance. Otherwise the termination is in high impedance. This field drives the output port 'xpcs_rx_term_en_o[0]'." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_RX_GENCTRL1,VR MII PHY Rx General Control 1" rbitfld.word 0x1 9.--11. "RX_TERM_ACDC_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 8. "RX_TERM_ACDC_0,Rx Termination control on PHY lane 0. - 0: DC Termination (Floating Rx) - 1: AC Termination (Grounded Rx) This field drives the output port xpcs_rx_term_acdc_o[0]." "0: DC Termination,1: AC Termination" newline rbitfld.word 0x1 5.--7. "RX_RST_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "RX_RST_0,Rx reset on PHY lane 0. When this bit is set RX data path all the receiver settings and state machines of the PHY are reset This field drives the output port xgxs_rx_reset_o[0] when XPCS is in POWER_GOOD state." "0,1" newline rbitfld.word 0x1 1.--3. "RX_INV_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "RX_INV_0,Rx Data Invert on PHY lane 0. When this bit is set the data on PHY Rx serial lines are logically inverted. This signal drives the output port xgxs_rx_invert_o[0]." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_RX_GENCTRL2,VR MII PHY Rx General Control 2" rbitfld.word 0x2 14.--15. "RX3_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 12.--13. "RX2_WIDTH,Reserved" "0,1,2,3" newline rbitfld.word 0x2 10.--11. "RX1_WIDTH,Reserved" "0,1,2,3" newline bitfld.word 0x2 8.--9. "RX0_WIDTH,Rx Datapath Width on lane 0 of the PHY This field controls the width of output receive data from PHY on lane 3. The encoding of the width is as follows : - 2'b00: 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit This field drives the.." "0: 8-bit,1: 10-bit,2: 16-bit,3: 20-bit This field drives the output port.." newline rbitfld.word 0x2 5.--7. "RX_LPD_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 4. "RX_LPD_0,Receiver Lane Power Down on PHY lane 0. This bit can be set to power down the receiver to a power state equivalent to that of P1. This bit drives the output port 'xpcs_rx_lpd_o[0]'." "0,1" newline rbitfld.word 0x2 1.--3. "RX_REQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 0. "RX_REQ_0,Receiver operation request on PHY lane 0 (RW SC Type). This bit can be set to 1 by application.This bit is self-cleared when 'xpcs_tx_ack_i[0]' is asserted. When this bit is set a new receiver setting request is made towards the PHY.This bit.." "0,1" line.word 0x3 "VR_MII_Gen5_12G_16G_RX_GENCTRL3,VR MII PHY Rx General Control 3" rbitfld.word 0x3 13.--15. "LOS_LFPS_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 12. "LOS_LFPS_EN_0,Rx LOS LFPS Enable on lane 0 of the PHY This field drives the output port xpcs_rx_los_lfps_en_o[0] to enable the LFPS filter on lane 0 of the PHY." "0,1" newline rbitfld.word 0x3 9.--11. "LOS_TRSHLD_3,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x3 6.--8. "LOS_TRSHLD_2,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x3 3.--5. "LOS_TRSHLD_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 0.--2. "LOS_TRSHLD_0,Loss of signal threshold on PHY lane 0. This field drives the output port xpcs_rx0_los_threshold_o[2:0]. Threshold voltages for various values are as follows : - 3'b000: Reserved - 3'b001: 90 mVpp - 3'b010: 120 mVpp - 3'b011: 150 mVpp -.." "0: Reserved,1: 90 mVpp,2: 120 mVpp,3: 150 mVpp,4: 180 mVpp,5: 210 mVpp,6: 240 mVpp,7: 270 mVpp" line.word 0x4 "VR_MII_Gen5_12G_16G_RX_RATE_CTRL,VR MII PHY Rx Rate Control" rbitfld.word 0x4 12.--13. "RX3_RATE,Reserved" "0,1,2,3" newline rbitfld.word 0x4 8.--9. "RX2_RATE,Reserved" "0,1,2,3" newline rbitfld.word 0x4 4.--5. "RX1_RATE,Reserved" "0,1,2,3" newline bitfld.word 0x4 0.--1. "RX0_RATE,Rx date rate on lane 0 of the PHY Data Rate Encoding is as follows : - 2'b00: baud - 2'b01: baud/2 - 2'b10: baud/4 - 2'b11: baud/8" "0: baud,1: baud/2,2: baud/4,3: baud/8" line.word 0x5 "VR_MII_Gen5_12G_16G_RX_POWER_STATE_CTRL,VR MII PHY Rx Power State" rbitfld.word 0x5 12. "EEE_OVR_RIDE,Reserved" "0,1" newline rbitfld.word 0x5 9.--11. "RX_DISABLE_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x5 8. "RX_DISABLE_0,Receiver Disable on lane 0 This bit can be set in P1 power state to put the receiver in a low power mode. This field drives the output port 'xpcs_rx_disable_o[0]'." "0,1" newline rbitfld.word 0x5 6.--7. "RX3_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 4.--5. "RX2_PSTATE,Reserved" "0,1,2,3" newline rbitfld.word 0x5 2.--3. "RX1_PSTATE,Reserved" "0,1,2,3" newline bitfld.word 0x5 0.--1. "RX0_PSTATE,Rx power state control for PHY lane 0. Power state encoding is as follows : - 2'b00: P0 - 2'b01: P0s - 2'b10: P1 - 2'b11: P2" "0: P0,1: P0s,2: P1,3: P2" line.word 0x6 "VR_MII_Gen5_12G_16G_RX_CDR_CTRL,VR MII PHY Rx CDR Control" rbitfld.word 0x6 9.--11. "VCO_LOW_FREQ_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 8. "VCO_LOW_FREQ_0,Rx VCO lower frequency band mode on lane 0 of the PHY This field controls the frequency of the Rx VCO to a lower-frequency operating band. This field drives the output port xpcs_rx_cdr_vco_lowfreq_o[0]." "0,1" newline rbitfld.word 0x6 5.--7. "CDR_SSC_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 4. "CDR_SSC_EN_0,Rx CDR SSC Mode Enable on lane 0 of the PHY This field controls the CDR tracking gains and duration. This bit should be set to 1 when receive data has a spread spectrum clock and should be cleared if receive data does not have SSC. This bit.." "0,1" newline rbitfld.word 0x6 1.--3. "CDR_TRACK_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 0. "CDR_TRACK_EN_0,Rx CDR Tracking Enable on lane 0 of the PHY This bit should be set to enable CDR tracking of receive data on lane 0 of the PHY. This bit drives the output port 'xpcs_rx_cdr_track_en_o[0]'." "0,1" line.word 0x7 "VR_MII_Gen5_12G_16G_RX_ATTN_CTRL,VR MII PHY Rx Attenuation Control" rbitfld.word 0x7 12.--14. "RX3_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x7 8.--10. "RX2_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.word 0x7 4.--6. "RX1_EQ_ATT_LVL,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x7 0.--2. "RX0_EQ_ATT_LVL,Rx Equalization Attenuation level for lane 0 of the PHY This field drives the output port xpcs_rx0_eq_att_lvl_o[2:0]. This field controls the AFE attenuation level of the PHY." "0,1,2,3,4,5,6,7" line.word 0x8 "VR_MII_Gen5_12G_RX_EQ_CTRL0,VR MII PHY Rx Equalization Control 0" hexmask.word.byte 0x8 12.--15. 1. "AFE_GAIN_0,Rx Equalization AFE Gain on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_afe_gain_o[3:0]." newline hexmask.word.byte 0x8 0.--4. 1. "CTLE_BOOST_0,Rx Equalization CTLE Boost value on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_ctle_boost_o[4:0].This field controls the CTLE boost level." group.word 0x1F805C++0x5 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_EQ_CTRL4,VR MII PHY Rx Equalization Control 4" rbitfld.word 0x0 12. "RX_AD_REQ,Reserved" "0,1" newline rbitfld.word 0x0 11. "RX_EQ_STRT_CTRL,Reserved" "0,1" newline rbitfld.word 0x0 10. "SELF_MAIN_EN,Reserved" "0,1" newline rbitfld.word 0x0 9. "PING_PONG_EN,Reserved" "0,1" newline rbitfld.word 0x0 8. "SEQ_EQ_EN,Reserved" "0,1" newline rbitfld.word 0x0 5.--7. "CONT_OFF_CAN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "CONT_OFF_CAN_0,Receiver offset cancellation continuous operation on lane 0 This bit can be set if continuous receiver offset cancellation is required. If this bit is 0 offset cancellation runs when receiver exits P2 power state. This bit drives the.." "0,1" newline rbitfld.word 0x0 1.--3. "CONT_ADAPT_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "CONT_ADAPT_0,Receiver Adaptation Continuous Operation on lane 0 This bit can be set to enable continuous receiver adaptation in the PHY. This bit drives the output port 'xpcs_rx_offcan_cont_o'." "0,1" line.word 0x1 "VR_MII_Gen5_12G_AFE_DFE_EN_CTRL,VR MII PHY AFE-DFE Enable" rbitfld.word 0x1 5.--7. "DFE_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 4. "DFE_EN_0,Rx DFE Enable on lane 0 of the PHY This bit drives the output port xpcs_rx_adapt_dfe_en_o[0]. This bit can be set to enable Rx adaption and decision feedback equalization (DFE) circuitry and applies the input setting of DFE Tap1:.." "0,1" newline rbitfld.word 0x1 1.--3. "AFE_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x1 0. "AFE_EN_0,Rx Adaptation AFE Enable on lane 0 of the PHY This bit drives the output port xpcs_rx_adapt_afe_en_o[0]. This bit can be set to enable Rx adaption circuitry and applies the following input receiver equalization settings to the PHY: -.." "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_DFE_TAP_CTRL0,VR MII PHY DFE Tap Control 0" hexmask.word.byte 0x2 8.--15. 1. "DFE_TAP1_1,Reserved" newline hexmask.word.byte 0x2 0.--7. 1. "DFE_TAP1_0,Rx Equalization DFE Tap1 value on lane 0 of the PHY This field drives the output port xpcs_rx0_eq_dfe_tap1_o[7:0]" rgroup.word 0x1F8060++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_RX_STS,VR MII PHY Rx Status" bitfld.word 0x0 1.--3. "RX_ACK_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "RX_ACK_0,Rx Acknowledge on PHY lane 0. This bit captures the value of the input port xpcs_rx_ack_i[0]. If this bit is set it indicates that the requested receiver setting is complete. This bit forms a hand-shake with 'RX_REQ_0' bit. Once this bit is.." "0,1" group.word 0x1F8064++0x1 line.word 0x0 "VR_MII_Consumer_10G_RX_TERM_CTRL,VR MII PHY Receive Termination Control" bitfld.word 0x0 0.--2. "RX0_TERM,Receive Termination Control for lane 0" "0,1,2,3,4,5,6,7" group.word 0x1F806B++0x1 line.word 0x0 "VR_MII_Consumer_10G_RX_IQ_CTRL0,VR MII PHY RX IQ Control 0" hexmask.word.byte 0x0 8.--11. 1. "RX0_DELTA_IQ,RX IQ Offset Value for lane0. This field drives the output port xpcs_rx0_delta_iq_o[3:0]." group.word 0x1F8070++0x11 line.word 0x0 "VR_MII_Gen5_12G_16G_MPLL_CMN_CTRL,VR MII PHY MPLL Common Control" rbitfld.word 0x0 5.--7. "MPLLB_SEL_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "MPLLB_SEL_0,Tx MPLLB Select-lane 0 When this bit is set PHY selects MPLLB to generate Tx analog clocks on lane 0" "0,1" newline rbitfld.word 0x0 1.--3. "MPLL_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLL_EN_0,Tx MPLL Enable-lane 0 This bit should be set to power-up the MPLL.This bit should be 1 for normal operation." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_MPLLA_CTRL0,VR MII PHY MPLLA Control 0" bitfld.word 0x1 15. "MPLLA_CAL_DISABLE,MPLLA Calibration Disable This field can be programmed to 1 to disable calibration of MPLLA by PHY firmware." "0,1" newline hexmask.word.byte 0x1 0.--7. 1. "MPLLA_MULTIPLIER,MPLLA frequency Multiplier Control This field controls the multiplication of reference clock to a frequency suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset to ensure that PHY is.." line.word 0x2 "VR_MII_Gen5_12G_MPLLA_CTRL1,VR MII PHY MPLLA Control 1" hexmask.word 0x2 5.--15. 1. "MPLLA_FRACN_CTRL,MPLLA Fractional Control This field drives the output port xpcs_mplla_fracn_ctrl_o." line.word 0x3 "VR_MII_Gen5_12G_16G_MPLLA_CTRL2,VR MII PHY MPLLA Control 2" bitfld.word 0x3 11.--13. "MPLLA_TX_CLK_DIV,MPLLA Tx Clock Divider. This field drives the output port 'xpcs_mplla_tx_clk_div_o[1:0]'." "0,1,2,3,4,5,6,7" newline bitfld.word 0x3 10. "MPLLA_DIV_CLK_EN,Enable mplla_div_clk from PHY. When asserted the frequency of mplla_div_clk from PHY is the MPLLA frequency divided by 'mplla_div_multiplier'" "0,1" newline bitfld.word 0x3 9. "MPLLA_DIV10_CLK_EN,MPLLA Divide by 10 Enable When this bit is set the frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 10." "0,1" newline bitfld.word 0x3 8. "MPLLA_DIV8_CLK_EN,MPLLA Divide by 8 Enable When this bit is set the frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 8." "0,1" newline hexmask.word.byte 0x3 0.--7. 1. "MPLLA_DIV_MULT,MPLLA Output Frequency Multiplier Control This field controls the frequency multiplication factor used to generate MPLLA clock output from the reference clock input as seen by the MPLL." line.word 0x4 "VR_MII_Gen5_12G_16G_MPLLB_CTRL0,VR MII PHY MPLLB Control 0" bitfld.word 0x4 15. "MPLLB_CAL_DISABLE,MPLLB Calibration Disable This field can be programmed to 1 to disable calibration of MPLLB by PHY firmware." "0,1" newline hexmask.word.byte 0x4 0.--7. 1. "MPLLB_MULTIPLIER,MPLLB frequency Multiplier Control This field controls the multiplication of reference clock to a frequency suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset to ensure that PHY is.." line.word 0x5 "VR_MII_Gen5_12G_MPLLB_CTRL1,VR MII PHY MPLLB Control 1" hexmask.word 0x5 5.--15. 1. "MPLLB_FRACN_CTRL,MPLLB Fractional Control This field drives the output port 'xpcs_mpllb_fracn_ctrl_o'." line.word 0x6 "VR_MII_Gen5_12G_16G_MPLLB_CTRL2,VR MII PHY MPLLB Control 2" bitfld.word 0x6 11.--13. "MPLLB_TX_CLK_DIV,MPLLB Tx Clock Divider. This field drives the output port 'xpcs_mpllb_tx_clk_div_o[1:0]'." "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 10. "MPLLB_DIV_CLK_EN,Enable mpllb_div_clk from PHY When asserted the frequency of mpllb_div_clk output from PHY is MPLLB frequency divided by 'mpllb_div_multiplier'" "0,1" newline bitfld.word 0x6 9. "MPLLB_DIV10_CLK_EN,MPLLB Divide by 10 Enable When this bit is set the frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 10." "0,1" newline bitfld.word 0x6 8. "MPLLB_DIV8_CLK_EN,MPLLB Divide by 8 Enable When this bit is set the frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 8." "0,1" newline hexmask.word.byte 0x6 0.--7. 1. "MPLLB_DIV_MULT,MPLLB Output Frequency Multiplier Control This field controls the frequency multiplication factor used to generate MPLLB clock output from the reference clock input as seen by the MPLL." line.word 0x7 "VR_MII_Gen5_12G_MPLLA_CTRL3,VR MII PHY MPLLA Control 3" hexmask.word 0x7 0.--15. 1. "MPLLA_BANDWIDTH,MPLLA Bandwidth Control This field controls the bandwidth of MPLLA present in the PHY. This field drives the output port 'xpcs_mplla_bandwidth_o'." line.word 0x8 "VR_MII_Gen5_12G_MPLLB_CTRL3,VR MII PHY MPLLB Control 3" hexmask.word 0x8 0.--15. 1. "MPLLB_BANDWIDTH,MPLLB Bandwidth Control This field controls the bandwidth of MPLLB present in the PHY. This field drives the output port 'xpcs_mpllb_bandwidth_o'." group.word 0x1F8090++0x5 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_CTRL0,VR MII PHY Miscellaneous Control 0" bitfld.word 0x0 15. "PLL_CTRL,PLL Reinitialization Control" "0,1" newline bitfld.word 0x0 14. "CR_PARA_SEL,Select CR Para Port This bit select the interface for accessing PHY registers * 0 -JTAG * 1 -CR parallel port This bit should be changed only after disabling 'jtag_tck'to PHY." "0,1" newline bitfld.word 0x0 13. "RTUNE_REQ,Resistor Tuning Request This bit can be set to trigger a resistor tune request to the PHY. This bit controls the 'xgxs_rtune_req_o' output port." "0,1" newline hexmask.word.byte 0x0 8.--12. 1. "RX_VREF_CTRL,Rx Biasing Current Control" newline rbitfld.word 0x0 5.--7. "RX2TX_LB_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "RX2TX_LB_EN_0,Enable Parallel Rx-to-Tx Loopback on lane 0 When this bit is set recovered parallel data from PHY receiver is looped back to the transmit serializer. This loop-back takes place internal to the PHY (not within XPCS)." "0,1" newline rbitfld.word 0x0 1.--3. "TX2RX_LB_EN_3_1,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "TX2RX_LB_EN_0,Enable Analog Tx-to-Rx Serial Loopback on lane 0 This bit can be set to enable serial loopback in the PHY from Tx pre-driver to Rx analog front-end." "0,1" line.word 0x1 "VR_MII_Gen5_12G_16G_REF_CLK_CTRL,VR MII SPHY Reference Control" bitfld.word 0x1 8. "REF_RPT_CLK_EN,Repeat Reference Clock Enable If this bit is set ref_repeat_clk_{p m} clock from PHY is enabled." "0,1" newline bitfld.word 0x1 7. "REF_MPLLB_DIV2,MPLLB Reference Clock Divider Control" "0,1" newline bitfld.word 0x1 6. "REF_MPLLA_DIV2,MPLLA Reference Clock Divider Control" "0,1" newline bitfld.word 0x1 3.--5. "REF_RANGE,Input Reference Clock Range" "0: 20 - 26 MHz,1: 26.1 - 52 MHz,2: 52.1 - 78 MHz,3: 78.1 - 104 MHz,4: 104.1 - 130 MHz,5: 130.1 - 156 MHz,6: 156.1 - 182 MHz,7: 182.1 - 200 MHz" newline bitfld.word 0x1 2. "REF_CLK_DIV2,Reference Clock divide by 2" "0,1" newline bitfld.word 0x1 1. "REF_USE_PAD,Use Pad Clock As Reference Clock" "0: Internal PLL,1: External clock" newline bitfld.word 0x1 0. "REF_CLK_EN,Reference Clock Enable" "0,1" line.word 0x2 "VR_MII_Gen5_12G_16G_VCO_CAL_LD0,VR MII PHY VCO Calibration Load 0" hexmask.word 0x2 0.--12. 1. "VCO_LD_VAL_0,Rx VCO calibration load value on lane 0 of the PHY" group.word 0x1F8096++0x1 line.word 0x0 "VR_MII_Gen5_12G_VCO_CAL_REF0,VR MII PHY VCO Calibration Reference 0" hexmask.word.byte 0x0 8.--13. 1. "VCO_REF_LD_1,Reserved" newline hexmask.word.byte 0x0 0.--5. 1. "VCO_REF_LD_0,Rx VCO calibration reference load value -lane 0" rgroup.word 0x1F8098++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_STS,VR MII PHY Miscellaneous Status" bitfld.word 0x0 11. "REF_CLKDET_RESULT,Reserved" "0,1" newline bitfld.word 0x0 10. "MPLLB_STS,Status of MPLLB from PHY This bit denotes the value of xpcs_mpllb_state_i input." "0,1" newline bitfld.word 0x0 9. "MPLLA_STS,Status of MPLLA from PHY. This bit denotes the value of xpcs_mplla_state_i input" "0,1" newline bitfld.word 0x0 8. "RTUNE_ACK,Acknowledgment for Resistor Tune Request This bit denotes the value of 'xgxs_rtune_ack_i' input." "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "FOM,Reserved" group.word 0x1F8099++0x1 line.word 0x0 "VR_MII_Gen5_12G_16G_MISC_CTRL1,VR MII PHY Miscellaneous Control 1" hexmask.word 0x0 0.--15. 1. "RX_LNK_UP_TIME,Wait Time before PLL Re-initialization" group.word 0x1F80A0++0x5 line.word 0x0 "VR_MII_SNPS_CR_CTRL,VR MII PHY CR Control" bitfld.word 0x0 1. "WR_RDN,Write or Read Indicator This bit indicates whether a read or write operation is to be performed to the Synopsys PHY registers: - 0: Read - 1: Write" "0: Read,1: Write" newline bitfld.word 0x0 0. "START_BUSY,Start CR Port Access or Busy Indicator (WS SC Type)" "0,1" line.word 0x1 "VR_MII_SNPS_CR_ADDR,VR MII PHY CR Address" hexmask.word 0x1 0.--15. 1. "ADDRESS,CR Port Address" line.word 0x2 "VR_MII_SNPS_CR_DATA,VR MII CR Data" hexmask.word 0x2 0.--15. 1. "DATA,CR Port Data" group.word 0x1F80E1++0x1 line.word 0x0 "VR_MII_DIG_CTRL2,VR MII MMD Digital Control 2" bitfld.word 0x0 4. "TX_POL_INV_0,Tx Polarity Invert" "0: Not inverted,1: Inverted" newline bitfld.word 0x0 0. "RX_POL_INV_0,Rx Polarity Invert" "0: Not inverted,1: Inverted" tree.end tree.end tree "SIUL2 (System Integration Unit Lite2)" base ad:0x0 tree "SIUL2_0" base ad:0x4009C000 rgroup.long 0x4++0x7 line.long 0x0 "MIDR1,SIUL2 MCU ID 1" hexmask.long.byte 0x0 26.--31. 1. "PRODUCT_LINE_LETTER,Product Line Letter" hexmask.long.word 0x0 16.--25. 1. "PART_NO,MCU Part Number" newline hexmask.long.byte 0x0 8.--15. 1. "CC_REVISION,CC Revision" hexmask.long.byte 0x0 4.--7. 1. "MAJOR_MASK,Major Mask Revision" newline hexmask.long.byte 0x0 0.--3. 1. "MINOR_MASK,Minor Mask Revision" line.long 0x4 "MIDR2,SIUL2 MCU ID 2" bitfld.long 0x4 29.--31. "TECHNOLOGY,Technology" "0: C55FC,1: C40EFS3,2: 16FFC,?,?,?,?,?" bitfld.long 0x4 26.--28. "TEMPERATURE,Temperature" "0: C = 85C,?,2: V = 105C,?,4: M = 125C,?,?,?" newline hexmask.long.byte 0x4 20.--25. 1. "PACKAGE,Package" hexmask.long.byte 0x4 16.--19. 1. "FREQUENCY,Frequency" newline bitfld.long 0x4 14.--15. "FLASH_CODE,Flash Code" "0: None,1: SiP,2: Monolithic,?" bitfld.long 0x4 12.--13. "FLASH_DATA,Flash Data" "0: None,1: AE,2: Monolithic,3: Configurable within Code Flash" newline hexmask.long.byte 0x4 8.--11. 1. "FLASH_SIZE_DATA,Flash Size Data" hexmask.long.byte 0x4 0.--7. 1. "FLASH_SIZE_CODE,Flash Size Code" group.long 0x10++0x3 line.long 0x0 "DISR0,SIUL2 DMA/Interrupt Status Flag 0" eventfld.long 0x0 11. "EIF11,External Interrupt Status Flag 11" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER11 and.." eventfld.long 0x0 10. "EIF10,External Interrupt Status Flag 10" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER10 and.." newline eventfld.long 0x0 9. "EIF9,External Interrupt Status Flag 9" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER9 and.." eventfld.long 0x0 8. "EIF8,External Interrupt Status Flag 8" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER8 and.." newline eventfld.long 0x0 7. "EIF7,External Interrupt Status Flag 7" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER7 and.." eventfld.long 0x0 6. "EIF6,External Interrupt Status Flag 6" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER6 and.." newline eventfld.long 0x0 5. "EIF5,External Interrupt Status Flag 5" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER5 and.." eventfld.long 0x0 4. "EIF4,External Interrupt Status Flag 4" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER4 and.." newline eventfld.long 0x0 3. "EIF3,External Interrupt Status Flag 3" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER3 and.." eventfld.long 0x0 2. "EIF2,External Interrupt Status Flag 2" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER2 and.." newline eventfld.long 0x0 1. "EIF1,External Interrupt Status Flag 1" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER1 and.." eventfld.long 0x0 0. "EIF0,External Interrupt Status Flag 0" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER0 and.." group.long 0x18++0x3 line.long 0x0 "DIRER0,SIUL2 DMA/Interrupt Request Enable 0" bitfld.long 0x0 11. "EIRE11,External Interrupt Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 10. "EIRE10,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "EIRE9,External Interrupt Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 8. "EIRE8,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "EIRE7,External Interrupt Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 6. "EIRE6,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "EIRE5,External Interrupt Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 4. "EIRE4,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "EIRE3,External Interrupt Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 2. "EIRE2,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "EIRE1,External Interrupt Request Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 0. "EIRE0,External Interrupt Request Enable" "0: Disabled,1: Enabled" group.long 0x20++0x3 line.long 0x0 "DIRSR0,SIUL2 DMA/Interrupt Request Select 0" bitfld.long 0x0 11. "DIRSR11,DMA/Interrupt Request Select Register" "0: Interrupt request,?" bitfld.long 0x0 10. "DIRSR10,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 9. "DIRSR9,DMA/Interrupt Request Select Register" "0: Interrupt request,?" bitfld.long 0x0 8. "DIRSR8,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 7. "DIRSR7,DMA/Interrupt Request Select Register" "0: Interrupt request,?" bitfld.long 0x0 6. "DIRSR6,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 5. "DIRSR5,DMA/Interrupt Request Select Register" "0: Interrupt request,?" bitfld.long 0x0 4. "DIRSR4,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 3. "DIRSR3,DMA/Interrupt Request Select Register" "0: Interrupt request,?" bitfld.long 0x0 2. "DIRSR2,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 1. "DIRSR1,DMA/Interrupt Request Select Register" "0: Interrupt request,?" bitfld.long 0x0 0. "DIRSR0,DMA/Interrupt Request Select Register" "0: Interrupt request,?" group.long 0x28++0x3 line.long 0x0 "IREER0,SIUL2 Interrupt Rising-Edge Event Enable 0" bitfld.long 0x0 11. "IREE11,Enables rising-edge events to set DISR0[EIF11]." "0: Disabled,1: Enabled" bitfld.long 0x0 10. "IREE10,Enables rising-edge events to set DISR0[EIF10]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IREE9,Enables rising-edge events to set DISR0[EIF9]." "0: Disabled,1: Enabled" bitfld.long 0x0 8. "IREE8,Enables rising-edge events to set DISR0[EIF8]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IREE7,Enables rising-edge events to set DISR0[EIF7]." "0: Disabled,1: Enabled" bitfld.long 0x0 6. "IREE6,Enables rising-edge events to set DISR0[EIF6]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IREE5,Enables rising-edge events to set DISR0[EIF5]." "0: Disabled,1: Enabled" bitfld.long 0x0 4. "IREE4,Enables rising-edge events to set DISR0[EIF4]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IREE3,Enables rising-edge events to set DISR0[EIF3]." "0: Disabled,1: Enabled" bitfld.long 0x0 2. "IREE2,Enables rising-edge events to set DISR0[EIF2]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IREE1,Enables rising-edge events to set DISR0[EIF1]." "0: Disabled,1: Enabled" bitfld.long 0x0 0. "IREE0,Enables rising-edge events to set DISR0[EIF0]." "0: Disabled,1: Enabled" group.long 0x30++0x3 line.long 0x0 "IFEER0,SIUL2 Interrupt Falling-Edge Event Enable 0" bitfld.long 0x0 11. "IFEE11,Enables falling-edge events to set DISR0[EIF11]." "0: Disabled,1: Enabled" bitfld.long 0x0 10. "IFEE10,Enables falling-edge events to set DISR0[EIF10]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IFEE9,Enables falling-edge events to set DISR0[EIF9]." "0: Disabled,1: Enabled" bitfld.long 0x0 8. "IFEE8,Enables falling-edge events to set DISR0[EIF8]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IFEE7,Enables falling-edge events to set DISR0[EIF7]." "0: Disabled,1: Enabled" bitfld.long 0x0 6. "IFEE6,Enables falling-edge events to set DISR0[EIF6]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IFEE5,Enables falling-edge events to set DISR0[EIF5]." "0: Disabled,1: Enabled" bitfld.long 0x0 4. "IFEE4,Enables falling-edge events to set DISR0[EIF4]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IFEE3,Enables falling-edge events to set DISR0[EIF3]." "0: Disabled,1: Enabled" bitfld.long 0x0 2. "IFEE2,Enables falling-edge events to set DISR0[EIF2]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IFEE1,Enables falling-edge events to set DISR0[EIF1]." "0: Disabled,1: Enabled" bitfld.long 0x0 0. "IFEE0,Enables falling-edge events to set DISR0[EIF0]." "0: Disabled,1: Enabled" group.long 0x38++0x3 line.long 0x0 "IFER0,SIUL2 Interrupt Filter Enable 0" bitfld.long 0x0 11. "IFE11,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" bitfld.long 0x0 10. "IFE10,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IFE9,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" bitfld.long 0x0 8. "IFE8,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IFE7,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" bitfld.long 0x0 6. "IFE6,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IFE5,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" bitfld.long 0x0 4. "IFE4,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IFE3,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" bitfld.long 0x0 2. "IFE2,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IFE1,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" bitfld.long 0x0 0. "IFE0,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" group.long 0x40++0x2F line.long 0x0 "IFMCR0,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x0 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x4 "IFMCR1,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x4 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x8 "IFMCR2,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x8 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0xC "IFMCR3,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0xC 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x10 "IFMCR4,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x10 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x14 "IFMCR5,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x14 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x18 "IFMCR6,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x18 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x1C "IFMCR7,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x1C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x20 "IFMCR8,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x20 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x24 "IFMCR9,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x24 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x28 "IFMCR10,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x28 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x2C "IFMCR11,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x2C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" group.long 0xC0++0x3 line.long 0x0 "IFCPR,SIUL2 Interrupt Filter Clock Prescaler" hexmask.long.byte 0x0 0.--3. 1. "IFCP,Interrupt Filter Clock Prescaler setting" group.long 0x240++0x197 line.long 0x0 "MSCR0,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "MSCR1,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x4 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "MSCR2,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x8 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "MSCR3,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xC 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "MSCR4,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x10 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x10 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x10 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x10 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x10 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x10 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "MSCR5,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x14 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x14 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x14 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x14 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x14 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x14 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "MSCR6,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x18 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x18 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x18 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x18 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x18 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x18 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "MSCR7,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x1C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x1C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x1C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x1C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x1C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "MSCR8,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x20 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x20 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x20 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x20 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x20 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "MSCR9,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x24 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x24 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x24 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x24 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "MSCR10,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x28 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x28 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x28 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x28 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x28 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x28 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x2C "MSCR11,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x2C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x2C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x2C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x2C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x2C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x2C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x30 "MSCR12,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x30 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x30 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x30 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x30 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x30 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x30 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x30 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x34 "MSCR13,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x34 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x34 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x34 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x34 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x34 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x34 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x34 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x38 "MSCR14,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x38 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x38 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x38 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x38 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x38 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x38 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x38 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x3C "MSCR15,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x3C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x3C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x3C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x3C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x3C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x3C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x40 "MSCR16,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x40 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x40 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x40 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x40 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x40 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x40 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x40 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x44 "MSCR17,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x44 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x44 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x44 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x44 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x44 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x44 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x44 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x48 "MSCR18,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x48 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x48 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x48 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x48 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x48 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x48 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x48 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4C "MSCR19,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x4C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x4C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x4C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x4C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x4C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x50 "MSCR20,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x50 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x50 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x50 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x50 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x50 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x50 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x50 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x54 "MSCR21,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x54 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x54 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x54 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x54 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x54 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x54 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x54 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x58 "MSCR22,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x58 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x58 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x58 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x58 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x58 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x58 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x58 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x5C "MSCR23,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x5C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x5C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x5C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x5C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x5C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x5C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x60 "MSCR24,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x60 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x60 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x60 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x60 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x60 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x60 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x60 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x64 "MSCR25,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x64 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x64 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x64 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x64 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x64 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x64 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x64 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x68 "MSCR26,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x68 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x68 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x68 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x68 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x68 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x68 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x68 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x6C "MSCR27,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x6C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x6C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x6C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x6C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x6C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x6C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x70 "MSCR28,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x70 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x70 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x70 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x70 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x70 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x70 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x70 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x74 "MSCR29,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x74 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x74 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x74 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x74 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x74 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x74 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x74 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x78 "MSCR30,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x78 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x78 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x78 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x78 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x78 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x78 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x78 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x7C "MSCR31,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x7C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x7C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x7C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x7C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x7C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x7C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x80 "MSCR32,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x80 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x80 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x80 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x80 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x80 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x80 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x80 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x84 "MSCR33,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x84 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x84 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x84 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x84 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x84 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x84 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x84 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x88 "MSCR34,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x88 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x88 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x88 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x88 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x88 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x88 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x88 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8C "MSCR35,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x8C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x8C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x8C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x8C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x8C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x8C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x90 "MSCR36,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x90 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x90 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x90 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x90 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x90 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x90 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x90 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x94 "MSCR37,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x94 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x94 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x94 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x94 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x94 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x94 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x94 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x94 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x98 "MSCR38,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x98 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x98 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x98 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x98 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x98 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x98 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x98 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x9C "MSCR39,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x9C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x9C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x9C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x9C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x9C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x9C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x9C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x9C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xA0 "MSCR40,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xA0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xA0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xA0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xA0 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xA0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xA0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xA4 "MSCR41,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xA4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xA4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xA4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xA4 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xA4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xA4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xA8 "MSCR42,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xA8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xA8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xA8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xA8 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xA8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xA8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xAC "MSCR43,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xAC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xAC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xAC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xAC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xAC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xAC 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xAC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xAC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xB0 "MSCR44,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xB0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xB0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xB0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xB0 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xB0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xB0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xB4 "MSCR45,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xB4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xB4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xB4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xB4 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xB4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xB4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xB8 "MSCR46,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xB8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xB8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xB8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xB8 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xB8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xB8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xBC "MSCR47,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xBC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xBC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xBC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xBC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xBC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xBC 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xBC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xBC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC0 "MSCR48,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xC0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xC0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xC0 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xC0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xC0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC4 "MSCR49,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xC4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xC4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xC4 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xC4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xC4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC8 "MSCR50,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xC8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xC8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xC8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xC8 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xC8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xC8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xCC "MSCR51,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xCC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xCC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xCC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xCC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xCC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xCC 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xCC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xCC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xD0 "MSCR52,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xD0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xD0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xD0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xD0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xD0 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xD0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xD0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xD4 "MSCR53,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xD4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xD4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xD4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xD4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xD4 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xD4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xD4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xD8 "MSCR54,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xD8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xD8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xD8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xD8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xD8 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xD8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xD8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xDC "MSCR55,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xDC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xDC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xDC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xDC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xDC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xDC 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xDC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xDC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xE0 "MSCR56,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xE0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xE0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xE0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xE0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xE0 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xE0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xE0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xE4 "MSCR57,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xE4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xE4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xE4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xE4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xE4 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xE4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xE4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xE8 "MSCR58,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xE8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xE8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xE8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xE8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xE8 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xE8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xE8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xEC "MSCR59,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xEC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xEC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xEC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xEC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xEC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xEC 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xEC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xEC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xF0 "MSCR60,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xF0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xF0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xF0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xF0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xF0 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xF0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xF0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xF4 "MSCR61,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xF4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xF4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xF4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xF4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xF4 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xF4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xF4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xF8 "MSCR62,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xF8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xF8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xF8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xF8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xF8 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xF8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xF8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xFC "MSCR63,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xFC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0xFC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xFC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0xFC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xFC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0xFC 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0xFC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0xFC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x100 "MSCR64,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x100 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x100 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x100 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x100 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x100 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x100 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x100 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x104 "MSCR65,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x104 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x104 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x104 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x104 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x104 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x104 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x104 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x108 "MSCR66,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x108 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x108 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x108 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x108 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x108 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x108 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x108 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10C "MSCR67,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x10C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x10C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x10C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x10C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x10C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x10C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x10C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x110 "MSCR68,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x110 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x110 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x110 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x110 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x110 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x110 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x110 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x114 "MSCR69,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x114 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x114 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x114 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x114 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x114 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x114 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x114 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x118 "MSCR70,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x118 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x118 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x118 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x118 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x118 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x118 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x118 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x11C "MSCR71,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x11C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x11C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x11C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x11C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x11C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x11C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x11C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x11C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x120 "MSCR72,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x120 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x120 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x120 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x120 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x120 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x120 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x120 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x120 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x124 "MSCR73,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x124 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x124 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x124 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x124 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x124 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x124 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x124 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x124 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x128 "MSCR74,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x128 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x128 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x128 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x128 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x128 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x128 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x128 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x128 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x12C "MSCR75,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x12C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x12C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x12C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x12C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x12C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x12C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x12C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x12C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x130 "MSCR76,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x130 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x130 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x130 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x130 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x130 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x130 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x130 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x130 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x134 "MSCR77,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x134 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x134 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x134 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x134 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x134 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x134 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x134 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x134 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x138 "MSCR78,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x138 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x138 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x138 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x138 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x138 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x138 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x138 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x138 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x13C "MSCR79,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x13C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x13C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x13C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x13C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x13C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x13C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x13C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x13C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x140 "MSCR80,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x140 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x140 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x140 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x140 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x140 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x140 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x140 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x140 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x144 "MSCR81,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x144 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x144 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x144 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x144 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x144 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x144 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x144 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x144 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x148 "MSCR82,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x148 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x148 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x148 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x148 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x148 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x148 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x148 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x148 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14C "MSCR83,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x14C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x14C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x14C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x14C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x14C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x14C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x14C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x150 "MSCR84,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x150 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x150 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x150 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x150 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x150 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x150 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x150 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x150 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x154 "MSCR85,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x154 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x154 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x154 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x154 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x154 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x154 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x154 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x154 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x158 "MSCR86,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x158 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x158 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x158 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x158 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x158 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x158 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x158 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x158 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x15C "MSCR87,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x15C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x15C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x15C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x15C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x15C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x15C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x15C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x15C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x160 "MSCR88,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x160 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x160 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x160 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x160 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x160 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x160 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x160 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x160 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x164 "MSCR89,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x164 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x164 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x164 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x164 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x164 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x164 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x164 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x164 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x168 "MSCR90,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x168 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x168 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x168 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x168 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x168 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x168 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x168 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x168 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x16C "MSCR91,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x16C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x16C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x16C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x16C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x16C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x16C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x16C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x16C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x170 "MSCR92,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x170 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x170 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x170 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x170 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x170 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x170 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x170 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x170 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x174 "MSCR93,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x174 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x174 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x174 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x174 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x174 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x174 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x174 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x174 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x178 "MSCR94,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x178 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x178 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x178 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x178 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x178 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x178 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x178 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x178 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x17C "MSCR95,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x17C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x17C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x17C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x17C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x17C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x17C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x17C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x17C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x180 "MSCR96,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x180 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x180 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x180 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x180 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x180 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x180 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x180 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x180 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x184 "MSCR97,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x184 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x184 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x184 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x184 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x184 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x184 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x184 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x184 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x188 "MSCR98,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x188 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x188 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x188 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x188 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x188 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x188 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x188 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x188 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18C "MSCR99,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x18C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x18C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x18C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x18C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x18C 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x18C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x18C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x190 "MSCR100,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x190 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x190 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x190 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x190 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x190 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x190 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x190 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x190 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x194 "MSCR101,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x194 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" bitfld.long 0x194 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x194 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" bitfld.long 0x194 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x194 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" bitfld.long 0x194 12. "PUS,Pull Select" "0: Pulldown,1: Pullup" newline bitfld.long 0x194 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" bitfld.long 0x194 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xA40++0x7 line.long 0x0 "IMCR0,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR1,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xA4C++0xEB line.long 0x0 "IMCR3,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR4,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR5,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR6,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR7,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR8,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR9,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR10,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR11,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "IMCR12,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "IMCR13,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x2C "IMCR14,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x2C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x30 "IMCR15,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x30 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x34 "IMCR16,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x34 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x38 "IMCR17,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x38 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x3C "IMCR18,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x3C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x40 "IMCR19,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x40 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x44 "IMCR20,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x44 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x48 "IMCR21,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x48 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4C "IMCR22,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x50 "IMCR23,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x50 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x54 "IMCR24,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x54 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x58 "IMCR25,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x58 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x5C "IMCR26,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x5C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x60 "IMCR27,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x60 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x64 "IMCR28,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x64 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x68 "IMCR29,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x68 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x6C "IMCR30,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x6C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x70 "IMCR31,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x70 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x74 "IMCR32,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x74 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x78 "IMCR33,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x78 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x7C "IMCR34,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x7C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x80 "IMCR35,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x80 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x84 "IMCR36,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x84 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x88 "IMCR37,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x88 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8C "IMCR38,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x90 "IMCR39,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x90 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x94 "IMCR40,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x94 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x98 "IMCR41,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x98 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x9C "IMCR42,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x9C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xA0 "IMCR43,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xA0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xA4 "IMCR44,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xA4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xA8 "IMCR45,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xA8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xAC "IMCR46,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xAC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xB0 "IMCR47,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xB0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xB4 "IMCR48,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xB4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xB8 "IMCR49,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xB8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xBC "IMCR50,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xBC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC0 "IMCR51,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC4 "IMCR52,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC8 "IMCR53,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xCC "IMCR54,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xCC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xD0 "IMCR55,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xD0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xD4 "IMCR56,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xD4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xD8 "IMCR57,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xD8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xDC "IMCR58,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xDC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xE0 "IMCR59,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xE0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xE4 "IMCR60,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xE4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xE8 "IMCR61,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xE8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xB50++0x3F line.long 0x0 "IMCR68,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR69,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR70,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR71,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR72,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR73,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR74,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR75,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR76,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "IMCR77,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "IMCR78,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x2C "IMCR79,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x2C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x30 "IMCR80,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x30 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x34 "IMCR81,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x34 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x38 "IMCR82,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x38 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x3C "IMCR83,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x3C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.byte 0x1300++0x63 line.byte 0x0 "GPDO3,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1 "GPDO2,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2 "GPDO1,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3 "GPDO0,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4 "GPDO7,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5 "GPDO6,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x6 "GPDO5,SIUL2 GPIO Pad Data Output" bitfld.byte 0x6 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x7 "GPDO4,SIUL2 GPIO Pad Data Output" bitfld.byte 0x7 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x8 "GPDO11,SIUL2 GPIO Pad Data Output" bitfld.byte 0x8 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x9 "GPDO10,SIUL2 GPIO Pad Data Output" bitfld.byte 0x9 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xA "GPDO9,SIUL2 GPIO Pad Data Output" bitfld.byte 0xA 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xB "GPDO8,SIUL2 GPIO Pad Data Output" bitfld.byte 0xB 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xC "GPDO15,SIUL2 GPIO Pad Data Output" bitfld.byte 0xC 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xD "GPDO14,SIUL2 GPIO Pad Data Output" bitfld.byte 0xD 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xE "GPDO13,SIUL2 GPIO Pad Data Output" bitfld.byte 0xE 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xF "GPDO12,SIUL2 GPIO Pad Data Output" bitfld.byte 0xF 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x10 "GPDO19,SIUL2 GPIO Pad Data Output" bitfld.byte 0x10 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x11 "GPDO18,SIUL2 GPIO Pad Data Output" bitfld.byte 0x11 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x12 "GPDO17,SIUL2 GPIO Pad Data Output" bitfld.byte 0x12 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x13 "GPDO16,SIUL2 GPIO Pad Data Output" bitfld.byte 0x13 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x14 "GPDO23,SIUL2 GPIO Pad Data Output" bitfld.byte 0x14 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x15 "GPDO22,SIUL2 GPIO Pad Data Output" bitfld.byte 0x15 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x16 "GPDO21,SIUL2 GPIO Pad Data Output" bitfld.byte 0x16 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x17 "GPDO20,SIUL2 GPIO Pad Data Output" bitfld.byte 0x17 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x18 "GPDO27,SIUL2 GPIO Pad Data Output" bitfld.byte 0x18 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x19 "GPDO26,SIUL2 GPIO Pad Data Output" bitfld.byte 0x19 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1A "GPDO25,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1B "GPDO24,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1C "GPDO31,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1D "GPDO30,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1E "GPDO29,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1F "GPDO28,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x20 "GPDO35,SIUL2 GPIO Pad Data Output" bitfld.byte 0x20 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x21 "GPDO34,SIUL2 GPIO Pad Data Output" bitfld.byte 0x21 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x22 "GPDO33,SIUL2 GPIO Pad Data Output" bitfld.byte 0x22 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x23 "GPDO32,SIUL2 GPIO Pad Data Output" bitfld.byte 0x23 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x24 "GPDO39,SIUL2 GPIO Pad Data Output" bitfld.byte 0x24 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x25 "GPDO38,SIUL2 GPIO Pad Data Output" bitfld.byte 0x25 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x26 "GPDO37,SIUL2 GPIO Pad Data Output" bitfld.byte 0x26 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x27 "GPDO36,SIUL2 GPIO Pad Data Output" bitfld.byte 0x27 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x28 "GPDO43,SIUL2 GPIO Pad Data Output" bitfld.byte 0x28 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x29 "GPDO42,SIUL2 GPIO Pad Data Output" bitfld.byte 0x29 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2A "GPDO41,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2B "GPDO40,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2C "GPDO47,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2D "GPDO46,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2E "GPDO45,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2F "GPDO44,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x30 "GPDO51,SIUL2 GPIO Pad Data Output" bitfld.byte 0x30 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x31 "GPDO50,SIUL2 GPIO Pad Data Output" bitfld.byte 0x31 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x32 "GPDO49,SIUL2 GPIO Pad Data Output" bitfld.byte 0x32 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x33 "GPDO48,SIUL2 GPIO Pad Data Output" bitfld.byte 0x33 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x34 "GPDO55,SIUL2 GPIO Pad Data Output" bitfld.byte 0x34 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x35 "GPDO54,SIUL2 GPIO Pad Data Output" bitfld.byte 0x35 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x36 "GPDO53,SIUL2 GPIO Pad Data Output" bitfld.byte 0x36 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x37 "GPDO52,SIUL2 GPIO Pad Data Output" bitfld.byte 0x37 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x38 "GPDO59,SIUL2 GPIO Pad Data Output" bitfld.byte 0x38 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x39 "GPDO58,SIUL2 GPIO Pad Data Output" bitfld.byte 0x39 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3A "GPDO57,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3B "GPDO56,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3C "GPDO63,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3D "GPDO62,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3E "GPDO61,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3F "GPDO60,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x40 "GPDO67,SIUL2 GPIO Pad Data Output" bitfld.byte 0x40 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x41 "GPDO66,SIUL2 GPIO Pad Data Output" bitfld.byte 0x41 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x42 "GPDO65,SIUL2 GPIO Pad Data Output" bitfld.byte 0x42 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x43 "GPDO64,SIUL2 GPIO Pad Data Output" bitfld.byte 0x43 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x44 "GPDO71,SIUL2 GPIO Pad Data Output" bitfld.byte 0x44 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x45 "GPDO70,SIUL2 GPIO Pad Data Output" bitfld.byte 0x45 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x46 "GPDO69,SIUL2 GPIO Pad Data Output" bitfld.byte 0x46 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x47 "GPDO68,SIUL2 GPIO Pad Data Output" bitfld.byte 0x47 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x48 "GPDO75,SIUL2 GPIO Pad Data Output" bitfld.byte 0x48 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x49 "GPDO74,SIUL2 GPIO Pad Data Output" bitfld.byte 0x49 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4A "GPDO73,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4B "GPDO72,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4C "GPDO79,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4D "GPDO78,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4E "GPDO77,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4F "GPDO76,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x50 "GPDO83,SIUL2 GPIO Pad Data Output" bitfld.byte 0x50 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x51 "GPDO82,SIUL2 GPIO Pad Data Output" bitfld.byte 0x51 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x52 "GPDO81,SIUL2 GPIO Pad Data Output" bitfld.byte 0x52 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x53 "GPDO80,SIUL2 GPIO Pad Data Output" bitfld.byte 0x53 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x54 "GPDO87,SIUL2 GPIO Pad Data Output" bitfld.byte 0x54 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x55 "GPDO86,SIUL2 GPIO Pad Data Output" bitfld.byte 0x55 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x56 "GPDO85,SIUL2 GPIO Pad Data Output" bitfld.byte 0x56 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x57 "GPDO84,SIUL2 GPIO Pad Data Output" bitfld.byte 0x57 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x58 "GPDO91,SIUL2 GPIO Pad Data Output" bitfld.byte 0x58 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x59 "GPDO90,SIUL2 GPIO Pad Data Output" bitfld.byte 0x59 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5A "GPDO89,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5B "GPDO88,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5C "GPDO95,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5D "GPDO94,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5E "GPDO93,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5F "GPDO92,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x60 "GPDO99,SIUL2 GPIO Pad Data Output" bitfld.byte 0x60 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x61 "GPDO98,SIUL2 GPIO Pad Data Output" bitfld.byte 0x61 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x62 "GPDO97,SIUL2 GPIO Pad Data Output" bitfld.byte 0x62 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x63 "GPDO96,SIUL2 GPIO Pad Data Output" bitfld.byte 0x63 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" group.byte 0x1366++0x1 line.byte 0x0 "GPDO101,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1 "GPDO100,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" rgroup.byte 0x1500++0x63 line.byte 0x0 "GPDI3,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1 "GPDI2,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2 "GPDI1,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3 "GPDI0,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4 "GPDI7,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5 "GPDI6,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x6 "GPDI5,SIUL2 GPIO Pad Data Input" bitfld.byte 0x6 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x7 "GPDI4,SIUL2 GPIO Pad Data Input" bitfld.byte 0x7 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x8 "GPDI11,SIUL2 GPIO Pad Data Input" bitfld.byte 0x8 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x9 "GPDI10,SIUL2 GPIO Pad Data Input" bitfld.byte 0x9 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xA "GPDI9,SIUL2 GPIO Pad Data Input" bitfld.byte 0xA 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xB "GPDI8,SIUL2 GPIO Pad Data Input" bitfld.byte 0xB 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xC "GPDI15,SIUL2 GPIO Pad Data Input" bitfld.byte 0xC 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xD "GPDI14,SIUL2 GPIO Pad Data Input" bitfld.byte 0xD 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xE "GPDI13,SIUL2 GPIO Pad Data Input" bitfld.byte 0xE 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xF "GPDI12,SIUL2 GPIO Pad Data Input" bitfld.byte 0xF 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x10 "GPDI19,SIUL2 GPIO Pad Data Input" bitfld.byte 0x10 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x11 "GPDI18,SIUL2 GPIO Pad Data Input" bitfld.byte 0x11 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x12 "GPDI17,SIUL2 GPIO Pad Data Input" bitfld.byte 0x12 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x13 "GPDI16,SIUL2 GPIO Pad Data Input" bitfld.byte 0x13 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x14 "GPDI23,SIUL2 GPIO Pad Data Input" bitfld.byte 0x14 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x15 "GPDI22,SIUL2 GPIO Pad Data Input" bitfld.byte 0x15 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x16 "GPDI21,SIUL2 GPIO Pad Data Input" bitfld.byte 0x16 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x17 "GPDI20,SIUL2 GPIO Pad Data Input" bitfld.byte 0x17 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x18 "GPDI27,SIUL2 GPIO Pad Data Input" bitfld.byte 0x18 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x19 "GPDI26,SIUL2 GPIO Pad Data Input" bitfld.byte 0x19 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1A "GPDI25,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1B "GPDI24,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1C "GPDI31,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1D "GPDI30,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1E "GPDI29,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1F "GPDI28,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x20 "GPDI35,SIUL2 GPIO Pad Data Input" bitfld.byte 0x20 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x21 "GPDI34,SIUL2 GPIO Pad Data Input" bitfld.byte 0x21 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x22 "GPDI33,SIUL2 GPIO Pad Data Input" bitfld.byte 0x22 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x23 "GPDI32,SIUL2 GPIO Pad Data Input" bitfld.byte 0x23 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x24 "GPDI39,SIUL2 GPIO Pad Data Input" bitfld.byte 0x24 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x25 "GPDI38,SIUL2 GPIO Pad Data Input" bitfld.byte 0x25 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x26 "GPDI37,SIUL2 GPIO Pad Data Input" bitfld.byte 0x26 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x27 "GPDI36,SIUL2 GPIO Pad Data Input" bitfld.byte 0x27 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x28 "GPDI43,SIUL2 GPIO Pad Data Input" bitfld.byte 0x28 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x29 "GPDI42,SIUL2 GPIO Pad Data Input" bitfld.byte 0x29 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2A "GPDI41,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2B "GPDI40,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2C "GPDI47,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2D "GPDI46,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2E "GPDI45,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2F "GPDI44,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x30 "GPDI51,SIUL2 GPIO Pad Data Input" bitfld.byte 0x30 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x31 "GPDI50,SIUL2 GPIO Pad Data Input" bitfld.byte 0x31 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x32 "GPDI49,SIUL2 GPIO Pad Data Input" bitfld.byte 0x32 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x33 "GPDI48,SIUL2 GPIO Pad Data Input" bitfld.byte 0x33 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x34 "GPDI55,SIUL2 GPIO Pad Data Input" bitfld.byte 0x34 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x35 "GPDI54,SIUL2 GPIO Pad Data Input" bitfld.byte 0x35 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x36 "GPDI53,SIUL2 GPIO Pad Data Input" bitfld.byte 0x36 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x37 "GPDI52,SIUL2 GPIO Pad Data Input" bitfld.byte 0x37 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x38 "GPDI59,SIUL2 GPIO Pad Data Input" bitfld.byte 0x38 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x39 "GPDI58,SIUL2 GPIO Pad Data Input" bitfld.byte 0x39 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3A "GPDI57,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3B "GPDI56,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3C "GPDI63,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3D "GPDI62,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3E "GPDI61,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3F "GPDI60,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x40 "GPDI67,SIUL2 GPIO Pad Data Input" bitfld.byte 0x40 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x41 "GPDI66,SIUL2 GPIO Pad Data Input" bitfld.byte 0x41 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x42 "GPDI65,SIUL2 GPIO Pad Data Input" bitfld.byte 0x42 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x43 "GPDI64,SIUL2 GPIO Pad Data Input" bitfld.byte 0x43 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x44 "GPDI71,SIUL2 GPIO Pad Data Input" bitfld.byte 0x44 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x45 "GPDI70,SIUL2 GPIO Pad Data Input" bitfld.byte 0x45 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x46 "GPDI69,SIUL2 GPIO Pad Data Input" bitfld.byte 0x46 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x47 "GPDI68,SIUL2 GPIO Pad Data Input" bitfld.byte 0x47 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x48 "GPDI75,SIUL2 GPIO Pad Data Input" bitfld.byte 0x48 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x49 "GPDI74,SIUL2 GPIO Pad Data Input" bitfld.byte 0x49 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4A "GPDI73,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4B "GPDI72,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4C "GPDI79,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4D "GPDI78,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4E "GPDI77,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4F "GPDI76,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x50 "GPDI83,SIUL2 GPIO Pad Data Input" bitfld.byte 0x50 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x51 "GPDI82,SIUL2 GPIO Pad Data Input" bitfld.byte 0x51 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x52 "GPDI81,SIUL2 GPIO Pad Data Input" bitfld.byte 0x52 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x53 "GPDI80,SIUL2 GPIO Pad Data Input" bitfld.byte 0x53 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x54 "GPDI87,SIUL2 GPIO Pad Data Input" bitfld.byte 0x54 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x55 "GPDI86,SIUL2 GPIO Pad Data Input" bitfld.byte 0x55 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x56 "GPDI85,SIUL2 GPIO Pad Data Input" bitfld.byte 0x56 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x57 "GPDI84,SIUL2 GPIO Pad Data Input" bitfld.byte 0x57 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x58 "GPDI91,SIUL2 GPIO Pad Data Input" bitfld.byte 0x58 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x59 "GPDI90,SIUL2 GPIO Pad Data Input" bitfld.byte 0x59 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5A "GPDI89,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5B "GPDI88,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5C "GPDI95,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5D "GPDI94,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5E "GPDI93,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5F "GPDI92,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x60 "GPDI99,SIUL2 GPIO Pad Data Input" bitfld.byte 0x60 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x61 "GPDI98,SIUL2 GPIO Pad Data Input" bitfld.byte 0x61 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x62 "GPDI97,SIUL2 GPIO Pad Data Input" bitfld.byte 0x62 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x63 "GPDI96,SIUL2 GPIO Pad Data Input" bitfld.byte 0x63 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" rgroup.byte 0x1566++0x1 line.byte 0x0 "GPDI101,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1 "GPDI100,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" group.word 0x1700++0xB line.word 0x0 "PGPDO1,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x0 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" bitfld.word 0x0 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" bitfld.word 0x0 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" bitfld.word 0x0 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" bitfld.word 0x0 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" bitfld.word 0x0 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" bitfld.word 0x0 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" bitfld.word 0x0 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x0 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" bitfld.word 0x0 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x2 "PGPDO0,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x2 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" bitfld.word 0x2 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x2 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" bitfld.word 0x2 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x2 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" bitfld.word 0x2 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x2 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" bitfld.word 0x2 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x2 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" bitfld.word 0x2 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x2 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" bitfld.word 0x2 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x2 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" bitfld.word 0x2 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x2 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" bitfld.word 0x2 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x4 "PGPDO3,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x4 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" bitfld.word 0x4 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x4 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" bitfld.word 0x4 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x4 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" bitfld.word 0x4 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x4 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" bitfld.word 0x4 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x4 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" bitfld.word 0x4 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x4 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" bitfld.word 0x4 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x4 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" bitfld.word 0x4 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x4 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" bitfld.word 0x4 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x6 "PGPDO2,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x6 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" bitfld.word 0x6 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x6 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" bitfld.word 0x6 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x6 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" bitfld.word 0x6 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x6 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" bitfld.word 0x6 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x6 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" bitfld.word 0x6 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x6 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" bitfld.word 0x6 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x6 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" bitfld.word 0x6 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x6 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" bitfld.word 0x6 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x8 "PGPDO5,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x8 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" bitfld.word 0x8 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x8 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" bitfld.word 0x8 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x8 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" bitfld.word 0x8 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x8 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" bitfld.word 0x8 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x8 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" bitfld.word 0x8 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x8 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" bitfld.word 0x8 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x8 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" bitfld.word 0x8 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x8 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" bitfld.word 0x8 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0xA "PGPDO4,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0xA 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" bitfld.word 0xA 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0xA 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" bitfld.word 0xA 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0xA 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" bitfld.word 0xA 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0xA 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" bitfld.word 0xA 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0xA 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" bitfld.word 0xA 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0xA 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" bitfld.word 0xA 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0xA 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" bitfld.word 0xA 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0xA 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" bitfld.word 0xA 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" group.word 0x170E++0x1 line.word 0x0 "PGPDO6,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x0 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" bitfld.word 0x0 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" bitfld.word 0x0 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" bitfld.word 0x0 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" rgroup.word 0x1740++0xB line.word 0x0 "PGPDI1,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x0 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" bitfld.word 0x0 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" bitfld.word 0x0 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" bitfld.word 0x0 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" bitfld.word 0x0 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" bitfld.word 0x0 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" bitfld.word 0x0 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" bitfld.word 0x0 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x0 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" bitfld.word 0x0 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x2 "PGPDI0,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x2 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" bitfld.word 0x2 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x2 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" bitfld.word 0x2 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x2 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" bitfld.word 0x2 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x2 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" bitfld.word 0x2 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x2 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" bitfld.word 0x2 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x2 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" bitfld.word 0x2 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x2 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" bitfld.word 0x2 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x2 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" bitfld.word 0x2 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x4 "PGPDI3,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x4 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" bitfld.word 0x4 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x4 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" bitfld.word 0x4 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x4 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" bitfld.word 0x4 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x4 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" bitfld.word 0x4 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x4 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" bitfld.word 0x4 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x4 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" bitfld.word 0x4 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x4 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" bitfld.word 0x4 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x4 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" bitfld.word 0x4 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x6 "PGPDI2,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x6 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" bitfld.word 0x6 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x6 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" bitfld.word 0x6 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x6 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" bitfld.word 0x6 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x6 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" bitfld.word 0x6 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x6 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" bitfld.word 0x6 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x6 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" bitfld.word 0x6 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x6 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" bitfld.word 0x6 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x6 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" bitfld.word 0x6 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x8 "PGPDI5,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x8 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" bitfld.word 0x8 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x8 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" bitfld.word 0x8 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x8 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" bitfld.word 0x8 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x8 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" bitfld.word 0x8 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x8 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" bitfld.word 0x8 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x8 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" bitfld.word 0x8 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x8 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" bitfld.word 0x8 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x8 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" bitfld.word 0x8 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0xA "PGPDI4,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0xA 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" bitfld.word 0xA 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0xA 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" bitfld.word 0xA 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0xA 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" bitfld.word 0xA 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0xA 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" bitfld.word 0xA 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0xA 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" bitfld.word 0xA 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0xA 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" bitfld.word 0xA 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0xA 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" bitfld.word 0xA 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0xA 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" bitfld.word 0xA 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" rgroup.word 0x174E++0x1 line.word 0x0 "PGPDI6,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x0 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" bitfld.word 0x0 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" bitfld.word 0x0 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" bitfld.word 0x0 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" group.long 0x1780++0x1B line.long 0x0 "MPGPDO0,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x0 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" bitfld.long 0x0 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x0 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" bitfld.long 0x0 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x0 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" bitfld.long 0x0 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x0 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" bitfld.long 0x0 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x0 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" bitfld.long 0x0 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x0 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" bitfld.long 0x0 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x0 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" bitfld.long 0x0 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x0 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" bitfld.long 0x0 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x0 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" bitfld.long 0x0 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x0 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" bitfld.long 0x0 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x0 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" bitfld.long 0x0 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x0 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" bitfld.long 0x0 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x0 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" bitfld.long 0x0 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x0 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" bitfld.long 0x0 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x0 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" bitfld.long 0x0 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x0 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" bitfld.long 0x0 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x4 "MPGPDO1,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x4 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" bitfld.long 0x4 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x4 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" bitfld.long 0x4 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x4 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" bitfld.long 0x4 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x4 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" bitfld.long 0x4 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x4 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" bitfld.long 0x4 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x4 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" bitfld.long 0x4 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x4 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" bitfld.long 0x4 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x4 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" bitfld.long 0x4 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x4 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" bitfld.long 0x4 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x4 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" bitfld.long 0x4 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x4 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" bitfld.long 0x4 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x4 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" bitfld.long 0x4 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x4 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" bitfld.long 0x4 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x4 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" bitfld.long 0x4 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x4 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" bitfld.long 0x4 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x4 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" bitfld.long 0x4 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x8 "MPGPDO2,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x8 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" bitfld.long 0x8 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x8 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" bitfld.long 0x8 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x8 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" bitfld.long 0x8 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x8 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" bitfld.long 0x8 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x8 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" bitfld.long 0x8 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x8 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" bitfld.long 0x8 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x8 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" bitfld.long 0x8 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x8 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" bitfld.long 0x8 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x8 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" bitfld.long 0x8 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x8 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" bitfld.long 0x8 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x8 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" bitfld.long 0x8 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x8 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" bitfld.long 0x8 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x8 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" bitfld.long 0x8 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x8 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" bitfld.long 0x8 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x8 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" bitfld.long 0x8 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x8 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" bitfld.long 0x8 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0xC "MPGPDO3,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0xC 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" bitfld.long 0xC 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0xC 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" bitfld.long 0xC 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0xC 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" bitfld.long 0xC 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0xC 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" bitfld.long 0xC 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0xC 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" bitfld.long 0xC 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0xC 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" bitfld.long 0xC 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0xC 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" bitfld.long 0xC 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0xC 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" bitfld.long 0xC 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0xC 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" bitfld.long 0xC 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0xC 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" bitfld.long 0xC 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0xC 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" bitfld.long 0xC 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0xC 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" bitfld.long 0xC 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0xC 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" bitfld.long 0xC 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0xC 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" bitfld.long 0xC 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0xC 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" bitfld.long 0xC 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0xC 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" bitfld.long 0xC 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x10 "MPGPDO4,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x10 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" bitfld.long 0x10 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x10 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" bitfld.long 0x10 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x10 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" bitfld.long 0x10 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x10 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" bitfld.long 0x10 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x10 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" bitfld.long 0x10 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x10 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" bitfld.long 0x10 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x10 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" bitfld.long 0x10 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x10 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" bitfld.long 0x10 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x10 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" bitfld.long 0x10 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x10 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" bitfld.long 0x10 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x10 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" bitfld.long 0x10 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x10 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" bitfld.long 0x10 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x10 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" bitfld.long 0x10 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x10 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" bitfld.long 0x10 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x10 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" bitfld.long 0x10 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x10 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" bitfld.long 0x10 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x14 "MPGPDO5,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x14 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" bitfld.long 0x14 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x14 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" bitfld.long 0x14 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x14 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" bitfld.long 0x14 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x14 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" bitfld.long 0x14 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x14 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" bitfld.long 0x14 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x14 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" bitfld.long 0x14 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x14 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" bitfld.long 0x14 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x14 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" bitfld.long 0x14 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x14 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" bitfld.long 0x14 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x14 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" bitfld.long 0x14 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x14 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" bitfld.long 0x14 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x14 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" bitfld.long 0x14 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x14 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" bitfld.long 0x14 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x14 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" bitfld.long 0x14 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x14 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" bitfld.long 0x14 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x14 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" bitfld.long 0x14 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x18 "MPGPDO6,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x18 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" bitfld.long 0x18 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x18 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" bitfld.long 0x18 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x18 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" bitfld.long 0x18 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x18 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" bitfld.long 0x18 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x18 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" bitfld.long 0x18 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x18 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" bitfld.long 0x18 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" tree.end tree "SIUL2_1" base ad:0x44010000 rgroup.long 0x4++0x7 line.long 0x0 "MIDR1,SIUL2 MCU ID 1" hexmask.long.byte 0x0 26.--31. 1. "PRODUCT_FAMILY_LETTER,Product Family Letter" newline hexmask.long.word 0x0 16.--25. 1. "PRODUCT_FAMILY_NO,Product Family Number" newline hexmask.long.byte 0x0 10.--15. 1. "PART_NO_LETTER,Part Number Letter" newline hexmask.long.byte 0x0 0.--5. 1. "SYSTEM_RAM_SIZE,System RAM Size" line.long 0x4 "MIDR2,SIUL2 MCU ID 2" bitfld.long 0x4 30.--31. "FLASH_VENDOR,Flash Vendor" "0: None,1: Macronix,?,?" newline bitfld.long 0x4 28.--29. "FLASH_CONFIG,Flash Configuration" "0: x1 I/O,1: x8 I/O,?,?" newline bitfld.long 0x4 26.--27. "SUBMINOR_MASK,Subminor Mask Revision" "0: Rev x.x.0,1: Rev x.x.1,?,?" newline hexmask.long.word 0x4 16.--25. 1. "COMPUTE_DIE_PART_NUMBER,Compute Die Part Number" newline bitfld.long 0x4 15. "SERDES,SerDes subsystem" "0: No,1: Yes" newline bitfld.long 0x4 14. "OTA,Over The Air" "0: No,1: Yes" newline bitfld.long 0x4 13. "HPBF,High Performance Buffered Flash" "0: No,1: Yes" newline bitfld.long 0x4 12. "LAX,Linear Algebraic Accelerator" "0: No,1: Yes" newline bitfld.long 0x4 1. "AE1,Application Extension 1" "0: No,1: Yes" newline bitfld.long 0x4 0. "AE0,Application Extension 0" "0: No,1: Yes" group.long 0x10++0x3 line.long 0x0 "DISR0,SIUL2 DMA/Interrupt Status Flag 0" eventfld.long 0x0 31. "EIF31,External Interrupt Status Flag 31" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER31 and.." newline eventfld.long 0x0 30. "EIF30,External Interrupt Status Flag 30" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER30 and.." newline eventfld.long 0x0 29. "EIF29,External Interrupt Status Flag 29" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER29 and.." newline eventfld.long 0x0 28. "EIF28,External Interrupt Status Flag 28" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER28 and.." newline eventfld.long 0x0 27. "EIF27,External Interrupt Status Flag 27" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER27 and.." newline eventfld.long 0x0 26. "EIF26,External Interrupt Status Flag 26" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER26 and.." newline eventfld.long 0x0 25. "EIF25,External Interrupt Status Flag 25" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER25 and.." newline eventfld.long 0x0 24. "EIF24,External Interrupt Status Flag 24" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER24 and.." newline eventfld.long 0x0 23. "EIF23,External Interrupt Status Flag 23" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER23 and.." newline eventfld.long 0x0 22. "EIF22,External Interrupt Status Flag 22" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER22 and.." newline eventfld.long 0x0 21. "EIF21,External Interrupt Status Flag 21" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER21 and.." newline eventfld.long 0x0 20. "EIF20,External Interrupt Status Flag 20" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER20 and.." newline eventfld.long 0x0 19. "EIF19,External Interrupt Status Flag 19" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER19 and.." newline eventfld.long 0x0 18. "EIF18,External Interrupt Status Flag 18" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER18 and.." newline eventfld.long 0x0 17. "EIF17,External Interrupt Status Flag 17" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER17 and.." newline eventfld.long 0x0 16. "EIF16,External Interrupt Status Flag 16" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER16 and.." newline eventfld.long 0x0 15. "EIF15,External Interrupt Status Flag 15" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER15 and.." newline eventfld.long 0x0 14. "EIF14,External Interrupt Status Flag 14" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER14 and.." newline eventfld.long 0x0 13. "EIF13,External Interrupt Status Flag 13" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER13 and.." newline eventfld.long 0x0 12. "EIF12,External Interrupt Status Flag 12" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER12 and.." newline eventfld.long 0x0 11. "EIF11,External Interrupt Status Flag 11" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER11 and.." newline eventfld.long 0x0 10. "EIF10,External Interrupt Status Flag 10" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER10 and.." newline eventfld.long 0x0 9. "EIF9,External Interrupt Status Flag 9" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER9 and.." newline eventfld.long 0x0 8. "EIF8,External Interrupt Status Flag 8" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER8 and.." newline eventfld.long 0x0 7. "EIF7,External Interrupt Status Flag 7" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER7 and.." newline eventfld.long 0x0 6. "EIF6,External Interrupt Status Flag 6" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER6 and.." newline eventfld.long 0x0 5. "EIF5,External Interrupt Status Flag 5" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER5 and.." newline eventfld.long 0x0 4. "EIF4,External Interrupt Status Flag 4" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER4 and.." newline eventfld.long 0x0 3. "EIF3,External Interrupt Status Flag 3" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER3 and.." newline eventfld.long 0x0 2. "EIF2,External Interrupt Status Flag 2" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER2 and.." newline eventfld.long 0x0 1. "EIF1,External Interrupt Status Flag 1" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER1 and.." newline eventfld.long 0x0 0. "EIF0,External Interrupt Status Flag 0" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER0 and.." group.long 0x18++0x3 line.long 0x0 "DIRER0,SIUL2 DMA/Interrupt Request Enable 0" bitfld.long 0x0 31. "EIRE31,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "EIRE30,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "EIRE29,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "EIRE28,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "EIRE27,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "EIRE26,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "EIRE25,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "EIRE24,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "EIRE23,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "EIRE22,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "EIRE21,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "EIRE20,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "EIRE19,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "EIRE18,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "EIRE17,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "EIRE16,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "EIRE15,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "EIRE14,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "EIRE13,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "EIRE12,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "EIRE11,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "EIRE10,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "EIRE9,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "EIRE8,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "EIRE7,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "EIRE6,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "EIRE5,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "EIRE4,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "EIRE3,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "EIRE2,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "EIRE1,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "EIRE0,External Interrupt Request Enable" "0: Disabled,1: Enabled" group.long 0x20++0x3 line.long 0x0 "DIRSR0,SIUL2 DMA/Interrupt Request Select 0" bitfld.long 0x0 31. "DIRSR31,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 30. "DIRSR30,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 29. "DIRSR29,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 28. "DIRSR28,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 27. "DIRSR27,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 26. "DIRSR26,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 25. "DIRSR25,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 24. "DIRSR24,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 23. "DIRSR23,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 22. "DIRSR22,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 21. "DIRSR21,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 20. "DIRSR20,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 19. "DIRSR19,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 18. "DIRSR18,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 17. "DIRSR17,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 16. "DIRSR16,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 15. "DIRSR15,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 14. "DIRSR14,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 13. "DIRSR13,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 12. "DIRSR12,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 11. "DIRSR11,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 10. "DIRSR10,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 9. "DIRSR9,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 8. "DIRSR8,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 7. "DIRSR7,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 6. "DIRSR6,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 5. "DIRSR5,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 4. "DIRSR4,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 3. "DIRSR3,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 2. "DIRSR2,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 1. "DIRSR1,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 0. "DIRSR0,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" group.long 0x28++0x3 line.long 0x0 "IREER0,SIUL2 Interrupt Rising-Edge Event Enable 0" bitfld.long 0x0 31. "IREE31,Enables rising-edge events to set DISR0[EIF31]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "IREE30,Enables rising-edge events to set DISR0[EIF30]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "IREE29,Enables rising-edge events to set DISR0[EIF29]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "IREE28,Enables rising-edge events to set DISR0[EIF28]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "IREE27,Enables rising-edge events to set DISR0[EIF27]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "IREE26,Enables rising-edge events to set DISR0[EIF26]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "IREE25,Enables rising-edge events to set DISR0[EIF25]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "IREE24,Enables rising-edge events to set DISR0[EIF24]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "IREE23,Enables rising-edge events to set DISR0[EIF23]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "IREE22,Enables rising-edge events to set DISR0[EIF22]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "IREE21,Enables rising-edge events to set DISR0[EIF21]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "IREE20,Enables rising-edge events to set DISR0[EIF20]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "IREE19,Enables rising-edge events to set DISR0[EIF19]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "IREE18,Enables rising-edge events to set DISR0[EIF18]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "IREE17,Enables rising-edge events to set DISR0[EIF17]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "IREE16,Enables rising-edge events to set DISR0[EIF16]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "IREE15,Enables rising-edge events to set DISR0[EIF15]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "IREE14,Enables rising-edge events to set DISR0[EIF14]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "IREE13,Enables rising-edge events to set DISR0[EIF13]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "IREE12,Enables rising-edge events to set DISR0[EIF12]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "IREE11,Enables rising-edge events to set DISR0[EIF11]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "IREE10,Enables rising-edge events to set DISR0[EIF10]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IREE9,Enables rising-edge events to set DISR0[EIF9]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "IREE8,Enables rising-edge events to set DISR0[EIF8]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IREE7,Enables rising-edge events to set DISR0[EIF7]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IREE6,Enables rising-edge events to set DISR0[EIF6]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IREE5,Enables rising-edge events to set DISR0[EIF5]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "IREE4,Enables rising-edge events to set DISR0[EIF4]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IREE3,Enables rising-edge events to set DISR0[EIF3]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IREE2,Enables rising-edge events to set DISR0[EIF2]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IREE1,Enables rising-edge events to set DISR0[EIF1]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "IREE0,Enables rising-edge events to set DISR0[EIF0]." "0: Disabled,1: Enabled" group.long 0x30++0x3 line.long 0x0 "IFEER0,SIUL2 Interrupt Falling-Edge Event Enable 0" bitfld.long 0x0 31. "IFEE31,Enables falling-edge events to set DISR0[EIF31]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "IFEE30,Enables falling-edge events to set DISR0[EIF30]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "IFEE29,Enables falling-edge events to set DISR0[EIF29]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "IFEE28,Enables falling-edge events to set DISR0[EIF28]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "IFEE27,Enables falling-edge events to set DISR0[EIF27]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "IFEE26,Enables falling-edge events to set DISR0[EIF26]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "IFEE25,Enables falling-edge events to set DISR0[EIF25]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "IFEE24,Enables falling-edge events to set DISR0[EIF24]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "IFEE23,Enables falling-edge events to set DISR0[EIF23]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "IFEE22,Enables falling-edge events to set DISR0[EIF22]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "IFEE21,Enables falling-edge events to set DISR0[EIF21]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "IFEE20,Enables falling-edge events to set DISR0[EIF20]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "IFEE19,Enables falling-edge events to set DISR0[EIF19]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "IFEE18,Enables falling-edge events to set DISR0[EIF18]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "IFEE17,Enables falling-edge events to set DISR0[EIF17]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "IFEE16,Enables falling-edge events to set DISR0[EIF16]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "IFEE15,Enables falling-edge events to set DISR0[EIF15]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "IFEE14,Enables falling-edge events to set DISR0[EIF14]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "IFEE13,Enables falling-edge events to set DISR0[EIF13]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "IFEE12,Enables falling-edge events to set DISR0[EIF12]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "IFEE11,Enables falling-edge events to set DISR0[EIF11]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "IFEE10,Enables falling-edge events to set DISR0[EIF10]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IFEE9,Enables falling-edge events to set DISR0[EIF9]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "IFEE8,Enables falling-edge events to set DISR0[EIF8]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IFEE7,Enables falling-edge events to set DISR0[EIF7]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IFEE6,Enables falling-edge events to set DISR0[EIF6]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IFEE5,Enables falling-edge events to set DISR0[EIF5]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "IFEE4,Enables falling-edge events to set DISR0[EIF4]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IFEE3,Enables falling-edge events to set DISR0[EIF3]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IFEE2,Enables falling-edge events to set DISR0[EIF2]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IFEE1,Enables falling-edge events to set DISR0[EIF1]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "IFEE0,Enables falling-edge events to set DISR0[EIF0]." "0: Disabled,1: Enabled" group.long 0x38++0x3 line.long 0x0 "IFER0,SIUL2 Interrupt Filter Enable 0" bitfld.long 0x0 31. "IFE31,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "IFE30,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "IFE29,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "IFE28,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "IFE27,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "IFE26,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "IFE25,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "IFE24,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "IFE23,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "IFE22,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "IFE21,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "IFE20,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "IFE19,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "IFE18,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "IFE17,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "IFE16,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "IFE15,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "IFE14,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "IFE13,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "IFE12,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "IFE11,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "IFE10,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IFE9,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "IFE8,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IFE7,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IFE6,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IFE5,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "IFE4,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IFE3,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IFE2,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IFE1,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "IFE0,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" group.long 0x40++0x83 line.long 0x0 "IFMCR0,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x0 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x4 "IFMCR1,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x4 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x8 "IFMCR2,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x8 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0xC "IFMCR3,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0xC 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x10 "IFMCR4,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x10 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x14 "IFMCR5,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x14 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x18 "IFMCR6,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x18 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x1C "IFMCR7,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x1C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x20 "IFMCR8,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x20 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x24 "IFMCR9,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x24 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x28 "IFMCR10,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x28 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x2C "IFMCR11,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x2C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x30 "IFMCR12,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x30 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x34 "IFMCR13,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x34 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x38 "IFMCR14,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x38 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x3C "IFMCR15,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x3C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x40 "IFMCR16,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x40 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x44 "IFMCR17,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x44 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x48 "IFMCR18,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x48 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x4C "IFMCR19,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x4C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x50 "IFMCR20,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x50 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x54 "IFMCR21,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x54 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x58 "IFMCR22,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x58 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x5C "IFMCR23,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x5C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x60 "IFMCR24,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x60 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x64 "IFMCR25,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x64 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x68 "IFMCR26,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x68 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x6C "IFMCR27,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x6C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x70 "IFMCR28,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x70 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x74 "IFMCR29,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x74 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x78 "IFMCR30,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x78 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x7C "IFMCR31,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x7C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x80 "IFCPR,SIUL2 Interrupt Filter Clock Prescaler" hexmask.long.byte 0x80 0.--3. 1. "IFCP,Interrupt Filter Clock Prescaler setting" group.long 0x400++0x2B line.long 0x0 "MSCR112,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "MSCR113,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "MSCR114,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "MSCR115,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "MSCR116,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x10 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x10 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x10 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x10 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "MSCR117,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x14 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x14 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x14 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x14 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "MSCR118,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x18 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x18 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x18 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x18 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "MSCR119,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x1C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x1C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x1C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x1C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "MSCR120,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x20 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x20 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x20 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x20 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "MSCR121,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x24 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x24 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x24 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x24 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "MSCR122,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x28 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x28 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x28 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x28 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0x480++0xBB line.long 0x0 "MSCR144,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "MSCR145,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "MSCR146,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "MSCR147,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "MSCR148,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x10 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x10 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x10 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x10 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "MSCR149,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x14 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x14 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x14 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x14 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "MSCR150,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x18 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x18 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x18 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x18 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "MSCR151,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x1C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x1C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x1C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x1C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "MSCR152,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x20 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x20 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x20 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x20 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "MSCR153,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x24 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x24 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x24 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x24 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "MSCR154,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x28 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x28 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x28 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x28 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x2C "MSCR155,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x2C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x2C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x2C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x2C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x2C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x30 "MSCR156,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x30 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x30 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x30 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x30 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x30 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x34 "MSCR157,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x34 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x34 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x34 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x34 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x34 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x38 "MSCR158,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x38 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x38 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x38 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x38 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x38 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x3C "MSCR159,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x3C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x3C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x3C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x3C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x3C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x40 "MSCR160,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x40 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x40 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x40 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x40 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x40 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x44 "MSCR161,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x44 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x44 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x44 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x44 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x44 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x48 "MSCR162,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x48 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x48 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x48 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x48 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x48 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4C "MSCR163,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x4C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x4C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x4C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x4C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x50 "MSCR164,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x50 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x50 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x50 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x50 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x50 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x54 "MSCR165,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x54 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x54 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x54 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x54 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x54 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x58 "MSCR166,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x58 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x58 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x58 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x58 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x58 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x5C "MSCR167,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x5C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x5C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x5C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x5C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x5C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x60 "MSCR168,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x60 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x60 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x60 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x60 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x60 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x64 "MSCR169,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x64 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x64 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x64 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x64 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x64 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x68 "MSCR170,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x68 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x68 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x68 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x68 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x68 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x6C "MSCR171,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x6C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x6C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x6C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x6C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x6C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x70 "MSCR172,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x70 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x70 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x70 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x70 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x70 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x74 "MSCR173,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x74 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x74 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x74 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x74 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x74 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x78 "MSCR174,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x78 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x78 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x78 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x78 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x78 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x7C "MSCR175,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x7C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x7C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x7C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x7C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x7C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x80 "MSCR176,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x80 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x80 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x80 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x80 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x80 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x84 "MSCR177,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x84 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x84 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x84 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x84 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x84 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x88 "MSCR178,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x88 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x88 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x88 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x88 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x88 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8C "MSCR179,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x8C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x8C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x8C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x8C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x90 "MSCR180,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x90 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x90 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x90 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x90 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x90 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x94 "MSCR181,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x94 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x94 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x94 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x94 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x94 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x94 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x98 "MSCR182,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x98 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x98 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x98 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x98 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x98 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x9C "MSCR183,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x9C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x9C 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0x9C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x9C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x9C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x9C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xA0 "MSCR184,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xA0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xA0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xA0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xA0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xA4 "MSCR185,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xA4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xA4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xA4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xA4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xA8 "MSCR186,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xA8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xA8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xA8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xA8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xAC "MSCR187,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xAC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xAC 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xAC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xAC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xAC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xAC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xB0 "MSCR188,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xB0 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xB0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xB0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xB0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xB4 "MSCR189,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xB4 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xB4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xB4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xB4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xB8 "MSCR190,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xB8 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1" newline bitfld.long 0xB8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 12. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xB8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xB8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xC1C++0xB line.long 0x0 "IMCR119,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR120,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR121,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xC40++0x7 line.long 0x0 "IMCR128,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR129,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xC7C++0x23 line.long 0x0 "IMCR143,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR144,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR145,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR146,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR147,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR148,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR149,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR150,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR151,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xCA4++0x23 line.long 0x0 "IMCR153,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR154,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR155,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR156,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR157,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR158,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR159,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR160,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR161,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xD74++0x1F line.long 0x0 "IMCR205,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR206,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR207,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR208,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR209,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR210,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR211,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR212,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xDC0++0x7 line.long 0x0 "IMCR224,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR225,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xDE4++0x3F line.long 0x0 "IMCR233,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR234,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR235,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR236,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR237,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR238,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR239,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR240,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR241,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "IMCR242,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "IMCR243,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x2C "IMCR244,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x2C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x30 "IMCR245,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x30 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x34 "IMCR246,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x34 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x38 "IMCR247,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x38 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x3C "IMCR248,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x3C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xE84++0x7 line.long 0x0 "IMCR273,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR274,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xE98++0xF line.long 0x0 "IMCR278,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR279,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR280,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR281,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xEAC++0xF line.long 0x0 "IMCR283,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR284,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR285,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR286,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xEC0++0x1B line.long 0x0 "IMCR288,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR289,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR290,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR291,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR292,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR293,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR294,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xEE0++0x1B line.long 0x0 "IMCR296,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR297,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR298,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR299,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR300,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR301,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR302,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xF00++0x1B line.long 0x0 "IMCR304,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR305,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR306,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR307,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR308,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR309,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR310,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xF20++0xB line.long 0x0 "IMCR312,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR313,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR314,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xF30++0x3 line.long 0x0 "IMCR316,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xF38++0x3 line.long 0x0 "IMCR318,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xF48++0x4B line.long 0x0 "IMCR322,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR323,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR324,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR325,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR326,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR327,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR328,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR329,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR330,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "IMCR331,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "IMCR332,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x2C "IMCR333,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x2C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x30 "IMCR334,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x30 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x34 "IMCR335,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x34 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x38 "IMCR336,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x38 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x3C "IMCR337,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x3C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x40 "IMCR338,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x40 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x44 "IMCR339,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x44 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x48 "IMCR340,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x48 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xF9C++0x47 line.long 0x0 "IMCR343,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR344,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR345,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR346,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR347,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR348,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR349,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR350,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR351,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "IMCR352,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "IMCR353,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x2C "IMCR354,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x2C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x30 "IMCR355,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x30 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x34 "IMCR356,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x34 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x38 "IMCR357,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x38 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x3C "IMCR358,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x3C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x40 "IMCR359,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x40 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x44 "IMCR360,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x44 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0xFEC++0x47 line.long 0x0 "IMCR363,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR364,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR365,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR366,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR367,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR368,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR369,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR370,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR371,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "IMCR372,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "IMCR373,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x2C "IMCR374,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x2C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x30 "IMCR375,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x30 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x34 "IMCR376,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x34 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x38 "IMCR377,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x38 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x3C "IMCR378,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x3C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x40 "IMCR379,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x40 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x44 "IMCR380,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x44 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0x103C++0x2B line.long 0x0 "IMCR383,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR384,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR385,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR386,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR387,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR388,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR389,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR390,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR391,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "IMCR392,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "IMCR393,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0x1078++0x8F line.long 0x0 "IMCR398,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR399,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR400,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR401,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x10 "IMCR402,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x10 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x14 "IMCR403,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x14 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x18 "IMCR404,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x18 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x1C "IMCR405,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x1C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x20 "IMCR406,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x20 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x24 "IMCR407,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x24 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x28 "IMCR408,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x28 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x2C "IMCR409,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x2C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x30 "IMCR410,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x30 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x34 "IMCR411,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x34 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x38 "IMCR412,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x38 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x3C "IMCR413,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x3C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x40 "IMCR414,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x40 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x44 "IMCR415,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x44 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x48 "IMCR416,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x48 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4C "IMCR417,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x50 "IMCR418,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x50 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x54 "IMCR419,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x54 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x58 "IMCR420,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x58 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x5C "IMCR421,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x5C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x60 "IMCR422,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x60 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x64 "IMCR423,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x64 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x68 "IMCR424,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x68 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x6C "IMCR425,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x6C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x70 "IMCR426,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x70 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x74 "IMCR427,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x74 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x78 "IMCR428,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x78 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x7C "IMCR429,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x7C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x80 "IMCR430,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x80 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x84 "IMCR431,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x84 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x88 "IMCR432,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x88 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8C "IMCR433,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8C 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0x118C++0xF line.long 0x0 "IMCR467,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR468,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR469,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0xC "IMCR470,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0xC 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0x11A4++0xB line.long 0x0 "IMCR473,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR474,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR475,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0x11B8++0xB line.long 0x0 "IMCR478,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR479,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR480,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0x11CC++0xB line.long 0x0 "IMCR483,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR484,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR485,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0x11E0++0xB line.long 0x0 "IMCR488,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR489,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR490,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.long 0x11F4++0xB line.long 0x0 "IMCR493,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x0 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x4 "IMCR494,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x4 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" line.long 0x8 "IMCR495,SIUL2 Input Multiplexed Signal Configuration" bitfld.long 0x8 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7" group.byte 0x1370++0x7 line.byte 0x0 "GPDO115,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1 "GPDO114,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2 "GPDO113,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3 "GPDO112,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4 "GPDO119,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5 "GPDO118,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x6 "GPDO117,SIUL2 GPIO Pad Data Output" bitfld.byte 0x6 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x7 "GPDO116,SIUL2 GPIO Pad Data Output" bitfld.byte 0x7 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" group.byte 0x1379++0x2 line.byte 0x0 "GPDO122,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1 "GPDO121,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2 "GPDO120,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" group.byte 0x1390++0x2B line.byte 0x0 "GPDO147,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1 "GPDO146,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2 "GPDO145,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3 "GPDO144,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4 "GPDO151,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5 "GPDO150,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x6 "GPDO149,SIUL2 GPIO Pad Data Output" bitfld.byte 0x6 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x7 "GPDO148,SIUL2 GPIO Pad Data Output" bitfld.byte 0x7 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x8 "GPDO155,SIUL2 GPIO Pad Data Output" bitfld.byte 0x8 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x9 "GPDO154,SIUL2 GPIO Pad Data Output" bitfld.byte 0x9 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xA "GPDO153,SIUL2 GPIO Pad Data Output" bitfld.byte 0xA 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xB "GPDO152,SIUL2 GPIO Pad Data Output" bitfld.byte 0xB 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xC "GPDO159,SIUL2 GPIO Pad Data Output" bitfld.byte 0xC 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xD "GPDO158,SIUL2 GPIO Pad Data Output" bitfld.byte 0xD 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xE "GPDO157,SIUL2 GPIO Pad Data Output" bitfld.byte 0xE 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xF "GPDO156,SIUL2 GPIO Pad Data Output" bitfld.byte 0xF 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x10 "GPDO163,SIUL2 GPIO Pad Data Output" bitfld.byte 0x10 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x11 "GPDO162,SIUL2 GPIO Pad Data Output" bitfld.byte 0x11 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x12 "GPDO161,SIUL2 GPIO Pad Data Output" bitfld.byte 0x12 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x13 "GPDO160,SIUL2 GPIO Pad Data Output" bitfld.byte 0x13 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x14 "GPDO167,SIUL2 GPIO Pad Data Output" bitfld.byte 0x14 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x15 "GPDO166,SIUL2 GPIO Pad Data Output" bitfld.byte 0x15 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x16 "GPDO165,SIUL2 GPIO Pad Data Output" bitfld.byte 0x16 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x17 "GPDO164,SIUL2 GPIO Pad Data Output" bitfld.byte 0x17 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x18 "GPDO171,SIUL2 GPIO Pad Data Output" bitfld.byte 0x18 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x19 "GPDO170,SIUL2 GPIO Pad Data Output" bitfld.byte 0x19 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1A "GPDO169,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1B "GPDO168,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1C "GPDO175,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1D "GPDO174,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1E "GPDO173,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1F "GPDO172,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x20 "GPDO179,SIUL2 GPIO Pad Data Output" bitfld.byte 0x20 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x21 "GPDO178,SIUL2 GPIO Pad Data Output" bitfld.byte 0x21 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x22 "GPDO177,SIUL2 GPIO Pad Data Output" bitfld.byte 0x22 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x23 "GPDO176,SIUL2 GPIO Pad Data Output" bitfld.byte 0x23 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x24 "GPDO183,SIUL2 GPIO Pad Data Output" bitfld.byte 0x24 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x25 "GPDO182,SIUL2 GPIO Pad Data Output" bitfld.byte 0x25 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x26 "GPDO181,SIUL2 GPIO Pad Data Output" bitfld.byte 0x26 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x27 "GPDO180,SIUL2 GPIO Pad Data Output" bitfld.byte 0x27 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x28 "GPDO187,SIUL2 GPIO Pad Data Output" bitfld.byte 0x28 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x29 "GPDO186,SIUL2 GPIO Pad Data Output" bitfld.byte 0x29 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2A "GPDO185,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2B "GPDO184,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" group.byte 0x13BD++0x2 line.byte 0x0 "GPDO190,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1 "GPDO189,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2 "GPDO188,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" rgroup.byte 0x1570++0x7 line.byte 0x0 "GPDI115,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1 "GPDI114,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2 "GPDI113,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3 "GPDI112,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4 "GPDI119,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5 "GPDI118,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x6 "GPDI117,SIUL2 GPIO Pad Data Input" bitfld.byte 0x6 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x7 "GPDI116,SIUL2 GPIO Pad Data Input" bitfld.byte 0x7 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" rgroup.byte 0x1579++0x2 line.byte 0x0 "GPDI122,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1 "GPDI121,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2 "GPDI120,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" rgroup.byte 0x1590++0x2B line.byte 0x0 "GPDI147,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1 "GPDI146,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2 "GPDI145,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3 "GPDI144,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4 "GPDI151,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5 "GPDI150,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x6 "GPDI149,SIUL2 GPIO Pad Data Input" bitfld.byte 0x6 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x7 "GPDI148,SIUL2 GPIO Pad Data Input" bitfld.byte 0x7 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x8 "GPDI155,SIUL2 GPIO Pad Data Input" bitfld.byte 0x8 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x9 "GPDI154,SIUL2 GPIO Pad Data Input" bitfld.byte 0x9 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xA "GPDI153,SIUL2 GPIO Pad Data Input" bitfld.byte 0xA 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xB "GPDI152,SIUL2 GPIO Pad Data Input" bitfld.byte 0xB 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xC "GPDI159,SIUL2 GPIO Pad Data Input" bitfld.byte 0xC 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xD "GPDI158,SIUL2 GPIO Pad Data Input" bitfld.byte 0xD 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xE "GPDI157,SIUL2 GPIO Pad Data Input" bitfld.byte 0xE 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xF "GPDI156,SIUL2 GPIO Pad Data Input" bitfld.byte 0xF 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x10 "GPDI163,SIUL2 GPIO Pad Data Input" bitfld.byte 0x10 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x11 "GPDI162,SIUL2 GPIO Pad Data Input" bitfld.byte 0x11 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x12 "GPDI161,SIUL2 GPIO Pad Data Input" bitfld.byte 0x12 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x13 "GPDI160,SIUL2 GPIO Pad Data Input" bitfld.byte 0x13 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x14 "GPDI167,SIUL2 GPIO Pad Data Input" bitfld.byte 0x14 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x15 "GPDI166,SIUL2 GPIO Pad Data Input" bitfld.byte 0x15 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x16 "GPDI165,SIUL2 GPIO Pad Data Input" bitfld.byte 0x16 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x17 "GPDI164,SIUL2 GPIO Pad Data Input" bitfld.byte 0x17 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x18 "GPDI171,SIUL2 GPIO Pad Data Input" bitfld.byte 0x18 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x19 "GPDI170,SIUL2 GPIO Pad Data Input" bitfld.byte 0x19 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1A "GPDI169,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1B "GPDI168,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1C "GPDI175,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1D "GPDI174,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1E "GPDI173,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1F "GPDI172,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x20 "GPDI179,SIUL2 GPIO Pad Data Input" bitfld.byte 0x20 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x21 "GPDI178,SIUL2 GPIO Pad Data Input" bitfld.byte 0x21 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x22 "GPDI177,SIUL2 GPIO Pad Data Input" bitfld.byte 0x22 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x23 "GPDI176,SIUL2 GPIO Pad Data Input" bitfld.byte 0x23 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x24 "GPDI183,SIUL2 GPIO Pad Data Input" bitfld.byte 0x24 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x25 "GPDI182,SIUL2 GPIO Pad Data Input" bitfld.byte 0x25 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x26 "GPDI181,SIUL2 GPIO Pad Data Input" bitfld.byte 0x26 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x27 "GPDI180,SIUL2 GPIO Pad Data Input" bitfld.byte 0x27 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x28 "GPDI187,SIUL2 GPIO Pad Data Input" bitfld.byte 0x28 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x29 "GPDI186,SIUL2 GPIO Pad Data Input" bitfld.byte 0x29 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2A "GPDI185,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2B "GPDI184,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" rgroup.byte 0x15BD++0x2 line.byte 0x0 "GPDI190,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1 "GPDI189,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2 "GPDI188,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" group.word 0x170C++0x1 line.word 0x0 "PGPDO7,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x0 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" group.word 0x1710++0x1 line.word 0x0 "PGPDO9,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x0 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x0 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x0 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x0 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x0 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" group.word 0x1714++0x3 line.word 0x0 "PGPDO11,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x0 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x0 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x0 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x0 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" line.word 0x2 "PGPDO10,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x2 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x2 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x2 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x2 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x2 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x2 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x2 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x2 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x2 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x2 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x2 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x2 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x2 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x2 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x2 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x2 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" rgroup.word 0x174C++0x1 line.word 0x0 "PGPDI7,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x0 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" rgroup.word 0x1750++0x1 line.word 0x0 "PGPDI9,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x0 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x0 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x0 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x0 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x0 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" rgroup.word 0x1754++0x3 line.word 0x0 "PGPDI11,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x0 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x0 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x0 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x0 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" line.word 0x2 "PGPDI10,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x2 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x2 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x2 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x2 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x2 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x2 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x2 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x2 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x2 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x2 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x2 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x2 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x2 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x2 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x2 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x2 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" group.long 0x179C++0x3 line.long 0x0 "MPGPDO7,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x0 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x0 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x0 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x0 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x0 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x0 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x0 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x0 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x0 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x0 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x0 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x0 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x0 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x0 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x0 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x0 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x0 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x0 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x0 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x0 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x0 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x0 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" group.long 0x17A4++0xB line.long 0x0 "MPGPDO9,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x0 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x0 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x0 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x0 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x0 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x0 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x0 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x0 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x0 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x0 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x0 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x0 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x0 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x0 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x0 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x0 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x0 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x0 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x0 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x0 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x0 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x0 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x0 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x0 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x0 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x0 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x0 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x0 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x0 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x0 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x0 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x0 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x4 "MPGPDO10,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x4 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x4 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x4 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x4 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x4 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x4 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x4 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x4 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x4 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x4 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x4 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x4 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x4 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x4 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x4 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x4 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x4 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x4 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x4 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x4 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x4 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x4 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x4 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x4 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x4 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x4 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x4 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x4 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x4 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x4 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x4 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x4 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x8 "MPGPDO11,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x8 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x8 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x8 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x8 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x8 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x8 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x8 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x8 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x8 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x8 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x8 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x8 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x8 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x8 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x8 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x8 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x8 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x8 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x8 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x8 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x8 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x8 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x8 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x8 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x8 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x8 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x8 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x8 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x8 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x8 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" tree.end tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 tree "SPI_0" base ad:0x401D4000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: Enables Slave mode,1: Enables Master mode" bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled,1: Continuous SCK enabled" newline rbitfld.long 0x0 28.--29. "DCONF,SPI Configuration" "0: SPI,?,?,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in Debug mode.,1: Halt serial transfers in Debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Transfer Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS5/PCSS_b is used as the PCS[5] signal.,1: PCS5/PCSS_b is used as an active-low PCSS signal." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted to the Shift register." hexmask.long.byte 0x0 16.--23. 1. "PCSIS,Peripheral Chip Select x Inactive State" newline bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enables the module clocks,1: Allows external logic to disable the module clocks" bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: TX FIFO is enabled.,1: TX FIFO is disabled." newline bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: RX FIFO is enabled.,1: RX FIFO is disabled." bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the TX FIFO counter.,1: Clear the TX FIFO counter." newline bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the RX FIFO counter.,1: Clear the RX FIFO counter." bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: Zero protocol clock cycles between SCK edge and..,1: One protocol clock cycle between SCK edge and..,2: Two protocol clock cycles between SCK edge and..,?" newline bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI mode. Frame size can be up to 16 bits..,1: Extended SPI mode. Up to 32-bit SPI frames along.." bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode" "0: Normal or slow continuous PCS mode. Masking of..,1: Fast continuous PCS mode. Delays are masked via.." newline bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." bitfld.long 0x0 0. "HALT,Halt" "0: Starts transfers.,1: Stops transfers." group.long 0x8++0x7 line.long 0x0 "TCR,Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" group.long 0xC++0x17 line.long 0x0 "CTAR0_SLAVE,Clock and Transfer Attributes Register (in Slave mode)" hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." line.long 0x4 "CTAR1,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x8 "CTAR2,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler" line.long 0xC "CTAR3,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x10 "CTAR4,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x14 "CTAR5,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler" group.long 0x2C++0xB line.long 0x0 "SR,Status Register" eventfld.long 0x0 31. "TCF,Transfer Complete Flag" "0: Transfer is incomplete.,1: Transfer is complete." rbitfld.long 0x0 30. "TXRXS,TX and RX Status" "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled when.." newline eventfld.long 0x0 28. "EOQF,End of Queue Flag" "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." eventfld.long 0x0 27. "TFUF,Transmit FIFO Underflow Flag" "0: No TX FIFO underflow occurred.,1: TX FIFO underflow occurred." newline eventfld.long 0x0 25. "TFFF,Transmit FIFO Fill Flag" "0: TX FIFO is full.,1: TX FIFO is not full." rbitfld.long 0x0 24. "BSYF,Busy Flag" "0: No cyclic command transfer is in progress.,1: Cyclic command transfer is in progress. Current.." newline eventfld.long 0x0 23. "CMDTCF,Command Transfer Complete Flag" "0: Data transfer by current command is incomplete.,1: Data transfer by current command is complete." eventfld.long 0x0 21. "SPEF,SPI Parity Error Flag" "0: No parity error.,1: Parity error has occurred." newline eventfld.long 0x0 19. "RFOF,Receive FIFO Overflow Flag" "0: No RX FIFO overflow occurred.,1: RX FIFO overflow has occurred." eventfld.long 0x0 18. "TFIWF,Transmit FIFO Invalid Write Flag" "0: No invalid data is present in TX FIFO.,1: Invalid data is present in TX FIFO because CMD.." newline eventfld.long 0x0 17. "RFDF,Receive FIFO Drain Flag" "0: RX FIFO is empty.,1: RX FIFO is not empty." eventfld.long 0x0 16. "CMDFFF,Command FIFO Fill Flag" "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x0 12.--15. 1. "TXCTR,TX FIFO Counter" hexmask.long.byte 0x0 8.--11. 1. "TXNXTPTR,Transmit Next Pointer" newline hexmask.long.byte 0x0 4.--7. 1. "RXCTR,RX FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "POPNXTPTR,Pop Next Pointer" line.long 0x4 "RSER,DMA/Interrupt Request Select and Enable Register" bitfld.long 0x4 31. "TCF_RE,Transmission Complete Request Enable" "0: TCF interrupt requests are disabled.,1: TCF interrupt requests are enabled." bitfld.long 0x4 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable" "0: CMDFFF interrupts or DMA requests are disabled.,1: CMDFFF interrupts or DMA requests are enabled." newline bitfld.long 0x4 28. "EOQF_RE,Finished Request Enable" "0: EOQF interrupt requests are disabled.,1: EOQF interrupt requests are enabled." bitfld.long 0x4 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: TFUF interrupt requests are disabled.,1: TFUF interrupt requests are enabled." newline bitfld.long 0x4 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: TFFF interrupts or DMA requests are disabled.,1: TFFF interrupts or DMA requests are enabled." bitfld.long 0x4 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: TFFF flag generates interrupt requests.,1: TFFF flag generates DMA requests." newline bitfld.long 0x4 23. "CMDTCF_RE,Command Transmission Complete Request Enable" "0: CMDTCF interrupt requests are disabled.,1: CMDTCF interrupt requests are enabled." bitfld.long 0x4 21. "SPEF_RE,SPI Parity Error Request Enable" "0: SPEF interrupt requests are disabled.,1: SPEF interrupt requests are enabled." newline bitfld.long 0x4 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: RFOF interrupt requests are disabled.,1: RFOF interrupt requests are enabled." bitfld.long 0x4 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: TFIWF interrupt requests are disabled.,1: TFIWF interrupt requests are enabled." newline bitfld.long 0x4 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: RFDF interrupt or DMA requests are disabled.,1: RFDF interrupt or DMA requests are enabled." bitfld.long 0x4 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select" "0: Interrupt request,1: DMA request" newline bitfld.long 0x4 15. "CMDFFF_DIRS,Command FIFO Fill DMA or Interrupt Request Select" "0: CMDFFF flag generates interrupt requests.,1: CMDFFF flag generates DMA requests." line.long 0x8 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x8 31. "CONT,Continuous Peripheral Chip Select Enable" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x8 28.--30. "CTAS,Clock and Transfer Attributes Select" "0: CTAR0,1: CTAR1,2: CTAR2,3: CTAR3,4: CTAR4,5: CTAR5,?,?" newline bitfld.long 0x8 27. "EOQ,End of Queue" "0: SPI data is not the last data to transfer.,1: SPI data is the last data to transfer." bitfld.long 0x8 26. "CTCNT,Clear Transfer Counter" "0: Do not clear the TCR[TCNT] field.,1: Clear the TCR[TCNT] field." newline bitfld.long 0x8 25. "PE_MASC,Parity Enable or Mask TASC Delay in Current Frame" "0: PE - No parity bit is included/checked. MASC -..,1: PE - Parity bit is transmitted instead of the.." bitfld.long 0x8 24. "PP_MCSC,Parity Polarity or Mask TCSC Delay in Next Frame" "0: PP - Even Parity: the number of 1 bits in the..,1: PP - Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x8 16.--23. 1. "PCS,PCS" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x3 line.long 0x0 "POPR,POP RX FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x3C)++0x3 line.long 0x0 "TXFR[$1],Transmit FIFO Registers" hexmask.long.word 0x0 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x7C)++0x3 line.long 0x0 "RXFR[$1],Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x11C)++0x3 line.long 0x0 "CTARE[$1],Clock and Transfer Attributes Register Extended" bitfld.long 0x0 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16 bit SPI frames can be..,1: Up to 32 bit SPI frames can be transferred. Each.." hexmask.long.word 0x0 0.--10. 1. "DTCP,Data Transfer Count Preload" repeat.end rgroup.long 0x13C++0x3 line.long 0x0 "SREX,Status Register Extended" bitfld.long 0x0 14. "TXCTR4,TX FIFO Counter[4]" "0,1" bitfld.long 0x0 11. "RXCTR4,RX FIFO Counter[4]" "0,1" newline hexmask.long.byte 0x0 4.--8. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "SPI_1" base ad:0x401D8000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: Enables Slave mode,1: Enables Master mode" bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled,1: Continuous SCK enabled" newline rbitfld.long 0x0 28.--29. "DCONF,SPI Configuration" "0: SPI,?,?,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in Debug mode.,1: Halt serial transfers in Debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Transfer Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS5/PCSS_b is used as the PCS[5] signal.,1: PCS5/PCSS_b is used as an active-low PCSS signal." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted to the Shift register." hexmask.long.byte 0x0 16.--23. 1. "PCSIS,Peripheral Chip Select x Inactive State" newline bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enables the module clocks,1: Allows external logic to disable the module clocks" bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: TX FIFO is enabled.,1: TX FIFO is disabled." newline bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: RX FIFO is enabled.,1: RX FIFO is disabled." bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the TX FIFO counter.,1: Clear the TX FIFO counter." newline bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the RX FIFO counter.,1: Clear the RX FIFO counter." bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: Zero protocol clock cycles between SCK edge and..,1: One protocol clock cycle between SCK edge and..,2: Two protocol clock cycles between SCK edge and..,?" newline bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI mode. Frame size can be up to 16 bits..,1: Extended SPI mode. Up to 32-bit SPI frames along.." bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode" "0: Normal or slow continuous PCS mode. Masking of..,1: Fast continuous PCS mode. Delays are masked via.." newline bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." bitfld.long 0x0 0. "HALT,Halt" "0: Starts transfers.,1: Stops transfers." group.long 0x8++0x7 line.long 0x0 "TCR,Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" group.long 0xC++0x17 line.long 0x0 "CTAR0_SLAVE,Clock and Transfer Attributes Register (in Slave mode)" hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." line.long 0x4 "CTAR1,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x8 "CTAR2,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler" line.long 0xC "CTAR3,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x10 "CTAR4,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x14 "CTAR5,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler" group.long 0x2C++0xB line.long 0x0 "SR,Status Register" eventfld.long 0x0 31. "TCF,Transfer Complete Flag" "0: Transfer is incomplete.,1: Transfer is complete." rbitfld.long 0x0 30. "TXRXS,TX and RX Status" "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled when.." newline eventfld.long 0x0 28. "EOQF,End of Queue Flag" "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." eventfld.long 0x0 27. "TFUF,Transmit FIFO Underflow Flag" "0: No TX FIFO underflow occurred.,1: TX FIFO underflow occurred." newline eventfld.long 0x0 25. "TFFF,Transmit FIFO Fill Flag" "0: TX FIFO is full.,1: TX FIFO is not full." rbitfld.long 0x0 24. "BSYF,Busy Flag" "0: No cyclic command transfer is in progress.,1: Cyclic command transfer is in progress. Current.." newline eventfld.long 0x0 23. "CMDTCF,Command Transfer Complete Flag" "0: Data transfer by current command is incomplete.,1: Data transfer by current command is complete." eventfld.long 0x0 21. "SPEF,SPI Parity Error Flag" "0: No parity error.,1: Parity error has occurred." newline eventfld.long 0x0 19. "RFOF,Receive FIFO Overflow Flag" "0: No RX FIFO overflow occurred.,1: RX FIFO overflow has occurred." eventfld.long 0x0 18. "TFIWF,Transmit FIFO Invalid Write Flag" "0: No invalid data is present in TX FIFO.,1: Invalid data is present in TX FIFO because CMD.." newline eventfld.long 0x0 17. "RFDF,Receive FIFO Drain Flag" "0: RX FIFO is empty.,1: RX FIFO is not empty." eventfld.long 0x0 16. "CMDFFF,Command FIFO Fill Flag" "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x0 12.--15. 1. "TXCTR,TX FIFO Counter" hexmask.long.byte 0x0 8.--11. 1. "TXNXTPTR,Transmit Next Pointer" newline hexmask.long.byte 0x0 4.--7. 1. "RXCTR,RX FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "POPNXTPTR,Pop Next Pointer" line.long 0x4 "RSER,DMA/Interrupt Request Select and Enable Register" bitfld.long 0x4 31. "TCF_RE,Transmission Complete Request Enable" "0: TCF interrupt requests are disabled.,1: TCF interrupt requests are enabled." bitfld.long 0x4 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable" "0: CMDFFF interrupts or DMA requests are disabled.,1: CMDFFF interrupts or DMA requests are enabled." newline bitfld.long 0x4 28. "EOQF_RE,Finished Request Enable" "0: EOQF interrupt requests are disabled.,1: EOQF interrupt requests are enabled." bitfld.long 0x4 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: TFUF interrupt requests are disabled.,1: TFUF interrupt requests are enabled." newline bitfld.long 0x4 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: TFFF interrupts or DMA requests are disabled.,1: TFFF interrupts or DMA requests are enabled." bitfld.long 0x4 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: TFFF flag generates interrupt requests.,1: TFFF flag generates DMA requests." newline bitfld.long 0x4 23. "CMDTCF_RE,Command Transmission Complete Request Enable" "0: CMDTCF interrupt requests are disabled.,1: CMDTCF interrupt requests are enabled." bitfld.long 0x4 21. "SPEF_RE,SPI Parity Error Request Enable" "0: SPEF interrupt requests are disabled.,1: SPEF interrupt requests are enabled." newline bitfld.long 0x4 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: RFOF interrupt requests are disabled.,1: RFOF interrupt requests are enabled." bitfld.long 0x4 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: TFIWF interrupt requests are disabled.,1: TFIWF interrupt requests are enabled." newline bitfld.long 0x4 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: RFDF interrupt or DMA requests are disabled.,1: RFDF interrupt or DMA requests are enabled." bitfld.long 0x4 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select" "0: Interrupt request,1: DMA request" newline bitfld.long 0x4 15. "CMDFFF_DIRS,Command FIFO Fill DMA or Interrupt Request Select" "0: CMDFFF flag generates interrupt requests.,1: CMDFFF flag generates DMA requests." line.long 0x8 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x8 31. "CONT,Continuous Peripheral Chip Select Enable" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x8 28.--30. "CTAS,Clock and Transfer Attributes Select" "0: CTAR0,1: CTAR1,2: CTAR2,3: CTAR3,4: CTAR4,5: CTAR5,?,?" newline bitfld.long 0x8 27. "EOQ,End of Queue" "0: SPI data is not the last data to transfer.,1: SPI data is the last data to transfer." bitfld.long 0x8 26. "CTCNT,Clear Transfer Counter" "0: Do not clear the TCR[TCNT] field.,1: Clear the TCR[TCNT] field." newline bitfld.long 0x8 25. "PE_MASC,Parity Enable or Mask TASC Delay in Current Frame" "0: PE - No parity bit is included/checked. MASC -..,1: PE - Parity bit is transmitted instead of the.." bitfld.long 0x8 24. "PP_MCSC,Parity Polarity or Mask TCSC Delay in Next Frame" "0: PP - Even Parity: the number of 1 bits in the..,1: PP - Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x8 16.--23. 1. "PCS,PCS" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x3 line.long 0x0 "POPR,POP RX FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x3C)++0x3 line.long 0x0 "TXFR[$1],Transmit FIFO Registers" hexmask.long.word 0x0 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x7C)++0x3 line.long 0x0 "RXFR[$1],Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x11C)++0x3 line.long 0x0 "CTARE[$1],Clock and Transfer Attributes Register Extended" bitfld.long 0x0 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16 bit SPI frames can be..,1: Up to 32 bit SPI frames can be transferred. Each.." hexmask.long.word 0x0 0.--10. 1. "DTCP,Data Transfer Count Preload" repeat.end rgroup.long 0x13C++0x3 line.long 0x0 "SREX,Status Register Extended" bitfld.long 0x0 14. "TXCTR4,TX FIFO Counter[4]" "0,1" bitfld.long 0x0 11. "RXCTR4,RX FIFO Counter[4]" "0,1" newline hexmask.long.byte 0x0 4.--8. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "SPI_2" base ad:0x401DC000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: Enables Slave mode,1: Enables Master mode" bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled,1: Continuous SCK enabled" newline rbitfld.long 0x0 28.--29. "DCONF,SPI Configuration" "0: SPI,?,?,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in Debug mode.,1: Halt serial transfers in Debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Transfer Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS5/PCSS_b is used as the PCS[5] signal.,1: PCS5/PCSS_b is used as an active-low PCSS signal." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted to the Shift register." hexmask.long.byte 0x0 16.--23. 1. "PCSIS,Peripheral Chip Select x Inactive State" newline bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enables the module clocks,1: Allows external logic to disable the module clocks" bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: TX FIFO is enabled.,1: TX FIFO is disabled." newline bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: RX FIFO is enabled.,1: RX FIFO is disabled." bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the TX FIFO counter.,1: Clear the TX FIFO counter." newline bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the RX FIFO counter.,1: Clear the RX FIFO counter." bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: Zero protocol clock cycles between SCK edge and..,1: One protocol clock cycle between SCK edge and..,2: Two protocol clock cycles between SCK edge and..,?" newline bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI mode. Frame size can be up to 16 bits..,1: Extended SPI mode. Up to 32-bit SPI frames along.." bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode" "0: Normal or slow continuous PCS mode. Masking of..,1: Fast continuous PCS mode. Delays are masked via.." newline bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." bitfld.long 0x0 0. "HALT,Halt" "0: Starts transfers.,1: Stops transfers." group.long 0x8++0x7 line.long 0x0 "TCR,Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" group.long 0xC++0x17 line.long 0x0 "CTAR0_SLAVE,Clock and Transfer Attributes Register (in Slave mode)" hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." line.long 0x4 "CTAR1,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x8 "CTAR2,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler" line.long 0xC "CTAR3,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x10 "CTAR4,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x14 "CTAR5,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler" group.long 0x2C++0xB line.long 0x0 "SR,Status Register" eventfld.long 0x0 31. "TCF,Transfer Complete Flag" "0: Transfer is incomplete.,1: Transfer is complete." rbitfld.long 0x0 30. "TXRXS,TX and RX Status" "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled when.." newline eventfld.long 0x0 28. "EOQF,End of Queue Flag" "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." eventfld.long 0x0 27. "TFUF,Transmit FIFO Underflow Flag" "0: No TX FIFO underflow occurred.,1: TX FIFO underflow occurred." newline eventfld.long 0x0 25. "TFFF,Transmit FIFO Fill Flag" "0: TX FIFO is full.,1: TX FIFO is not full." rbitfld.long 0x0 24. "BSYF,Busy Flag" "0: No cyclic command transfer is in progress.,1: Cyclic command transfer is in progress. Current.." newline eventfld.long 0x0 23. "CMDTCF,Command Transfer Complete Flag" "0: Data transfer by current command is incomplete.,1: Data transfer by current command is complete." eventfld.long 0x0 21. "SPEF,SPI Parity Error Flag" "0: No parity error.,1: Parity error has occurred." newline eventfld.long 0x0 19. "RFOF,Receive FIFO Overflow Flag" "0: No RX FIFO overflow occurred.,1: RX FIFO overflow has occurred." eventfld.long 0x0 18. "TFIWF,Transmit FIFO Invalid Write Flag" "0: No invalid data is present in TX FIFO.,1: Invalid data is present in TX FIFO because CMD.." newline eventfld.long 0x0 17. "RFDF,Receive FIFO Drain Flag" "0: RX FIFO is empty.,1: RX FIFO is not empty." eventfld.long 0x0 16. "CMDFFF,Command FIFO Fill Flag" "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x0 12.--15. 1. "TXCTR,TX FIFO Counter" hexmask.long.byte 0x0 8.--11. 1. "TXNXTPTR,Transmit Next Pointer" newline hexmask.long.byte 0x0 4.--7. 1. "RXCTR,RX FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "POPNXTPTR,Pop Next Pointer" line.long 0x4 "RSER,DMA/Interrupt Request Select and Enable Register" bitfld.long 0x4 31. "TCF_RE,Transmission Complete Request Enable" "0: TCF interrupt requests are disabled.,1: TCF interrupt requests are enabled." bitfld.long 0x4 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable" "0: CMDFFF interrupts or DMA requests are disabled.,1: CMDFFF interrupts or DMA requests are enabled." newline bitfld.long 0x4 28. "EOQF_RE,Finished Request Enable" "0: EOQF interrupt requests are disabled.,1: EOQF interrupt requests are enabled." bitfld.long 0x4 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: TFUF interrupt requests are disabled.,1: TFUF interrupt requests are enabled." newline bitfld.long 0x4 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: TFFF interrupts or DMA requests are disabled.,1: TFFF interrupts or DMA requests are enabled." bitfld.long 0x4 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: TFFF flag generates interrupt requests.,1: TFFF flag generates DMA requests." newline bitfld.long 0x4 23. "CMDTCF_RE,Command Transmission Complete Request Enable" "0: CMDTCF interrupt requests are disabled.,1: CMDTCF interrupt requests are enabled." bitfld.long 0x4 21. "SPEF_RE,SPI Parity Error Request Enable" "0: SPEF interrupt requests are disabled.,1: SPEF interrupt requests are enabled." newline bitfld.long 0x4 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: RFOF interrupt requests are disabled.,1: RFOF interrupt requests are enabled." bitfld.long 0x4 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: TFIWF interrupt requests are disabled.,1: TFIWF interrupt requests are enabled." newline bitfld.long 0x4 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: RFDF interrupt or DMA requests are disabled.,1: RFDF interrupt or DMA requests are enabled." bitfld.long 0x4 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select" "0: Interrupt request,1: DMA request" newline bitfld.long 0x4 15. "CMDFFF_DIRS,Command FIFO Fill DMA or Interrupt Request Select" "0: CMDFFF flag generates interrupt requests.,1: CMDFFF flag generates DMA requests." line.long 0x8 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x8 31. "CONT,Continuous Peripheral Chip Select Enable" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x8 28.--30. "CTAS,Clock and Transfer Attributes Select" "0: CTAR0,1: CTAR1,2: CTAR2,3: CTAR3,4: CTAR4,5: CTAR5,?,?" newline bitfld.long 0x8 27. "EOQ,End of Queue" "0: SPI data is not the last data to transfer.,1: SPI data is the last data to transfer." bitfld.long 0x8 26. "CTCNT,Clear Transfer Counter" "0: Do not clear the TCR[TCNT] field.,1: Clear the TCR[TCNT] field." newline bitfld.long 0x8 25. "PE_MASC,Parity Enable or Mask TASC Delay in Current Frame" "0: PE - No parity bit is included/checked. MASC -..,1: PE - Parity bit is transmitted instead of the.." bitfld.long 0x8 24. "PP_MCSC,Parity Polarity or Mask TCSC Delay in Next Frame" "0: PP - Even Parity: the number of 1 bits in the..,1: PP - Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x8 16.--23. 1. "PCS,PCS" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x3 line.long 0x0 "POPR,POP RX FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x3C)++0x3 line.long 0x0 "TXFR[$1],Transmit FIFO Registers" hexmask.long.word 0x0 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x7C)++0x3 line.long 0x0 "RXFR[$1],Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x11C)++0x3 line.long 0x0 "CTARE[$1],Clock and Transfer Attributes Register Extended" bitfld.long 0x0 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16 bit SPI frames can be..,1: Up to 32 bit SPI frames can be transferred. Each.." hexmask.long.word 0x0 0.--10. 1. "DTCP,Data Transfer Count Preload" repeat.end rgroup.long 0x13C++0x3 line.long 0x0 "SREX,Status Register Extended" bitfld.long 0x0 14. "TXCTR4,TX FIFO Counter[4]" "0,1" bitfld.long 0x0 11. "RXCTR4,RX FIFO Counter[4]" "0,1" newline hexmask.long.byte 0x0 4.--8. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "SPI_3" base ad:0x402C8000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: Enables Slave mode,1: Enables Master mode" bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled,1: Continuous SCK enabled" newline rbitfld.long 0x0 28.--29. "DCONF,SPI Configuration" "0: SPI,?,?,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in Debug mode.,1: Halt serial transfers in Debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Transfer Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS5/PCSS_b is used as the PCS[5] signal.,1: PCS5/PCSS_b is used as an active-low PCSS signal." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted to the Shift register." hexmask.long.byte 0x0 16.--23. 1. "PCSIS,Peripheral Chip Select x Inactive State" newline bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enables the module clocks,1: Allows external logic to disable the module clocks" bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: TX FIFO is enabled.,1: TX FIFO is disabled." newline bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: RX FIFO is enabled.,1: RX FIFO is disabled." bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the TX FIFO counter.,1: Clear the TX FIFO counter." newline bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the RX FIFO counter.,1: Clear the RX FIFO counter." bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: Zero protocol clock cycles between SCK edge and..,1: One protocol clock cycle between SCK edge and..,2: Two protocol clock cycles between SCK edge and..,?" newline bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI mode. Frame size can be up to 16 bits..,1: Extended SPI mode. Up to 32-bit SPI frames along.." bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode" "0: Normal or slow continuous PCS mode. Masking of..,1: Fast continuous PCS mode. Delays are masked via.." newline bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." bitfld.long 0x0 0. "HALT,Halt" "0: Starts transfers.,1: Stops transfers." group.long 0x8++0x7 line.long 0x0 "TCR,Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" group.long 0xC++0x17 line.long 0x0 "CTAR0_SLAVE,Clock and Transfer Attributes Register (in Slave mode)" hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." line.long 0x4 "CTAR1,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x8 "CTAR2,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler" line.long 0xC "CTAR3,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x10 "CTAR4,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x14 "CTAR5,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler" group.long 0x2C++0xB line.long 0x0 "SR,Status Register" eventfld.long 0x0 31. "TCF,Transfer Complete Flag" "0: Transfer is incomplete.,1: Transfer is complete." rbitfld.long 0x0 30. "TXRXS,TX and RX Status" "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled when.." newline eventfld.long 0x0 28. "EOQF,End of Queue Flag" "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." eventfld.long 0x0 27. "TFUF,Transmit FIFO Underflow Flag" "0: No TX FIFO underflow occurred.,1: TX FIFO underflow occurred." newline eventfld.long 0x0 25. "TFFF,Transmit FIFO Fill Flag" "0: TX FIFO is full.,1: TX FIFO is not full." rbitfld.long 0x0 24. "BSYF,Busy Flag" "0: No cyclic command transfer is in progress.,1: Cyclic command transfer is in progress. Current.." newline eventfld.long 0x0 23. "CMDTCF,Command Transfer Complete Flag" "0: Data transfer by current command is incomplete.,1: Data transfer by current command is complete." eventfld.long 0x0 21. "SPEF,SPI Parity Error Flag" "0: No parity error.,1: Parity error has occurred." newline eventfld.long 0x0 19. "RFOF,Receive FIFO Overflow Flag" "0: No RX FIFO overflow occurred.,1: RX FIFO overflow has occurred." eventfld.long 0x0 18. "TFIWF,Transmit FIFO Invalid Write Flag" "0: No invalid data is present in TX FIFO.,1: Invalid data is present in TX FIFO because CMD.." newline eventfld.long 0x0 17. "RFDF,Receive FIFO Drain Flag" "0: RX FIFO is empty.,1: RX FIFO is not empty." eventfld.long 0x0 16. "CMDFFF,Command FIFO Fill Flag" "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x0 12.--15. 1. "TXCTR,TX FIFO Counter" hexmask.long.byte 0x0 8.--11. 1. "TXNXTPTR,Transmit Next Pointer" newline hexmask.long.byte 0x0 4.--7. 1. "RXCTR,RX FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "POPNXTPTR,Pop Next Pointer" line.long 0x4 "RSER,DMA/Interrupt Request Select and Enable Register" bitfld.long 0x4 31. "TCF_RE,Transmission Complete Request Enable" "0: TCF interrupt requests are disabled.,1: TCF interrupt requests are enabled." bitfld.long 0x4 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable" "0: CMDFFF interrupts or DMA requests are disabled.,1: CMDFFF interrupts or DMA requests are enabled." newline bitfld.long 0x4 28. "EOQF_RE,Finished Request Enable" "0: EOQF interrupt requests are disabled.,1: EOQF interrupt requests are enabled." bitfld.long 0x4 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: TFUF interrupt requests are disabled.,1: TFUF interrupt requests are enabled." newline bitfld.long 0x4 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: TFFF interrupts or DMA requests are disabled.,1: TFFF interrupts or DMA requests are enabled." bitfld.long 0x4 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: TFFF flag generates interrupt requests.,1: TFFF flag generates DMA requests." newline bitfld.long 0x4 23. "CMDTCF_RE,Command Transmission Complete Request Enable" "0: CMDTCF interrupt requests are disabled.,1: CMDTCF interrupt requests are enabled." bitfld.long 0x4 21. "SPEF_RE,SPI Parity Error Request Enable" "0: SPEF interrupt requests are disabled.,1: SPEF interrupt requests are enabled." newline bitfld.long 0x4 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: RFOF interrupt requests are disabled.,1: RFOF interrupt requests are enabled." bitfld.long 0x4 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: TFIWF interrupt requests are disabled.,1: TFIWF interrupt requests are enabled." newline bitfld.long 0x4 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: RFDF interrupt or DMA requests are disabled.,1: RFDF interrupt or DMA requests are enabled." bitfld.long 0x4 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select" "0: Interrupt request,1: DMA request" newline bitfld.long 0x4 15. "CMDFFF_DIRS,Command FIFO Fill DMA or Interrupt Request Select" "0: CMDFFF flag generates interrupt requests.,1: CMDFFF flag generates DMA requests." line.long 0x8 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x8 31. "CONT,Continuous Peripheral Chip Select Enable" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x8 28.--30. "CTAS,Clock and Transfer Attributes Select" "0: CTAR0,1: CTAR1,2: CTAR2,3: CTAR3,4: CTAR4,5: CTAR5,?,?" newline bitfld.long 0x8 27. "EOQ,End of Queue" "0: SPI data is not the last data to transfer.,1: SPI data is the last data to transfer." bitfld.long 0x8 26. "CTCNT,Clear Transfer Counter" "0: Do not clear the TCR[TCNT] field.,1: Clear the TCR[TCNT] field." newline bitfld.long 0x8 25. "PE_MASC,Parity Enable or Mask TASC Delay in Current Frame" "0: PE - No parity bit is included/checked. MASC -..,1: PE - Parity bit is transmitted instead of the.." bitfld.long 0x8 24. "PP_MCSC,Parity Polarity or Mask TCSC Delay in Next Frame" "0: PP - Even Parity: the number of 1 bits in the..,1: PP - Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x8 16.--23. 1. "PCS,PCS" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x3 line.long 0x0 "POPR,POP RX FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x3C)++0x3 line.long 0x0 "TXFR[$1],Transmit FIFO Registers" hexmask.long.word 0x0 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x7C)++0x3 line.long 0x0 "RXFR[$1],Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x11C)++0x3 line.long 0x0 "CTARE[$1],Clock and Transfer Attributes Register Extended" bitfld.long 0x0 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16 bit SPI frames can be..,1: Up to 32 bit SPI frames can be transferred. Each.." hexmask.long.word 0x0 0.--10. 1. "DTCP,Data Transfer Count Preload" repeat.end rgroup.long 0x13C++0x3 line.long 0x0 "SREX,Status Register Extended" bitfld.long 0x0 14. "TXCTR4,TX FIFO Counter[4]" "0,1" bitfld.long 0x0 11. "RXCTR4,RX FIFO Counter[4]" "0,1" newline hexmask.long.byte 0x0 4.--8. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "SPI_4" base ad:0x402CC000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: Enables Slave mode,1: Enables Master mode" bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled,1: Continuous SCK enabled" newline rbitfld.long 0x0 28.--29. "DCONF,SPI Configuration" "0: SPI,?,?,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in Debug mode.,1: Halt serial transfers in Debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Transfer Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS5/PCSS_b is used as the PCS[5] signal.,1: PCS5/PCSS_b is used as an active-low PCSS signal." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted to the Shift register." hexmask.long.byte 0x0 16.--23. 1. "PCSIS,Peripheral Chip Select x Inactive State" newline bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enables the module clocks,1: Allows external logic to disable the module clocks" bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: TX FIFO is enabled.,1: TX FIFO is disabled." newline bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: RX FIFO is enabled.,1: RX FIFO is disabled." bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the TX FIFO counter.,1: Clear the TX FIFO counter." newline bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the RX FIFO counter.,1: Clear the RX FIFO counter." bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: Zero protocol clock cycles between SCK edge and..,1: One protocol clock cycle between SCK edge and..,2: Two protocol clock cycles between SCK edge and..,?" newline bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI mode. Frame size can be up to 16 bits..,1: Extended SPI mode. Up to 32-bit SPI frames along.." bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode" "0: Normal or slow continuous PCS mode. Masking of..,1: Fast continuous PCS mode. Delays are masked via.." newline bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." bitfld.long 0x0 0. "HALT,Halt" "0: Starts transfers.,1: Stops transfers." group.long 0x8++0x7 line.long 0x0 "TCR,Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" group.long 0xC++0x17 line.long 0x0 "CTAR0_SLAVE,Clock and Transfer Attributes Register (in Slave mode)" hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." line.long 0x4 "CTAR1,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x8 "CTAR2,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler" line.long 0xC "CTAR3,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x10 "CTAR4,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x14 "CTAR5,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler" group.long 0x2C++0xB line.long 0x0 "SR,Status Register" eventfld.long 0x0 31. "TCF,Transfer Complete Flag" "0: Transfer is incomplete.,1: Transfer is complete." rbitfld.long 0x0 30. "TXRXS,TX and RX Status" "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled when.." newline eventfld.long 0x0 28. "EOQF,End of Queue Flag" "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." eventfld.long 0x0 27. "TFUF,Transmit FIFO Underflow Flag" "0: No TX FIFO underflow occurred.,1: TX FIFO underflow occurred." newline eventfld.long 0x0 25. "TFFF,Transmit FIFO Fill Flag" "0: TX FIFO is full.,1: TX FIFO is not full." rbitfld.long 0x0 24. "BSYF,Busy Flag" "0: No cyclic command transfer is in progress.,1: Cyclic command transfer is in progress. Current.." newline eventfld.long 0x0 23. "CMDTCF,Command Transfer Complete Flag" "0: Data transfer by current command is incomplete.,1: Data transfer by current command is complete." eventfld.long 0x0 21. "SPEF,SPI Parity Error Flag" "0: No parity error.,1: Parity error has occurred." newline eventfld.long 0x0 19. "RFOF,Receive FIFO Overflow Flag" "0: No RX FIFO overflow occurred.,1: RX FIFO overflow has occurred." eventfld.long 0x0 18. "TFIWF,Transmit FIFO Invalid Write Flag" "0: No invalid data is present in TX FIFO.,1: Invalid data is present in TX FIFO because CMD.." newline eventfld.long 0x0 17. "RFDF,Receive FIFO Drain Flag" "0: RX FIFO is empty.,1: RX FIFO is not empty." eventfld.long 0x0 16. "CMDFFF,Command FIFO Fill Flag" "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x0 12.--15. 1. "TXCTR,TX FIFO Counter" hexmask.long.byte 0x0 8.--11. 1. "TXNXTPTR,Transmit Next Pointer" newline hexmask.long.byte 0x0 4.--7. 1. "RXCTR,RX FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "POPNXTPTR,Pop Next Pointer" line.long 0x4 "RSER,DMA/Interrupt Request Select and Enable Register" bitfld.long 0x4 31. "TCF_RE,Transmission Complete Request Enable" "0: TCF interrupt requests are disabled.,1: TCF interrupt requests are enabled." bitfld.long 0x4 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable" "0: CMDFFF interrupts or DMA requests are disabled.,1: CMDFFF interrupts or DMA requests are enabled." newline bitfld.long 0x4 28. "EOQF_RE,Finished Request Enable" "0: EOQF interrupt requests are disabled.,1: EOQF interrupt requests are enabled." bitfld.long 0x4 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: TFUF interrupt requests are disabled.,1: TFUF interrupt requests are enabled." newline bitfld.long 0x4 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: TFFF interrupts or DMA requests are disabled.,1: TFFF interrupts or DMA requests are enabled." bitfld.long 0x4 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: TFFF flag generates interrupt requests.,1: TFFF flag generates DMA requests." newline bitfld.long 0x4 23. "CMDTCF_RE,Command Transmission Complete Request Enable" "0: CMDTCF interrupt requests are disabled.,1: CMDTCF interrupt requests are enabled." bitfld.long 0x4 21. "SPEF_RE,SPI Parity Error Request Enable" "0: SPEF interrupt requests are disabled.,1: SPEF interrupt requests are enabled." newline bitfld.long 0x4 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: RFOF interrupt requests are disabled.,1: RFOF interrupt requests are enabled." bitfld.long 0x4 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: TFIWF interrupt requests are disabled.,1: TFIWF interrupt requests are enabled." newline bitfld.long 0x4 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: RFDF interrupt or DMA requests are disabled.,1: RFDF interrupt or DMA requests are enabled." bitfld.long 0x4 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select" "0: Interrupt request,1: DMA request" newline bitfld.long 0x4 15. "CMDFFF_DIRS,Command FIFO Fill DMA or Interrupt Request Select" "0: CMDFFF flag generates interrupt requests.,1: CMDFFF flag generates DMA requests." line.long 0x8 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x8 31. "CONT,Continuous Peripheral Chip Select Enable" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x8 28.--30. "CTAS,Clock and Transfer Attributes Select" "0: CTAR0,1: CTAR1,2: CTAR2,3: CTAR3,4: CTAR4,5: CTAR5,?,?" newline bitfld.long 0x8 27. "EOQ,End of Queue" "0: SPI data is not the last data to transfer.,1: SPI data is the last data to transfer." bitfld.long 0x8 26. "CTCNT,Clear Transfer Counter" "0: Do not clear the TCR[TCNT] field.,1: Clear the TCR[TCNT] field." newline bitfld.long 0x8 25. "PE_MASC,Parity Enable or Mask TASC Delay in Current Frame" "0: PE - No parity bit is included/checked. MASC -..,1: PE - Parity bit is transmitted instead of the.." bitfld.long 0x8 24. "PP_MCSC,Parity Polarity or Mask TCSC Delay in Next Frame" "0: PP - Even Parity: the number of 1 bits in the..,1: PP - Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x8 16.--23. 1. "PCS,PCS" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x3 line.long 0x0 "POPR,POP RX FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x3C)++0x3 line.long 0x0 "TXFR[$1],Transmit FIFO Registers" hexmask.long.word 0x0 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x7C)++0x3 line.long 0x0 "RXFR[$1],Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x11C)++0x3 line.long 0x0 "CTARE[$1],Clock and Transfer Attributes Register Extended" bitfld.long 0x0 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16 bit SPI frames can be..,1: Up to 32 bit SPI frames can be transferred. Each.." hexmask.long.word 0x0 0.--10. 1. "DTCP,Data Transfer Count Preload" repeat.end rgroup.long 0x13C++0x3 line.long 0x0 "SREX,Status Register Extended" bitfld.long 0x0 14. "TXCTR4,TX FIFO Counter[4]" "0,1" bitfld.long 0x0 11. "RXCTR4,RX FIFO Counter[4]" "0,1" newline hexmask.long.byte 0x0 4.--8. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree "SPI_5" base ad:0x402D0000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 31. "MSTR,Master/Slave Mode Select" "0: Enables Slave mode,1: Enables Master mode" bitfld.long 0x0 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled,1: Continuous SCK enabled" newline rbitfld.long 0x0 28.--29. "DCONF,SPI Configuration" "0: SPI,?,?,?" bitfld.long 0x0 27. "FRZ,Freeze" "0: Do not halt serial transfers in Debug mode.,1: Halt serial transfers in Debug mode." newline bitfld.long 0x0 26. "MTFE,Modified Transfer Format Enable" "0: Modified SPI transfer format disabled.,1: Modified SPI transfer format enabled." bitfld.long 0x0 25. "PCSSE,Peripheral Chip Select Strobe Enable" "0: PCS5/PCSS_b is used as the PCS[5] signal.,1: PCS5/PCSS_b is used as an active-low PCSS signal." newline bitfld.long 0x0 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored.,1: Incoming data is shifted to the Shift register." hexmask.long.byte 0x0 16.--23. 1. "PCSIS,Peripheral Chip Select x Inactive State" newline bitfld.long 0x0 14. "MDIS,Module Disable" "0: Enables the module clocks,1: Allows external logic to disable the module clocks" bitfld.long 0x0 13. "DIS_TXF,Disable Transmit FIFO" "0: TX FIFO is enabled.,1: TX FIFO is disabled." newline bitfld.long 0x0 12. "DIS_RXF,Disable Receive FIFO" "0: RX FIFO is enabled.,1: RX FIFO is disabled." bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the TX FIFO counter.,1: Clear the TX FIFO counter." newline bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the RX FIFO counter.,1: Clear the RX FIFO counter." bitfld.long 0x0 8.--9. "SMPL_PT,Sample Point" "0: Zero protocol clock cycles between SCK edge and..,1: One protocol clock cycle between SCK edge and..,2: Two protocol clock cycles between SCK edge and..,?" newline bitfld.long 0x0 3. "XSPI,Extended SPI Mode" "0: Normal SPI mode. Frame size can be up to 16 bits..,1: Extended SPI mode. Up to 32-bit SPI frames along.." bitfld.long 0x0 2. "FCPCS,Fast Continuous PCS Mode" "0: Normal or slow continuous PCS mode. Masking of..,1: Fast continuous PCS mode. Delays are masked via.." newline bitfld.long 0x0 1. "PES,Parity Error Stop" "0: SPI frame transmission continues.,1: SPI frame transmission stops." bitfld.long 0x0 0. "HALT,Halt" "0: Starts transfers.,1: Stops transfers." group.long 0x8++0x7 line.long 0x0 "TCR,Transfer Count Register" hexmask.long.word 0x0 16.--31. 1. "SPI_TCNT,SPI Transfer Counter" line.long 0x4 "CTAR0,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" group.long 0xC++0x17 line.long 0x0 "CTAR0_SLAVE,Clock and Transfer Attributes Register (in Slave mode)" hexmask.long.byte 0x0 27.--31. 1. "FMSZ,Frame Size" bitfld.long 0x0 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." newline bitfld.long 0x0 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." bitfld.long 0x0 24. "PE,Parity Enable" "0: No parity bit included/checked.,1: Parity bit is transmitted instead of last data.." newline bitfld.long 0x0 23. "PP,Parity Polarity" "0: Even Parity: the number of 1 bits in the..,1: Odd Parity: the number of 1 bits in the.." line.long 0x4 "CTAR1,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x4 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x4 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x4 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x4 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x4 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x4 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x4 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x4 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x4 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x4 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x4 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x4 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x4 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x8 "CTAR2,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x8 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x8 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x8 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x8 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x8 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x8 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x8 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x8 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x8 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x8 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x8 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x8 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x8 0.--3. 1. "BR,Baud Rate Scaler" line.long 0xC "CTAR3,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0xC 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0xC 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0xC 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0xC 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0xC 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0xC 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0xC 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0xC 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0xC 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0xC 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0xC 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0xC 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0xC 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x10 "CTAR4,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x10 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x10 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x10 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x10 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x10 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x10 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x10 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x10 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x10 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x10 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x10 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x10 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x10 0.--3. 1. "BR,Baud Rate Scaler" line.long 0x14 "CTAR5,Clock and Transfer Attributes Register (in Master mode)" bitfld.long 0x14 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a 50/50..,1: The baud rate is doubled with the duty cycle.." hexmask.long.byte 0x14 27.--30. 1. "FMSZ,Frame Size" newline bitfld.long 0x14 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low.,1: The inactive state value of SCK is high." bitfld.long 0x14 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK and..,1: Data is changed on the leading edge of SCK and.." newline bitfld.long 0x14 24. "LSBFE,LSB First" "0: Data is transferred MSB first.,1: Data is transferred LSB first." bitfld.long 0x14 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1.,1: PCS to SCK Prescaler value is 3.,2: PCS to SCK Prescaler value is 5.,3: PCS to SCK Prescaler value is 7." newline bitfld.long 0x14 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." bitfld.long 0x14 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1.,1: Delay after Transfer Prescaler value is 3.,2: Delay after Transfer Prescaler value is 5.,3: Delay after Transfer Prescaler value is 7." newline bitfld.long 0x14 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2.,1: Baud Rate Prescaler value is 3.,2: Baud Rate Prescaler value is 5.,3: Baud Rate Prescaler value is 7." hexmask.long.byte 0x14 12.--15. 1. "CSSCK,PCS to SCK Delay Scaler" newline hexmask.long.byte 0x14 8.--11. 1. "ASC,After SCK Delay Scaler" hexmask.long.byte 0x14 4.--7. 1. "DT,Delay After Transfer Scaler" newline hexmask.long.byte 0x14 0.--3. 1. "BR,Baud Rate Scaler" group.long 0x2C++0xB line.long 0x0 "SR,Status Register" eventfld.long 0x0 31. "TCF,Transfer Complete Flag" "0: Transfer is incomplete.,1: Transfer is complete." rbitfld.long 0x0 30. "TXRXS,TX and RX Status" "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled when.." newline eventfld.long 0x0 28. "EOQF,End of Queue Flag" "0: EOQ is not set in the executing command.,1: EOQ is set in the executing SPI command." eventfld.long 0x0 27. "TFUF,Transmit FIFO Underflow Flag" "0: No TX FIFO underflow occurred.,1: TX FIFO underflow occurred." newline eventfld.long 0x0 25. "TFFF,Transmit FIFO Fill Flag" "0: TX FIFO is full.,1: TX FIFO is not full." rbitfld.long 0x0 24. "BSYF,Busy Flag" "0: No cyclic command transfer is in progress.,1: Cyclic command transfer is in progress. Current.." newline eventfld.long 0x0 23. "CMDTCF,Command Transfer Complete Flag" "0: Data transfer by current command is incomplete.,1: Data transfer by current command is complete." eventfld.long 0x0 21. "SPEF,SPI Parity Error Flag" "0: No parity error.,1: Parity error has occurred." newline eventfld.long 0x0 19. "RFOF,Receive FIFO Overflow Flag" "0: No RX FIFO overflow occurred.,1: RX FIFO overflow has occurred." eventfld.long 0x0 18. "TFIWF,Transmit FIFO Invalid Write Flag" "0: No invalid data is present in TX FIFO.,1: Invalid data is present in TX FIFO because CMD.." newline eventfld.long 0x0 17. "RFDF,Receive FIFO Drain Flag" "0: RX FIFO is empty.,1: RX FIFO is not empty." eventfld.long 0x0 16. "CMDFFF,Command FIFO Fill Flag" "0: CMD FIFO is full.,1: CMD FIFO is not full." newline hexmask.long.byte 0x0 12.--15. 1. "TXCTR,TX FIFO Counter" hexmask.long.byte 0x0 8.--11. 1. "TXNXTPTR,Transmit Next Pointer" newline hexmask.long.byte 0x0 4.--7. 1. "RXCTR,RX FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "POPNXTPTR,Pop Next Pointer" line.long 0x4 "RSER,DMA/Interrupt Request Select and Enable Register" bitfld.long 0x4 31. "TCF_RE,Transmission Complete Request Enable" "0: TCF interrupt requests are disabled.,1: TCF interrupt requests are enabled." bitfld.long 0x4 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable" "0: CMDFFF interrupts or DMA requests are disabled.,1: CMDFFF interrupts or DMA requests are enabled." newline bitfld.long 0x4 28. "EOQF_RE,Finished Request Enable" "0: EOQF interrupt requests are disabled.,1: EOQF interrupt requests are enabled." bitfld.long 0x4 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: TFUF interrupt requests are disabled.,1: TFUF interrupt requests are enabled." newline bitfld.long 0x4 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: TFFF interrupts or DMA requests are disabled.,1: TFFF interrupts or DMA requests are enabled." bitfld.long 0x4 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: TFFF flag generates interrupt requests.,1: TFFF flag generates DMA requests." newline bitfld.long 0x4 23. "CMDTCF_RE,Command Transmission Complete Request Enable" "0: CMDTCF interrupt requests are disabled.,1: CMDTCF interrupt requests are enabled." bitfld.long 0x4 21. "SPEF_RE,SPI Parity Error Request Enable" "0: SPEF interrupt requests are disabled.,1: SPEF interrupt requests are enabled." newline bitfld.long 0x4 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: RFOF interrupt requests are disabled.,1: RFOF interrupt requests are enabled." bitfld.long 0x4 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: TFIWF interrupt requests are disabled.,1: TFIWF interrupt requests are enabled." newline bitfld.long 0x4 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: RFDF interrupt or DMA requests are disabled.,1: RFDF interrupt or DMA requests are enabled." bitfld.long 0x4 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select" "0: Interrupt request,1: DMA request" newline bitfld.long 0x4 15. "CMDFFF_DIRS,Command FIFO Fill DMA or Interrupt Request Select" "0: CMDFFF flag generates interrupt requests.,1: CMDFFF flag generates DMA requests." line.long 0x8 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x8 31. "CONT,Continuous Peripheral Chip Select Enable" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers." bitfld.long 0x8 28.--30. "CTAS,Clock and Transfer Attributes Select" "0: CTAR0,1: CTAR1,2: CTAR2,3: CTAR3,4: CTAR4,5: CTAR5,?,?" newline bitfld.long 0x8 27. "EOQ,End of Queue" "0: SPI data is not the last data to transfer.,1: SPI data is the last data to transfer." bitfld.long 0x8 26. "CTCNT,Clear Transfer Counter" "0: Do not clear the TCR[TCNT] field.,1: Clear the TCR[TCNT] field." newline bitfld.long 0x8 25. "PE_MASC,Parity Enable or Mask TASC Delay in Current Frame" "0: PE - No parity bit is included/checked. MASC -..,1: PE - Parity bit is transmitted instead of the.." bitfld.long 0x8 24. "PP_MCSC,Parity Polarity or Mask TCSC Delay in Next Frame" "0: PP - Even Parity: the number of 1 bits in the..,1: PP - Odd Parity: the number of 1 bits in the.." newline hexmask.long.byte 0x8 16.--23. 1. "PCS,PCS" hexmask.long.word 0x8 0.--15. 1. "TXDATA,Transmit Data" group.long 0x34++0x3 line.long 0x0 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" rgroup.long 0x38++0x3 line.long 0x0 "POPR,POP RX FIFO Register" hexmask.long 0x0 0.--31. 1. "RXDATA,Received Data" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x3C)++0x3 line.long 0x0 "TXFR[$1],Transmit FIFO Registers" hexmask.long.word 0x0 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data" hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x7C)++0x3 line.long 0x0 "RXFR[$1],Receive FIFO Registers" hexmask.long 0x0 0.--31. 1. "RXDATA,Receive Data" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x11C)++0x3 line.long 0x0 "CTARE[$1],Clock and Transfer Attributes Register Extended" bitfld.long 0x0 16. "FMSZE,Frame Size Extended" "0: Default Mode. Up to 16 bit SPI frames can be..,1: Up to 32 bit SPI frames can be transferred. Each.." hexmask.long.word 0x0 0.--10. 1. "DTCP,Data Transfer Count Preload" repeat.end rgroup.long 0x13C++0x3 line.long 0x0 "SREX,Status Register Extended" bitfld.long 0x0 14. "TXCTR4,TX FIFO Counter[4]" "0,1" bitfld.long 0x0 11. "RXCTR4,RX FIFO Counter[4]" "0,1" newline hexmask.long.byte 0x0 4.--8. 1. "CMDCTR,CMD FIFO Counter" hexmask.long.byte 0x0 0.--3. 1. "CMDNXTPTR,Command Next Pointer" tree.end tree.end tree "SRAMC (SRAM Controller)" base ad:0x0 tree "SRAMC" base ad:0x4019C000 group.long 0x0++0xF line.long 0x0 "PRAMCR,Platform RAM Control Register" bitfld.long 0x0 1.--2. "IWS,Initialization Wait Cycles" "0: No wait cycles between memory writes,1: One wait cycle between memory writes,2: Two wait cycles between memory writes,3: Three wait cycles between memory writes" bitfld.long 0x0 0. "INITREQ,Initialization Request" "0: No initialization is requested.,1: An initialization is requested." line.long 0x4 "PRAMIAS,Platform RAM Initialization Address Register Start" hexmask.long.tbyte 0x4 0.--16. 1. "IAS,Initialization Start Address" line.long 0x8 "PRAMIAE,Platform RAM Initialization Address Register End" hexmask.long.tbyte 0x8 0.--16. 1. "IAE,Initialization End Address" line.long 0xC "PRAMSR,Platform RAM Status Register" hexmask.long.byte 0xC 8.--15. 1. "SYND,ECC Syndrome Value" eventfld.long 0xC 7. "SGLERR,ECC Single-bit Error" "0: No single-bit error,1: A single-bit error" newline eventfld.long 0xC 6. "MLTERR,ECC Multi-bit Error" "0: No multi-bit error,1: A multi-bit error" eventfld.long 0xC 5. "AERR,ECC Address Error" "0: No address error,1: An address error" newline rbitfld.long 0xC 4. "AEXT,Indicates whether address bits used in the ECC HMatrix were from external or local RAM address" "0: Address bits used in the ECC HMatrix were the..,1: Address bits used in the ECC HMatrix were from.." rbitfld.long 0xC 2. "IPEND,Initialization Progress Status" "0: Initialization is not in progress.,1: Initialization is in progress." newline eventfld.long 0xC 1. "IERR,Initialization Error" "0: No non-ECC error occurred on a previous access,1: A non-ECC error occurred on a previous access" eventfld.long 0xC 0. "IDONE,Initialization Done" "0: Initialization is not complete.,1: Initialization completed successfully." rgroup.long 0x10++0x3 line.long 0x0 "PRAMECCA,Platform RAM ECC Address" hexmask.long.byte 0x0 21.--24. 1. "CTRLID,Indicates the controller ID of the reported error" bitfld.long 0x0 20. "EBNK,Indicates the RAM bank that has the ECC error indicated in the error fields" "0: Bank 0 has the error,1: Bank 1 has the error" newline hexmask.long.tbyte 0x0 0.--16. 1. "EADR,The chip writes to report ECC address associated with the error indicated in the error field in PRAMSR" tree.end tree "SRAMC_1" base ad:0x401A0000 group.long 0x0++0xF line.long 0x0 "PRAMCR,Platform RAM Control Register" bitfld.long 0x0 1.--2. "IWS,Initialization Wait Cycles" "0: No wait cycles between memory writes,1: One wait cycle between memory writes,2: Two wait cycles between memory writes,3: Three wait cycles between memory writes" bitfld.long 0x0 0. "INITREQ,Initialization Request" "0: No initialization is requested.,1: An initialization is requested." line.long 0x4 "PRAMIAS,Platform RAM Initialization Address Register Start" hexmask.long.tbyte 0x4 0.--16. 1. "IAS,Initialization Start Address" line.long 0x8 "PRAMIAE,Platform RAM Initialization Address Register End" hexmask.long.tbyte 0x8 0.--16. 1. "IAE,Initialization End Address" line.long 0xC "PRAMSR,Platform RAM Status Register" hexmask.long.byte 0xC 8.--15. 1. "SYND,ECC Syndrome Value" eventfld.long 0xC 7. "SGLERR,ECC Single-bit Error" "0: No single-bit error,1: A single-bit error" newline eventfld.long 0xC 6. "MLTERR,ECC Multi-bit Error" "0: No multi-bit error,1: A multi-bit error" eventfld.long 0xC 5. "AERR,ECC Address Error" "0: No address error,1: An address error" newline rbitfld.long 0xC 4. "AEXT,Indicates whether address bits used in the ECC HMatrix were from external or local RAM address" "0: Address bits used in the ECC HMatrix were the..,1: Address bits used in the ECC HMatrix were from.." rbitfld.long 0xC 2. "IPEND,Initialization Progress Status" "0: Initialization is not in progress.,1: Initialization is in progress." newline eventfld.long 0xC 1. "IERR,Initialization Error" "0: No non-ECC error occurred on a previous access,1: A non-ECC error occurred on a previous access" eventfld.long 0xC 0. "IDONE,Initialization Done" "0: Initialization is not complete.,1: Initialization completed successfully." rgroup.long 0x10++0x3 line.long 0x0 "PRAMECCA,Platform RAM ECC Address" hexmask.long.byte 0x0 21.--24. 1. "CTRLID,Indicates the controller ID of the reported error" bitfld.long 0x0 20. "EBNK,Indicates the RAM bank that has the ECC error indicated in the error fields" "0: Bank 0 has the error,1: Bank 1 has the error" newline hexmask.long.tbyte 0x0 0.--16. 1. "EADR,The chip writes to report ECC address associated with the error indicated in the error field in PRAMSR" tree.end tree "STDBY_SRAM_CFG" base ad:0x44028000 group.long 0x0++0xF line.long 0x0 "PRAMCR,Platform RAM Control Register" bitfld.long 0x0 1.--2. "IWS,Initialization Wait Cycles" "0: No wait cycles between memory writes,1: One wait cycle between memory writes,2: Two wait cycles between memory writes,3: Three wait cycles between memory writes" bitfld.long 0x0 0. "INITREQ,Initialization Request" "0: No initialization is requested.,1: An initialization is requested." line.long 0x4 "PRAMIAS,Platform RAM Initialization Address Register Start" hexmask.long.tbyte 0x4 0.--16. 1. "IAS,Initialization Start Address" line.long 0x8 "PRAMIAE,Platform RAM Initialization Address Register End" hexmask.long.tbyte 0x8 0.--16. 1. "IAE,Initialization End Address" line.long 0xC "PRAMSR,Platform RAM Status Register" hexmask.long.byte 0xC 8.--15. 1. "SYND,ECC Syndrome Value" eventfld.long 0xC 7. "SGLERR,ECC Single-bit Error" "0: No single-bit error,1: A single-bit error" newline eventfld.long 0xC 6. "MLTERR,ECC Multi-bit Error" "0: No multi-bit error,1: A multi-bit error" eventfld.long 0xC 5. "AERR,ECC Address Error" "0: No address error,1: An address error" newline rbitfld.long 0xC 4. "AEXT,Indicates whether address bits used in the ECC HMatrix were from external or local RAM address" "0: Address bits used in the ECC HMatrix were the..,1: Address bits used in the ECC HMatrix were from.." rbitfld.long 0xC 2. "IPEND,Initialization Progress Status" "0: Initialization is not in progress.,1: Initialization is in progress." newline eventfld.long 0xC 1. "IERR,Initialization Error" "0: No non-ECC error occurred on a previous access,1: A non-ECC error occurred on a previous access" eventfld.long 0xC 0. "IDONE,Initialization Done" "0: Initialization is not complete.,1: Initialization completed successfully." rgroup.long 0x10++0x3 line.long 0x0 "PRAMECCA,Platform RAM ECC Address" hexmask.long.byte 0x0 21.--24. 1. "CTRLID,Indicates the controller ID of the reported error" bitfld.long 0x0 20. "EBNK,Indicates the RAM bank that has the ECC error indicated in the error fields" "0: Bank 0 has the error,1: Bank 1 has the error" newline hexmask.long.tbyte 0x0 0.--16. 1. "EADR,The chip writes to report ECC address associated with the error indicated in the error field in PRAMSR" tree.end tree.end tree "SRC (System Resource Controller)" base ad:0x4007C000 group.long 0x0++0x7 line.long 0x0 "SW_NCF,Software-Triggered Faults" bitfld.long 0x0 4. "SW_NCF5,Software-Triggered Fault 5" "0: Not asserted,1: Asserted" newline bitfld.long 0x0 3. "SW_NCF4,Software-Triggered Fault 4" "0: Not asserted,1: Asserted" newline bitfld.long 0x0 2. "SW_NCF3,Software-Triggered Fault 3" "0: Not asserted,1: Asserted" newline bitfld.long 0x0 1. "SW_NCF2,Software-Triggered Fault 2" "0: Not asserted,1: Asserted" newline bitfld.long 0x0 0. "SW_NCF1,Software-Triggered Fault 1" "0: Not asserted,1: Asserted" line.long 0x4 "GMAC_0_CTRL_STS,GMAC Control" bitfld.long 0x4 11. "FTM1_SEL,FTM_1 Select" "0: GMAC_0,?" newline bitfld.long 0x4 10. "FTM0_SEL,FTM_0 Select" "0: GMAC_0,?" newline bitfld.long 0x4 1.--3. "PHY_INTF_SEL,PHY Interface Select" "0: MII,1: RGMII,?,?,4: RMII,?,?,?" newline bitfld.long 0x4 0. "PHY_MODE,PHY Mode" "0: Other PHY modes (for example: RGMII RMII MII),1: SGMII mode" group.long 0x28++0xB line.long 0x0 "CMU_STATUS_REG1,CMU Status 1" eventfld.long 0x0 31. "FLL_FHH_STAT_31,CMU_21 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 30. "FLL_FHH_STAT_30,CMU_21 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 29. "FLL_FHH_STAT_29,cm7_cluster_2 CMU FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 28. "FLL_FHH_STAT_28,cm7_cluster_2 CMU FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 27. "FLL_FHH_STAT_27,cm7_cluster_1 CMU FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 26. "FLL_FHH_STAT_26,cm7_cluster_1 CMU FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 25. "FLL_FHH_STAT_25,cm7_cluster_0 CMU FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 24. "FLL_FHH_STAT_24,cm7_cluster_0 CMU FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 23. "FLL_FHH_STAT_23,CMU_20 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 22. "FLL_FHH_STAT_22,CMU_20 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 19. "FLL_FHH_STAT_19,CMU_18 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 18. "FLL_FHH_STAT_18,CMU_18 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 17. "FLL_FHH_STAT_17,CMU_17 FHH Interrupt Event Status" "0: Event has not occurred.,1: Event has occurred." newline eventfld.long 0x0 16. "FLL_FHH_STAT_16,CMU_17 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 15. "FLL_FHH_STAT_15,CMU_16 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 14. "FLL_FHH_STAT_14,CMU_16 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 13. "FLL_FHH_STAT_13,CMU_15 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 12. "FLL_FHH_STAT_12,CMU_15 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 11. "FLL_FHH_STAT_11,CMU_14 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 10. "FLL_FHH_STAT_10,CMU_14 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 9. "FLL_FHH_STAT_9,CMU_13 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 8. "FLL_FHH_STAT_8,CMU_13 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 7. "FLL_FHH_STAT_7,CMU_12 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 6. "FLL_FHH_STAT_6,CMU_12 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 5. "FLL_FHH_STAT_5,CMU_11 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 4. "FLL_FHH_STAT_4,CMU_11 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 3. "FLL_FHH_STAT_3,CMU_10 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 2. "FLL_FHH_STAT_2,CMU_10 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 1. "FLL_FHH_STAT_1,CMU_7 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x0 0. "FLL_FHH_STAT_0,CMU_7 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" line.long 0x4 "CMU_STATUS_REG2,CMUs Status 2" eventfld.long 0x4 5. "FLL_FHH_STAT_5,a53_cluster1 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x4 4. "FLL_FHH_STAT_4,a53_cluster1 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x4 3. "FLL_FHH_STAT_3,a53_cluster0 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x4 2. "FLL_FHH_STAT_2,a53_cluster0 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x4 1. "FLL_FHH_STAT_1,CMU_22 FHH Interrupt Event Status" "0: Event did not occur,1: Event occurred" newline eventfld.long 0x4 0. "FLL_FHH_STAT_0,CMU_22 FLL Interrupt Event Status" "0: Event did not occur,1: Event occurred" line.long 0x8 "FCCU_EOUT_OVERRIDE_CLEAR_REG,FCCU EOUT Override Clear" bitfld.long 0x8 1. "EOUT_OVERRIDE_DISABLE_DURING_SELFTEST,EOUT Override Disable" "0: Move the FCCU_ERR0 to LOW and FCCU_ERR1 to HIGH..,1: Move the FCCU_ERR0 and FCCU_ERR1 to HIGH Z.." newline bitfld.long 0x8 0. "EOUT_OVERRIDE_CLEAR,EOUT Override Clear" "0: Do not clear,1: Clear" group.long 0x38++0x3 line.long 0x0 "SRC_POR_CTRL_REG,SRC POR Control" hexmask.long.word 0x0 16.--31. 1. "HSE_FW_ROLLBACK_MARKER,HSE_H Firmware Rollback Marker" newline hexmask.long.byte 0x0 8.--15. 1. "HSE_FW_ROLLBACK_COUNT_B,HSE Firmware Rollback Count - Backup Image" newline hexmask.long.byte 0x0 0.--7. 1. "HSE_FW_ROLLBACK_COUNT_A,HSE Firmware Rollback Count - Primary Image" group.long 0x54++0x3 line.long 0x0 "GPR21,GPR21" hexmask.long.tbyte 0x0 0.--19. 1. "PCIE_PARITY_MODE_data,Parity Mode Data" group.long 0xCC++0x3 line.long 0x0 "DEBUG_CONTROL,Debug Control" bitfld.long 0x0 9. "READY_FOR_DEBUG,Handshake With Debugger" "0: Debug configuration cannot start,1: Debug configuration can start" newline bitfld.long 0x0 8. "DBG_RST_MSK_1a,Mask Domain Reset" "0: Not masked,1: Masked" newline bitfld.long 0x0 7. "DBG_RST_MSK_0a,Mask nPRESETDBG" "0: Not masked,1: Masked" newline bitfld.long 0x0 6. "CA53_1_L2RSTDISABLE,L2RSTDISABLE Driver Input Of Cortex-A53 Cluster 1" "0: Enable,1: Disable" newline bitfld.long 0x0 5. "CA53_0_L2RSTDISABLE,L2RSTDISABLE Driver Input Of Cortex-A53 Cluster 0" "0: Enable,1: Disable" newline rbitfld.long 0x0 4. "JTAG_ACTIVE,JTAG_ACTIVE Status" "0: JTAG_ACTIVE is low,1: JTAG_ACTIVE is high" newline rbitfld.long 0x0 3. "DBG_SETUP_DONE,Status Of Debug Setup Completion By Debugger" "0: Debug setup not complete,1: Debug setup complete" newline bitfld.long 0x0 2. "CA53_1_DBGL1RSTDISABLE,DBGL1RSTDISABLE Driver Input Of Cortex-A53 Cluster 1" "0: Enable,1: Disable" newline bitfld.long 0x0 1. "CA53_0_DBGL1RSTDISABLE,DBGL1RSTDISABLE Driver Input Of Cortex-A53 Cluster 0" "0: Enable,1: Disable" newline bitfld.long 0x0 0. "DEBUG_CLK_DISABLE,Disable Clocks Of Debug And Trace Components In Functional Mode" "0: Enable clock,1: Disable clock" group.long 0xF0++0x7 line.long 0x0 "TIMESTAMP_CONTROL_REGISTER,Timestamp Control" bitfld.long 0x0 2. "TS_ENABLE,Timestamp Enable Control" "0: Disable,1: Enable" newline bitfld.long 0x0 0.--1. "CAN_TS_CNT_SEL,Timestamp Counter Select" "0: Select Timestamp 0 counter output,1: Select Timestamp 1 counter output,2: Select Timestamp 2 counter output,?" line.long 0x4 "FLEXRAY_OS_TICK_INPUT_SELECT_REG,FlexRay OS Tick Input Select" bitfld.long 0x4 2.--3. "FLEXRAY_1_STOPWATCH_MUX_SELECT,FlexRay_1 Stopwatch Mux Select" "0: PIT_1 channel number 5,1: STM_0 int0,2: STM_1 int0,3: STM_2 int0" newline bitfld.long 0x4 0.--1. "FLEXRAY_0_STOPWATCH_MUX_SELECT,FlexRay_0 Stopwatch Mux Select" "0: PIT_0 channel number 4,1: STM_0 int0,2: STM_1 int0,3: STM_2 int0" tree.end tree "SRC_GPR (SRC General Purpose Register)" base ad:0x4007C800 group.long 0x30++0x3 line.long 0x0 "GPR12,GPR12 Register" hexmask.long 0x0 0.--31. 1. "GPR12,GPR12" tree.end tree "STCU2 (Self-Test Control Unit)" base ad:0x40028000 group.long 0x4++0x3 line.long 0x0 "RUNSW,STCU2 Run Software" bitfld.long 0x0 11. "MBIE,MBIST Interrupt Enable" "0: Interrupt is not generated at the end of the..,1: At the end of the software MBIST execution phase.." bitfld.long 0x0 10. "LBIE,LBIST Interrupt Enable" "0: Interrupt is not generated at the end of the..,1: At the end of the software LBIST execution phase.." newline bitfld.long 0x0 0. "RUNSW,The RUNSW bit is automatically cleared by STCU2 when the online self-testing procedure is complete." "0: Idle,1: Online self-testing procedure is running" wgroup.long 0x8++0x3 line.long 0x0 "SKC,STCU2 SK Code" hexmask.long 0x0 0.--31. 1. "SKC,STCU2 SK Code" group.long 0xC++0x3 line.long 0x0 "CFG,STCU2 Configuration" hexmask.long.word 0x0 21.--30. 1. "PTR,First LBIST or MBIST pointer PTR defines the logical pointer to the first LBIST or MBIST to be scheduled when the self-testing procedure is enabled" hexmask.long.byte 0x0 13.--20. 1. "LB_DELAY,Delay LBIST run LB_DELAY defines the delay between the LBIST starts when more than a single LBIST is selected to be executed concurrently with the purpose of smoothing the power consumption transient" newline bitfld.long 0x0 8. "WRP,Write Protection 0: Specific STCU2 registers can be written through IPS bus interface 1: STCU2 registers cannot be written through IPS preventing any user application write operation" "0: Specific STCU2 registers can be written through..,1: STCU2 registers cannot be written through IPS" bitfld.long 0x0 0.--2. "CLK_CFG,Logic Memory BIST and STCU2 CORE_CLK configuration CLK_CFG defines the ratio between the sys_clk and the internal clock used to program both the LBIST and the MBIST and the STCU2 CORE_CLK" "0: sys_clk/1,1: sys_clk/2,2: sys_clk/3,3: sys_clk/4,4: sys_clk/5,5: sys_clk/6,6: sys_clk/7,7: sys_clk/8" group.long 0x14++0x7 line.long 0x0 "WDG,STCU2 Watchdog Granularity" hexmask.long 0x0 0.--31. 1. "WDGEOC,Watchdog End of Count Timer This value has to be set to define the time budget related to the online self-test execution and check that everything is correctly working within this slot of time" line.long 0x4 "INT_FLG,STCU2 Interrupt Flag" eventfld.long 0x4 1. "MBIFLG,MBIST Interrupt Flag" "0: No interrupt is pending,1: An interrupt highlighting that the online.." eventfld.long 0x4 0. "LBIFLG,LBIST Interrupt Flag" "0: No interrupt is pending.,1: An interrupt highlighting that the online.." group.long 0x24++0x7 line.long 0x0 "ERR_STAT,STCU2 Error" rbitfld.long 0x0 25. "ABORTHW,Online hardware abort flag You can always read this field" "0: No hardware abort was requested during the..,1: A hardware abort was detected during the online.." rbitfld.long 0x0 19. "WDTOSW,Online watchdog timeout You can always read this field" "0: LBIST and MBIST time slots completed within the..,1: LBIST and MBIST time slots not completed within.." newline rbitfld.long 0x0 17. "ENGESW,Online engine error You can always read this field" "0: Valid engine execution,1: Invalid engine execution. The error conditions.." rbitfld.long 0x0 16. "INVPSW,Online invalid pointer You can always read this field" "0: Valid linked pointer list,1: Invalid linked pointer list. The following.." newline bitfld.long 0x0 9. "UFSF,Unrecoverable Faults Status Flag This flag reports the global status of the Unrecoverable Faults(UF)" "0: No errors that trigger the UF condition.,1: There are errors that trigger the UF condition." bitfld.long 0x0 8. "RFSF,Recoverable Faults Status Flag This flag reports the global status of the Recoverable Fault (RF)" "0: No errors that trigger the Recoverable Faults..,1: There are errors that trigger the Recoverable.." line.long 0x4 "ERR_FM,STCU2 Error FM" bitfld.long 0x4 3. "WDTOUFM,Watchdog Timeout Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Fault Mapping" bitfld.long 0x4 1. "ENGEUFM,Engine Error Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Fault Mapping" newline bitfld.long 0x4 0. "INVPUFM,Invalid Pointer Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Mapping" rgroup.long 0x4C++0x7 line.long 0x0 "LBSSW0,STCU2 Online LBIST Status" bitfld.long 0x0 31. "LBSSW31,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 30. "LBSSW30,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 29. "LBSSW29,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 28. "LBSSW28,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 27. "LBSSW27,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 26. "LBSSW26,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 25. "LBSSW25,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 24. "LBSSW24,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 23. "LBSSW23,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 22. "LBSSW22,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 21. "LBSSW21,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 20. "LBSSW20,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 19. "LBSSW19,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 18. "LBSSW18,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 17. "LBSSW17,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 16. "LBSSW16,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 15. "LBSSW15,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 14. "LBSSW14,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 13. "LBSSW13,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 12. "LBSSW12,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 11. "LBSSW11,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 10. "LBSSW10,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 9. "LBSSW9,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 8. "LBSSW8,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 7. "LBSSW7,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 6. "LBSSW6,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 5. "LBSSW5,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 4. "LBSSW4,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 3. "LBSSW3,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 2. "LBSSW2,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x0 1. "LBSSW1,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x0 0. "LBSSW0,online status of the selected LBIST" "0: Failed LBIST execution,1: Successful LBIST execution" line.long 0x4 "LBSSW1,STCU2 Online LBIST Status" bitfld.long 0x4 27. "LBSSW59,LBSSW27" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 26. "LBSSW58,LBSSW26" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 25. "LBSSW57,LBSSW25" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 24. "LBSSW56,LBSSW24" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 23. "LBSSW55,LBSSW23" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 22. "LBSSW54,LBSSW22" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 21. "LBSSW53,LBSSW21" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 20. "LBSSW52,LBSSW20" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 19. "LBSSW51,LBSSW19" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 18. "LBSSW50,LBSSW18" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 17. "LBSSW49,LBSSW17" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 16. "LBSSW48,LBSSW16" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 15. "LBSSW47,LBSSW15" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 14. "LBSSW46,LBSSW14" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 13. "LBSSW45,LBSSW13" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 12. "LBSSW44,LBSSW12" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 11. "LBSSW43,LBSSW11" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 10. "LBSSW42,LBSSW10" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 9. "LBSSW41,LBSSW9" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 8. "LBSSW40,LBSSW8" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 7. "LBSSW39,LBSSW7" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 6. "LBSSW38,LBSSW6" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 5. "LBSSW37,LBSSW5" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 4. "LBSSW36,LBSSW4" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 3. "LBSSW35,LBSSW3" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 2. "LBSSW34,LBSSW2" "0: Failed LBIST execution,1: Successful LBIST execution" newline bitfld.long 0x4 1. "LBSSW33,LBSSW1" "0: Failed LBIST execution,1: Successful LBIST execution" bitfld.long 0x4 0. "LBSSW32,LBSSW0" "0: Failed LBIST execution,1: Successful LBIST execution" rgroup.long 0x5C++0x7 line.long 0x0 "LBESW0,STCU2 Online LBIST End Flag" bitfld.long 0x0 31. "LBESW31,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 30. "LBESW30,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 29. "LBESW29,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 28. "LBESW28,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 27. "LBESW27,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 26. "LBESW26,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 25. "LBESW25,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 24. "LBESW24,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 23. "LBESW23,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 22. "LBESW22,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 21. "LBESW21,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 20. "LBESW20,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 19. "LBESW19,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 18. "LBESW18,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 17. "LBESW17,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 16. "LBESW16,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 15. "LBESW15,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 14. "LBESW14,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 13. "LBESW13,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 12. "LBESW12,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 11. "LBESW11,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 10. "LBESW10,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 9. "LBESW9,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 8. "LBESW8,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 7. "LBESW7,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 6. "LBESW6,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 5. "LBESW5,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 4. "LBESW4,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 3. "LBESW3,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 2. "LBESW2,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x0 1. "LBESW1,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x0 0. "LBESW0,LBESWx: online LBIST end status" "0: LBIST execution not yet completed,1: LBIST execution finished" line.long 0x4 "LBESW1,STCU2 Online LBIST End Flag" bitfld.long 0x4 27. "LBESW59,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 26. "LBESW58,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 25. "LBESW57,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 24. "LBESW56,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 23. "LBESW55,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 22. "LBESW54,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 21. "LBESW53,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 20. "LBESW52,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 19. "LBESW51,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 18. "LBESW50,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 17. "LBESW49,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 16. "LBESW48,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 15. "LBESW47,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 14. "LBESW46,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 13. "LBESW45,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 12. "LBESW44,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 11. "LBESW43,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 10. "LBESW42,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 9. "LBESW41,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 8. "LBESW40,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 7. "LBESW39,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 6. "LBESW38,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 5. "LBESW37,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 4. "LBESW36,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 3. "LBESW35,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 2. "LBESW34,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" newline bitfld.long 0x4 1. "LBESW33,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" bitfld.long 0x4 0. "LBESW32,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" group.long 0x7C++0x7 line.long 0x0 "LBUFM0,STCU2 Online LBIST Unrecoverable FM" bitfld.long 0x0 31. "LBUFM31,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 30. "LBUFM30,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 29. "LBUFM29,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 28. "LBUFM28,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 27. "LBUFM27,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 26. "LBUFM26,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 25. "LBUFM25,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 24. "LBUFM24,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 23. "LBUFM23,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 22. "LBUFM22,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 21. "LBUFM21,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 20. "LBUFM20,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 19. "LBUFM19,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 18. "LBUFM18,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 17. "LBUFM17,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 16. "LBUFM16,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 15. "LBUFM15,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 14. "LBUFM14,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 13. "LBUFM13,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 12. "LBUFM12,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 11. "LBUFM11,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 10. "LBUFM10,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 9. "LBUFM9,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 8. "LBUFM8,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 7. "LBUFM7,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 6. "LBUFM6,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 5. "LBUFM5,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 4. "LBUFM4,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 3. "LBUFM3,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 2. "LBUFM2,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x0 1. "LBUFM1,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x0 0. "LBUFM0,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" line.long 0x4 "LBUFM1,STCU2 Online LBIST Unrecoverable FM" bitfld.long 0x4 27. "LBUFM59,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 26. "LBUFM58,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 25. "LBUFM57,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 24. "LBUFM56,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 23. "LBUFM55,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 22. "LBUFM54,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 21. "LBUFM53,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 20. "LBUFM52,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 19. "LBUFM51,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 18. "LBUFM50,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 17. "LBUFM49,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 16. "LBUFM48,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 15. "LBUFM47,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 14. "LBUFM46,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 13. "LBUFM45,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 12. "LBUFM44,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 11. "LBUFM43,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 10. "LBUFM42,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 9. "LBUFM41,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 8. "LBUFM40,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 7. "LBUFM39,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 6. "LBUFM38,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 5. "LBUFM37,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 4. "LBUFM36,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 3. "LBUFM35,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 2. "LBUFM34,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" newline bitfld.long 0x4 1. "LBUFM33,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" bitfld.long 0x4 0. "LBUFM32,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" rgroup.long 0x10C++0xF line.long 0x0 "MBSSW0,STCU2 Online MBIST Status" bitfld.long 0x0 31. "MBSSW31,MBSSW31" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 30. "MBSSW30,MBSSW30" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 29. "MBSSW29,MBSSW29" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 28. "MBSSW28,MBSSW28" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 27. "MBSSW27,MBSSW27" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 26. "MBSSW26,MBSSW26" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 25. "MBSSW25,MBSSW25" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 24. "MBSSW24,MBSSW24" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 23. "MBSSW23,MBSSW23" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 22. "MBSSW22,MBSSW22" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 21. "MBSSW21,MBSSW21" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 20. "MBSSW20,MBSSW20" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 19. "MBSSW19,MBSSW19" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 18. "MBSSW18,MBSSW18" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 17. "MBSSW17,MBSSW17" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 16. "MBSSW16,MBSSW16" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 15. "MBSSW15,MBSSW15" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 14. "MBSSW14,MBSSW14" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 13. "MBSSW13,MBSSW13" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 12. "MBSSW12,MBSSW12" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 11. "MBSSW11,MBSSW11" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 10. "MBSSW10,MBSSW10" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 9. "MBSSW9,MBSSW9" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 8. "MBSSW8,MBSSW8" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 7. "MBSSW7,MBSSW7" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 6. "MBSSW6,MBSSW6" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 5. "MBSSW5,MBSSW5" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 4. "MBSSW4,MBSSW4" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 3. "MBSSW3,MBSSW3" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 2. "MBSSW2,MBSSW2" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 1. "MBSSW1,MBSSW1" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 0. "MBSSW0,MBSSW0" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" line.long 0x4 "MBSSW1,STCU2 Online MBIST Status" bitfld.long 0x4 31. "MBSSW63,MBSSW63" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 30. "MBSSW62,MBSSW62" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 29. "MBSSW61,MBSSW61" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 28. "MBSSW60,MBSSW60" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 27. "MBSSW59,MBSSW59" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 26. "MBSSW58,MBSSW58" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 25. "MBSSW57,MBSSW57" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 24. "MBSSW56,MBSSW56" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 23. "MBSSW55,MBSSW55" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 22. "MBSSW54,MBSSW54" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 21. "MBSSW53,MBSSW53" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 20. "MBSSW52,MBSSW52" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 19. "MBSSW51,MBSSW51" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 18. "MBSSW50,MBSSW50" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 17. "MBSSW49,MBSSW49" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 16. "MBSSW48,MBSSW48" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 15. "MBSSW47,MBSSW47" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 14. "MBSSW46,MBSSW46" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 13. "MBSSW45,MBSSW45" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 12. "MBSSW44,MBSSW44" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 11. "MBSSW43,MBSSW43" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 10. "MBSSW42,MBSSW42" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 9. "MBSSW41,MBSSW41" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 8. "MBSSW40,MBSSW40" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 7. "MBSSW39,MBSSW39" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 6. "MBSSW38,MBSSW38" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 5. "MBSSW37,MBSSW37" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 4. "MBSSW36,MBSSW36" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 3. "MBSSW35,MBSSW35" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 2. "MBSSW34,MBSSW34" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x4 1. "MBSSW33,MBSSW33" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x4 0. "MBSSW32,MBSSW32" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" line.long 0x8 "MBSSW2,STCU2 Online MBIST Status" bitfld.long 0x8 31. "MBSSW95,MBSSW95" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 30. "MBSSW94,MBSSW94" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 29. "MBSSW93,MBSSW93" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 28. "MBSSW92,MBSSW92" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 27. "MBSSW91,MBSSW91" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 26. "MBSSW90,MBSSW90" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 25. "MBSSW89,MBSSW89" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 24. "MBSSW88,MBSSW88" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 23. "MBSSW87,MBSSW87" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 22. "MBSSW86,MBSSW86" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 21. "MBSSW85,MBSSW85" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 20. "MBSSW84,MBSSW84" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 19. "MBSSW83,MBSSW83" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 18. "MBSSW82,MBSSW82" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 17. "MBSSW81,MBSSW81" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 16. "MBSSW80,MBSSW80" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 15. "MBSSW79,MBSSW79" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 14. "MBSSW78,MBSSW78" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 13. "MBSSW77,MBSSW77" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 12. "MBSSW76,MBSSW76" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 11. "MBSSW75,MBSSW75" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 10. "MBSSW74,MBSSW74" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 9. "MBSSW73,MBSSW73" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 8. "MBSSW72,MBSSW72" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 7. "MBSSW71,MBSSW71" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 6. "MBSSW70,MBSSW70" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 5. "MBSSW69,MBSSW69" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 4. "MBSSW68,MBSSW68" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 3. "MBSSW67,MBSSW67" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 2. "MBSSW66,MBSSW66" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x8 1. "MBSSW65,MBSSW65" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x8 0. "MBSSW64,MBSSW64" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" line.long 0xC "MBSSW3,STCU2 Online MBIST Status" bitfld.long 0xC 13. "MBSSW109,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0xC 12. "MBSSW108,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0xC 11. "MBSSW107,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0xC 10. "MBSSW106,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0xC 9. "MBSSW105,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0xC 8. "MBSSW104,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0xC 7. "MBSSW103,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0xC 6. "MBSSW102,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0xC 5. "MBSSW101,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0xC 4. "MBSSW100,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0xC 3. "MBSSW99,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0xC 2. "MBSSW98,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0xC 1. "MBSSW97,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0xC 0. "MBSSW96,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" rgroup.long 0x14C++0xF line.long 0x0 "MBESW0,STCU2 Online MBIST End Flag" bitfld.long 0x0 31. "MBESW31,Online end status of MBISTn (where n = 62:31)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 30. "MBESW30,Online end status of MBISTn (where n = 61:30)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 29. "MBESW29,Online end status of MBISTn (where n = 60:29)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 28. "MBESW28,Online end status of MBISTn (where n = 59:28)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 27. "MBESW27,Online end status of MBISTn (where n = 58:27)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 26. "MBESW26,Online end status of MBISTn (where n = 57:26)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 25. "MBESW25,Online end status of MBISTn (where n = 56:25)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 24. "MBESW24,Online end status of MBISTn (where n = 55:24)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 23. "MBESW23,Online end status of MBISTn (where n = 54:23)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 22. "MBESW22,Online end status of MBISTn (where n = 53:22)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 21. "MBESW21,Online end status of MBISTn (where n = 52:21)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 20. "MBESW20,Online end status of MBISTn (where n = 51:20)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 19. "MBESW19,Online end status of MBISTn (where n = 50:19)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 18. "MBESW18,Online end status of MBISTn (where n = 49:18)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 17. "MBESW17,Online end status of MBISTn (where n = 48:17)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 16. "MBESW16,Online end status of MBISTn (where n = 47:16)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBESW15,Online end status of MBISTn (where n = 46:15)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 14. "MBESW14,Online end status of MBISTn (where n = 45:14)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBESW13,Online end status of MBISTn (where n = 44:13)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 12. "MBESW12,Online end status of MBISTn (where n = 43:12)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBESW11,Online end status of MBISTn (where n = 42:11)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 10. "MBESW10,Online end status of MBISTn (where n = 41:10)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBESW9,Online end status of MBISTn (where n = 40:9)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 8. "MBESW8,Online end status of MBISTn (where n = 39:8)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBESW7,Online end status of MBISTn (where n = 38:7)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 6. "MBESW6,Online end status of MBISTn (where n = 37:6)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBESW5,Online end status of MBISTn (where n = 36:5)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 4. "MBESW4,Online end status of MBISTn (where n = 35:4)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBESW3,Online end status of MBISTn (where n = 34:3)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 2. "MBESW2,Online end status of MBISTn (where n = 33:2)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBESW1,Online end status of MBISTn (where n = 32:1)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 0. "MBESW0,Online end status of MBISTn (where n = 31:0)" "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x4 "MBESW1,STCU2 Online MBIST End Flag" bitfld.long 0x4 31. "MBESW63,Online end status of MBISTn (where n = 94:63)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 30. "MBESW62,Online end status of MBISTn (where n = 93:62)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 29. "MBESW61,Online end status of MBISTn (where n = 92:61)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 28. "MBESW60,Online end status of MBISTn (where n = 91:60)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 27. "MBESW59,Online end status of MBISTn (where n = 90:59)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 26. "MBESW58,Online end status of MBISTn (where n = 89:58)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 25. "MBESW57,Online end status of MBISTn (where n = 88:57)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 24. "MBESW56,Online end status of MBISTn (where n = 87:56)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 23. "MBESW55,Online end status of MBISTn (where n = 86:55)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 22. "MBESW54,Online end status of MBISTn (where n = 85:54)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 21. "MBESW53,Online end status of MBISTn (where n = 84:53)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 20. "MBESW52,Online end status of MBISTn (where n = 83:52)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 19. "MBESW51,Online end status of MBISTn (where n = 82:51)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 18. "MBESW50,Online end status of MBISTn (where n = 81:50)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 17. "MBESW49,Online end status of MBISTn (where n = 80:49)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 16. "MBESW48,Online end status of MBISTn (where n = 79:48)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 15. "MBESW47,Online end status of MBISTn (where n = 78:47)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 14. "MBESW46,Online end status of MBISTn (where n = 77:46)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 13. "MBESW45,Online end status of MBISTn (where n = 76:45)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 12. "MBESW44,Online end status of MBISTn (where n = 75:44)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 11. "MBESW43,Online end status of MBISTn (where n = 74:43)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 10. "MBESW42,Online end status of MBISTn (where n = 73:42)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 9. "MBESW41,Online end status of MBISTn (where n = 72:41)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 8. "MBESW40,Online end status of MBISTn (where n = 71:40)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 7. "MBESW39,Online end status of MBISTn (where n = 70:39)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 6. "MBESW38,Online end status of MBISTn (where n = 69:38)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 5. "MBESW37,Online end status of MBISTn (where n = 68:37)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 4. "MBESW36,Online end status of MBISTn (where n = 67:36)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 3. "MBESW35,Online end status of MBISTn (where n = 66:35)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 2. "MBESW34,Online end status of MBISTn (where n = 65:34)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x4 1. "MBESW33,Online end status of MBISTn (where n = 64:33)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x4 0. "MBESW32,Online end status of MBISTn (where n = 63:32)" "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0x8 "MBESW2,STCU2 Online MBIST End Flag" bitfld.long 0x8 31. "MBESW95,Online end status of MBISTn (where n = 126:95)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 30. "MBESW94,Online end status of MBISTn (where n = 125:94)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 29. "MBESW93,Online end status of MBISTn (where n = 124:93)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 28. "MBESW92,Online end status of MBISTn (where n = 123:92)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 27. "MBESW91,Online end status of MBISTn (where n = 122:91)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 26. "MBESW90,Online end status of MBISTn (where n = 121:90)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 25. "MBESW89,Online end status of MBISTn (where n = 120:89)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 24. "MBESW88,Online end status of MBISTn (where n = 119:88)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 23. "MBESW87,Online end status of MBISTn (where n = 118:87)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 22. "MBESW86,Online end status of MBISTn (where n = 117:86)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 21. "MBESW85,Online end status of MBISTn (where n = 116:85)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 20. "MBESW84,Online end status of MBISTn (where n = 115:84)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 19. "MBESW83,Online end status of MBISTn (where n = 114:83)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 18. "MBESW82,Online end status of MBISTn (where n = 113:82)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 17. "MBESW81,Online end status of MBISTn (where n = 112:81)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 16. "MBESW80,Online end status of MBISTn (where n = 111:80)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 15. "MBESW79,Online end status of MBISTn (where n = 110:79)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 14. "MBESW78,Online end status of MBISTn (where n = 109:78)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 13. "MBESW77,Online end status of MBISTn (where n = 108:77)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 12. "MBESW76,Online end status of MBISTn (where n = 107:76)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 11. "MBESW75,Online end status of MBISTn (where n = 106:75)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 10. "MBESW74,Online end status of MBISTn (where n = 105:74)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 9. "MBESW73,Online end status of MBISTn (where n = 104:73)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 8. "MBESW72,Online end status of MBISTn (where n = 103:72)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 7. "MBESW71,Online end status of MBISTn (where n = 102:71)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 6. "MBESW70,Online end status of MBISTn (where n = 101:70)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 5. "MBESW69,Online end status of MBISTn (where n = 100:69)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 4. "MBESW68,Online end status of MBISTn (where n = 99:68)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 3. "MBESW67,Online end status of MBISTn (where n = 98:67)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 2. "MBESW66,Online end status of MBISTn (where n = 97:66)" "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x8 1. "MBESW65,Online end status of MBISTn (where n = 96:65)" "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x8 0. "MBESW64,Online end status of MBISTn (where n = 95:64)" "0: MBIST execution still ongoing,1: MBIST execution finished" line.long 0xC "MBESW3,STCU2 Online MBIST End Flag" bitfld.long 0xC 13. "MBESW109,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0xC 12. "MBESW108,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0xC 11. "MBESW107,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0xC 10. "MBESW106,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0xC 9. "MBESW105,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0xC 8. "MBESW104,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0xC 7. "MBESW103,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0xC 6. "MBESW102,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0xC 5. "MBESW101,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0xC 4. "MBESW100,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0xC 3. "MBESW99,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0xC 2. "MBESW98,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0xC 1. "MBESW97,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0xC 0. "MBESW96,Online end status of MBISTn (where n = 109:96)." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x18C++0xF line.long 0x0 "MBUFM0,STCU2 MBIST Unrecoverable FM" bitfld.long 0x0 31. "MBUFM31,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 30. "MBUFM30,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 29. "MBUFM29,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 28. "MBUFM28,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 27. "MBUFM27,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 26. "MBUFM26,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 25. "MBUFM25,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 24. "MBUFM24,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 23. "MBUFM23,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 22. "MBUFM22,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 21. "MBUFM21,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 20. "MBUFM20,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 19. "MBUFM19,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 18. "MBUFM18,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 17. "MBUFM17,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 16. "MBUFM16,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MBUFM15,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 14. "MBUFM14,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MBUFM13,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 12. "MBUFM12,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MBUFM11,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 10. "MBUFM10,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MBUFM9,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 8. "MBUFM8,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MBUFM7,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 6. "MBUFM6,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MBUFM5,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 4. "MBUFM4,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MBUFM3,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 2. "MBUFM2,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MBUFM1,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 0. "MBUFM0,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" line.long 0x4 "MBUFM1,STCU2 MBIST Unrecoverable FM" bitfld.long 0x4 31. "MBUFM63,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 30. "MBUFM62,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 29. "MBUFM61,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 28. "MBUFM60,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 27. "MBUFM59,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 26. "MBUFM58,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 25. "MBUFM57,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 24. "MBUFM56,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 23. "MBUFM55,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 22. "MBUFM54,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 21. "MBUFM53,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 20. "MBUFM52,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 19. "MBUFM51,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 18. "MBUFM50,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 17. "MBUFM49,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 16. "MBUFM48,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 15. "MBUFM47,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 14. "MBUFM46,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 13. "MBUFM45,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 12. "MBUFM44,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 11. "MBUFM43,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 10. "MBUFM42,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 9. "MBUFM41,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 8. "MBUFM40,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 7. "MBUFM39,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 6. "MBUFM38,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 5. "MBUFM37,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 4. "MBUFM36,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 3. "MBUFM35,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 2. "MBUFM34,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x4 1. "MBUFM33,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x4 0. "MBUFM32,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" line.long 0x8 "MBUFM2,STCU2 MBIST Unrecoverable FM" bitfld.long 0x8 31. "MBUFM95,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 30. "MBUFM94,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 29. "MBUFM93,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 28. "MBUFM92,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 27. "MBUFM91,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 26. "MBUFM90,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 25. "MBUFM89,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 24. "MBUFM88,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 23. "MBUFM87,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 22. "MBUFM86,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 21. "MBUFM85,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 20. "MBUFM84,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 19. "MBUFM83,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 18. "MBUFM82,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 17. "MBUFM81,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 16. "MBUFM80,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 15. "MBUFM79,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 14. "MBUFM78,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 13. "MBUFM77,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 12. "MBUFM76,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 11. "MBUFM75,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 10. "MBUFM74,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 9. "MBUFM73,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 8. "MBUFM72,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 7. "MBUFM71,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 6. "MBUFM70,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 5. "MBUFM69,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 4. "MBUFM68,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 3. "MBUFM67,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 2. "MBUFM66,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x8 1. "MBUFM65,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x8 0. "MBUFM64,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" line.long 0xC "MBUFM3,STCU2 MBIST Unrecoverable FM" bitfld.long 0xC 13. "MBUFM109,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0xC 12. "MBUFM108,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0xC 11. "MBUFM107,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0xC 10. "MBUFM106,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0xC 9. "MBUFM105,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0xC 8. "MBUFM104,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0xC 7. "MBUFM103,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0xC 6. "MBUFM102,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0xC 5. "MBUFM101,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0xC 4. "MBUFM100,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0xC 3. "MBUFM99,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0xC 2. "MBUFM98,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0xC 1. "MBUFM97,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0xC 0. "MBUFM96,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" group.long 0x200++0x7 line.long 0x0 "LB_CTRL0,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS0,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x220++0x7 line.long 0x0 "LB_MISRELSW0,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW0,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x228++0x7 line.long 0x0 "LB_MISRRLSW0,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW0,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x240++0x7 line.long 0x0 "LB_CTRL1,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS1,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x260++0x7 line.long 0x0 "LB_MISRELSW1,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW1,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x268++0x7 line.long 0x0 "LB_MISRRLSW1,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW1,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x280++0x7 line.long 0x0 "LB_CTRL2,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS2,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x2A0++0x7 line.long 0x0 "LB_MISRELSW2,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW2,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x2A8++0x7 line.long 0x0 "LB_MISRRLSW2,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW2,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x2C0++0x7 line.long 0x0 "LB_CTRL3,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS3,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x2E0++0x7 line.long 0x0 "LB_MISRELSW3,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW3,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x2E8++0x7 line.long 0x0 "LB_MISRRLSW3,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW3,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x300++0x7 line.long 0x0 "LB_CTRL4,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS4,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x320++0x7 line.long 0x0 "LB_MISRELSW4,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW4,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x328++0x7 line.long 0x0 "LB_MISRRLSW4,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW4,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x340++0x7 line.long 0x0 "LB_CTRL5,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS5,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x360++0x7 line.long 0x0 "LB_MISRELSW5,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW5,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x368++0x7 line.long 0x0 "LB_MISRRLSW5,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW5,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x380++0x7 line.long 0x0 "LB_CTRL6,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS6,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x3A0++0x7 line.long 0x0 "LB_MISRELSW6,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW6,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x3A8++0x7 line.long 0x0 "LB_MISRRLSW6,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW6,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x3C0++0x7 line.long 0x0 "LB_CTRL7,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS7,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x3E0++0x7 line.long 0x0 "LB_MISRELSW7,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW7,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x3E8++0x7 line.long 0x0 "LB_MISRRLSW7,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW7,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x400++0x7 line.long 0x0 "LB_CTRL8,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS8,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x420++0x7 line.long 0x0 "LB_MISRELSW8,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW8,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x428++0x7 line.long 0x0 "LB_MISRRLSW8,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW8,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x440++0x7 line.long 0x0 "LB_CTRL9,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS9,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x460++0x7 line.long 0x0 "LB_MISRELSW9,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW9,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x468++0x7 line.long 0x0 "LB_MISRRLSW9,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW9,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x480++0x7 line.long 0x0 "LB_CTRL10,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS10,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x4A0++0x7 line.long 0x0 "LB_MISRELSW10,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW10,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x4A8++0x7 line.long 0x0 "LB_MISRRLSW10,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW10,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x4C0++0x7 line.long 0x0 "LB_CTRL11,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS11,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x4E0++0x7 line.long 0x0 "LB_MISRELSW11,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW11,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x4E8++0x7 line.long 0x0 "LB_MISRRLSW11,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW11,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x500++0x7 line.long 0x0 "LB_CTRL12,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS12,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x520++0x7 line.long 0x0 "LB_MISRELSW12,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW12,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x528++0x7 line.long 0x0 "LB_MISRRLSW12,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW12,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x540++0x7 line.long 0x0 "LB_CTRL13,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS13,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x560++0x7 line.long 0x0 "LB_MISRELSW13,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW13,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x568++0x7 line.long 0x0 "LB_MISRRLSW13,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW13,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x580++0x7 line.long 0x0 "LB_CTRL14,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS14,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x5A0++0x7 line.long 0x0 "LB_MISRELSW14,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW14,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x5A8++0x7 line.long 0x0 "LB_MISRRLSW14,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW14,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x5C0++0x7 line.long 0x0 "LB_CTRL15,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS15,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x5E0++0x7 line.long 0x0 "LB_MISRELSW15,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW15,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x5E8++0x7 line.long 0x0 "LB_MISRRLSW15,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW15,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x600++0x7 line.long 0x0 "LB_CTRL16,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS16,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x620++0x7 line.long 0x0 "LB_MISRELSW16,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW16,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x628++0x7 line.long 0x0 "LB_MISRRLSW16,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW16,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x640++0x7 line.long 0x0 "LB_CTRL17,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS17,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x660++0x7 line.long 0x0 "LB_MISRELSW17,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW17,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x668++0x7 line.long 0x0 "LB_MISRRLSW17,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW17,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x680++0x7 line.long 0x0 "LB_CTRL18,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS18,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x6A0++0x7 line.long 0x0 "LB_MISRELSW18,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW18,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x6A8++0x7 line.long 0x0 "LB_MISRRLSW18,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW18,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x6C0++0x7 line.long 0x0 "LB_CTRL19,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS19,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x6E0++0x7 line.long 0x0 "LB_MISRELSW19,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW19,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x6E8++0x7 line.long 0x0 "LB_MISRRLSW19,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW19,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x700++0x7 line.long 0x0 "LB_CTRL20,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS20,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x720++0x7 line.long 0x0 "LB_MISRELSW20,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW20,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x728++0x7 line.long 0x0 "LB_MISRRLSW20,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW20,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x740++0x7 line.long 0x0 "LB_CTRL21,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS21,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x760++0x7 line.long 0x0 "LB_MISRELSW21,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW21,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x768++0x7 line.long 0x0 "LB_MISRRLSW21,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW21,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x780++0x7 line.long 0x0 "LB_CTRL22,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS22,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x7A0++0x7 line.long 0x0 "LB_MISRELSW22,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW22,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x7A8++0x7 line.long 0x0 "LB_MISRRLSW22,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW22,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x7C0++0x7 line.long 0x0 "LB_CTRL23,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS23,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x7E0++0x7 line.long 0x0 "LB_MISRELSW23,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW23,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x7E8++0x7 line.long 0x0 "LB_MISRRLSW23,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW23,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x800++0x7 line.long 0x0 "LB_CTRL24,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS24,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x820++0x7 line.long 0x0 "LB_MISRELSW24,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW24,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x828++0x7 line.long 0x0 "LB_MISRRLSW24,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW24,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x840++0x7 line.long 0x0 "LB_CTRL25,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS25,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x860++0x7 line.long 0x0 "LB_MISRELSW25,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW25,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x868++0x7 line.long 0x0 "LB_MISRRLSW25,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW25,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x880++0x7 line.long 0x0 "LB_CTRL26,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS26,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x8A0++0x7 line.long 0x0 "LB_MISRELSW26,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW26,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x8A8++0x7 line.long 0x0 "LB_MISRRLSW26,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW26,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x8C0++0x7 line.long 0x0 "LB_CTRL27,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS27,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x8E0++0x7 line.long 0x0 "LB_MISRELSW27,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW27,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x8E8++0x7 line.long 0x0 "LB_MISRRLSW27,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW27,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x900++0x7 line.long 0x0 "LB_CTRL28,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS28,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x920++0x7 line.long 0x0 "LB_MISRELSW28,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW28,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x928++0x7 line.long 0x0 "LB_MISRRLSW28,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW28,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x940++0x7 line.long 0x0 "LB_CTRL29,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS29,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x960++0x7 line.long 0x0 "LB_MISRELSW29,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW29,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x968++0x7 line.long 0x0 "LB_MISRRLSW29,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW29,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x980++0x7 line.long 0x0 "LB_CTRL30,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS30,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x9A0++0x7 line.long 0x0 "LB_MISRELSW30,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW30,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x9A8++0x7 line.long 0x0 "LB_MISRRLSW30,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW30,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x9C0++0x7 line.long 0x0 "LB_CTRL31,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS31,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x9E0++0x7 line.long 0x0 "LB_MISRELSW31,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW31,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x9E8++0x7 line.long 0x0 "LB_MISRRLSW31,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW31,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xA00++0x7 line.long 0x0 "LB_CTRL32,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS32,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xA20++0x7 line.long 0x0 "LB_MISRELSW32,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW32,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xA28++0x7 line.long 0x0 "LB_MISRRLSW32,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW32,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xA40++0x7 line.long 0x0 "LB_CTRL33,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS33,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xA60++0x7 line.long 0x0 "LB_MISRELSW33,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW33,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xA68++0x7 line.long 0x0 "LB_MISRRLSW33,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW33,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xA80++0x7 line.long 0x0 "LB_CTRL34,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS34,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xAA0++0x7 line.long 0x0 "LB_MISRELSW34,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW34,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xAA8++0x7 line.long 0x0 "LB_MISRRLSW34,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW34,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xAC0++0x7 line.long 0x0 "LB_CTRL35,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS35,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xAE0++0x7 line.long 0x0 "LB_MISRELSW35,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW35,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xAE8++0x7 line.long 0x0 "LB_MISRRLSW35,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW35,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xB00++0x7 line.long 0x0 "LB_CTRL36,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS36,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xB20++0x7 line.long 0x0 "LB_MISRELSW36,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW36,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xB28++0x7 line.long 0x0 "LB_MISRRLSW36,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW36,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xB40++0x7 line.long 0x0 "LB_CTRL37,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS37,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xB60++0x7 line.long 0x0 "LB_MISRELSW37,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW37,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xB68++0x7 line.long 0x0 "LB_MISRRLSW37,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW37,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xB80++0x7 line.long 0x0 "LB_CTRL38,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS38,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xBA0++0x7 line.long 0x0 "LB_MISRELSW38,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW38,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xBA8++0x7 line.long 0x0 "LB_MISRRLSW38,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW38,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xBC0++0x7 line.long 0x0 "LB_CTRL39,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS39,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xBE0++0x7 line.long 0x0 "LB_MISRELSW39,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW39,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xBE8++0x7 line.long 0x0 "LB_MISRRLSW39,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW39,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xC00++0x7 line.long 0x0 "LB_CTRL40,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS40,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xC20++0x7 line.long 0x0 "LB_MISRELSW40,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW40,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xC28++0x7 line.long 0x0 "LB_MISRRLSW40,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW40,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xC40++0x7 line.long 0x0 "LB_CTRL41,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS41,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xC60++0x7 line.long 0x0 "LB_MISRELSW41,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW41,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xC68++0x7 line.long 0x0 "LB_MISRRLSW41,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW41,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xC80++0x7 line.long 0x0 "LB_CTRL42,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS42,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xCA0++0x7 line.long 0x0 "LB_MISRELSW42,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW42,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xCA8++0x7 line.long 0x0 "LB_MISRRLSW42,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW42,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xCC0++0x7 line.long 0x0 "LB_CTRL43,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS43,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xCE0++0x7 line.long 0x0 "LB_MISRELSW43,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW43,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xCE8++0x7 line.long 0x0 "LB_MISRRLSW43,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW43,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xD00++0x7 line.long 0x0 "LB_CTRL44,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS44,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xD20++0x7 line.long 0x0 "LB_MISRELSW44,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW44,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xD28++0x7 line.long 0x0 "LB_MISRRLSW44,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW44,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xD40++0x7 line.long 0x0 "LB_CTRL45,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS45,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xD60++0x7 line.long 0x0 "LB_MISRELSW45,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW45,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xD68++0x7 line.long 0x0 "LB_MISRRLSW45,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW45,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xD80++0x7 line.long 0x0 "LB_CTRL46,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS46,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xDA0++0x7 line.long 0x0 "LB_MISRELSW46,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW46,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xDA8++0x7 line.long 0x0 "LB_MISRRLSW46,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW46,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xDC0++0x7 line.long 0x0 "LB_CTRL47,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS47,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xDE0++0x7 line.long 0x0 "LB_MISRELSW47,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW47,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xDE8++0x7 line.long 0x0 "LB_MISRRLSW47,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW47,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xE00++0x7 line.long 0x0 "LB_CTRL48,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS48,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xE20++0x7 line.long 0x0 "LB_MISRELSW48,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW48,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xE28++0x7 line.long 0x0 "LB_MISRRLSW48,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW48,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xE40++0x7 line.long 0x0 "LB_CTRL49,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS49,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xE60++0x7 line.long 0x0 "LB_MISRELSW49,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW49,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xE68++0x7 line.long 0x0 "LB_MISRRLSW49,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW49,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xE80++0x7 line.long 0x0 "LB_CTRL50,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS50,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xEA0++0x7 line.long 0x0 "LB_MISRELSW50,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW50,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xEA8++0x7 line.long 0x0 "LB_MISRRLSW50,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW50,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xEC0++0x7 line.long 0x0 "LB_CTRL51,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS51,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xEE0++0x7 line.long 0x0 "LB_MISRELSW51,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW51,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xEE8++0x7 line.long 0x0 "LB_MISRRLSW51,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW51,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xF00++0x7 line.long 0x0 "LB_CTRL52,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS52,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xF20++0x7 line.long 0x0 "LB_MISRELSW52,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW52,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xF28++0x7 line.long 0x0 "LB_MISRRLSW52,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW52,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xF40++0x7 line.long 0x0 "LB_CTRL53,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS53,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xF60++0x7 line.long 0x0 "LB_MISRELSW53,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW53,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xF68++0x7 line.long 0x0 "LB_MISRRLSW53,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW53,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xF80++0x7 line.long 0x0 "LB_CTRL54,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS54,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xFA0++0x7 line.long 0x0 "LB_MISRELSW54,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW54,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xFA8++0x7 line.long 0x0 "LB_MISRRLSW54,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW54,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0xFC0++0x7 line.long 0x0 "LB_CTRL55,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS55,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0xFE0++0x7 line.long 0x0 "LB_MISRELSW55,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW55,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0xFE8++0x7 line.long 0x0 "LB_MISRRLSW55,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW55,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x1000++0x7 line.long 0x0 "LB_CTRL56,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS56,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x1020++0x7 line.long 0x0 "LB_MISRELSW56,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW56,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x1028++0x7 line.long 0x0 "LB_MISRRLSW56,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW56,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x1040++0x7 line.long 0x0 "LB_CTRL57,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS57,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x1060++0x7 line.long 0x0 "LB_MISRELSW57,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW57,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x1068++0x7 line.long 0x0 "LB_MISRRLSW57,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW57,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x1080++0x7 line.long 0x0 "LB_CTRL58,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS58,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x10A0++0x7 line.long 0x0 "LB_MISRELSW58,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW58,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x10A8++0x7 line.long 0x0 "LB_MISRRLSW58,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW58,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x10C0++0x7 line.long 0x0 "LB_CTRL59,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS59,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x10E0++0x7 line.long 0x0 "LB_MISRELSW59,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW59,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x10E8++0x7 line.long 0x0 "LB_MISRRLSW59,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW59,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x2200++0x3 line.long 0x0 "ALGOSEL,STCU2 Algorithm Select" bitfld.long 0x0 31. "ALGOSEL31,Algorithm Select" "0,1" bitfld.long 0x0 30. "ALGOSEL30,Algorithm Select" "0,1" newline bitfld.long 0x0 29. "ALGOSEL29,Algorithm Select" "0,1" bitfld.long 0x0 28. "ALGOSEL28,Algorithm Select" "0,1" newline bitfld.long 0x0 27. "ALGOSEL27,Algorithm Select" "0,1" bitfld.long 0x0 26. "ALGOSEL26,Algorithm Select" "0,1" newline bitfld.long 0x0 25. "ALGOSEL25,Algorithm Select" "0,1" bitfld.long 0x0 24. "ALGOSEL24,Algorithm Select" "0,1" newline bitfld.long 0x0 23. "ALGOSEL23,Algorithm Select" "0,1" bitfld.long 0x0 22. "ALGOSEL22,Algorithm Select" "0,1" newline bitfld.long 0x0 21. "ALGOSEL21,Algorithm Select" "0,1" bitfld.long 0x0 20. "ALGOSEL20,Algorithm Select" "0,1" newline bitfld.long 0x0 19. "ALGOSEL19,Algorithm Select" "0,1" bitfld.long 0x0 18. "ALGOSEL18,Algorithm Select" "0,1" newline bitfld.long 0x0 17. "ALGOSEL17,Algorithm Select" "0,1" bitfld.long 0x0 16. "ALGOSEL16,Algorithm Select" "0,1" newline bitfld.long 0x0 15. "ALGOSEL15,Algorithm Select" "0,1" bitfld.long 0x0 14. "ALGOSEL14,Algorithm Select" "0,1" newline bitfld.long 0x0 13. "ALGOSEL13,Algorithm Select" "0,1" bitfld.long 0x0 12. "ALGOSEL12,Algorithm Select" "0,1" newline bitfld.long 0x0 11. "ALGOSEL11,Algorithm Select" "0,1" bitfld.long 0x0 10. "ALGOSEL10,Algorithm Select" "0,1" newline bitfld.long 0x0 9. "ALGOSEL9,Algorithm Select" "0,1" bitfld.long 0x0 8. "ALGOSEL8,Algorithm Select" "0,1" newline bitfld.long 0x0 7. "ALGOSEL7,Algorithm Select" "0,1" bitfld.long 0x0 6. "ALGOSEL6,Algorithm Select" "0,1" newline bitfld.long 0x0 5. "ALGOSEL5,Algorithm Select" "0,1" bitfld.long 0x0 4. "ALGOSEL4,Algorithm Select" "0,1" newline bitfld.long 0x0 3. "ALGOSEL3,Algorithm Select" "0,1" bitfld.long 0x0 2. "ALGOSEL2,Algorithm Select" "0,1" newline bitfld.long 0x0 1. "ALGOSEL1,Algorithm Select" "0,1" bitfld.long 0x0 0. "ALGOSEL0,Algorithm Select" "0,1" group.long 0x220C++0x1BF line.long 0x0 "STGGR,STCU2 MBIST Stagger" hexmask.long 0x0 0.--31. 1. "STAG,STAG" line.long 0x4 "BSTART,STCU2 BIST Start" bitfld.long 0x4 31. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 4. "BSR,BIST Status Reset" "0,1" newline bitfld.long 0x4 0.--2. "BSTART,no description available" "0: NOP (reset value),1: Run the selected BISTs without programming them..,?,?,4: Program BISTs only but do not start them. This..,5: Program BISTs and start them.,?,?" line.long 0x8 "MB_CTRL0,STCU2 MBIST Control" bitfld.long 0x8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x8 21.--30. 1. "PTR,PTR" newline bitfld.long 0x8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xC "MB_CTRL1,STCU2 MBIST Control" bitfld.long 0xC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xC 21.--30. 1. "PTR,PTR" newline bitfld.long 0xC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x10 "MB_CTRL2,STCU2 MBIST Control" bitfld.long 0x10 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x10 21.--30. 1. "PTR,PTR" newline bitfld.long 0x10 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x14 "MB_CTRL3,STCU2 MBIST Control" bitfld.long 0x14 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x14 21.--30. 1. "PTR,PTR" newline bitfld.long 0x14 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x18 "MB_CTRL4,STCU2 MBIST Control" bitfld.long 0x18 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x18 21.--30. 1. "PTR,PTR" newline bitfld.long 0x18 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1C "MB_CTRL5,STCU2 MBIST Control" bitfld.long 0x1C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x20 "MB_CTRL6,STCU2 MBIST Control" bitfld.long 0x20 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x20 21.--30. 1. "PTR,PTR" newline bitfld.long 0x20 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x24 "MB_CTRL7,STCU2 MBIST Control" bitfld.long 0x24 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x24 21.--30. 1. "PTR,PTR" newline bitfld.long 0x24 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x28 "MB_CTRL8,STCU2 MBIST Control" bitfld.long 0x28 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x28 21.--30. 1. "PTR,PTR" newline bitfld.long 0x28 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x2C "MB_CTRL9,STCU2 MBIST Control" bitfld.long 0x2C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x2C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x2C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x30 "MB_CTRL10,STCU2 MBIST Control" bitfld.long 0x30 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x30 21.--30. 1. "PTR,PTR" newline bitfld.long 0x30 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x34 "MB_CTRL11,STCU2 MBIST Control" bitfld.long 0x34 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x34 21.--30. 1. "PTR,PTR" newline bitfld.long 0x34 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x38 "MB_CTRL12,STCU2 MBIST Control" bitfld.long 0x38 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x38 21.--30. 1. "PTR,PTR" newline bitfld.long 0x38 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x3C "MB_CTRL13,STCU2 MBIST Control" bitfld.long 0x3C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x3C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x3C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x40 "MB_CTRL14,STCU2 MBIST Control" bitfld.long 0x40 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x40 21.--30. 1. "PTR,PTR" newline bitfld.long 0x40 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x44 "MB_CTRL15,STCU2 MBIST Control" bitfld.long 0x44 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x44 21.--30. 1. "PTR,PTR" newline bitfld.long 0x44 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x48 "MB_CTRL16,STCU2 MBIST Control" bitfld.long 0x48 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x48 21.--30. 1. "PTR,PTR" newline bitfld.long 0x48 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x4C "MB_CTRL17,STCU2 MBIST Control" bitfld.long 0x4C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x4C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x4C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x50 "MB_CTRL18,STCU2 MBIST Control" bitfld.long 0x50 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x50 21.--30. 1. "PTR,PTR" newline bitfld.long 0x50 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x54 "MB_CTRL19,STCU2 MBIST Control" bitfld.long 0x54 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x54 21.--30. 1. "PTR,PTR" newline bitfld.long 0x54 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x58 "MB_CTRL20,STCU2 MBIST Control" bitfld.long 0x58 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x58 21.--30. 1. "PTR,PTR" newline bitfld.long 0x58 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x5C "MB_CTRL21,STCU2 MBIST Control" bitfld.long 0x5C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x5C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x5C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x60 "MB_CTRL22,STCU2 MBIST Control" bitfld.long 0x60 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x60 21.--30. 1. "PTR,PTR" newline bitfld.long 0x60 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x64 "MB_CTRL23,STCU2 MBIST Control" bitfld.long 0x64 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x64 21.--30. 1. "PTR,PTR" newline bitfld.long 0x64 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x68 "MB_CTRL24,STCU2 MBIST Control" bitfld.long 0x68 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x68 21.--30. 1. "PTR,PTR" newline bitfld.long 0x68 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x6C "MB_CTRL25,STCU2 MBIST Control" bitfld.long 0x6C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x6C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x6C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x70 "MB_CTRL26,STCU2 MBIST Control" bitfld.long 0x70 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x70 21.--30. 1. "PTR,PTR" newline bitfld.long 0x70 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x74 "MB_CTRL27,STCU2 MBIST Control" bitfld.long 0x74 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x74 21.--30. 1. "PTR,PTR" newline bitfld.long 0x74 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x78 "MB_CTRL28,STCU2 MBIST Control" bitfld.long 0x78 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x78 21.--30. 1. "PTR,PTR" newline bitfld.long 0x78 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x7C "MB_CTRL29,STCU2 MBIST Control" bitfld.long 0x7C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x7C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x7C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x80 "MB_CTRL30,STCU2 MBIST Control" bitfld.long 0x80 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x80 21.--30. 1. "PTR,PTR" newline bitfld.long 0x80 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x84 "MB_CTRL31,STCU2 MBIST Control" bitfld.long 0x84 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x84 21.--30. 1. "PTR,PTR" newline bitfld.long 0x84 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x88 "MB_CTRL32,STCU2 MBIST Control" bitfld.long 0x88 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x88 21.--30. 1. "PTR,PTR" newline bitfld.long 0x88 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x8C "MB_CTRL33,STCU2 MBIST Control" bitfld.long 0x8C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x8C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x8C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x90 "MB_CTRL34,STCU2 MBIST Control" bitfld.long 0x90 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x90 21.--30. 1. "PTR,PTR" newline bitfld.long 0x90 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x94 "MB_CTRL35,STCU2 MBIST Control" bitfld.long 0x94 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x94 21.--30. 1. "PTR,PTR" newline bitfld.long 0x94 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x98 "MB_CTRL36,STCU2 MBIST Control" bitfld.long 0x98 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x98 21.--30. 1. "PTR,PTR" newline bitfld.long 0x98 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x9C "MB_CTRL37,STCU2 MBIST Control" bitfld.long 0x9C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x9C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x9C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xA0 "MB_CTRL38,STCU2 MBIST Control" bitfld.long 0xA0 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xA0 21.--30. 1. "PTR,PTR" newline bitfld.long 0xA0 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xA4 "MB_CTRL39,STCU2 MBIST Control" bitfld.long 0xA4 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xA4 21.--30. 1. "PTR,PTR" newline bitfld.long 0xA4 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xA8 "MB_CTRL40,STCU2 MBIST Control" bitfld.long 0xA8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xA8 21.--30. 1. "PTR,PTR" newline bitfld.long 0xA8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xAC "MB_CTRL41,STCU2 MBIST Control" bitfld.long 0xAC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xAC 21.--30. 1. "PTR,PTR" newline bitfld.long 0xAC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xB0 "MB_CTRL42,STCU2 MBIST Control" bitfld.long 0xB0 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xB0 21.--30. 1. "PTR,PTR" newline bitfld.long 0xB0 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xB4 "MB_CTRL43,STCU2 MBIST Control" bitfld.long 0xB4 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xB4 21.--30. 1. "PTR,PTR" newline bitfld.long 0xB4 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xB8 "MB_CTRL44,STCU2 MBIST Control" bitfld.long 0xB8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xB8 21.--30. 1. "PTR,PTR" newline bitfld.long 0xB8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xBC "MB_CTRL45,STCU2 MBIST Control" bitfld.long 0xBC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xBC 21.--30. 1. "PTR,PTR" newline bitfld.long 0xBC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xC0 "MB_CTRL46,STCU2 MBIST Control" bitfld.long 0xC0 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xC0 21.--30. 1. "PTR,PTR" newline bitfld.long 0xC0 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xC4 "MB_CTRL47,STCU2 MBIST Control" bitfld.long 0xC4 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xC4 21.--30. 1. "PTR,PTR" newline bitfld.long 0xC4 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xC8 "MB_CTRL48,STCU2 MBIST Control" bitfld.long 0xC8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xC8 21.--30. 1. "PTR,PTR" newline bitfld.long 0xC8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xCC "MB_CTRL49,STCU2 MBIST Control" bitfld.long 0xCC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xCC 21.--30. 1. "PTR,PTR" newline bitfld.long 0xCC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xD0 "MB_CTRL50,STCU2 MBIST Control" bitfld.long 0xD0 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xD0 21.--30. 1. "PTR,PTR" newline bitfld.long 0xD0 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xD4 "MB_CTRL51,STCU2 MBIST Control" bitfld.long 0xD4 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xD4 21.--30. 1. "PTR,PTR" newline bitfld.long 0xD4 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xD8 "MB_CTRL52,STCU2 MBIST Control" bitfld.long 0xD8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xD8 21.--30. 1. "PTR,PTR" newline bitfld.long 0xD8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xDC "MB_CTRL53,STCU2 MBIST Control" bitfld.long 0xDC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xDC 21.--30. 1. "PTR,PTR" newline bitfld.long 0xDC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xE0 "MB_CTRL54,STCU2 MBIST Control" bitfld.long 0xE0 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xE0 21.--30. 1. "PTR,PTR" newline bitfld.long 0xE0 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xE4 "MB_CTRL55,STCU2 MBIST Control" bitfld.long 0xE4 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xE4 21.--30. 1. "PTR,PTR" newline bitfld.long 0xE4 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xE8 "MB_CTRL56,STCU2 MBIST Control" bitfld.long 0xE8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xE8 21.--30. 1. "PTR,PTR" newline bitfld.long 0xE8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xEC "MB_CTRL57,STCU2 MBIST Control" bitfld.long 0xEC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xEC 21.--30. 1. "PTR,PTR" newline bitfld.long 0xEC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xF0 "MB_CTRL58,STCU2 MBIST Control" bitfld.long 0xF0 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xF0 21.--30. 1. "PTR,PTR" newline bitfld.long 0xF0 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xF4 "MB_CTRL59,STCU2 MBIST Control" bitfld.long 0xF4 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xF4 21.--30. 1. "PTR,PTR" newline bitfld.long 0xF4 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xF8 "MB_CTRL60,STCU2 MBIST Control" bitfld.long 0xF8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xF8 21.--30. 1. "PTR,PTR" newline bitfld.long 0xF8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xFC "MB_CTRL61,STCU2 MBIST Control" bitfld.long 0xFC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xFC 21.--30. 1. "PTR,PTR" newline bitfld.long 0xFC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x100 "MB_CTRL62,STCU2 MBIST Control" bitfld.long 0x100 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x100 21.--30. 1. "PTR,PTR" newline bitfld.long 0x100 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x104 "MB_CTRL63,STCU2 MBIST Control" bitfld.long 0x104 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x104 21.--30. 1. "PTR,PTR" newline bitfld.long 0x104 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x108 "MB_CTRL64,STCU2 MBIST Control" bitfld.long 0x108 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x108 21.--30. 1. "PTR,PTR" newline bitfld.long 0x108 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x10C "MB_CTRL65,STCU2 MBIST Control" bitfld.long 0x10C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x10C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x10C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x110 "MB_CTRL66,STCU2 MBIST Control" bitfld.long 0x110 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x110 21.--30. 1. "PTR,PTR" newline bitfld.long 0x110 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x114 "MB_CTRL67,STCU2 MBIST Control" bitfld.long 0x114 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x114 21.--30. 1. "PTR,PTR" newline bitfld.long 0x114 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x118 "MB_CTRL68,STCU2 MBIST Control" bitfld.long 0x118 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x118 21.--30. 1. "PTR,PTR" newline bitfld.long 0x118 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x11C "MB_CTRL69,STCU2 MBIST Control" bitfld.long 0x11C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x11C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x11C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x120 "MB_CTRL70,STCU2 MBIST Control" bitfld.long 0x120 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x120 21.--30. 1. "PTR,PTR" newline bitfld.long 0x120 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x124 "MB_CTRL71,STCU2 MBIST Control" bitfld.long 0x124 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x124 21.--30. 1. "PTR,PTR" newline bitfld.long 0x124 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x128 "MB_CTRL72,STCU2 MBIST Control" bitfld.long 0x128 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x128 21.--30. 1. "PTR,PTR" newline bitfld.long 0x128 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x12C "MB_CTRL73,STCU2 MBIST Control" bitfld.long 0x12C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x12C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x12C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x130 "MB_CTRL74,STCU2 MBIST Control" bitfld.long 0x130 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x130 21.--30. 1. "PTR,PTR" newline bitfld.long 0x130 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x134 "MB_CTRL75,STCU2 MBIST Control" bitfld.long 0x134 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x134 21.--30. 1. "PTR,PTR" newline bitfld.long 0x134 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x138 "MB_CTRL76,STCU2 MBIST Control" bitfld.long 0x138 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x138 21.--30. 1. "PTR,PTR" newline bitfld.long 0x138 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x13C "MB_CTRL77,STCU2 MBIST Control" bitfld.long 0x13C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x13C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x13C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x140 "MB_CTRL78,STCU2 MBIST Control" bitfld.long 0x140 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x140 21.--30. 1. "PTR,PTR" newline bitfld.long 0x140 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x144 "MB_CTRL79,STCU2 MBIST Control" bitfld.long 0x144 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x144 21.--30. 1. "PTR,PTR" newline bitfld.long 0x144 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x148 "MB_CTRL80,STCU2 MBIST Control" bitfld.long 0x148 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x148 21.--30. 1. "PTR,PTR" newline bitfld.long 0x148 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x14C "MB_CTRL81,STCU2 MBIST Control" bitfld.long 0x14C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x14C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x14C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x150 "MB_CTRL82,STCU2 MBIST Control" bitfld.long 0x150 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x150 21.--30. 1. "PTR,PTR" newline bitfld.long 0x150 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x154 "MB_CTRL83,STCU2 MBIST Control" bitfld.long 0x154 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x154 21.--30. 1. "PTR,PTR" newline bitfld.long 0x154 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x158 "MB_CTRL84,STCU2 MBIST Control" bitfld.long 0x158 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x158 21.--30. 1. "PTR,PTR" newline bitfld.long 0x158 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x15C "MB_CTRL85,STCU2 MBIST Control" bitfld.long 0x15C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x15C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x15C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x160 "MB_CTRL86,STCU2 MBIST Control" bitfld.long 0x160 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x160 21.--30. 1. "PTR,PTR" newline bitfld.long 0x160 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x164 "MB_CTRL87,STCU2 MBIST Control" bitfld.long 0x164 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x164 21.--30. 1. "PTR,PTR" newline bitfld.long 0x164 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x168 "MB_CTRL88,STCU2 MBIST Control" bitfld.long 0x168 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x168 21.--30. 1. "PTR,PTR" newline bitfld.long 0x168 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x16C "MB_CTRL89,STCU2 MBIST Control" bitfld.long 0x16C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x16C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x16C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x170 "MB_CTRL90,STCU2 MBIST Control" bitfld.long 0x170 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x170 21.--30. 1. "PTR,PTR" newline bitfld.long 0x170 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x174 "MB_CTRL91,STCU2 MBIST Control" bitfld.long 0x174 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x174 21.--30. 1. "PTR,PTR" newline bitfld.long 0x174 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x178 "MB_CTRL92,STCU2 MBIST Control" bitfld.long 0x178 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x178 21.--30. 1. "PTR,PTR" newline bitfld.long 0x178 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x17C "MB_CTRL93,STCU2 MBIST Control" bitfld.long 0x17C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x17C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x17C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x180 "MB_CTRL94,STCU2 MBIST Control" bitfld.long 0x180 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x180 21.--30. 1. "PTR,PTR" newline bitfld.long 0x180 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x184 "MB_CTRL95,STCU2 MBIST Control" bitfld.long 0x184 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x184 21.--30. 1. "PTR,PTR" newline bitfld.long 0x184 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x188 "MB_CTRL96,STCU2 MBIST Control" bitfld.long 0x188 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x188 21.--30. 1. "PTR,PTR" newline bitfld.long 0x188 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x18C "MB_CTRL97,STCU2 MBIST Control" bitfld.long 0x18C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x18C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x18C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x190 "MB_CTRL98,STCU2 MBIST Control" bitfld.long 0x190 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x190 21.--30. 1. "PTR,PTR" newline bitfld.long 0x190 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x194 "MB_CTRL99,STCU2 MBIST Control" bitfld.long 0x194 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x194 21.--30. 1. "PTR,PTR" newline bitfld.long 0x194 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x198 "MB_CTRL100,STCU2 MBIST Control" bitfld.long 0x198 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x198 21.--30. 1. "PTR,PTR" newline bitfld.long 0x198 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x19C "MB_CTRL101,STCU2 MBIST Control" bitfld.long 0x19C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x19C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x19C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1A0 "MB_CTRL102,STCU2 MBIST Control" bitfld.long 0x1A0 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1A0 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1A0 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1A4 "MB_CTRL103,STCU2 MBIST Control" bitfld.long 0x1A4 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1A4 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1A4 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1A8 "MB_CTRL104,STCU2 MBIST Control" bitfld.long 0x1A8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1A8 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1A8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1AC "MB_CTRL105,STCU2 MBIST Control" bitfld.long 0x1AC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1AC 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1AC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1B0 "MB_CTRL106,STCU2 MBIST Control" bitfld.long 0x1B0 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1B0 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1B0 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1B4 "MB_CTRL107,STCU2 MBIST Control" bitfld.long 0x1B4 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1B4 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1B4 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1B8 "MB_CTRL108,STCU2 MBIST Control" bitfld.long 0x1B8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1B8 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1B8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1BC "MB_CTRL109,STCU2 MBIST Control" bitfld.long 0x1BC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1BC 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1BC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." tree.end tree "STM (System Timer Module)" base ad:0x0 tree "STM_0" base ad:0x4011C000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4011C010 ad:0x4011C020 ad:0x4011C030 ad:0x4011C040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_1" base ad:0x40120000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40120010 ad:0x40120020 ad:0x40120030 ad:0x40120040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_2" base ad:0x40124000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40124010 ad:0x40124020 ad:0x40124030 ad:0x40124040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_3" base ad:0x40128000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40128010 ad:0x40128020 ad:0x40128030 ad:0x40128040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_4" base ad:0x4021C000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4021C010 ad:0x4021C020 ad:0x4021C030 ad:0x4021C040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_5" base ad:0x40220000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40220010 ad:0x40220020 ad:0x40220030 ad:0x40220040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_6" base ad:0x40224000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40224010 ad:0x40224020 ad:0x40224030 ad:0x40224040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_7" base ad:0x40228000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40228010 ad:0x40228020 ad:0x40228030 ad:0x40228040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_TS" base ad:0x4400C000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4400C010 ad:0x4400C020 ad:0x4400C030 ad:0x4400C040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree.end tree "SWT (Software Watchdog Timer)" base ad:0x0 tree "SWT_0" base ad:0x40100000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 2. "STP,Stop Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" newline bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree "SWT_1" base ad:0x40104000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 2. "STP,Stop Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" newline bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree "SWT_2" base ad:0x40108000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 2. "STP,Stop Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" newline bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree "SWT_3" base ad:0x4010C000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 2. "STP,Stop Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" newline bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree "SWT_4" base ad:0x40200000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 2. "STP,Stop Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" newline bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree "SWT_5" base ad:0x40204000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 2. "STP,Stop Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" newline bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree "SWT_6" base ad:0x40208000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 2. "STP,Stop Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" newline bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree.end tree "TMU (Thermal Monitoring Unit)" base ad:0x400A8000 group.long 0x0++0xF line.long 0x0 "TMR,Mode" bitfld.long 0x0 30.--31. "MODE,Mode" "0: Idle; low-power mode,?,2: Monitoring of sites as defined by TMSR[SITE],?" bitfld.long 0x0 29. "CMD,Central Module Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x0 24.--25. "ALPF,Average Low Pass Filter Setting" "0: 1.0,1: 0.5,2: 0.25,3: 0.125" line.long 0x4 "TSR,Status" rbitfld.long 0x4 31. "TB,TMU Busy" "0: TMU is idle,1: TMU is busy" eventfld.long 0x4 30. "MIE,Monitoring Interval Exceeded" "0: Monitoring interval not exceeded,1: Monitoring interval exceeded" newline eventfld.long 0x4 29. "ORL,Out-of-Range Low Temperature Measurement" "0: No out-of-range low temperature measurement..,1: Out-of-range low temperature measurement detected" eventfld.long 0x4 28. "ORH,Out-of-Range High Temperature Measurement" "0: No out-of-range high temperature measurement..,1: Out-of-range high temperature measurement detected" line.long 0x8 "TMSR,Monitor Site" bitfld.long 0x8 0.--2. "SITE,Monitoring Site Select 2-0" "0,1,2,3,4,5,6,7" line.long 0xC "TMTMIR,Monitor Temperature Measurement Interval" hexmask.long.byte 0xC 0.--3. 1. "TMI,Temperature Monitoring Interval in Seconds" group.long 0x20++0x7 line.long 0x0 "TIER,Interrupt Enable" bitfld.long 0x0 31. "IHTTIE,Immediate High Temperature Threshold Interrupt Enable" "0: Disabled,1: Interrupt enabled; generates an interrupt if.." bitfld.long 0x0 30. "AHTTIE,Average High Temperature Threshold Interrupt Enable" "0: Disabled,1: Interrupt enabled; generates an interrupt if.." newline bitfld.long 0x0 29. "AHTCTIE,Average High Temperature Critical Threshold Interrupt Enable" "0: Disabled,1: Interrupt enabled; generates an interrupt if.." bitfld.long 0x0 28. "ILTTIE,Immediate Low Temperature Threshold Interrupt Enable" "0: Disabled,1: Interrupt enabled; generates an interrupt if.." newline bitfld.long 0x0 27. "ALTTIE,Average Low Temperature Threshold Interrupt Enable" "0: Disabled,1: Interrupt enabled; generates an interrupt if.." bitfld.long 0x0 26. "ALTCTIE,Average Low Temperature Critical Threshold Interrupt Enable" "0: Disabled,1: Interrupt enabled; generates an interrupt if.." newline bitfld.long 0x0 25. "RTRCTIE,Rising Temperature Rate Critical Threshold Interrupt Enable" "0: Disabled,1: Interrupt enabled; generates an interrupt if.." bitfld.long 0x0 24. "FTRCTIE,Falling Temperature Rate Critical Threshold Interrupt Enable" "0: Disabled,1: Interrupt enabled; generates an interrupt if.." line.long 0x4 "TIDR,Interrupt Detect" eventfld.long 0x4 31. "IHTT,Immediate High Temperature Threshold Exceeded" "0: No threshold exceeded,1: One or more monitored sites has exceeded the.." eventfld.long 0x4 30. "AHTT,Average High Temperature Threshold Exceeded" "0: No threshold exceeded,1: One or more monitored sites exceed the average.." newline eventfld.long 0x4 29. "AHTCT,Average High Temperature Critical Threshold Exceeded" "0: No threshold exceeded,1: One or more monitored sites exceed the average.." eventfld.long 0x4 28. "ILTT,Immediate Low Temperature Threshold" "0: No threshold exceeded,1: One or more monitored sites has passed the.." newline eventfld.long 0x4 27. "ALTT,Average Low Temperature Threshold" "0: No threshold exceeded,1: One or more monitored sites pass the average low.." eventfld.long 0x4 26. "ALTCT,Average Low Temperature Critical Threshold" "0: No threshold exceeded,1: One or more monitored sites pass the average low.." newline eventfld.long 0x4 25. "RTRCT,Rising Temperature Rate Critical Threshold" "0: No threshold exceeded,1: One or more monitored sites pass the rising.." eventfld.long 0x4 24. "FTRCT,Falling Temperature Rate Critical Threshold" "0: No threshold exceeded,1: One or more monitored sites exceed the falling.." group.long 0x30++0xB line.long 0x0 "TIISCR,Interrupt Immediate Site Capture" bitfld.long 0x0 0.--2. "SITE,Temperature Sensor Site" "0,1,2,3,4,5,6,7" line.long 0x4 "TIASCR,Interrupt Average Site Capture" bitfld.long 0x4 0.--2. "SITE,Temperature Sensor Site" "0,1,2,3,4,5,6,7" line.long 0x8 "TICSCR,Interrupt Critical Site Capture" bitfld.long 0x8 0.--2. "SITE,Temperature Sensor Site" "0,1,2,3,4,5,6,7" group.long 0x40++0x1B line.long 0x0 "TMHTCR,Monitor High Temperature Capture" eventfld.long 0x0 31. "V,Valid Reading" "0: Temperature reading is not valid due to no..,1: Temperature reading is valid" rbitfld.long 0x0 9. "TP5,Highest Temperature Recorded in Kelvin by Any Enabled Monitored Site" "0,1" newline hexmask.long.word 0x0 0.--8. 1. "TEMP,Highest Temperature Recorded in Kelvin by Any Enabled Monitored Site" line.long 0x4 "TMLTCR,Monitor Low Temperature Capture" eventfld.long 0x4 31. "V,Valid Reading" "0: Temperature reading is not valid because of no..,1: Temperature reading is valid" rbitfld.long 0x4 9. "TP5,Lowest Temperature in Kelvin that Any Enabled Monitored Site Records" "0,1" newline hexmask.long.word 0x4 0.--8. 1. "TEMP,Lowest Temperature in Kelvin that Any Enabled Monitored Site Records" line.long 0x8 "TMRTRCR,Monitor Rising Temperature Rate Capture" eventfld.long 0x8 31. "V,Valid Reading" "0: Temperature reading is not valid because of no..,1: Temperature reading is valid" hexmask.long.byte 0x8 0.--7. 1. "TEMP,Highest Rising Temperature Rate Change in Kelvin that Any Enabled Monitored Site Records" line.long 0xC "TMFTRCR,Monitor Falling Temperature Rate Capture" eventfld.long 0xC 31. "V,Valid Reading" "0: Temperature reading is not valid because of no..,1: Temperature reading is valid" hexmask.long.byte 0xC 0.--7. 1. "TEMP,Highest Falling Temperature Rate Change in Kelvin that Any Enabled Monitored Site Records" line.long 0x10 "TMHTITR,Monitor High Temperature Immediate Threshold" bitfld.long 0x10 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled" hexmask.long.word 0x10 0.--8. 1. "TEMP,High Temperature Immediate Threshold Value" line.long 0x14 "TMHTATR,Monitor High Temperature Average Threshold" bitfld.long 0x14 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled" hexmask.long.word 0x14 0.--8. 1. "TEMP,High Temperature Average Threshold Value" line.long 0x18 "TMHTACTR,Monitor High Temperature Average Critical Threshold" bitfld.long 0x18 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled" hexmask.long.word 0x18 0.--8. 1. "TEMP,High Temperature Average Critical Threshold Value" group.long 0x60++0xB line.long 0x0 "TMLTITR,Monitor Low Temperature Immediate Threshold" bitfld.long 0x0 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled" hexmask.long.word 0x0 0.--8. 1. "TEMP,Low Temperature Immediate Threshold Value" line.long 0x4 "TMLTATR,Monitor Low Temperature Average Threshold" bitfld.long 0x4 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled" hexmask.long.word 0x4 0.--8. 1. "TEMP,Low Temperature Average Threshold Value" line.long 0x8 "TMLTACTR,Monitor Low Temperature Average Critical Threshold" bitfld.long 0x8 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled" hexmask.long.word 0x8 0.--8. 1. "TEMP,Low Temperature Average Critical Threshold Value" group.long 0x70++0x7 line.long 0x0 "TMRTRCTR,Monitor Rising Temperature Rate Critical Threshold" bitfld.long 0x0 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled" hexmask.long.byte 0x0 0.--7. 1. "TEMP,Temperature Difference Between Two Measurements From the Same Site" line.long 0x4 "TMFTRCTR,Monitor Falling Temperature Rate Critical Threshold" bitfld.long 0x4 31. "EN,Enable threshold" "0: Disabled,1: Threshold Enabled" hexmask.long.byte 0x4 0.--7. 1. "TEMP,Temperature Difference Between Two Measurements From the Same Site" group.long 0x80++0x7 line.long 0x0 "TTCFGR,Temperature Configuration" hexmask.long.byte 0x0 0.--3. 1. "CAL_PT,Calibration Point" line.long 0x4 "TSCFGR,Sensor Configuration" hexmask.long.word 0x4 0.--8. 1. "SENSOR,Sensor Value" repeat 3. (list 0x0 0x1 0x2)(list ad:0x400A8100 ad:0x400A8110 ad:0x400A8120) tree "TRITRATSR[$1]" base $2 rgroup.long ($2)++0x7 line.long 0x0 "TRITSR,Report Immediate Temperature at Site" bitfld.long 0x0 31. "V,Valid Measured Temperature" "0: Not valid; temperature is out of sensor..,1: Valid" bitfld.long 0x0 9. "TP5,Last Temperature Reading in Kelvin at the Site" "0,1" hexmask.long.word 0x0 0.--8. 1. "TEMP,Last Temperature Reading in Kelvin at the Site" line.long 0x4 "TRATSR,Report Average Temperature at Site" bitfld.long 0x4 31. "V,Valid Measured Temperature" "0: Not valid; temperature is out of sensor range or..,1: Valid" hexmask.long.word 0x4 0.--8. 1. "TEMP,Average Temperature Reading in Kelvin at the Site" tree.end repeat.end base ad:0x400A8000 group.long 0xF00++0x3 line.long 0x0 "TCMCFG,Central Module Configuration" bitfld.long 0x0 31. "DPM,Dynamic Power Management" "0,1" bitfld.long 0x0 30. "OCM,Offset Cancellation Mode" "0,1" newline bitfld.long 0x0 29. "OCS,Offset Cancellation Manual Setting" "0,1" bitfld.long 0x0 28. "DEMA,Dynamic Element Match Averaging Mode" "0,1" newline bitfld.long 0x0 24.--26. "RCTC,RC Time Constant Setting" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16. "SAR_RDY,SAR Ready" "0: SAR not ready to receive command,1: SAR ready to receive command" newline hexmask.long.byte 0x0 12.--15. 1. "CLK_DIV,Clock Divider" bitfld.long 0x0 10.--11. "DFD,Digital Filter Depth" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CMET,Central Module Enable Time" "0,1,2,3" hexmask.long.byte 0x0 0.--6. 1. "DAC_OFFSET,DAC Offset" repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xF10)++0x3 line.long 0x0 "TTRCR[$1],Temperature Range Control index" bitfld.long 0x0 31. "V,Calibration Point is Valid" "0: Not valid,1: Valid" hexmask.long.word 0x0 0.--8. 1. "TEMP,Temperature in Kelvin for the Calibration Point" repeat.end tree.end tree "UMCTL2_MP" base ad:0x403C03F8 rgroup.long 0x4++0x3 line.long 0x0 "PSTAT,Port Status" bitfld.long 0x0 18. "wr_port_busy_2,Indicates if there are outstanding writes for AXI port 2. Programming Mode: Dynamic" "0,1" bitfld.long 0x0 17. "wr_port_busy_1,Indicates if there are outstanding writes for AXI port 1. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "wr_port_busy_0,Indicates if there are outstanding writes for AXI port 0. Programming Mode: Dynamic" "0,1" bitfld.long 0x0 2. "rd_port_busy_2,Indicates if there are outstanding reads for AXI port 2. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "rd_port_busy_1,Indicates if there are outstanding reads for AXI port 1. Programming Mode: Dynamic" "0,1" bitfld.long 0x0 0. "rd_port_busy_0,Indicates if there are outstanding reads for AXI port 0. Programming Mode: Dynamic" "0,1" group.long 0x8++0xB line.long 0x0 "PCCFG,Port Common Configuration" bitfld.long 0x0 8. "bl_exp_mode,Burst expansion mode" "0: Full BL,1: Half BL" bitfld.long 0x0 4. "pagematch_limit,Page match four limit" "0: No limit,1: Limit of four" newline bitfld.long 0x0 0. "go2critical_en,Go to critical enable" "0: Disable,1: Enable" line.long 0x4 "PCFGR_0,Port n Configuration Read" bitfld.long 0x4 16. "rdwr_ordered_en,Ordered read/writes enable" "0: Disable,1: Enable" bitfld.long 0x4 14. "rd_port_pagematch_en,Read Page Match enable" "0: Disable,1: Enable" newline bitfld.long 0x4 13. "rd_port_urgent_en,Read AXI urgent sideband enable" "0: Disable,1: Enable" bitfld.long 0x4 12. "rd_port_aging_en,Read aging enable" "0: Disable,1: Enable" newline hexmask.long.word 0x4 0.--9. 1. "rd_port_priority,Read aging counter value" line.long 0x8 "PCFGW_0,Port n Configuration Write" bitfld.long 0x8 14. "wr_port_pagematch_en,Write Page Match enable" "0: Disable,1: Enable" bitfld.long 0x8 13. "wr_port_urgent_en,Write AXI urgent sideband enable" "0: Disable,1: Enable" newline bitfld.long 0x8 12. "wr_port_aging_en,Write aging enable" "0: Disable,1: Enable" hexmask.long.word 0x8 0.--9. 1. "wr_port_priority,Write aging counter value" group.long 0x98++0x13 line.long 0x0 "PCTRL_0,Port n Control" bitfld.long 0x0 0. "port_en,Enables AXI port n. Programming Mode: Dynamic" "0,1" line.long 0x4 "PCFGQOS0_0,Port n Read QoS Configuration Register 0" bitfld.long 0x4 24.--25. "rqos_map_region2,Region 2 traffic class" "0: Invalid,1: VPR,2: HPR (not value for dual-address-queue..,3: Invalid" bitfld.long 0x4 20.--21. "rqos_map_region1,Region 1 traffic class" "0: LPR,1: VPR,2: HPR (not valid for dual-address-queue..,3: Invalid" newline bitfld.long 0x4 16.--17. "rqos_map_region0,Read region 0 traffic class" "0: LPR,1: VPR,2: HPR (not valid for dual-address-queue..,3: Invalid" hexmask.long.byte 0x4 8.--11. 1. "rqos_map_level2,Read separation level 2" newline hexmask.long.byte 0x4 0.--3. 1. "rqos_map_level1,Read separation level 1" line.long 0x8 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x8 16.--26. 1. "rqos_map_timeoutr,Read red address queue timeout interval" hexmask.long.word 0x8 0.--10. 1. "rqos_map_timeoutb,Read blue address queue timeout interval" line.long 0xC "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0xC 24.--25. "wqos_map_region2,Write region 2 traffic class" "0: LPR,1: VPR,2: Invalid,3: Invalid" bitfld.long 0xC 20.--21. "wqos_map_region1,Write region 1 traffic class" "0: LPR,1: VPR,2: Invalid,3: Invalid" newline bitfld.long 0xC 16.--17. "wqos_map_region0,Write region 0 traffic class" "0: LPR,1: VPR,2: Invalid,3: Invalid" hexmask.long.byte 0xC 8.--11. 1. "wqos_map_level2,Write separation level 2" newline hexmask.long.byte 0xC 0.--3. 1. "wqos_map_level1,Write separation level 1" line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 16.--26. 1. "wqos_map_timeout2,Write region 2 timeout interval" hexmask.long.word 0x10 0.--10. 1. "wqos_map_timeout1,Write region 0 and 1 timeout interval" group.long 0xBC++0x7 line.long 0x0 "PCFGR_1,Port n Configuration Read" bitfld.long 0x0 16. "rdwr_ordered_en,Enable ordered read/writes. If set to 1 preserves the ordering between read transaction and write transaction issued to the same address on a given port. In other words the controller ensures that all same address read and write.." "0,1" bitfld.long 0x0 14. "rd_port_pagematch_en,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also.." "0,1" newline bitfld.long 0x0 13. "rd_port_urgent_en,If set to 1 enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to MC is asserted if.." "0,1" bitfld.long 0x0 12. "rd_port_aging_en,If set to 1 enables aging function for the read channel of the port. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 0.--9. 1. "rd_port_priority,Determines the initial load value of read aging counters. These counters will be parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but.." line.long 0x4 "PCFGW_1,Port n Configuration Write" bitfld.long 0x4 14. "wr_port_pagematch_en,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also.." "0,1" bitfld.long 0x4 13. "wr_port_urgent_en,If set to 1 enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_wr signal to the MC is asserted if enabled in.." "0,1" newline bitfld.long 0x4 12. "wr_port_aging_en,If set to 1 enables aging function for the write channel of the port. Programming Mode: Static" "0,1" hexmask.long.word 0x4 0.--9. 1. "wr_port_priority,Determines the initial load value of write aging counters. These counters will be parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting.." group.long 0x148++0x13 line.long 0x0 "PCTRL_1,Port n Control" bitfld.long 0x0 0. "port_en,Enables AXI port n. Programming Mode: Dynamic" "0,1" line.long 0x4 "PCFGQOS0_1,Port n Read QoS Configuration Register 0" bitfld.long 0x4 24.--25. "rqos_map_region2,This bitfield indicates the traffic class of region2. For dual address queue configurations region2 maps to the red address queue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic.." "?,1: VPR and,2: HPR only,?" bitfld.long 0x4 20.--21. "rqos_map_region1,This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR 1: VPR 2: HPR. For dual address queue configurations region1 maps to the blue address queue. In this case valid values are 0: LPR and 1: VPR only. When.." "0: LPR and,1: VPR only,2: HPR,?" newline bitfld.long 0x4 16.--17. "rqos_map_region0,This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR 1: VPR 2: HPR. For dual address queue configurations region 0 maps to the blue address queue. In this case valid values are: 0: LPR and 1: VPR only. When.." "0: LPR and,1: VPR only,2: HPR,?" hexmask.long.byte 0x4 8.--11. 1. "rqos_map_level2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA arqos.." newline hexmask.long.byte 0x4 0.--3. 1. "rqos_map_level1,Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA arqos values are used directly.." line.long 0x8 "PCFGQOS1_1,Port n Read QoS Configuration Register 1" hexmask.long.word 0x8 16.--26. 1. "rqos_map_timeoutr,Specifies the timeout value for transactions mapped to the red address queue. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x8 0.--10. 1. "rqos_map_timeoutb,Specifies the timeout value for transactions mapped to the blue address queue. Programming Mode: Quasi-dynamic Group 3" line.long 0xC "PCFGWQOS0_1,Port n Write QoS Configuration Register 0" bitfld.long 0xC 24.--25. "wqos_map_region2,This bitfield indicates the traffic class of region 2. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 2 is set to 1 (VPW) VPW traffic is aliased to NPW traffic. Programming.." "0: NPW,1: VPW,?,?" bitfld.long 0xC 20.--21. "wqos_map_region1,This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) VPW traffic is aliased to NPW traffic. Programming.." "0: NPW,1: VPW,?,?" newline bitfld.long 0xC 16.--17. "wqos_map_region0,This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 0 is set to 1 (VPW) VPW traffic is aliased to NPW traffic. Programming.." "0: NPW,1: VPW,?,?" hexmask.long.byte 0xC 8.--11. 1. "wqos_map_level2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. Region2 starts from (level2 + 1) up to 15. Note that for PA awqos.." newline hexmask.long.byte 0xC 0.--3. 1. "wqos_map_level1,Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. Note that for PA awqos values are used directly as port priorities where the higher the.." line.long 0x10 "PCFGWQOS1_1,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 16.--26. 1. "wqos_map_timeout2,Specifies the timeout value for write transactions in region 2. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x10 0.--10. 1. "wqos_map_timeout1,Specifies the timeout value for write transactions in region 0 and 1. Programming Mode: Quasi-dynamic Group 3" group.long 0x16C++0x7 line.long 0x0 "PCFGR_2,Port n Configuration Read" bitfld.long 0x0 16. "rdwr_ordered_en,Enable ordered read/writes. If set to 1 preserves the ordering between read transaction and write transaction issued to the same address on a given port. In other words the controller ensures that all same address read and write.." "0,1" bitfld.long 0x0 14. "rd_port_pagematch_en,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also.." "0,1" newline bitfld.long 0x0 13. "rd_port_urgent_en,If set to 1 enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to the MC is asserted if.." "0,1" bitfld.long 0x0 12. "rd_port_aging_en,If set to 1 enables aging function for the read channel of the port. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 0.--9. 1. "rd_port_priority,Determines the initial load value of read aging counters. These counters will be parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but.." line.long 0x4 "PCFGW_2,Port n Configuration Write" bitfld.long 0x4 14. "wr_port_pagematch_en,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also.." "0,1" bitfld.long 0x4 13. "wr_port_urgent_en,If set to 1 enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_wr signal to the MC is asserted if enabled in.." "0,1" newline bitfld.long 0x4 12. "wr_port_aging_en,If set to 1 enables aging function for the write channel of the port. Programming Mode: Static" "0,1" hexmask.long.word 0x4 0.--9. 1. "wr_port_priority,Determines the initial load value of write aging counters. These counters will be parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting.." group.long 0x1F8++0x13 line.long 0x0 "PCTRL_2,Port n Control" bitfld.long 0x0 0. "port_en,Enables AXI port n. Programming Mode: Dynamic" "0,1" line.long 0x4 "PCFGQOS0_2,Port n Read QoS Configuration Register 0" bitfld.long 0x4 24.--25. "rqos_map_region2,This bitfield indicates the traffic class of region2. For dual address queue configurations region2 maps to the red address queue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic.." "?,1: VPR and,2: HPR only,?" bitfld.long 0x4 20.--21. "rqos_map_region1,This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR 1: VPR 2: HPR. For dual address queue configurations region1 maps to the blue address queue. In this case valid values are 0: LPR and 1: VPR only. When.." "0: LPR and,1: VPR only,2: HPR,?" newline bitfld.long 0x4 16.--17. "rqos_map_region0,This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR 1: VPR 2: HPR. For dual address queue configurations region 0 maps to the blue address queue. In this case valid values are: 0: LPR and 1: VPR only. When.." "0: LPR and,1: VPR only,2: HPR,?" hexmask.long.byte 0x4 8.--11. 1. "rqos_map_level2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA arqos.." newline hexmask.long.byte 0x4 0.--3. 1. "rqos_map_level1,Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA arqos values are used directly.." line.long 0x8 "PCFGQOS1_2,Port n Read QoS Configuration Register 1" hexmask.long.word 0x8 16.--26. 1. "rqos_map_timeoutr,Specifies the timeout value for transactions mapped to the red address queue. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x8 0.--10. 1. "rqos_map_timeoutb,Specifies the timeout value for transactions mapped to the blue address queue. Programming Mode: Quasi-dynamic Group 3" line.long 0xC "PCFGWQOS0_2,Port n Write QoS Configuration Register 0" bitfld.long 0xC 24.--25. "wqos_map_region2,This bitfield indicates the traffic class of region 2. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 2 is set to 1 (VPW) VPW traffic is aliased to NPW traffic. Programming.." "0: NPW,1: VPW,?,?" bitfld.long 0xC 20.--21. "wqos_map_region1,This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) VPW traffic is aliased to NPW traffic. Programming.." "0: NPW,1: VPW,?,?" newline bitfld.long 0xC 16.--17. "wqos_map_region0,This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 0 is set to 1 (VPW) VPW traffic is aliased to NPW traffic. Programming.." "0: NPW,1: VPW,?,?" hexmask.long.byte 0xC 8.--11. 1. "wqos_map_level2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. Region2 starts from (level2 + 1) up to 15. Note that for PA awqos.." newline hexmask.long.byte 0xC 0.--3. 1. "wqos_map_level1,Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. Note that for PA awqos values are used directly as port priorities where the higher the.." line.long 0x10 "PCFGWQOS1_2,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 16.--26. 1. "wqos_map_timeout2,Specifies the timeout value for write transactions in region 2. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x10 0.--10. 1. "wqos_map_timeout1,Specifies the timeout value for write transactions in region 0 and 1. Programming Mode: Quasi-dynamic Group 3" group.long 0xB2C++0x3 line.long 0x0 "SBRCTL,Scrubber Control" hexmask.long.word 0x0 8.--20. 1. "scrub_interval,Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0 scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full.." bitfld.long 0x0 4.--6. "scrub_burst,Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes both normal operation mode and low-power mode with Inline ECC. During.." "?,1: 8 reads,2: 16 reads,3: 32 reads,?,?,?,?" newline bitfld.long 0x0 2. "scrub_mode,scrub_mode:0 ECC scrubber will perform reads scrub_mode:1 ECC scrubber will perform writes Programming Mode: Dynamic" "0,1" bitfld.long 0x0 1. "scrub_during_lowpower,Continue scrubbing during low power. If set to 1 burst of scrubs will be issued in HW controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by Hardware low power interface. If set to.." "0,1" newline bitfld.long 0x0 0. "scrub_en,Enable ECC scrubber. If set to 1 enables the scrubber to generate background read commands after the memories are initialized. If set to 0 disables the scrubber resets the address generator to 0 and clears the scrubber status. This bitfield.." "0,1" rgroup.long 0xB30++0x3 line.long 0x0 "SBRSTAT,Scrubber Status" bitfld.long 0x0 1. "scrub_done,Scrubber done. Controller sets this bit to 1 after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal scrub.." "0,1" bitfld.long 0x0 0. "scrub_busy,Scrubber busy. Controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. Programming Mode: Dynamic" "0,1" group.long 0xB34++0x3 line.long 0x0 "SBRWDATA0,Scrubber Write Data Pattern0" hexmask.long 0x0 0.--31. 1. "scrub_pattern0,ECC Scrubber write data pattern for data bus[31:0] Programming Mode: Dynamic" tree.end tree "UMCTL2_REGS" base ad:0x403C0000 group.long 0x0++0x3 line.long 0x0 "MSTR,Master" bitfld.long 0x0 30.--31. "device_config,Device configuration" "0: x4 device,1: x8 device,2: x16 device,3: x32 device" newline hexmask.long.byte 0x0 24.--27. 1. "active_ranks,Active ranks" newline hexmask.long.byte 0x0 16.--19. 1. "burst_rdwr,DRAM burst length" newline bitfld.long 0x0 15. "dll_off_mode,Dll-off mode" "0: DLL-on mode,1: DLL-off mode" newline bitfld.long 0x0 12.--13. "data_bus_width,Data bus width" "0: Full DQ bus width,1: Half DQ bus width,2: Half DQ bus width,?" newline bitfld.long 0x0 11. "geardown_mode,Geardown" "0: Normal (1N) mode,1: Geardown (2N) mode" newline bitfld.long 0x0 10. "en_2t_timing_mode,2T timing" "0: 1T timing,1: 2T timing" newline bitfld.long 0x0 9. "burstchop,Burst" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "lpddr4,LPDDR4" "0: Not selected,1: Selected" newline bitfld.long 0x0 4. "ddr4,DDR4" "0: Not selected,1: Selected" newline bitfld.long 0x0 3. "lpddr3,LPDDR3" "0: Not selected,1: Selected" newline bitfld.long 0x0 2. "lpddr2,LPDDR2" "0: Not selected,1: Selected" newline bitfld.long 0x0 0. "ddr3,DDR3" "0: Not selected,1: Selected" rgroup.long 0x4++0x3 line.long 0x0 "STAT,Operating mode status" bitfld.long 0x0 12. "selfref_cam_not_empty,Self refresh with CAMs not empty" "0: DRAM has exited Self Refresh state,1: DRAM is in Self Refresh state but CAMs are not.." newline bitfld.long 0x0 8.--9. "selfref_state,Self refresh state" "0: Not in Self Refresh state,1: In Self Refresh 1 state,2: In Self Refresh Power Down state,3: In Self Refresh 2 state" newline bitfld.long 0x0 4.--5. "selfref_type,Self refresh mode" "0: Not in Self Refresh (except LPDDR4) or Self..,1: In Self Refresh (except LPDDR4) or Self Refresh..,2: In Self Refresh (except LPDDR4) or Self Refresh..,3: In Self Refresh (except LPDDR4) or Self Refresh.." newline bitfld.long 0x0 0.--2. "operating_mode,Operating state" "0: mDDR LPDDR2 LPDDR3 or DDR4: Deep Power Down or..,1: Normal,2: Power Down,3: Self Refresh. LPPD4: Self Refresh Power Down,4: mDDR LPDDR2 LPDDR3 or DDR4: Deep Power Down or..,5: mDDR LPDDR2 LPDDR3 or DDR4: Deep Power Down or..,6: mDDR LPDDR2 LPDDR3 or DDR4: Deep Power Down or..,7: mDDR LPDDR2 LPDDR3 or DDR4: Deep Power Down or.." group.long 0x10++0x7 line.long 0x0 "MRCTRL0,Mode Register read/write control 0" bitfld.long 0x0 31. "mr_wr,Mode Register read/write" "0,1" newline bitfld.long 0x0 30. "pba_mode,Per buffer addressability" "0: PDA,1: PBA" newline hexmask.long.byte 0x0 12.--15. 1. "mr_addr,Mode Register address" newline bitfld.long 0x0 4.--5. "mr_rank,Rank access" "0,1,2,3" newline bitfld.long 0x0 3. "sw_init_int,Software intervention" "0: Not allowed,1: Allowed" newline bitfld.long 0x0 2. "pda_en,Per DRAM addressability" "0: MRS,1: MRS in PDA mode" newline bitfld.long 0x0 1. "mpr_en,Multi-purpose register" "0: MRS,1: WR/RD for MPR" newline bitfld.long 0x0 0. "mr_type,Mode Register operation" "0: Write,1: Read" line.long 0x4 "MRCTRL1,Mode Register Read/Write Control 1" hexmask.long.tbyte 0x4 0.--17. 1. "mr_data,Mode Register write data" rgroup.long 0x18++0x3 line.long 0x0 "MRSTAT,Mode Register Read/Write Status" bitfld.long 0x0 8. "pda_done,PDA operation complete" "0: In progress or not yet started,1: Completed" newline bitfld.long 0x0 0. "mr_wr_busy,MR busy" "0: Not busy,1: Busy" group.long 0x1C++0xB line.long 0x0 "MRCTRL2,Mode Register Read/Write Control 2" hexmask.long 0x0 0.--31. 1. "mr_device_sel,MRS device select" line.long 0x4 "DERATEEN,Temperature derate enable" bitfld.long 0x4 8.--10. "rc_derate_value,tRC derate value" "0: Derating uses +1,1: Derating uses +2,2: Derating uses +3,3: Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x4 4.--7. 1. "derate_byte,Derate byte" newline bitfld.long 0x4 1.--2. "derate_value,Derate value" "0: Derating uses +1,1: Derating uses +2,?,?" newline bitfld.long 0x4 0. "derate_enable,Derate enable" "0: Disable,1: Enable" line.long 0x8 "DERATEINT,Temperature derate interval" hexmask.long 0x8 0.--31. 1. "mr4_read_interval,MR4 read interval" group.long 0x2C++0xF line.long 0x0 "DERATECTL,Temperature derate control" bitfld.long 0x0 2. "derate_temp_limit_intr_force,Temperature derate limit interrupt clear" "0,1" newline bitfld.long 0x0 1. "derate_temp_limit_intr_clr,Temperature derate limit interrupt clear" "0,1" newline bitfld.long 0x0 0. "derate_temp_limit_intr_en,Temperature derate limit interrupt enable" "0: Disable,1: Enable" line.long 0x4 "PWRCTL,Low power control" bitfld.long 0x4 8. "lpddr4_sr_allowed,LPDDR4 SRPD-SR transition" "0: Prohibit transition,1: Allow transition" newline bitfld.long 0x4 7. "dis_cam_drain_selfref,Skip CAM draining" "0: CAMs must be drained,1: CAMs do not have to be drained (unsupported)" newline bitfld.long 0x4 6. "stay_in_selfref,Stay in self refresh" "0: Allow transition,1: Prohibit transition" newline bitfld.long 0x4 5. "selfref_sw,Software self refresh" "0: Exit,1: Entry" newline bitfld.long 0x4 4. "mpsm_en,Maximum power saving mode enable" "0: Disable,1: Enable" newline bitfld.long 0x4 3. "en_dfi_dram_clk_disable,Enable DFI DRAM clock disable" "0: Disable,1: Enable" newline bitfld.long 0x4 2. "deeppowerdown_en,Deep power down enable" "0,1" newline bitfld.long 0x4 1. "powerdown_en,Power down enable" "0: Disable,1: Enable" newline bitfld.long 0x4 0. "selfref_en,Self-refresh enable" "0: Disable,1: Enable" line.long 0x8 "PWRTMG,Low Power Timing" hexmask.long.byte 0x8 16.--23. 1. "selfref_to_x32,Self-refresh idle period" newline hexmask.long.byte 0x8 8.--15. 1. "t_dpd_x4096,Minimum deep power down period" newline hexmask.long.byte 0x8 0.--4. 1. "powerdown_to_x32,Power down idle period" line.long 0xC "HWLPCTL,Hardware low power control" hexmask.long.word 0xC 16.--27. 1. "hw_lp_idle_x32,Hardware low power idle period" newline bitfld.long 0xC 1. "hw_lp_exit_idle_en,Hardware low power exit enable" "0,1" newline bitfld.long 0xC 0. "hw_lp_en,Hardware low power interface enable" "0: Disable,1: Enable" group.long 0x50++0x7 line.long 0x0 "RFSHCTL0,Refresh Control 0" hexmask.long.byte 0x0 20.--23. 1. "refresh_margin,Refresh margin" newline hexmask.long.byte 0x0 12.--16. 1. "refresh_to_x1_x32,Speculative refresh period" newline hexmask.long.byte 0x0 4.--9. 1. "refresh_burst,Burst refresh" newline bitfld.long 0x0 2. "per_bank_refresh,Per-bank refresh enable" "0: All-bank refresh,1: Per bank refresh" line.long 0x4 "RFSHCTL1,Refresh control 1" hexmask.long.word 0x4 16.--27. 1. "refresh_timer1_start_value_x32,Refresh timer start rank 1" newline hexmask.long.word 0x4 0.--11. 1. "refresh_timer0_start_value_x32,Refresh timer start rank 0" group.long 0x60++0xB line.long 0x0 "RFSHCTL3,Refresh Control 3" bitfld.long 0x0 4.--6. "refresh_mode,Fine granularity refresh mode" "0: Fixed 1x (normal mode),1: Fixed 2x,2: Fixed 4x,?,?,?,?,?" newline bitfld.long 0x0 1. "refresh_update_level,Refresh update level" "0,1" newline bitfld.long 0x0 0. "dis_auto_refresh,Auto refresh disable" "0: Enable,1: Disable" line.long 0x4 "RFSHTMG,Refresh Timing" bitfld.long 0x4 31. "t_rfc_nom_x1_sel,Refresh units" "0,1" newline hexmask.long.word 0x4 16.--27. 1. "t_rfc_nom_x1_x32,Average refresh interval per rank" newline bitfld.long 0x4 15. "lpddr3_trefbw_en,Burst refresh window parameter enable" "0: tREFBW not used,1: tREFBW used" newline hexmask.long.word 0x4 0.--9. 1. "t_rfc_min,Refresh cycle time minimum" line.long 0x8 "RFSHTMG1,Refresh timing 1" hexmask.long.byte 0x8 16.--23. 1. "t_pbr2pbr,Per-bank refresh to per-bank refresh different bank time" group.long 0x70++0x7 line.long 0x0 "ECCCFG0,ECC Configuration 0" bitfld.long 0x0 30.--31. "ecc_region_map_granu,Selectable protected region granularity" "0: 1/8 of memory space,1: 1/16 of memory space,2: 1/32 of memory space,3: 1/64 of memory space" newline bitfld.long 0x0 24.--26. "ecc_ap_err_threshold,Address parity error threshold" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--21. 1. "blk_channel_idle_time_x32,Block channel idle time" newline hexmask.long.byte 0x0 8.--14. 1. "ecc_region_map,Selectable protected region map" newline bitfld.long 0x0 6. "ecc_ap_en,Address protection enable" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "dis_scrub,ECC scrubs disable" "0: Enable,1: Disable" newline bitfld.long 0x0 0.--2. "ecc_mode,ECC mode" "0: ECC disabled,?,?,?,4: ECC enabled - SEC/DED over 1 beat,5: ECC enabled - Advanced ECC,?,?" line.long 0x4 "ECCCFG1,ECC Configuration 1" hexmask.long.byte 0x4 8.--11. 1. "active_blk_channel,Active block channels" newline bitfld.long 0x4 7. "blk_channel_active_term,Block channel active terminate enable" "0: Disable (use only for debug purposes),1: Enable (default for normal operation)" newline bitfld.long 0x4 5. "ecc_region_waste_lock,ECC waste region lock" "0: Unlocked,1: Locked" newline bitfld.long 0x4 4. "ecc_region_parity_lock,ECC parity section lock" "0: Unlocked,1: Locked" newline bitfld.long 0x4 1. "data_poison_bit,Data poison bits" "0: Two bits (uncorrectable),1: One bit (correctable)" newline bitfld.long 0x4 0. "data_poison_en,ECC data poisoning enable" "0,1" rgroup.long 0x78++0x3 line.long 0x0 "ECCSTAT,SECDED ECC Status" bitfld.long 0x0 16. "ecc_uncorrected_err,Double-bit error indicator" "0: No error,1: Double-bit error" newline bitfld.long 0x0 8. "ecc_corrected_err,Single-bit error indicator" "0: No error,1: Single-bit error" newline hexmask.long.byte 0x0 0.--6. 1. "ecc_corrected_bit_num,ECC corrected bit number" group.long 0x7C++0x3 line.long 0x0 "ECCCTL,ECC Control" eventfld.long 0x0 18. "ecc_ap_err_intr_force,ECC address protection error interrupt force" "0: No effect,1: Force the interrupt" newline eventfld.long 0x0 17. "ecc_uncorrected_err_intr_force,Uncorrected ECC error interrupt force" "0: No effect,1: Force the interrupt" newline eventfld.long 0x0 16. "ecc_corrected_err_intr_force,Corrected ECC error interrupt force" "0: No effect,1: Force the interrupt" newline bitfld.long 0x0 10. "ecc_ap_err_intr_en,ECC address protection error interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "ecc_uncorrected_err_intr_en,Uncorrected ECC error interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8. "ecc_corrected_err_intr_en,Corrected ECC error interrupt enable" "0: Disable,1: Enable" newline eventfld.long 0x0 4. "ecc_ap_err_intr_clr,Clear ECC address protection error interrupt" "0: No effect,1: Clear the ECC address protection error interrupt" newline eventfld.long 0x0 3. "ecc_uncorr_err_cnt_clr,Clear uncorrected ECC error count" "0: No effect,1: Clear the uncorrected ECC error count" newline eventfld.long 0x0 2. "ecc_corr_err_cnt_clr,Clear corrected ECC error count" "0: No effect,1: Clear the corrected ECC error count" newline eventfld.long 0x0 1. "ecc_uncorrected_err_clr,Clear uncorrected ECC error" "0: No effect,1: Clear the uncorrected ECC error" newline eventfld.long 0x0 0. "ecc_corrected_err_clr,Clear corrected ECC error" "0: No effect,1: Clear the corrected ECC error" rgroup.long 0x80++0x37 line.long 0x0 "ECCERRCNT,ECC Error Counter" hexmask.long.word 0x0 16.--31. 1. "ecc_uncorr_err_cnt,Uncorrectable ECC errors count" newline hexmask.long.word 0x0 0.--15. 1. "ecc_corr_err_cnt,Correctable ECC errors count" line.long 0x4 "ECCCADDR0,ECC Corrected Error Address 0" bitfld.long 0x4 24. "ecc_corr_rank,Rank number" "0,1" newline hexmask.long.tbyte 0x4 0.--17. 1. "ecc_corr_row,Page/row number" line.long 0x8 "ECCCADDR1,ECC Corrected Error Address 1" bitfld.long 0x8 24.--25. "ecc_corr_bg,Bank group" "0,1,2,3" newline bitfld.long 0x8 16.--18. "ecc_corr_bank,Bank number" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--11. 1. "ecc_corr_col,Block number" line.long 0xC "ECCCSYN0,ECC Corrected Syndrome 0" hexmask.long 0xC 0.--31. 1. "ecc_corr_syndromes_31_0,Corrected ECC error data pattern: bits 31-0" line.long 0x10 "ECCCSYN1,ECC Corrected Syndrome 1" hexmask.long 0x10 0.--31. 1. "ecc_corr_syndromes_63_32,Corrected ECC error data pattern: bits 63-31" line.long 0x14 "ECCCSYN2,ECC Corrected Syndrome 2" hexmask.long.byte 0x14 0.--7. 1. "ecc_corr_syndromes_71_64,Corrected ECC error data pattern: ECC byte" line.long 0x18 "ECCBITMASK0,ECC Corrected Data Bit Mask 0" hexmask.long 0x18 0.--31. 1. "ecc_corr_bit_mask_31_0,Corrected data bit mask: bits 31-0" line.long 0x1C "ECCBITMASK1,ECC Corrected Data Bit Mask 1" hexmask.long 0x1C 0.--31. 1. "ecc_corr_bit_mask_63_32,Corrected data bit mask: bits 63-32" line.long 0x20 "ECCBITMASK2,ECC Corrected Data Bit Mask 2" hexmask.long.byte 0x20 0.--7. 1. "ecc_corr_bit_mask_71_64,Corrected data bit mask: ECC byte" line.long 0x24 "ECCUADDR0,ECC Uncorrected Error Address 0" bitfld.long 0x24 24. "ecc_uncorr_rank,Rank number" "0,1" newline hexmask.long.tbyte 0x24 0.--17. 1. "ecc_uncorr_row,Page/row number" line.long 0x28 "ECCUADDR1,ECC Uncorrected Error Address 1" bitfld.long 0x28 24.--25. "ecc_uncorr_bg,Bank group" "0,1,2,3" newline bitfld.long 0x28 16.--18. "ecc_uncorr_bank,Bank number" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x28 0.--11. 1. "ecc_uncorr_col,Block number" line.long 0x2C "ECCUSYN0,ECC Uncorrected Syndrome 0" hexmask.long 0x2C 0.--31. 1. "ecc_uncorr_syndromes_31_0,Uncorrected ECC error data pattern: bits 31-0" line.long 0x30 "ECCUSYN1,ECC Uncorrected Syndrome 1" hexmask.long 0x30 0.--31. 1. "ecc_uncorr_syndromes_63_32,Uncorrected ECC error data pattern: bits 63-31" line.long 0x34 "ECCUSYN2,ECC Uncorrected Syndrome 2" hexmask.long.byte 0x34 0.--7. 1. "ecc_uncorr_syndromes_71_64,Uncorrected ECC error data pattern: ECC byte" group.long 0xD0++0x1F line.long 0x0 "INIT0,DRAM Initialization 0" bitfld.long 0x0 30.--31. "skip_dram_init,Skip DRAM Initialization/Reset State" "0: Run DRAM initialization routine on power-up.,1: Skip DRAM initialization routine on power-up and..,?,3: Skip DRAM initialization routine on power-up and.." newline hexmask.long.word 0x0 16.--25. 1. "post_cke_x1024,Post-CKE Interval" newline hexmask.long.word 0x0 0.--11. 1. "pre_cke_x1024,Pre-CKE Interval" line.long 0x4 "INIT1,DRAM Initialization 1" hexmask.long.word 0x4 16.--24. 1. "dram_rstn_x1024,Reset Signal Assert Interval" newline hexmask.long.byte 0x4 0.--3. 1. "pre_ocd_x32,Pre-OCD Interval" line.long 0x8 "INIT2,DRAM Initialization 2" hexmask.long.byte 0x8 8.--15. 1. "idle_after_reset_x32,Idle time after the reset command tINIT4. Present only in designs configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode program this to JEDEC spec value divided by 2 and round it up to the next.." newline hexmask.long.byte 0x8 0.--3. 1. "min_stable_clock_x1,Time to wait after the first CKE high tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the controller is operating in 1:2 frequency ratio mode program this to.." line.long 0xC "INIT3,DRAM Initialization 3" hexmask.long.word 0xC 16.--31. 1. "mr,Mode Register Value" newline hexmask.long.word 0xC 0.--15. 1. "emr,Extended Mode Register Value" line.long 0x10 "INIT4,DRAM Initialization 4" hexmask.long.word 0x10 16.--31. 1. "emr2,Extended Mode Register 2 Value" newline hexmask.long.word 0x10 0.--15. 1. "emr3,Extended Mode Register 3 Value" line.long 0x14 "INIT5,DRAM Initialization 5" hexmask.long.byte 0x14 16.--23. 1. "dev_zqinit_x32,ZQ initial calibration tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 DRAM clock cycles. DDR4 requires 1024 DRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the.." newline hexmask.long.word 0x14 0.--9. 1. "max_auto_init_x1024,Maximum duration of the auto initialization tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: Multiples of 1024 DFI clock cycles. Programming Mode: Static" line.long 0x18 "INIT6,DRAM Initialization 6" hexmask.long.word 0x18 16.--31. 1. "mr4,Mode Register 4 Value" newline hexmask.long.word 0x18 0.--15. 1. "mr5,Mode Register 5 Value" line.long 0x1C "INIT7,DRAM Initialization 7" hexmask.long.word 0x1C 16.--31. 1. "mr22,Mode Register 22 Value" newline hexmask.long.word 0x1C 0.--15. 1. "mr6,Mode Register 6 Value" group.long 0xF4++0x3 line.long 0x0 "RANKCTL,Rank Control" hexmask.long.byte 0x0 8.--11. 1. "diff_rank_wr_gap,Different rank write gap" newline hexmask.long.byte 0x0 4.--7. 1. "diff_rank_rd_gap,Different rank read gap" newline hexmask.long.byte 0x0 0.--3. 1. "max_rank_rd,Rank Maximum Reads" group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,DRAM Timing 0" hexmask.long.byte 0x0 24.--30. 1. "wr2pre,Write to precharge minimum interval" newline hexmask.long.byte 0x0 16.--21. 1. "t_faw,Four active window (tFAW)" newline hexmask.long.byte 0x0 8.--14. 1. "t_ras_max,Activate to precharge maximum interval" newline hexmask.long.byte 0x0 0.--5. 1. "t_ras_min,Activate to precharge minimum interval" line.long 0x4 "DRAMTMG1,DRAM Timing 1" hexmask.long.byte 0x4 16.--20. 1. "t_xp,tXP" newline hexmask.long.byte 0x4 8.--13. 1. "rd2pre,Read to precharge minimum interval (tRTP)" newline hexmask.long.byte 0x4 0.--6. 1. "t_rc,Same bank activate internal (tRC)" line.long 0x8 "DRAMTMG2,DRAM Timing 2" hexmask.long.byte 0x8 24.--29. 1. "write_latency,Write latency" newline hexmask.long.byte 0x8 16.--21. 1. "read_latency,Read Latency" newline hexmask.long.byte 0x8 8.--13. 1. "rd2wr,Read To Write Minimum Time" newline hexmask.long.byte 0x8 0.--5. 1. "wr2rd,Write To Read Minimum Time" line.long 0xC "DRAMTMG3,DRAM Timing 3" hexmask.long.word 0xC 20.--29. 1. "t_mrw,tMRW" newline hexmask.long.byte 0xC 12.--17. 1. "t_mrd,tMRD" newline hexmask.long.word 0xC 0.--9. 1. "t_mod,tMOD" line.long 0x10 "DRAMTMG4,DRAM Timing 4" hexmask.long.byte 0x10 24.--28. 1. "t_rcd,tRCD - tAL" newline hexmask.long.byte 0x10 16.--19. 1. "t_ccd,tCCD" newline hexmask.long.byte 0x10 8.--11. 1. "t_rrd,tRRD" newline hexmask.long.byte 0x10 0.--4. 1. "t_rp,tRP" line.long 0x14 "DRAMTMG5,DRAM Timing 5" hexmask.long.byte 0x14 24.--27. 1. "t_cksrx,tCKSRX" newline hexmask.long.byte 0x14 16.--19. 1. "t_cksre,tCKSRE" newline hexmask.long.byte 0x14 8.--13. 1. "t_ckesr,tCKESR" newline hexmask.long.byte 0x14 0.--4. 1. "t_cke,tCKE" line.long 0x18 "DRAMTMG6,DRAM Timing 6" hexmask.long.byte 0x18 24.--27. 1. "t_ckdpde,tCKDPDE" newline hexmask.long.byte 0x18 16.--19. 1. "t_ckdpdx,Specifies the time interval in DFI clock cycles to maintain CK as a valid clock before the Deep Power Down Exit (DPDX) command" newline hexmask.long.byte 0x18 0.--3. 1. "t_ckcsx,tCKCSX" line.long 0x1C "DRAMTMG7,DRAM Timing 7" hexmask.long.byte 0x1C 8.--11. 1. "t_ckpde,tCKPDEX" newline hexmask.long.byte 0x1C 0.--3. 1. "t_ckpdx,tCKPDX" line.long 0x20 "DRAMTMG8,DRAM Timing 8" hexmask.long.byte 0x20 24.--30. 1. "t_xs_fast_x32,tXS_FAST: Exit Self Refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the above value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "t_xs_abort_x32,tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the above value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 8.--14. 1. "t_xs_dll_x32,tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the above value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." newline hexmask.long.byte 0x20 0.--6. 1. "t_xs_x32,tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the above value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and DDR4.." line.long 0x24 "DRAMTMG9,DRAM Timing 9" bitfld.long 0x24 30. "ddr4_wr_preamble,DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 Programming Mode: Quasi-dynamic Group 2 Group 4" "0: 1tCK preamble,1: 2tCK preamble Present only with.." newline bitfld.long 0x24 16.--18. "t_ccd_s,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "?,1: 2 frequency ratio mode,?,?,?,?,?,?" newline hexmask.long.byte 0x24 8.--11. 1. "t_rrd_s,tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x24 0.--5. 1. "wr2rd_s,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,DRAM Timing 10" hexmask.long.byte 0x28 16.--20. 1. "t_sync_gear,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "t_cmd_gear,Sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in 1:2 mode .." newline bitfld.long 0x28 2.--3. "t_gear_setup,Geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to (tGEAR_setup/2) and.." "?,1: 2 frequency ratio mode,?,?" newline bitfld.long 0x28 0.--1. "t_gear_hold,Geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to (tGEAR_hold/2) and round.." "?,1: 2 frequency ratio mode,?,?" line.long 0x2C "DRAMTMG11,DRAM Timing 11" hexmask.long.byte 0x2C 24.--30. 1. "post_mpsm_gap_x32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "t_mpx_lh,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "t_mpx_s,tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: DFI clock.." "?,1: 2 frequency ratio mode,?,?" newline hexmask.long.byte 0x2C 0.--4. 1. "t_ckmpe,tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the above equation by 2 and round it up.." line.long 0x30 "DRAMTMG12,DRAM Timing 12" bitfld.long 0x30 16.--17. "t_cmdcke,tCMDCKE" "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "t_mrd_pda,tMRD_PDA" line.long 0x34 "DRAMTMG13,DRAM Timing 13" hexmask.long.byte 0x34 24.--30. 1. "odtloff,tODTLoff" newline hexmask.long.byte 0x34 16.--21. 1. "t_ccd_mw,tCCDMW" newline bitfld.long 0x34 0.--2. "t_ppd,tPPD" "0,1,2,3,4,5,6,7" line.long 0x38 "DRAMTMG14,DRAM Timing 14" hexmask.long.word 0x38 0.--11. 1. "t_xsr,tXSR" line.long 0x3C "DRAMTMG15,DRAM Timing 15" bitfld.long 0x3C 31. "en_dfi_lp_t_stab,- 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline hexmask.long.byte 0x3C 0.--7. 1. "t_stab_x32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM : - when exiting power saving mode if the clock was stopped after re-enabling it the clock must be stable for a time specified by tSTAB - in the case of.." group.long 0x180++0xB line.long 0x0 "ZQCTL0,ZQ Control 0" bitfld.long 0x0 31. "dis_auto_zq,Disable automatic ZQCS|MPC" "0: Enable,1: Disable" newline bitfld.long 0x0 30. "dis_srx_zqcl,Disable ZQCL|MPC on SR|SRPD exit" "0: Enable,1: Disable" newline bitfld.long 0x0 29. "zq_resistor_shared,Shared ZQ resistor" "0: No shared,1: Shared" newline bitfld.long 0x0 28. "dis_mpsmx_zqcl,Disable ZQCL on MPSM exit" "0: Enable,1: Disable" newline hexmask.long.word 0x0 16.--26. 1. "t_zq_long_nop,tZQoper (DDR3 DDR4) | tZQCL (LPDDR2 LPDDR3) | tZQCAL (LPDDR4)" newline hexmask.long.word 0x0 0.--9. 1. "t_zq_short_nop,tZQCS (DDR3 DDR4 LPDDR2 LPDDR3) | tZQLAT (LPDDR4)" line.long 0x4 "ZQCTL1,ZQ Control 1" hexmask.long.word 0x4 20.--29. 1. "t_zq_reset_nop,ZQreset NOP" newline hexmask.long.tbyte 0x4 0.--19. 1. "t_zq_short_interval_x1024,ZQ calibration short interval" line.long 0x8 "ZQCTL2,ZQ Control 2" bitfld.long 0x8 0. "zq_reset,Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete the uMCTL2 automatically clears this bit. It is recommended NOT to set this register bit if in Init in Self-Refresh(except LPDDR4) or.." "0,1" rgroup.long 0x18C++0x3 line.long 0x0 "ZQSTAT,ZQ Status" bitfld.long 0x0 0. "zq_reset_busy,SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the DRAM and the associated NOP.." "0,1" group.long 0x190++0x1B line.long 0x0 "DFITMG0,DFI Timing 0" hexmask.long.byte 0x0 24.--28. 1. "dfi_t_ctrl_delay,DFI control delay" newline bitfld.long 0x0 23. "dfi_rddata_use_dfi_phy_clk,DFI or DFI PHY clock for read control" "0: DFI clock (HDR),1: DFI PHY clock (SDR)" newline hexmask.long.byte 0x0 16.--22. 1. "dfi_t_rddata_en,Time to read data enable" newline bitfld.long 0x0 15. "dfi_wrdata_use_dfi_phy_clk,DFI or DFI PHY clock for write control" "0: DFI clock (HDR),1: DFI PHY clock (SDR)" newline hexmask.long.byte 0x0 8.--13. 1. "dfi_tphy_wrdata,Write data driven" newline hexmask.long.byte 0x0 0.--5. 1. "dfi_tphy_wrlat,Write latency" line.long 0x4 "DFITMG1,DFI Timing 1" hexmask.long.byte 0x4 28.--31. 1. "dfi_t_cmd_lat,Command latency" newline bitfld.long 0x4 24.--25. "dfi_t_parin_lat,Parity in latency" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "dfi_t_wrdata_delay,Write delay" newline hexmask.long.byte 0x4 8.--12. 1. "dfi_t_dram_clk_disable,DRAM clock disable latency" newline hexmask.long.byte 0x4 0.--4. 1. "dfi_t_dram_clk_enable,DRAM clock enable latency" line.long 0x8 "DFILPCFG0,DFI Low Power Configuration 0" hexmask.long.byte 0x8 24.--28. 1. "dfi_tlp_resp,Setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both Power Down Self Refresh Deep Power Down and Maximum Power Saving modes. DFI 2.1 specification onwards recommends using a fixed value of 7 always. Unit: DFI.." newline hexmask.long.byte 0x8 20.--23. 1. "dfi_lp_wakeup_dpd,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 -.." newline bitfld.long 0x8 16. "dfi_lp_en_dpd,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Static" "0,1" newline hexmask.long.byte 0x8 12.--15. 1. "dfi_lp_wakeup_sr,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512.." newline bitfld.long 0x8 8. "dfi_lp_en_sr,Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "dfi_lp_wakeup_pd,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512.." newline bitfld.long 0x8 0. "dfi_lp_en_pd,Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "0,1" line.long 0xC "DFILPCFG1,DFI Low Power Configuration 1" hexmask.long.byte 0xC 4.--7. 1. "dfi_lp_wakeup_mpsm,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles -.." newline bitfld.long 0xC 0. "dfi_lp_en_mpsm,Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 devices. Programming Mode: Static" "0,1" line.long 0x10 "DFIUPD0,DFI Update 0" bitfld.long 0x10 31. "dis_auto_ctrlupd,Disable automatic update request" "0: Enable,1: Disable" newline bitfld.long 0x10 30. "dis_auto_ctrlupd_srx,Disable automatic update request on SRX" "0: Enable,1: Disable" newline bitfld.long 0x10 29. "ctrlupd_pre_srx,Update request on SRX" "0: After,1: After" newline hexmask.long.word 0x10 16.--25. 1. "dfi_t_ctrlup_max,Maximum update request time" newline hexmask.long.word 0x10 0.--9. 1. "dfi_t_ctrlup_min,Update request latency" line.long 0x14 "DFIUPD1,DFI Update 1" hexmask.long.byte 0x14 16.--23. 1. "dfi_t_ctrlupd_interval_min_x1024,Minimum update interval" newline hexmask.long.byte 0x14 0.--7. 1. "dfi_t_ctrlupd_interval_max_x1024,Maximum update interval" line.long 0x18 "DFIUPD2,DFI Update 2" bitfld.long 0x18 31. "dfi_phyupd_en,PHY update acknowledge enable" "0: Disable,1: Enable" group.long 0x1B0++0xB line.long 0x0 "DFIMISC,DFI Miscellaneous Control" hexmask.long.byte 0x0 8.--12. 1. "dfi_frequency,Operating frequency" newline bitfld.long 0x0 6. "dis_dyn_adr_tri,Disable Dynamic Tristating" "0: Enable,1: Disable" newline bitfld.long 0x0 5. "dfi_init_start,PHY init start" "0,1" newline bitfld.long 0x0 2. "dfi_data_cs_polarity,Chip select polarity" "0: Active low,1: Active high" newline bitfld.long 0x0 1. "phy_dbi_mode,DBI mode" "0: MC,1: PHY" newline bitfld.long 0x0 0. "dfi_init_complete_en,PHY initialization complete enable" "0: Disable,1: Enable" line.long 0x4 "DFITMG2,DFI Timing 2" hexmask.long.byte 0x4 8.--14. 1. "dfi_tphy_rdcslat,DFI read to chip select latency" newline hexmask.long.byte 0x4 0.--5. 1. "dfi_tphy_wrcslat,DFI write to chip select latency" line.long 0x8 "DFITMG3,DFI Timing 3" hexmask.long.byte 0x8 0.--4. 1. "dfi_t_geardown_delay,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." rgroup.long 0x1BC++0x3 line.long 0x0 "DFISTAT,DFI Status" bitfld.long 0x0 1. "dfi_lp_ack,Stores the value of the dfi_lp_ack input to the controller. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "dfi_init_complete,The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. Programming.." "0,1" group.long 0x1C0++0x7 line.long 0x0 "DBICTL,DM/DBI Control" bitfld.long 0x0 2. "rd_dbi_en,Read DBI enable" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "wr_dbi_en,Write DBI enable" "0: Disable,1: Enable" newline bitfld.long 0x0 0. "dm_en,Data mask enable" "0: Disable,1: Enable" line.long 0x4 "DFIPHYMSTR,DFI PHY Master" bitfld.long 0x4 0. "dfi_phymstr_en,Enables the PHY Master Interface. Programming Mode: Static" "0: Disable,1: Enable" group.long 0x200++0x2F line.long 0x0 "ADDRMAP0,Address Map 0" hexmask.long.byte 0x0 0.--4. 1. "addrmap_cs_bit0,Rank address bit 0" line.long 0x4 "ADDRMAP1,Address Map 1" hexmask.long.byte 0x4 16.--21. 1. "addrmap_bank_b2,Bank address bit 2" newline hexmask.long.byte 0x4 8.--13. 1. "addrmap_bank_b1,Bank address bit 1" newline hexmask.long.byte 0x4 0.--5. 1. "addrmap_bank_b0,Bank address bit 0" line.long 0x8 "ADDRMAP2,Address Map 2" hexmask.long.byte 0x8 24.--27. 1. "addrmap_col_b5,Column address bit 5" newline hexmask.long.byte 0x8 16.--19. 1. "addrmap_col_b4,Column address bit 4" newline hexmask.long.byte 0x8 8.--12. 1. "addrmap_col_b3,Column address bit 3" newline hexmask.long.byte 0x8 0.--3. 1. "addrmap_col_b2,Column address bit 2" line.long 0xC "ADDRMAP3,Address Map 3" hexmask.long.byte 0xC 24.--28. 1. "addrmap_col_b9,Column address bit 9" newline hexmask.long.byte 0xC 16.--20. 1. "addrmap_col_b8,Column address bit 8" newline hexmask.long.byte 0xC 8.--12. 1. "addrmap_col_b7,Column address bit 7" newline hexmask.long.byte 0xC 0.--4. 1. "addrmap_col_b6,Column address bit 6" line.long 0x10 "ADDRMAP4,Address Map 4" bitfld.long 0x10 31. "col_addr_shift,Column address shift 2" "0: No shift,1: Shift" newline hexmask.long.byte 0x10 8.--12. 1. "addrmap_col_b11,Column address bit 11" newline hexmask.long.byte 0x10 0.--4. 1. "addrmap_col_b10,Column address bit 10" line.long 0x14 "ADDRMAP5,Address Map 5" hexmask.long.byte 0x14 24.--27. 1. "addrmap_row_b11,Row address bit 11" newline hexmask.long.byte 0x14 16.--19. 1. "addrmap_row_b2_10,Row address bits 2 to 10" newline hexmask.long.byte 0x14 8.--11. 1. "addrmap_row_b1,Row address bit 1" newline hexmask.long.byte 0x14 0.--3. 1. "addrmap_row_b0,Row address bit 0" line.long 0x18 "ADDRMAP6,Address Map 6" bitfld.long 0x18 31. "lpddr3_6gb_12gb,Indicates that a 6 GB or 12 GB LPDDR3 DRAM device is being used" "0: No LPDDR3 DRAM. All addresses are valid.,1: 6 GB or 12 GB LPDDR3 DRAM is present. Every.." newline bitfld.long 0x18 29.--30. "lpddr4_6gb_12gb_24gb,LPDDR4 type" "0: No LPDDR4 DRAM. All addresses are valid.,1: 6 GB LPDDR4 DRAM. Every address with row[14:13]..,2: 12 GB LPDDR4 DRAM. Every address with row[15:14]..,3: 24 GB LPDDR4 DRAM. Every address with row[16:15].." newline hexmask.long.byte 0x18 24.--27. 1. "addrmap_row_b15,Row address bit 15" newline hexmask.long.byte 0x18 16.--19. 1. "addrmap_row_b14,Row address bit 14" newline hexmask.long.byte 0x18 8.--11. 1. "addrmap_row_b13,Row address bit 13" newline hexmask.long.byte 0x18 0.--3. 1. "addrmap_row_b12,Row address bit 12" line.long 0x1C "ADDRMAP7,Address Map 7" hexmask.long.byte 0x1C 8.--11. 1. "addrmap_row_b17,Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11 and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x1C 0.--3. 1. "addrmap_row_b16,Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11 and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x20 "ADDRMAP8,Address Map 8" hexmask.long.byte 0x20 8.--13. 1. "addrmap_bg_b1,Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." newline hexmask.long.byte 0x20 0.--5. 1. "addrmap_bg_b0,Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." line.long 0x24 "ADDRMAP9,Address Map 9" hexmask.long.byte 0x24 24.--27. 1. "addrmap_row_b5,Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." newline hexmask.long.byte 0x24 16.--19. 1. "addrmap_row_b4,Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." newline hexmask.long.byte 0x24 8.--11. 1. "addrmap_row_b3,Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register.." newline hexmask.long.byte 0x24 0.--3. 1. "addrmap_row_b2,Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register.." line.long 0x28 "ADDRMAP10,Address Map 10" hexmask.long.byte 0x28 24.--27. 1. "addrmap_row_b9,Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." newline hexmask.long.byte 0x28 16.--19. 1. "addrmap_row_b8,Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." newline hexmask.long.byte 0x28 8.--11. 1. "addrmap_row_b7,Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." newline hexmask.long.byte 0x28 0.--3. 1. "addrmap_row_b6,Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." line.long 0x2C "ADDRMAP11,Address Map 11" hexmask.long.byte 0x2C 0.--3. 1. "addrmap_row_b10,Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." group.long 0x240++0x7 line.long 0x0 "ODTCFG,ODT Configuration" hexmask.long.byte 0x0 24.--27. 1. "wr_odt_hold,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "wr_odt_delay,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL.." newline hexmask.long.byte 0x0 8.--11. 1. "rd_odt_hold,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "rd_odt_delay,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL -.." line.long 0x4 "ODTMAP,ODT/Rank Map" bitfld.long 0x4 12.--13. "rank1_rd_odt,ODTs for read from rank 1" "0: No ODTs during read from rank 1,1: Rank 0 ODT on during read from rank 1,2: Rank 1 ODT on during read from rank 1,3: Both rank 0 and 1 ODTs on during read from rank 1" newline bitfld.long 0x4 8.--9. "rank1_wr_odt,ODTs for write to rank 1" "0: No ODTs during write to rank 1,1: Rank 0 ODT on during write to rank 1,2: Rank 1 ODT on during write to rank 1,3: Both rank 0 and 1 ODTs on during write to rank 1" newline bitfld.long 0x4 4.--5. "rank0_rd_odt,ODTs for read from rank 0" "0: No ODTs during read from rank 0,1: Rank 0 ODT on during read from rank 0,2: Rank 1 ODT on during read from rank 0,3: Both rank 0 and 1 ODTs on during read from rank 0" newline bitfld.long 0x4 0.--1. "rank0_wr_odt,ODTs for write to rank 0" "0: No ODTs during write to rank 0,1: Rank 0 ODT on during write to rank 0,2: Rank 1 ODT on during write to rank 0,3: Both rank 0 and 1 ODTs on during write to rank 0" group.long 0x250++0x7 line.long 0x0 "SCHED,Scheduler Control" hexmask.long.byte 0x0 24.--30. 1. "rdwr_idle_gap,Specifies the time interval in DFI clock cycles for the preferred transaction store to be empty before switching to the alternate transaction store if the alternate store is not empty" newline hexmask.long.byte 0x0 8.--12. 1. "lpr_num_entries,Low-priority transaction store entries" newline bitfld.long 0x0 2. "pageclose,Paging policy" "0,1" newline bitfld.long 0x0 1. "prefer_write,Prefer writes over reads" "0: No preference,1: Prefer writes over reads" newline bitfld.long 0x0 0. "force_low_pri_n,Force low priority" "0: Force low priority,1: Do not force low priority" line.long 0x4 "SCHED1,Scheduler Control 1" hexmask.long.byte 0x4 0.--7. 1. "pageclose_timer,Specifies the time interval in DFI clock cycles that a bank is kept open while there are page hit transactions in the CAM for that bank" group.long 0x25C++0x3 line.long 0x0 "PERFHPR1,High Priority Read CAM 1" hexmask.long.byte 0x0 24.--31. 1. "hpr_xact_run_length,HPR transactions after critical" newline hexmask.long.word 0x0 0.--15. 1. "hpr_max_starve,HPR maximimum starve interval" group.long 0x264++0x3 line.long 0x0 "PERFLPR1,Low Priority Read CAM 1" hexmask.long.byte 0x0 24.--31. 1. "lpr_xact_run_length,LPR transactions after critical" newline hexmask.long.word 0x0 0.--15. 1. "lpr_max_starve,LPR maximimum starve interval" group.long 0x26C++0x3 line.long 0x0 "PERFWR1,Write CAM 1" hexmask.long.byte 0x0 24.--31. 1. "w_xact_run_length,WR transactions after critical" newline hexmask.long.word 0x0 0.--15. 1. "w_max_starve,WR maximimum starve interval" group.long 0x300++0x7 line.long 0x0 "DBG0,Debug 0" bitfld.long 0x0 4. "dis_collision_page_opt,When this is set to '0' auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address read followed by write to same address or write followed by write to same.." "0,1" newline bitfld.long 0x0 0. "dis_wc,When 1 disable write combine. FOR DEBUG ONLY Programming Mode: Static" "0,1" line.long 0x4 "DBG1,Debug 1" bitfld.long 0x4 1. "dis_hif,When 1 uMCTL2 asserts the HIF command signal hif_cmd_stall. uMCTL2 will ignore the hif_cmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x4 0. "dis_dq,When 1 uMCTL2 will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to DRAM as long as this is asserted. This bit may be used to prevent reads or writes.." "0,1" rgroup.long 0x308++0x3 line.long 0x0 "DBGCAM,CAM Debug" bitfld.long 0x0 29. "wr_data_pipeline_empty,This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 28. "rd_data_pipeline_empty,This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 26. "dbg_wr_q_empty,This field is used for debug purposes. When its value is 1 all the write command queues and write data buffers inside the memory controller are empty." "0,1" newline bitfld.long 0x0 25. "dbg_rd_q_empty,This field is used for debug purposes. When its value is 1 all the read command queues and read data buffers inside the memory controller are empty." "0,1" newline bitfld.long 0x0 24. "dbg_stall,Stall FOR DEBUG ONLY Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "dbg_w_q_depth,Write queue depth The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline hexmask.long.byte 0x0 8.--13. 1. "dbg_lpr_q_depth,Low priority read queue depth The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline hexmask.long.byte 0x0 0.--5. 1. "dbg_hpr_q_depth,High priority read queue depth FOR DEBUG ONLY Programming Mode: Dynamic" group.long 0x30C++0x3 line.long 0x0 "DBGCMD,Command Debug" bitfld.long 0x0 5. "ctrlupd,Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1." "0,1" newline bitfld.long 0x0 4. "zq_calib_short,Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the DRAM. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation can be.." "0,1" newline bitfld.long 0x0 1. "rank1_refresh,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" newline bitfld.long 0x0 0. "rank0_refresh,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" rgroup.long 0x310++0x3 line.long 0x0 "DBGSTAT,Status Debug" bitfld.long 0x0 5. "ctrlupd_busy,SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the uMCTL2. It is recommended not.." "0,1" newline bitfld.long 0x0 4. "zq_calib_short_busy,SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the uMCTL2. It.." "0,1" newline bitfld.long 0x0 1. "rank1_refresh_busy,SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is.." "0,1" newline bitfld.long 0x0 0. "rank0_refresh_busy,SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is.." "0,1" rgroup.long 0x318++0x3 line.long 0x0 "DBGCAM1,CAM Debug 1" hexmask.long.byte 0x0 0.--5. 1. "dbg_wrecc_q_depth,Write ECC queue depth FOR DEBUG ONLY Programming Mode: Dynamic" group.long 0x320++0x3 line.long 0x0 "SWCTL,Software Register Programming Control Enable" bitfld.long 0x0 0. "sw_done,Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. Programming Mode: Dynamic" "0,1" rgroup.long 0x324++0x3 line.long 0x0 "SWSTAT,Software Register Programming Control Status" bitfld.long 0x0 0. "sw_done_ack,Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination.." "0,1" group.long 0x330++0x7 line.long 0x0 "OCPARCFG0,On-Chip Parity Configuration 0" eventfld.long 0x0 26. "par_raddr_err_intr_force,Interrupt force bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline eventfld.long 0x0 25. "par_waddr_err_intr_force,Interrupt force bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline eventfld.long 0x0 24. "par_raddr_err_intr_clr,Interrupt clear bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 23. "par_raddr_err_intr_en,Enables interrupt generation if set to 1 for all ports on signal par_raddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline eventfld.long 0x0 22. "par_waddr_err_intr_clr,Interrupt clear bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 21. "par_waddr_err_intr_en,Enables interrupt generation if set to 1 for all ports on signal par_waddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 20. "par_addr_slverr_en,Enables SLVERR generation on read response or write response when address parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline eventfld.long 0x0 15. "par_rdata_err_intr_force,Interrupt force bit for all par_rdata_err_intr_n and par_rdata_in_err_ecc_intr (Inline-ECC only). uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline eventfld.long 0x0 14. "par_rdata_err_intr_clr,Interrupt clear bit for par_rdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 13. "par_rdata_err_intr_en,Enables interrupt generation if set to 1 for all ports on signal par_rdata_err_intr_n upon detection of parity error at the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 12. "par_rdata_slverr_en,Enables SLVERR generation on read response when read data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline eventfld.long 0x0 7. "par_wdata_err_intr_force,Interrupt force bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline eventfld.long 0x0 6. "par_wdata_err_intr_clr,Interrupt clear bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 5. "par_wdata_slverr_en,Enables SLVERR generation on write response when write data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "par_wdata_err_intr_en,Enables write data interrupt generation (par_wdata_err_intr) upon detection of parity error at the AXI or DFI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "oc_parity_type,Parity type: - 0: Even parity - 1: Odd parity Programming Mode: Quasi-dynamic Group 3" "0: Even parity,1: Odd parity Programming Mode: Quasi-dynamic Group 3" newline bitfld.long 0x0 0. "oc_parity_en,Parity enable register. Enables On-Chip parity for all interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "OCPARCFG1,On-Chip Parity Configuration 1" hexmask.long.byte 0x4 8.--11. 1. "par_poison_loc_wr_port,Enables parity poisoning on write data at the AXI interface before the input parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Programming Mode:.." newline hexmask.long.byte 0x4 4.--7. 1. "par_poison_loc_rd_port,Enables parity poisoning on read data at the AXI interface after the parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Error can be injected to one port at.." newline bitfld.long 0x4 3. "par_poison_loc_rd_iecc_type,Selects which parity to poison at the DFI when inline ECC is enabled. If this register is set to 0 parity error is injected on the first read data going through the ECC path; if this register is set to 1 parity error is.." "0,1" newline bitfld.long 0x4 2. "par_poison_loc_rd_dfi,Enables parity poisoning on read data at the DFI interface after the parity generation logic and when MEMC_INLINE_ECC=1 enables poisoning of ECC word after the ECC encoder at the write data interface at the DFI. Programming Mode:.." "0,1" newline bitfld.long 0x4 0. "par_poison_en,Enables on-chip parity poisoning on the data interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x338++0xB line.long 0x0 "OCPARSTAT0,On-Chip Parity Status 0" bitfld.long 0x0 18. "par_raddr_err_intr_2,Read address parity error interrupt for port 2. This interrupt is asserted when an on-chip read address parity error occurred on the corresponding AXI port's read address channel. Programming Mode: Static" "0,1" newline bitfld.long 0x0 17. "par_raddr_err_intr_1,Read address parity error interrupt for port 1. This interrupt is asserted when an on-chip read address parity error occurred on the corresponding AXI port's read address channel. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "par_raddr_err_intr_0,Read address parity error interrupt for port 0. This interrupt is asserted when an on-chip read address parity error occurred on the corresponding AXI port's read address channel. Programming Mode: Static" "0,1" newline bitfld.long 0x0 2. "par_waddr_err_intr_2,Write address parity error interrupt for port 2. This interrupt is asserted when an on-chip write address parity error occurred on the corresponding AXI port's write address channel. Programming Mode: Static" "0,1" newline bitfld.long 0x0 1. "par_waddr_err_intr_1,Write address parity error interrupt for port 1. This interrupt is asserted when an on-chip write address parity error occurred on the corresponding AXI port's write address channel. Programming Mode: Static" "0,1" newline bitfld.long 0x0 0. "par_waddr_err_intr_0,Write address parity error interrupt for port 0. This interrupt is asserted when an on-chip write address parity error occurred on the corresponding AXI port's write address channel. Programming Mode: Static" "0,1" line.long 0x4 "OCPARSTAT1,On-Chip Parity Status 1" bitfld.long 0x4 18. "par_rdata_err_intr_2,Read data parity error interrupt for port 2. This interrupt is asserted when an on-chip read data parity error occurred on the corresponding AXI port's read data channel. Bit 0 corresponds to Port 0 and so on. Cleared by register.." "0,1" newline bitfld.long 0x4 17. "par_rdata_err_intr_1,Read data parity error interrupt for port 1. This interrupt is asserted when an on-chip read data parity error occurred on the corresponding AXI port's read data channel. Bit 0 corresponds to Port 0 and so on. Cleared by register.." "0,1" newline bitfld.long 0x4 16. "par_rdata_err_intr_0,Read data parity error interrupt for port 0. This interrupt is asserted when an on-chip read data parity error occurred on the corresponding AXI port's read data channel. Bit 0 corresponds to Port 0 and so on. Cleared by register.." "0,1" newline bitfld.long 0x4 2. "par_wdata_in_err_intr_2,Write data parity error interrupt on input for port 2. This interrupt is asserted when an on-chip write data parity error occurred on the corresponding AXI port's write data channel. Bit 0 corresponds to Port 0 and so on. Cleared.." "0,1" newline bitfld.long 0x4 1. "par_wdata_in_err_intr_1,Write data parity error interrupt on input for port 1. This interrupt is asserted when an on-chip write data parity error occurred on the corresponding AXI port's write data channel. Bit 0 corresponds to Port 0 and so on. Cleared.." "0,1" newline bitfld.long 0x4 0. "par_wdata_in_err_intr_0,Write data parity error interrupt on input for port 0. This interrupt is asserted when an on-chip write data parity error occurred on the corresponding AXI port's write data channel. Bit 0 corresponds to Port 0 and so on. Cleared.." "0,1" line.long 0x8 "OCPARSTAT2,On-Chip Parity Status 2" bitfld.long 0x8 4. "par_rdata_in_err_ecc_intr,Interrupt on ECC data going into inline ECC decoder. Cleared by par_rdata_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x8 0.--1. "par_wdata_out_err_intr,Write data parity error interrupt on output. Cleared by register par_wdata_err_intr_clr. Programming Mode: Static" "0,1,2,3" group.long 0x36C++0x3 line.long 0x0 "POISONCFG,AXI Poison Configuration" eventfld.long 0x0 24. "rd_poison_intr_clr,Read poison interrupt clear" "0: No effect,1: Clear" newline bitfld.long 0x0 20. "rd_poison_intr_en,Read poison interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x0 16. "rd_poison_slverr_en,Read SLVERR enable" "0: Disable,1: Enable" newline eventfld.long 0x0 8. "wr_poison_intr_clr,Write poison interrupt clear" "0: No effect,1: Clear" newline bitfld.long 0x0 4. "wr_poison_intr_en,Write poison interrupt enable" "0: Disable,1: Enable" newline bitfld.long 0x0 0. "wr_poison_slverr_en,Write SLVERR enable" "0: Disable,1: Enable" rgroup.long 0x370++0x3 line.long 0x0 "POISONSTAT,AXI Poison Status" bitfld.long 0x0 18. "rd_poison_intr_2,Read transaction poisoning error interrupt for port 2. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0.." "0,1" newline bitfld.long 0x0 17. "rd_poison_intr_1,Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0.." "0,1" newline bitfld.long 0x0 16. "rd_poison_intr_0,Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0.." "0,1" newline bitfld.long 0x0 2. "wr_poison_intr_2,Write transaction poisoning error interrupt for port 2. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit.." "0,1" newline bitfld.long 0x0 1. "wr_poison_intr_1,Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit.." "0,1" newline bitfld.long 0x0 0. "wr_poison_intr_0,Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit.." "0,1" rgroup.long 0x388++0x3 line.long 0x0 "ECCAPSTAT,Address protection within ECC Status" bitfld.long 0x0 0. "ecc_ap_err,Indicates the number of ECC errors (correctable/uncorrectable) within one burst exceeded the threshold.(ECCCFG0.ecc_ap_err_threshold) Programming Mode: Dynamic" "0,1" group.long 0x3C0++0x3 line.long 0x0 "REGPARCFG,Register parity configuration" bitfld.long 0x0 8. "reg_par_poison_en,Enable register parity poisoning. Programming Mode: Dynamic Quasi-Dynamic and static registers." "0,1" newline eventfld.long 0x0 3. "reg_par_err_intr_force,Interrupt force bit for reg_par_err_intr setting this register will cause the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing.." "0,1" newline eventfld.long 0x0 2. "reg_par_err_intr_clr,Interupt clear bit for reg_par_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "reg_par_err_intr_en,Enables interrupt generation if set to 1 on signal reg_par_err_intr upon detection of register parity error. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "reg_par_en,Register parity enable register. Programming Mode: Dynamic" "0,1" rgroup.long 0x3C4++0x3 line.long 0x0 "REGPARSTAT,Register parity status" bitfld.long 0x0 0. "reg_par_err_intr,Interrupt asserted when Register Parity error is detected. Cleared by setting REGPARCFG.reg_par_err_intr_clr to 1. Programming Mode: Static" "0,1" group.long 0x3E0++0x3 line.long 0x0 "OCCAPCFG,On-Chip command/Address Protection Configuration" bitfld.long 0x0 27. "occap_arb_raq_poison_en,Enables poisoning for the Read Address Queues (RAQ) inside each XPI. Poisoning inverts all parity bits generated by the parity generator. Error will be flagged as soon as the first RAQ is read. This register is not cleared.." "0,1" newline bitfld.long 0x0 26. "occap_arb_cmp_poison_err_inj,Enable error injection in the poisoning of OCCAP Arbiter logic Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to corrupt.." "0: OCCAPSTAT,1: OCCAPSTAT" newline eventfld.long 0x0 25. "occap_arb_cmp_poison_parallel,Enables full poisoning for compare logic inside XPI. Poisoning inverts all bits of all outputs coming from the duplicated modules before the XOR comparators together. uMCTL2 automatically clears this bit. Programming Mode:.." "0,1" newline eventfld.long 0x0 24. "occap_arb_cmp_poison_seq,Enables poisoning for compare logic inside XPI. Poisoning inverts all bits coming from the duplicated modules before the XOR comparators one output at the time per each comparator. uMCTL2 automatically clears this bit." "0,1" newline eventfld.long 0x0 18. "occap_arb_intr_force,Interrupt force bit for occap_arb_err_intr setting this register will cause the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing.." "0,1" newline eventfld.long 0x0 17. "occap_arb_intr_clr,Interrupt clear bit for occap_arb_err_intr and occap_arb_cmp_poison_complete. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "occap_arb_intr_en,Enables interrupt generation upon detection of OCCAP Arbiter errors. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "occap_en,On Chip Command/Address Path Protection (OCCAP) enable register. Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x3E4++0x3 line.long 0x0 "OCCAPSTAT,On-Chip command/Address Protection Status" bitfld.long 0x0 25. "occap_arb_cmp_poison_parallel_err,Error when occap_arb_cmp_poison_full_en was active due to incorrect no. of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_arb_cmp_poison_full_en. It checks.." "0,1" newline bitfld.long 0x0 24. "occap_arb_cmp_poison_seq_err,Error when occap_arb_cmp_poison_en was active due to incorrect no. of errors being occurring. Internal logic checks that the correct number of errors detected while poisoning one output at the time occurred for.." "0,1" newline bitfld.long 0x0 17. "occap_arb_cmp_poison_complete,OCCAP ARB comparator poisoning complete interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "occap_arb_err_intr,OCCAP Arbiter error interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" group.long 0x3E8++0x3 line.long 0x0 "OCCAPCFG1,On-Chip command/Address Protection Configuration 1" bitfld.long 0x0 26. "occap_ddrc_ctrl_poison_err_inj,Enable error injection in the poisoning of OCCAP MC CTRL logic Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "0: OCCAPSTAT1,1: OCCAPSTAT1" newline eventfld.long 0x0 25. "occap_ddrc_ctrl_poison_parallel,Enables poisoning of OCCAP MC CTRL logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline eventfld.long 0x0 24. "occap_ddrc_ctrl_poison_seq,Enables poisoning of OCCAP MC CTRL logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related signals.." "0,1" newline eventfld.long 0x0 18. "occap_ddrc_ctrl_intr_force,Interrupt force bit for occap_ddrc_ctrl_err_intr setting this register will cause the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt.." "0,1" newline eventfld.long 0x0 17. "occap_ddrc_ctrl_intr_clr,Interrupt clear bit for occap_ddrc_ctrl_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "occap_ddrc_ctrl_intr_en,Enables interrupt generation on signal occap_ddrc_ctrl_err_intr upon detection of OCCAP MC CTRL errors. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 10. "occap_ddrc_data_poison_err_inj,Enable error injection in the poisoning of OCCAP MC DATA logic Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "0: OCCAPSTAT1,1: OCCAPSTAT1" newline eventfld.long 0x0 9. "occap_ddrc_data_poison_parallel,Enables poisoning of OCCAP MC DATA logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of instance[0].." "0,1" newline eventfld.long 0x0 8. "occap_ddrc_data_poison_seq,Enables poisoning of OCCAP MC DATA logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of instance[0] of.." "0,1" newline eventfld.long 0x0 2. "occap_ddrc_data_intr_force,Interrupt force bit for occap_ddrc_data_err_intr setting this register will cause the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt.." "0,1" newline eventfld.long 0x0 1. "occap_ddrc_data_intr_clr,Interrupt clear bit for occap_ddrc_data_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "occap_ddrc_data_intr_en,Enables interrupt generation on signal occap_ddrc_data_err_intr upon detection of OCCAP MC DATA errors. Programming Mode: Dynamic" "0,1" rgroup.long 0x3EC++0x7 line.long 0x0 "OCCAPSTAT1,On-Chip command/Address Protection Status 1" bitfld.long 0x0 25. "occap_ddrc_ctrl_poison_parallel_err,Error when occap_ddrc_ctrl_poison_parallel was active due to incorrect no. of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_parallel. It.." "0,1" newline bitfld.long 0x0 24. "occap_ddrc_ctrl_poison_seq_err,Error when occap_ddrc_ctrl_poison_seq was active due to incorrect no. of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_seq. It checks for.." "0,1" newline bitfld.long 0x0 17. "occap_ddrc_ctrl_poison_complete,OCCAP MC CTRL poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "occap_ddrc_ctrl_err_intr,OCCAP MC CTRL error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 9. "occap_ddrc_data_poison_parallel_err,Error when occap_ddrc_data_poison_parallel was active due to incorrect no. of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_parallel. It.." "0,1" newline bitfld.long 0x0 8. "occap_ddrc_data_poison_seq_err,Error when occap_ddrc_data_poison_seq was active due to incorrect no. of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_seq. It checks for.." "0,1" newline bitfld.long 0x0 1. "occap_ddrc_data_poison_complete,OCCAP MC DATA poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 0. "occap_ddrc_data_err_intr,OCCAP MC DATA error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" line.long 0x4 "DERATESTAT,Temperature Derate Status" bitfld.long 0x4 0. "derate_temp_limit_intr,Derate temperature interrupt indicating LPDDR2/3/4 DRAM temperature operating limit is exceeded. This register field is set to 1 when the value read from MR4[2:0] is 3'b000 or 3'b111. Cleared by register.." "0,1" tree.end tree "UOTG (USB On-The-Go Core Registers)" base ad:0x44064000 rgroup.long 0x0++0x17 line.long 0x0 "ID,Identification" hexmask.long.byte 0x0 21.--24. 1. "REVISION,Revision Number of the Controller Core" newline hexmask.long.byte 0x0 8.--13. 1. "NID,Complement Version of ID" newline hexmask.long.byte 0x0 0.--5. 1. "ID,Configuration Number" line.long 0x4 "HWGENERAL,General Hardware Parameters" bitfld.long 0x4 10.--11. "SM,Serial Interface Mode Capability" "0: No serial engine; always use parallel signaling,1: Serial engine present; always use serial..,2: Software-programmable reset to use parallel..,3: Software-programmable reset to use serial.." newline hexmask.long.byte 0x4 6.--9. 1. "PHYM,Transceiver Type" newline bitfld.long 0x4 4.--5. "PHYW,Data Width of the Transceiver connected to the controller core" "0: 8-bit wide data bus [60 MHz clock from the..,1: 16-bit wide data bus [30 MHZ clock from the..,2: Software-programmable reset to 8-bit width,3: Software-programmable reset to 16-bit width" line.long 0x8 "HWHOST,Host Hardware Parameters" bitfld.long 0x8 1.--3. "NPORT,Number of Ports" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "HC,Host Capable" "0: Host operation mode not supported,1: Host operation mode supported" line.long 0xC "HWDEVICE,Device Hardware Parameters" hexmask.long.byte 0xC 1.--6. 1. "DEVEP,Device Endpoint Number" newline bitfld.long 0xC 0. "DC,Device Capable" "0: Device operation mode not supported,1: Device operation mode supported" line.long 0x10 "HWTXBUF,TX Buffer Hardware Parameters" hexmask.long.byte 0x10 16.--23. 1. "TXCHANADD,TX Channel Address" newline hexmask.long.byte 0x10 8.--15. 1. "TXADD,TX Address" newline hexmask.long.byte 0x10 0.--7. 1. "TXBURST,TX Burst Size" line.long 0x14 "HWRXBUF,RX Buffer Hardware Parameters" hexmask.long.byte 0x14 8.--15. 1. "RXADD,RX Address" newline hexmask.long.byte 0x14 0.--7. 1. "RXBURST,RX Burst size" repeat 2. (list 0x0 0x1)(list ad:0x44064080 ad:0x44064088) tree "GPTIMER[$1]" base $2 group.long ($2)++0x7 line.long 0x0 "GPTIMERLD,General Purpose Timer Load" hexmask.long.tbyte 0x0 0.--23. 1. "GPTLD,General Purpose Timer Load Value" line.long 0x4 "GPTIMERCTRL,General Purpose Timer Controller" bitfld.long 0x4 31. "GPTRUN,General Purpose Timer Run The GPTCNT bits are not affected when setting or clearing this field." "0: Stop counting,1: Run" bitfld.long 0x4 30. "GPTRST,General Purpose Timer Reset" "0: No action,1: Load the counter value from GPT0LD[GPTLD]" bitfld.long 0x4 24. "GPTMODE,General Purpose Timer Mode" "0: One-Shot mode,1: Repeat mode" hexmask.long.tbyte 0x4 0.--23. 1. "GPTCNT,General Purpose Timer Counter" tree.end repeat.end base ad:0x44064000 group.long 0x90++0x3 line.long 0x0 "SBUSCFG,System Bus Configuration" bitfld.long 0x0 6.--8. "BAWR,AMBA Burst Alignment for Writes" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "BARD,AMBA Burst Alignment for Reads" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "AHBBRST,AHB Master Interface Burst Configuration Controls the AHB master transfer type sequence (or priority)" "0: Incremental burst of unspecified length only,1: INCR4 burst then single transfer,2: INCR8 burst INCR4 burst then single transfer,3: INCR16 burst INCR8 burst INCR4 burst then single..,?,5: INCR4 burst then incremental burst of..,6: INCR8 burst INCR4 burst then incremental burst..,7: INCR16 burst INCR8 burst INCR4 burst then.." rgroup.byte 0x100++0x0 line.byte 0x0 "CAPLENGTH,Capability Register Length" hexmask.byte 0x0 0.--7. 1. "CAPLENGTH,This field is used as an offset to be added to the register base to find the beginning of the Operational register" rgroup.word 0x102++0x1 line.word 0x0 "HCIVERSION,Host Controller Interface Version" hexmask.word 0x0 0.--15. 1. "HCIVERSION,Host Controller Interface Version Number For example the value 10h indicates EHCI revision 1.0" rgroup.long 0x104++0x7 line.long 0x0 "HCSPARAMS,Host Controller Structural Parameters" hexmask.long.byte 0x0 24.--27. 1. "N_TT,Number of Transaction Translators" newline hexmask.long.byte 0x0 20.--23. 1. "N_PTT,Number of Ports Per Transaction Translator" newline bitfld.long 0x0 16. "PI,Port Indicators" "0: The ports do not support port indicator control.,1: The port status and control registers include a.." newline hexmask.long.byte 0x0 12.--15. 1. "N_CC,Number of Companion Controllers" newline hexmask.long.byte 0x0 8.--11. 1. "N_PCC,Number of Ports Per Companion Controller Indicates the number of ports supported per internal companion controller" newline bitfld.long 0x0 4. "PPC,Port Power Control Indicates whether the host controller implementation includes port power control" "0: The ports do not have port power switches.,1: The ports have port power switches." newline hexmask.long.byte 0x0 0.--3. 1. "N_PORTS,Number of Downstream Ports" line.long 0x4 "HCCPARAMS,Host Controller Capability Parameters" hexmask.long.byte 0x4 8.--15. 1. "EECP,EHCI Extended Capabilities Pointer Indicates the existence of a capabilities list" newline hexmask.long.byte 0x4 4.--7. 1. "IST,Isochronous Scheduling Threshold Indicates relative to the current position of the executing host controller where you can reliably update the isochronous schedule" newline bitfld.long 0x4 2. "ASP,Asynchronous Schedule Park Capability Supports the park feature for HS QHs in the asynchronous schedule" "0,1" newline bitfld.long 0x4 1. "PFL,Programmable Frame List Flag If you write 0 to this field then the system software must use a frame list length of 1024 elements with this host controller" "0,1" newline bitfld.long 0x4 0. "ADC,64-bit Addressing Capability This field has a fixed value of 0 and 64-bit addressing capability is not supported" "0,1" rgroup.word 0x120++0x1 line.word 0x0 "DCIVERSION,Device Controller Interface Version" hexmask.word 0x0 0.--15. 1. "DCIFVER,Device Controller Interface Version Number For example 01h means rev0.1." rgroup.long 0x124++0x3 line.long 0x0 "DCCPARAMS,Device Controller Capability Parameters" bitfld.long 0x0 8. "HC,Host Capable When the value of this field is 1 this controller is capable of operating as an EHCI compatible USB 2" "0,1" newline bitfld.long 0x0 7. "DC,Device Capable When the value of this field is 1 this controller is capable of operating as a USB 2" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DEN,Device Endpoint Number Indicates the number of endpoints built into the device controller" group.long 0x140++0xF line.long 0x0 "USBCMD,USB Command" hexmask.long.byte 0x0 16.--23. 1. "ITC,Interrupt Threshold Control" newline bitfld.long 0x0 15. "FS1,Frame List Size" "0,1" newline bitfld.long 0x0 14. "ATDTW,Add device transfer descriptor (dTD) TripWire" "0,1" newline bitfld.long 0x0 13. "SUTW,Setup TripWire" "0,1" newline bitfld.long 0x0 11. "ASPE,Asynchronous Schedule Park Mode Enable If HCCPARAMS[ASP] is 0 then this field defaults to 1h and is R/W" "0,1" newline bitfld.long 0x0 8.--9. "ASP,Asynchronous Schedule Park Mode Count" "0,1,2,3" newline bitfld.long 0x0 6. "IAA,Interrupt on Async Advance Doorbell" "0,1" newline bitfld.long 0x0 5. "ASE,Asynchronous Schedule Enable" "0: Do not process the asynchronous schedule,1: Use ASYNCLISTADDR to access the asynchronous.." newline bitfld.long 0x0 4. "PSE,Periodic Schedule Enable" "0: Do not process the periodic schedule,1: Use PERIODICLISTBASE to access the periodic.." newline bitfld.long 0x0 2.--3. "FS0,FS0" "0,1,2,3" newline bitfld.long 0x0 1. "RST,Controller Reset" "0,1" newline bitfld.long 0x0 0. "RS,Run/Stop" "0: Stop,1: Run" line.long 0x4 "USBSTS,USB Status" eventfld.long 0x4 25. "TI1,General Purpose Timer Interrupt 1" "0,1" newline eventfld.long 0x4 24. "TI0,General Purpose Timer Interrupt 0" "0,1" newline eventfld.long 0x4 19. "UPI,USB Host Periodic Interrupt" "0,1" newline eventfld.long 0x4 18. "UAI,USB Host Asynchronous Interrupt" "0,1" newline rbitfld.long 0x4 16. "NAKI,NAK Interrupt" "0,1" newline rbitfld.long 0x4 15. "AS,Asynchronous Schedule Status" "0,1" newline rbitfld.long 0x4 14. "PS,Periodic Schedule Status" "0,1" newline rbitfld.long 0x4 13. "RCL,Reclamation" "0,1" newline rbitfld.long 0x4 12. "HCH,HC Halted" "0,1" newline eventfld.long 0x4 11. "UALTI,ULPI alt_int Interrupt" "0,1" newline eventfld.long 0x4 10. "ULPII,ULPI Interrupt" "0,1" newline eventfld.long 0x4 8. "SLI,DC Suspend" "0,1" newline eventfld.long 0x4 7. "SRI,SOF Received" "0,1" newline eventfld.long 0x4 6. "URI,USB Reset Received" "0,1" newline eventfld.long 0x4 5. "AAI,Interrupt on Async Advance" "0,1" newline eventfld.long 0x4 4. "SEI,System Error" "0,1" newline eventfld.long 0x4 3. "FRI,Frame List Rollover" "0,1" newline eventfld.long 0x4 2. "PCI,Port Change Detect" "0,1" newline eventfld.long 0x4 1. "UEI,USB Error Interrupt" "0,1" newline eventfld.long 0x4 0. "UI,USB Interrupt" "0,1" line.long 0x8 "USBINTR,Interrupt Enable" bitfld.long 0x8 25. "TIE1,General Purpose Timer 1 Interrupt Enable When this field is 1 and USBSTS[TI1] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 24. "TIE0,General Purpose Timer 0 Interrupt Enable When this field is 1 and USBSTS[TI0] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 19. "UPIE,USB Host Periodic Interrupt Enable When this field is 1 and USBSTS[UPI] is 1 the host controller issues an interrupt at the next interrupt threshold" "0,1" newline bitfld.long 0x8 18. "UAIE,USB Host Asynchronous Interrupt Enable When this field is 1 and USBSTS[UAI] is 1 the host controller issues an interrupt at the next interrupt threshold" "0,1" newline bitfld.long 0x8 16. "NAKE,NAK Interrupt Enable When this field is 1 and USBSTS[NAKI] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 10. "ULPIE,ULPI Interrupt Enable When this field is 1 and USBSTS[ULPII] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 8. "SLE,Sleep Interrupt Enable When this field is 1 and USBSTS[SLI] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 7. "SRE,SOF Received Interrupt Enable When this field is 1 and USBSTS[SRI] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 6. "URE,USB Reset Interrupt Enable When this field is 1 and USBSTS[URI] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 5. "AAE,Async Advance Interrupt Enable When this field is 1 and USBSTS[AAI] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 4. "SEE,System Error Interrupt Enable When this field is 1 and USBSTS[SEI] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 3. "FRE,Frame List Rollover Interrupt Enable When this field is 1 and USBSTS[FRI] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 2. "PCE,Port Change Detect Interrupt Enable When this field is 1 and USBSTS[PCI] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 1. "UEE,USB Error Interrupt Enable When this field is 1 and USBSTS[UEI] is 1 the controller issues an interrupt" "0,1" newline bitfld.long 0x8 0. "UE,USB Interrupt Enable When this field is 1 and USBSTS[UI] is 1 the controller issues an interrupt." "0,1" line.long 0xC "FRINDEX,USB Frame Index" hexmask.long.word 0xC 0.--13. 1. "FRINDEX,Frame Index In this field the value increments at the end of each time frame (microframe)" group.long 0x154++0x7 line.long 0x0 "PERIODICLISTBASE_or_DEVICEADDR,Frame List Base Address or Device Address" hexmask.long.byte 0x0 25.--31. 1. "USBADR_or_PERBASE,Device Address (For Device mode) or PERBASE (For Host mode)" newline bitfld.long 0x0 24. "USBADDRA,Device Address Advance (For Device mode) or Reserved (For Host mode)" "0,1" newline hexmask.long.word 0x0 12.--23. 1. "PERBASE,PERBASE (For Host mode) or Reserved (for Device mode)" line.long 0x4 "ASYNCLISTADDR_or_ENDPOINTLISTADDR,Next Asynchronous Address or Endpoint List Address" hexmask.long.tbyte 0x4 11.--31. 1. "EPBASE_or_ASYBASE,Endpoint List Pointer (Low) (for Device mode) or Link Pointer Low (LPL) (for Host mode)" newline hexmask.long.byte 0x4 5.--10. 1. "ASYBASE_or_RESERVED,Link Pointer Low (LPL) (for Host mode) or Reserved (for Device mode)" group.long 0x160++0x7 line.long 0x0 "BURSTSIZE,Programmable Burst Size" hexmask.long.byte 0x0 8.--15. 1. "TXPBURST,Programmable TX Burst Size HWTXBUF[TXBURST] determines the default value" newline hexmask.long.byte 0x0 0.--7. 1. "RXPBURST,Programmable RX Burst Size HWRXBUF[RXBURST] determines the default value" line.long 0x4 "TXFILLTUNING,TX FIFO Fill Tuning" hexmask.long.byte 0x4 16.--21. 1. "TXFIFOTHRES,FIFO Burst Threshold" newline hexmask.long.byte 0x4 8.--12. 1. "TXSCHHEALTH,Scheduler Health Counter" newline hexmask.long.byte 0x4 0.--6. 1. "TXSCHOH,Scheduler Overhead" group.long 0x16C++0x7 line.long 0x0 "IC_USB,IC_USB Enable and Voltage Negotiation" bitfld.long 0x0 3. "IC1,Inter-Chip Transceiver Enable Enables the inter-chip transceiver" "0,1" newline rbitfld.long 0x0 0.--2. "IC_VDD1,Indicates which voltage is being supplied to the peripheral" "0: No voltage,1: 1.0 V,2: 1.2 V,3: 1.5 V,4: 1.8 V,5: 3.0 V,?,?" line.long 0x4 "ULPI_VIEWPORT,ULPI Register Access" bitfld.long 0x4 31. "ULPI_WU,ULPI Wake-Up" "0,1" newline bitfld.long 0x4 30. "ULPI_RUN,ULPI Run" "0,1" newline bitfld.long 0x4 29. "ULPI_RW,ULPI Read/Write" "0: Read,1: Write" newline rbitfld.long 0x4 27. "ULPI_SS,ULPI Sync State" "0: Any other state (that is carkit serial low-power),1: Normal sync state" newline bitfld.long 0x4 24.--26. "ULPI_PORT,ULPI Port Number" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--23. 1. "ULPI_ADDR,ULPI Data Address" newline hexmask.long.byte 0x4 8.--15. 1. "ULPI_DATRD,ULPI Data Read" newline hexmask.long.byte 0x4 0.--7. 1. "ULPI_DATWR,ULPI Data Write" group.long 0x178++0x7 line.long 0x0 "ENDPTNAK,Endpoint NAK" hexmask.long.byte 0x0 16.--21. 1. "EPTN,TX Endpoint NAK" newline hexmask.long.byte 0x0 0.--5. 1. "EPRN,RX Endpoint NAK" line.long 0x4 "ENDPTNAKEN,Endpoint NAK Enable" hexmask.long.byte 0x4 16.--21. 1. "EPTNE,TX Endpoint NAK Enable" newline hexmask.long.byte 0x4 0.--5. 1. "EPRNE,RX Endpoint NAK Enable" rgroup.long 0x180++0x3 line.long 0x0 "CONFIGFLAG,Configure Flag" group.long 0x184++0x3 line.long 0x0 "PORTSC1,Port Status and Control" rbitfld.long 0x0 30.--31. "PTS1,Parallel Transceiver Select" "0,1,2,3" newline rbitfld.long 0x0 29. "STS,Serial Transceiver Select" "0: Parallel interface signals selected,1: Serial interface engine selected" newline bitfld.long 0x0 28. "PTW,Parallel Transceiver Width" "0: Select the 8-bit UTMI interface [60MHz],1: Select the 16-bit UTMI interface [30MHz]" newline rbitfld.long 0x0 26.--27. "PSPD,Port Speed" "0: FS,1: LS,2: HS,3: Undefined" newline bitfld.long 0x0 25. "PTS0,PTS0" "0,1" newline bitfld.long 0x0 24. "PFSC,Port Force FS Connect" "0: Normal operation,1: Forced to FS" newline bitfld.long 0x0 23. "PHCD,PHY Low Power Suspend - Clock Disable" "0: Enable PHY clock,1: Disable PHY clock" newline bitfld.long 0x0 22. "WKOC,Wake on Over-current Enable" "0,1" newline bitfld.long 0x0 21. "WKDS,Wake on Disconnect Enable" "0,1" newline bitfld.long 0x0 20. "WKCN,Wake on Connect Enable" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PTC,Port Test Control" newline bitfld.long 0x0 14.--15. "PIC,Port Indicator Control" "0: Port indicators are off,1: Amber,2: Green,3: Undefined" newline bitfld.long 0x0 13. "PO,Port Owner" "0,1" newline bitfld.long 0x0 12. "PP,Port Power The function of this field depends on the value of HCSPARAMS[PPC]" "0,1" newline rbitfld.long 0x0 10.--11. "LS,Line Status" "0: SE0,1: K-state,2: J-state,3: Undefined" newline rbitfld.long 0x0 9. "HSP,HS Port" "0,1" newline bitfld.long 0x0 8. "PR,Port Reset" "0: Port is not in Reset,1: Port is in Reset" newline bitfld.long 0x0 7. "SUSP,Suspend" "0,1" newline bitfld.long 0x0 6. "FPR,Force Port Resume" "0: No resume (K-state) detected/driven on port,1: Resume detected/driven on port" newline eventfld.long 0x0 5. "OCC,Over-Current Change" "0,1" newline rbitfld.long 0x0 4. "OCA,Over-Current Active" "0: This port does not have an over-current condition,1: This port presently has an over-current condition" newline eventfld.long 0x0 3. "PEC,Port Enable/Disable Change" "0: No change,1: Port enabled/disabled status has changed" newline bitfld.long 0x0 2. "PE,Port Enabled/Disabled" "0: Disabled,1: Enabled" newline eventfld.long 0x0 1. "CSC,Connect Status Change" "0,1" newline rbitfld.long 0x0 0. "CCS,Current Connect Status" "0,1" group.long 0x1A4++0x13 line.long 0x0 "OTGSC,OTG Status Control" bitfld.long 0x0 30. "DPIE,Data Pulse Interrupt Enable" "0,1" newline bitfld.long 0x0 29. "TIMIE,One-Millisecond Timer Interrupt Enable (1MsE)" "0,1" newline bitfld.long 0x0 28. "BSEIE,B Session End Interrupt Enable" "0,1" newline bitfld.long 0x0 27. "BSVIE,B Session Valid Interrupt Enable" "0,1" newline bitfld.long 0x0 26. "ASVIE,A Session Valid Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "AVVIE,A VBus Valid Interrupt Enable" "0,1" newline bitfld.long 0x0 24. "IDIE,USB ID Interrupt Enable" "0,1" newline eventfld.long 0x0 22. "DPIS,Data Pulse Interrupt Status" "0,1" newline eventfld.long 0x0 21. "TIMIS,One-Millisecond Timer Interrupt Status (1MsS)" "0,1" newline eventfld.long 0x0 20. "BSEIS,B Session End Interrupt Status" "0,1" newline eventfld.long 0x0 19. "BSVIS,B Session Valid Interrupt Status" "0,1" newline eventfld.long 0x0 18. "ASVIS,A Session Valid Interrupt Status" "0,1" newline eventfld.long 0x0 17. "AVVIS,A VBus Valid Interrupt Status" "0,1" newline bitfld.long 0x0 16. "IDIS,USB ID Interrupt Status" "0,1" newline rbitfld.long 0x0 14. "DPS,Data Bus Pulsing Status" "0: Data bus pulsing is not being detected on the port,1: Data bus pulsing is being detected on the port" newline rbitfld.long 0x0 13. "TIM_TOG,One-Millisecond Timer Toggle" "0,1" newline rbitfld.long 0x0 12. "BSE,B Session End" "0,1" newline rbitfld.long 0x0 11. "BSV,B Session Valid" "0,1" newline rbitfld.long 0x0 10. "ASV,A Session Valid" "0,1" newline rbitfld.long 0x0 9. "AVV,A VBus Valid" "0,1" newline rbitfld.long 0x0 8. "ID,USB ID" "0: A device,1: B device" newline bitfld.long 0x0 7. "HABA,Hardware Assist B-Disconnect to A-connect." "0: Disabled,1: Enable automatic B-disconnect to A-connect.." newline bitfld.long 0x0 6. "HADP,HADP Hardware Assist Data." "0,1" newline bitfld.long 0x0 5. "IDPU,ID Pullup" "0: Pull-up resistor is off,1: Pull-up resistor is on (default)" newline bitfld.long 0x0 4. "DP,Data Pulsing" "0,1" newline bitfld.long 0x0 3. "OT,OTG Termination" "0,1" newline bitfld.long 0x0 2. "HAAR,Hardware Assist Auto-Reset" "0: Disabled,1: Enable automatic reset after connect on host port" newline bitfld.long 0x0 1. "VC,VBUS Charge" "0,1" newline bitfld.long 0x0 0. "VD,VBUS Discharge" "0,1" line.long 0x4 "USBMODE,USB Device Mode" hexmask.long.byte 0x4 16.--23. 1. "ALP,Auto Low Power" newline bitfld.long 0x4 15. "SRT,Shorten Reset Time" "0,1" newline bitfld.long 0x4 12.--14. "TXHSD,Tx to Tx HS Delay" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "SDIS,Stream Disable Mode" "0,1" newline bitfld.long 0x4 3. "SLOM,Setup Lockout Mode" "0: Setup lockouts on (default),1: Setup lockouts off (DCD requires use of Setup.." newline bitfld.long 0x4 2. "ES,Endian Select" "0: Little Endian,1: Big Endian" newline bitfld.long 0x4 0.--1. "CM,Controller Mode" "0: Idle,?,2: Device Controller,3: Host Controller" line.long 0x8 "ENDPTSETUPSTAT,Endpoint Setup Status" hexmask.long.word 0x8 0.--15. 1. "ENDPTSETUPSTAT,Setup Endpoint Status" line.long 0xC "ENDPTPRIME,Endpoint Initialization" hexmask.long.byte 0xC 16.--21. 1. "PETB,Prime Endpoint Transmit Buffer" newline hexmask.long.byte 0xC 0.--5. 1. "PERB,Prime Endpoint Receive Buffer" line.long 0x10 "ENDPTFLUSH,Endpoint De-Initialize" hexmask.long.byte 0x10 16.--21. 1. "FETB,Flush Endpoint Transmit Buffer" newline hexmask.long.byte 0x10 0.--5. 1. "FERB,Flush Endpoint Receive Buffer" rgroup.long 0x1B8++0x3 line.long 0x0 "ENDPTSTAT,Endpoint Status" hexmask.long.byte 0x0 16.--21. 1. "ETBR,Endpoint Transmit Buffer Ready" newline hexmask.long.byte 0x0 0.--5. 1. "ERBR,Endpoint Receive Buffer Ready" group.long 0x1BC++0x1B line.long 0x0 "ENDPTCOMPLETE,Endpoint Complete" hexmask.long.byte 0x0 16.--21. 1. "ETCE,Endpoint Transmit Complete Event" newline hexmask.long.byte 0x0 0.--5. 1. "ERCE,Endpoint Receive Complete Event" line.long 0x4 "ENDPTCTRL0,Endpoint Control 0" bitfld.long 0x4 23. "TXE,TX Endpoint Enable" "?,1: Enabled (Endpoint 0 is always enabled)" newline bitfld.long 0x4 18.--19. "TXT,TX Endpoint Type" "0: Control,?,?,?" newline bitfld.long 0x4 16. "TXS,TX Endpoint Stall" "0: Endpoint okay,1: Endpoint stalled" newline bitfld.long 0x4 7. "RXE,RX Endpoint Enable" "?,1: Enabled (Endpoint 0 is always enabled)" newline bitfld.long 0x4 2.--3. "RXT,RX Endpoint Type" "0: Control,?,?,?" newline bitfld.long 0x4 0. "RXS,RX Endpoint Stall" "0: Endpoint is okay,1: Endpoint is stalled" line.long 0x8 "ENDPTCTRL1,Endpoint Control" bitfld.long 0x8 23. "TXE,TX Endpoint Enable An endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0x8 22. "TXR,TX Data Toggle Reset" "0,1" newline bitfld.long 0x8 21. "TXI,TX Data Toggle Inhibit Only used for test and must always be written as 0" "0: PID sequencing enabled,1: PID sequencing disabled" newline bitfld.long 0x8 18.--19. "TXT,TX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x8 17. "TXD,TX Endpoint Data Source" "0: 0 Dual Port Memory Buffer/DMA Engine [DEFAULT]..,?" newline bitfld.long 0x8 16. "TXS,TX Endpoint Stall This field is automatically set to 1 upon receipt of a SETUP request if this Endpoint is not configured as a Control Endpoint" "0: Endpoint is okay,1: Endpoint is stalled" newline bitfld.long 0x8 7. "RXE,RX Endpoint Enable An Endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0x8 6. "RXR,RX Data Toggle Reset" "?,1: Reset PID Sequence" newline bitfld.long 0x8 5. "RXI,RX Data Toggle Inhibit" "0: Disabled,1: Enabled" newline bitfld.long 0x8 2.--3. "RXT,RX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,?" newline bitfld.long 0x8 1. "RXD,RX Endpoint Data Sink" "0: Dual Port Memory Buffer/DMA Engine,?" newline bitfld.long 0x8 0. "RXS,RX Endpoint Stall" "0: Endpoint is okay,1: Endpoint is stalled" line.long 0xC "ENDPTCTRL2,Endpoint Control" bitfld.long 0xC 23. "TXE,TX Endpoint Enable An endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0xC 22. "TXR,TX Data Toggle Reset" "0,1" newline bitfld.long 0xC 21. "TXI,TX Data Toggle Inhibit Only used for test and must always be written as 0" "0: PID sequencing enabled,1: PID sequencing disabled" newline bitfld.long 0xC 18.--19. "TXT,TX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0xC 17. "TXD,TX Endpoint Data Source" "0: 0 Dual Port Memory Buffer/DMA Engine [DEFAULT]..,?" newline bitfld.long 0xC 16. "TXS,TX Endpoint Stall This field is automatically set to 1 upon receipt of a SETUP request if this Endpoint is not configured as a Control Endpoint" "0: Endpoint is okay,1: Endpoint is stalled" newline bitfld.long 0xC 7. "RXE,RX Endpoint Enable An Endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0xC 6. "RXR,RX Data Toggle Reset" "?,1: Reset PID Sequence" newline bitfld.long 0xC 5. "RXI,RX Data Toggle Inhibit" "0: Disabled,1: Enabled" newline bitfld.long 0xC 2.--3. "RXT,RX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,?" newline bitfld.long 0xC 1. "RXD,RX Endpoint Data Sink" "0: Dual Port Memory Buffer/DMA Engine,?" newline bitfld.long 0xC 0. "RXS,RX Endpoint Stall" "0: Endpoint is okay,1: Endpoint is stalled" line.long 0x10 "ENDPTCTRL3,Endpoint Control" bitfld.long 0x10 23. "TXE,TX Endpoint Enable An endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0x10 22. "TXR,TX Data Toggle Reset" "0,1" newline bitfld.long 0x10 21. "TXI,TX Data Toggle Inhibit Only used for test and must always be written as 0" "0: PID sequencing enabled,1: PID sequencing disabled" newline bitfld.long 0x10 18.--19. "TXT,TX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x10 17. "TXD,TX Endpoint Data Source" "0: 0 Dual Port Memory Buffer/DMA Engine [DEFAULT]..,?" newline bitfld.long 0x10 16. "TXS,TX Endpoint Stall This field is automatically set to 1 upon receipt of a SETUP request if this Endpoint is not configured as a Control Endpoint" "0: Endpoint is okay,1: Endpoint is stalled" newline bitfld.long 0x10 7. "RXE,RX Endpoint Enable An Endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0x10 6. "RXR,RX Data Toggle Reset" "?,1: Reset PID Sequence" newline bitfld.long 0x10 5. "RXI,RX Data Toggle Inhibit" "0: Disabled,1: Enabled" newline bitfld.long 0x10 2.--3. "RXT,RX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,?" newline bitfld.long 0x10 1. "RXD,RX Endpoint Data Sink" "0: Dual Port Memory Buffer/DMA Engine,?" newline bitfld.long 0x10 0. "RXS,RX Endpoint Stall" "0: Endpoint is okay,1: Endpoint is stalled" line.long 0x14 "ENDPTCTRL4,Endpoint Control" bitfld.long 0x14 23. "TXE,TX Endpoint Enable An endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0x14 22. "TXR,TX Data Toggle Reset" "0,1" newline bitfld.long 0x14 21. "TXI,TX Data Toggle Inhibit Only used for test and must always be written as 0" "0: PID sequencing enabled,1: PID sequencing disabled" newline bitfld.long 0x14 18.--19. "TXT,TX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x14 17. "TXD,TX Endpoint Data Source" "0: 0 Dual Port Memory Buffer/DMA Engine [DEFAULT]..,?" newline bitfld.long 0x14 16. "TXS,TX Endpoint Stall This field is automatically set to 1 upon receipt of a SETUP request if this Endpoint is not configured as a Control Endpoint" "0: Endpoint is okay,1: Endpoint is stalled" newline bitfld.long 0x14 7. "RXE,RX Endpoint Enable An Endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0x14 6. "RXR,RX Data Toggle Reset" "?,1: Reset PID Sequence" newline bitfld.long 0x14 5. "RXI,RX Data Toggle Inhibit" "0: Disabled,1: Enabled" newline bitfld.long 0x14 2.--3. "RXT,RX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,?" newline bitfld.long 0x14 1. "RXD,RX Endpoint Data Sink" "0: Dual Port Memory Buffer/DMA Engine,?" newline bitfld.long 0x14 0. "RXS,RX Endpoint Stall" "0: Endpoint is okay,1: Endpoint is stalled" line.long 0x18 "ENDPTCTRL5,Endpoint Control" bitfld.long 0x18 23. "TXE,TX Endpoint Enable An endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0x18 22. "TXR,TX Data Toggle Reset" "0,1" newline bitfld.long 0x18 21. "TXI,TX Data Toggle Inhibit Only used for test and must always be written as 0" "0: PID sequencing enabled,1: PID sequencing disabled" newline bitfld.long 0x18 18.--19. "TXT,TX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,3: Interrupt" newline bitfld.long 0x18 17. "TXD,TX Endpoint Data Source" "0: 0 Dual Port Memory Buffer/DMA Engine [DEFAULT]..,?" newline bitfld.long 0x18 16. "TXS,TX Endpoint Stall This field is automatically set to 1 upon receipt of a SETUP request if this Endpoint is not configured as a Control Endpoint" "0: Endpoint is okay,1: Endpoint is stalled" newline bitfld.long 0x18 7. "RXE,RX Endpoint Enable An Endpoint must only be enabled after it has been configured." "0: Disabled,1: Enabled" newline bitfld.long 0x18 6. "RXR,RX Data Toggle Reset" "?,1: Reset PID Sequence" newline bitfld.long 0x18 5. "RXI,RX Data Toggle Inhibit" "0: Disabled,1: Enabled" newline bitfld.long 0x18 2.--3. "RXT,RX Endpoint Type" "0: Control,1: Isochronous,2: Bulk,?" newline bitfld.long 0x18 1. "RXD,RX Endpoint Data Sink" "0: Dual Port Memory Buffer/DMA Engine,?" newline bitfld.long 0x18 0. "RXS,RX Endpoint Stall" "0: Endpoint is okay,1: Endpoint is stalled" tree.end tree "UOTGNC (USB On-The-Go nON-Core Registers)" base ad:0x44064200 group.long 0x0++0x3 line.long 0x0 "CR,Control register" bitfld.long 0x0 15. "UCMALLBE,USB Core Master All Byte Enable" "0: No change on line levels.,1: Assert all byte enables." bitfld.long 0x0 11. "WAKEUPEN,User Wake-Up Enable" "0: Disable,1: Enable" bitfld.long 0x0 10. "WAKEUPCTRL,User Wake-Up Control" "0: No wake-up request,1: Wake-up request is received" newline rbitfld.long 0x0 9. "WAKEUPIS,USB Wake-Up Interrupt Status" "0: Wake-up interrupt received,1: Wake-up interrupt is not received" rbitfld.long 0x0 8. "PWRFLTDF,Vbus Power Fault Status" "0,1" bitfld.long 0x0 7. "PWRFLTEN,Enable Vbus Power Fault Detection" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "WAKEUPIC,Clear USB Wake-Up Interrupt" "0,1" bitfld.long 0x0 2. "PWRFLT,Vbus Power Fault Polarity Control" "?,1: Reverse the polarity of Power fault" bitfld.long 0x0 1. "CORE_IE,Enable Interrupt from Core" "0: Disable,1: Enable" newline bitfld.long 0x0 0. "WAKEUP_IE,USB Wake-Up Interrupt Enable" "0: Disable,1: Enable" tree.end tree "USDHC (Ultra Secured Digital Host Controller)" base ad:0x402F0000 group.long 0x0++0xF line.long 0x0 "DS_ADDR,DMA System Address" hexmask.long 0x0 0.--31. 1. "DS_ADDR,System address" line.long 0x4 "BLK_ATT,Block Attributes" hexmask.long.word 0x4 16.--31. 1. "BLKCNT,Blocks count for current transfer" newline hexmask.long.word 0x4 0.--12. 1. "BLKSIZE,Transfer block size" line.long 0x8 "CMD_ARG,Command Argument" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument" line.long 0xC "CMD_XFR_TYP,Command Transfer Type" hexmask.long.byte 0xC 24.--29. 1. "CMDINX,Command index" newline bitfld.long 0xC 22.--23. "CMDTYP,Command type" "0: Normal other commands,1: Suspend CMD52 for writing bus suspend in CCCR,2: Resume CMD52 for writing function select in CCCR,3: Abort CMD12 CMD52 for writing I/O Abort in CCCR" newline bitfld.long 0xC 21. "DPSEL,Data present select" "0: No data present,1: Data present" newline bitfld.long 0xC 20. "CICEN,Command index check enable" "0: Disable command index check,1: Enables command index check" newline bitfld.long 0xC 19. "CCCEN,Command CRC check enable" "0: Disables command CRC check,1: Enables command CRC check" newline bitfld.long 0xC 16.--17. "RSPTYP,Response type select" "0: No response,1: Response length 136,2: Response length 48,3: Response length 48 check busy after response" newline rbitfld.long 0xC 7. "AC23EN,AC23EN" "0: Disable,1: Enable" newline rbitfld.long 0xC 6. "NIBBLE_POS,NIBBLE_POS" "0: Disable,1: Enable" newline rbitfld.long 0xC 5. "MSBSEL,MSBSEL" "0: Disable,1: Enable" newline rbitfld.long 0xC 4. "DTDSEL,DTDSEL" "0: Disable,1: Enable" newline rbitfld.long 0xC 3. "DDR_EN,DDR_EN" "0: Disable,1: Enable" newline rbitfld.long 0xC 2. "AC12EN,AC12EN" "0: Disable,1: Enable" newline rbitfld.long 0xC 1. "BCEN,BCEN" "0: Disable,1: Enable" newline rbitfld.long 0xC 0. "DMAEN,DMAEN" "0: Disable,1: Enable" rgroup.long 0x10++0xF line.long 0x0 "CMD_RSP0,Command Response0" hexmask.long 0x0 0.--31. 1. "CMDRSP0,Command response 0" line.long 0x4 "CMD_RSP1,Command Response1" hexmask.long 0x4 0.--31. 1. "CMDRSP1,Command response 1" line.long 0x8 "CMD_RSP2,Command Response2" hexmask.long 0x8 0.--31. 1. "CMDRSP2,Command response 2" line.long 0xC "CMD_RSP3,Command Response3" hexmask.long 0xC 0.--31. 1. "CMDRSP3,Command response 3" group.long 0x20++0x3 line.long 0x0 "DATA_BUFF_ACC_PORT,Data Buffer Access Port" hexmask.long 0x0 0.--31. 1. "DATCONT,Data content" rgroup.long 0x24++0x3 line.long 0x0 "PRES_STATE,Present State" hexmask.long.byte 0x0 24.--31. 1. "DLSL,DATA[7:0] line signal level" newline bitfld.long 0x0 23. "CLSL,CMD line signal level" "0,1" newline bitfld.long 0x0 19. "WPSPL,Write protect switch pin level" "0: Write protected (WP = 1),1: Write enabled (WP = 0)" newline bitfld.long 0x0 18. "CDPL,Card detect pin level" "0: No card present (CD_B = 1),1: Card present (CD_B = 0)" newline bitfld.long 0x0 16. "CINST,Card inserted" "0: Power on reset or no card,1: Card inserted" newline bitfld.long 0x0 15. "TSCD,Tap select change done" "0: Delay cell select change is not finished.,1: Delay cell select change is finished." newline bitfld.long 0x0 12. "RTR,Re-Tuning Request (only for SD3.0 SDR104 mode and eMMC HS200 mode)" "0: Fixed or well tuned sampling clock,1: Sampling clock needs re-tuning" newline bitfld.long 0x0 11. "BREN,Buffer read enable" "0: Read disable,1: Read enable" newline bitfld.long 0x0 10. "BWEN,Buffer write enable" "0: Write disable,1: Write enable" newline bitfld.long 0x0 9. "RTA,Read transfer active" "0: No valid data,1: Transferring data" newline bitfld.long 0x0 8. "WTA,Write transfer active" "0: No valid data,1: Transferring data" newline bitfld.long 0x0 3. "SDSTB,SD clock stable" "0: Clock is changing frequency and not stable.,1: Clock is stable." newline bitfld.long 0x0 2. "DLA,Data line active" "0: DATA line inactive,1: DATA line active" newline bitfld.long 0x0 1. "CDIHB,Command Inhibit Data (DATA)" "0: Can issue command that uses the DATA line,1: Cannot issue command that uses the DATA line" newline bitfld.long 0x0 0. "CIHB,Command inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command" group.long 0x28++0x23 line.long 0x0 "PROT_CTRL,Protocol Control" bitfld.long 0x0 30. "NON_EXACT_BLK_RD,Non-exact block read" "0: The block read is exact block read. Host driver..,1: The block read is non-exact block read. Host.." newline bitfld.long 0x0 26. "WECRM,Wakeup event enable on SD card removal" "0: Disables wakeup event enable on SD card removal,1: Enables wakeup event enable on SD card removal" newline bitfld.long 0x0 25. "WECINS,Wakeup event enable on SD card insertion" "0: Disable wakeup event enable on SD card insertion,1: Enable wakeup event enable on SD card insertion" newline bitfld.long 0x0 24. "WECINT,Wakeup event enable on card interrupt" "0: Disables wakeup event enable on card interrupt,1: Enables wakeup event enable on card interrupt" newline bitfld.long 0x0 20. "RD_DONE_NO_8CLK,Read performed number 8 clock" "0,1" newline bitfld.long 0x0 19. "IABG,Interrupt at block gap" "0: Disables interrupt at block gap,1: Enables interrupt at block gap" newline bitfld.long 0x0 18. "RWCTL,Read wait control" "0: Disables read wait control and stop SD clock at..,1: Enables read wait control and assert read wait.." newline bitfld.long 0x0 17. "CREQ,Continue request" "0: No effect,1: Restart" newline bitfld.long 0x0 16. "SABGREQ,Stop at block gap request" "0: Transfer,1: Stop" newline bitfld.long 0x0 8.--9. "DMASEL,DMA select" "0: No DMA or simple DMA is selected.,1: ADMA1 is selected.,2: ADMA2 is selected.,?" newline bitfld.long 0x0 7. "CDSS,Card detect signal selection" "0: Card detection level is selected (for normal..,1: Card detection test level is selected (for test.." newline bitfld.long 0x0 6. "CDTL,Card detect test level" "0: Card detect test level is 0 no card inserted,1: Card detect test level is 1 card inserted" newline bitfld.long 0x0 4.--5. "EMODE,Endian mode" "0: Big endian mode,1: Half word big endian mode,2: Little endian mode,?" newline bitfld.long 0x0 3. "D3CD,DATA3 as card detection pin" "0: DATA3 does not monitor card insertion,1: DATA3 as card detection pin" newline bitfld.long 0x0 1.--2. "DTW,Data transfer width" "0: 1-bit mode,1: 4-bit mode,2: 8-bit mode,?" line.long 0x4 "SYS_CTRL,System Control" bitfld.long 0x4 28. "RSTT,Reset tuning" "0,1" newline bitfld.long 0x4 27. "INITA,Initialization active" "0,1" newline bitfld.long 0x4 26. "RSTD,Software reset for data line" "0: No reset,1: Reset" newline bitfld.long 0x4 25. "RSTC,Software reset for CMD line" "0: No reset,1: Reset" newline bitfld.long 0x4 24. "RSTA,Software reset for all" "0: No reset,1: Reset" newline bitfld.long 0x4 23. "IPP_RST_N,Hardware reset" "0,1" newline hexmask.long.byte 0x4 16.--19. 1. "DTOCV,Data timeout counter value" newline hexmask.long.byte 0x4 8.--15. 1. "SDCLKFS,SDCLK frequency select" newline hexmask.long.byte 0x4 4.--7. 1. "DVS,Divisor" line.long 0x8 "INT_STATUS,Interrupt Status" eventfld.long 0x8 28. "DMAE,DMA error" "0: No error,1: Error" newline eventfld.long 0x8 26. "TNE,Tuning error: (only for SD3.0 SDR104 mode and eMMC HS200 mode)" "0,1" newline eventfld.long 0x8 24. "AC12E,Auto CMD12 error" "0: No error,1: Error" newline eventfld.long 0x8 22. "DEBE,Data end bit error" "0: No error,1: Error" newline eventfld.long 0x8 21. "DCE,Data CRC error" "0: No error,1: Error" newline eventfld.long 0x8 20. "DTOE,Data timeout error" "0: No error,1: Time out" newline eventfld.long 0x8 19. "CIE,Command index error" "0: No error,1: Error" newline eventfld.long 0x8 18. "CEBE,Command end bit error" "0: No error,1: End bit error generated" newline eventfld.long 0x8 17. "CCE,Command CRC error" "0: No error,1: CRC error generated" newline eventfld.long 0x8 16. "CTOE,Command timeout error" "0: No error,1: Time out" newline rbitfld.long 0x8 15. "ERR_INT_STATUS,Error Interrupt Status" "0,1" newline eventfld.long 0x8 14. "CQI,Command queuing interrupt" "0,1" newline eventfld.long 0x8 13. "TP,Tuning pass:(only for SD3.0 SDR104 mode and eMMC HS200 mode)" "0,1" newline eventfld.long 0x8 12. "RTE,Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode)" "0: Re-tuning is not required.,1: Re-tuning should be performed." newline eventfld.long 0x8 8. "CINT,Card interrupt" "0: No card interrupt,1: Generate card interrupt" newline eventfld.long 0x8 7. "CRM,Card removal" "0: Card state unstable or inserted,1: Card removed" newline eventfld.long 0x8 6. "CINS,Card insertion" "0: Card state unstable or removed,1: Card inserted" newline eventfld.long 0x8 5. "BRR,Buffer read ready" "0: Not ready to read buffer,1: Ready to read buffer" newline eventfld.long 0x8 4. "BWR,Buffer write ready" "0: Not ready to write buffer,1: Ready to write buffer" newline eventfld.long 0x8 3. "DINT,DMA interrupt" "0: No DMA interrupt,1: DMA interrupt is generated." newline eventfld.long 0x8 2. "BGE,Block gap event" "0: No block gap event,1: Transaction stopped at block gap" newline eventfld.long 0x8 1. "TC,Transfer complete" "0: Transfer does not complete,1: Transfer complete" newline eventfld.long 0x8 0. "CC,Command complete" "0: Command not complete,1: Command complete" line.long 0xC "INT_STATUS_EN,Interrupt Status Enable" bitfld.long 0xC 28. "DMAESEN,DMA error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 26. "TNESEN,Tuning error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 24. "AC12ESEN,Auto CMD12 error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 22. "DEBESEN,Data end bit error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 21. "DCESEN,Data CRC error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 20. "DTOESEN,Data timeout error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 19. "CIESEN,Command index error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 18. "CEBESEN,Command end bit error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 17. "CCESEN,Command CRC error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 16. "CTOESEN,Command timeout error status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 14. "CQISEN,Command queuing status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 13. "TPSEN,Tuning pass status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 12. "RTESEN,Re-tuning event status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 8. "CINTSEN,Card interrupt status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 7. "CRMSEN,Card removal status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 6. "CINSSEN,Card insertion status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 5. "BRRSEN,Buffer read ready status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 4. "BWRSEN,Buffer write ready status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 3. "DINTSEN,DMA interrupt status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 2. "BGESEN,Block gap event status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 1. "TCSEN,Transfer complete status enable" "0: Masked,1: Enabled" newline bitfld.long 0xC 0. "CCSEN,Command complete status enable" "0: Masked,1: Enabled" line.long 0x10 "INT_SIGNAL_EN,Interrupt Signal Enable" bitfld.long 0x10 28. "DMAEIEN,DMA error interrupt enable" "0: Masked,1: Enable" newline bitfld.long 0x10 26. "TNEIEN,Tuning error interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 24. "AC12EIEN,Auto CMD12 error interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 22. "DEBEIEN,Data end bit error interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 21. "DCEIEN,Data CRC error interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 20. "DTOEIEN,Data timeout error interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 19. "CIEIEN,Command index error interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 18. "CEBEIEN,Command end bit error interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 17. "CCEIEN,Command CRC error interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 16. "CTOEIEN,Command timeout error interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 14. "CQIIEN,Command queuing signal enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 13. "TPIEN,Tuning pass interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 12. "RTEIEN,Re-tuning event interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 8. "CINTIEN,Card interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 7. "CRMIEN,Card removal interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 6. "CINSIEN,Card insertion interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 5. "BRRIEN,Buffer read ready interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 4. "BWRIEN,Buffer write ready interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 3. "DINTIEN,DMA interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 2. "BGEIEN,Block gap event interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 1. "TCIEN,Transfer complete interrupt enable" "0: Masked,1: Enabled" newline bitfld.long 0x10 0. "CCIEN,Command complete interrupt enable" "0: Masked,1: Enabled" line.long 0x14 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status" bitfld.long 0x14 23. "SMP_CLK_SEL,Sample clock select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data" newline bitfld.long 0x14 22. "EXECUTE_TUNING,Execute tuning" "0: Tuning procedure is aborted,1: Start tuning procedure" newline rbitfld.long 0x14 7. "CNIBAC12E,Command not issued by Auto CMD12 error" "0: No error,1: Not issued" newline rbitfld.long 0x14 4. "AC12IE,Auto CMD12 / 23 index error" "0: No error,1: Error the CMD index in response is not CMD12/23" newline rbitfld.long 0x14 3. "AC12EBE,Auto CMD12 / 23 end bit error" "0: No error,1: End bit error generated" newline rbitfld.long 0x14 2. "AC12CE,Auto CMD12 / 23 CRC error" "0: No CRC error,1: CRC error met in Auto CMD12/23 response" newline rbitfld.long 0x14 1. "AC12TOE,Auto CMD12 / 23 timeout error" "0: No error,1: Time out" newline rbitfld.long 0x14 0. "AC12NE,Auto CMD12 not executed" "0: Executed,1: Not executed" line.long 0x18 "HOST_CTRL_CAP,Host Controller Capabilities" rbitfld.long 0x18 26. "VS18,Voltage support 1.8 V" "0: 1.8 V not supported,1: 1.8 V supported" newline rbitfld.long 0x18 25. "VS30,Voltage support 3.0 V" "0: 3.0 V not supported,1: 3.0 V supported" newline rbitfld.long 0x18 24. "VS33,Voltage support 3.3 V" "0: 3.3 V not supported,1: 3.3 V supported" newline rbitfld.long 0x18 23. "SRS,Suspend / resume support" "0: Not supported,1: Supported" newline rbitfld.long 0x18 22. "DMAS,DMA support" "0: DMA not supported,1: DMA supported" newline rbitfld.long 0x18 21. "HSS,High speed support" "0: High speed not supported,1: High speed supported" newline rbitfld.long 0x18 20. "ADMAS,ADMA support" "0: Advanced DMA not supported,1: Advanced DMA supported" newline rbitfld.long 0x18 16.--18. "MBL,Max block length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,3: 4096 bytes,?,?,?,?" newline rbitfld.long 0x18 14.--15. "RETUNING_MODE,Retuning Mode" "0: Mode 1,1: Mode 2,2: Mode 3,?" newline bitfld.long 0x18 13. "USE_TUNING_SDR50,Use Tuning for SDR50" "0: SDR50 does not support tuning,1: SDR50 supports tuning" newline hexmask.long.byte 0x18 8.--11. 1. "TIME_COUNT_RETUNING,Time counter for retuning" newline rbitfld.long 0x18 2. "DDR50_SUPPORT,DDR50 support" "0,1" newline rbitfld.long 0x18 1. "SDR104_SUPPORT,SDR104 support" "0,1" newline rbitfld.long 0x18 0. "SDR50_SUPPORT,SDR50 support" "0,1" line.long 0x1C "WTMK_LVL,Watermark Level" hexmask.long.byte 0x1C 16.--23. 1. "WR_WML,Write watermark level" newline hexmask.long.byte 0x1C 0.--7. 1. "RD_WML,Read watermark level" line.long 0x20 "MIX_CTRL,Mixer Control" bitfld.long 0x20 27. "EN_HS400_MODE,Enable enhance HS400 mode" "0,1" newline bitfld.long 0x20 26. "HS400_MODE,Enable HS400 mode" "0,1" newline bitfld.long 0x20 25. "FBCLK_SEL,Feedback clock source selection (Only used for SD3.0 SDR104 mode and eMMC HS200 mode)" "0: Feedback clock comes from the loopback CLK,1: Feedback clock comes from the ipp_card_clk_out" newline bitfld.long 0x20 24. "AUTO_TUNE_EN,Auto tuning enable (Only used for SD3.0 SDR104 mode and eMMC HS200 mode)" "0: Disable auto tuning,1: Enable auto tuning" newline bitfld.long 0x20 23. "SMP_CLK_SEL,Clock selection" "0: Fixed clock is used to sample data / cmd,1: Tuned clock is used to sample data / cmd" newline bitfld.long 0x20 22. "EXE_TUNE,Execute tuning: (Only used for SD3.0 SDR104 mode and eMMC HS200 mode)" "0: Not tuned or tuning completed,1: Execute tuning" newline bitfld.long 0x20 7. "AC23EN,Auto CMD23 enable" "0,1" newline bitfld.long 0x20 6. "NIBBLE_POS,Nibble position indication" "0,1" newline bitfld.long 0x20 5. "MSBSEL,Multi / Single block select" "0: Single block,1: Multiple blocks" newline bitfld.long 0x20 4. "DTDSEL,Data transfer direction select" "0: Write (Host to card),1: Read (Card to host)" newline bitfld.long 0x20 3. "DDR_EN,Dual data rate mode selection" "0,1" newline bitfld.long 0x20 2. "AC12EN,Auto CMD12 enable" "0: Disable,1: Enable" newline bitfld.long 0x20 1. "BCEN,Block count enable" "0: Disable,1: Enable" newline bitfld.long 0x20 0. "DMAEN,DMA enable" "0: Disable,1: Enable" group.long 0x50++0x3 line.long 0x0 "FORCE_EVENT,Force Event" bitfld.long 0x0 31. "FEVTCINT,Force event card interrupt" "0,1" newline bitfld.long 0x0 28. "FEVTDMAE,Force event DMA error" "0,1" newline bitfld.long 0x0 26. "FEVTTNE,Force tuning error" "0,1" newline bitfld.long 0x0 24. "FEVTAC12E,Force event Auto Command 12 error" "0,1" newline bitfld.long 0x0 22. "FEVTDEBE,Force event data end bit error" "0,1" newline bitfld.long 0x0 21. "FEVTDCE,Force event data CRC error" "0,1" newline bitfld.long 0x0 20. "FEVTDTOE,Force event data time out error" "0,1" newline bitfld.long 0x0 19. "FEVTCIE,Force event command index error" "0,1" newline bitfld.long 0x0 18. "FEVTCEBE,Force event command end bit error" "0,1" newline bitfld.long 0x0 17. "FEVTCCE,Force event command CRC error" "0,1" newline bitfld.long 0x0 16. "FEVTCTOE,Force event command time out error" "0,1" newline bitfld.long 0x0 7. "FEVTCNIBAC12E,Force event command not executed by Auto Command 12 error" "0,1" newline bitfld.long 0x0 4. "FEVTAC12IE,Force event Auto Command 12 index error" "0,1" newline bitfld.long 0x0 3. "FEVTAC12EBE,Force event Auto Command 12 end bit error" "0,1" newline bitfld.long 0x0 2. "FEVTAC12CE,Force event auto command 12 CRC error" "0,1" newline bitfld.long 0x0 1. "FEVTAC12TOE,Force event auto command 12 time out error" "0,1" newline bitfld.long 0x0 0. "FEVTAC12NE,Force event auto command 12 not executed" "0,1" rgroup.long 0x54++0x3 line.long 0x0 "ADMA_ERR_STATUS,ADMA Error Status" bitfld.long 0x0 3. "ADMADCE,ADMA descriptor error" "0: No error,1: Error" newline bitfld.long 0x0 2. "ADMALME,ADMA length mismatch error" "0: No error,1: Error" newline bitfld.long 0x0 0.--1. "ADMAES,ADMA error state (when ADMA error is occurred)" "0,1,2,3" group.long 0x58++0x3 line.long 0x0 "ADMA_SYS_ADDR,ADMA System Address" hexmask.long 0x0 2.--31. 1. "ADS_ADDR,ADMA system address" group.long 0x60++0x3 line.long 0x0 "DLL_CTRL,DLL (Delay Line) Control" hexmask.long.byte 0x0 28.--31. 1. "DLL_CTRL_REF_UPDATE_INT,DLL control loop update interval" newline hexmask.long.byte 0x0 20.--27. 1. "DLL_CTRL_SLV_UPDATE_INT,Slave delay line update interval" newline bitfld.long 0x0 16.--18. "DLL_CTRL_SLV_DLY_TARGET1,DLL slave delay target1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 9.--15. 1. "DLL_CTRL_SLV_OVERRIDE_VAL,DLL slave override val" newline bitfld.long 0x0 8. "DLL_CTRL_SLV_OVERRIDE,DLL slave override" "0,1" newline bitfld.long 0x0 7. "DLL_CTRL_GATE_UPDATE,DLL gate update" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DLL_CTRL_SLV_DLY_TARGET0,DLL slave delay target0" newline bitfld.long 0x0 2. "DLL_CTRL_SLV_FORCE_UPD,DLL slave delay line" "0,1" newline bitfld.long 0x0 1. "DLL_CTRL_RESET,DLL reset" "0,1" newline bitfld.long 0x0 0. "DLL_CTRL_ENABLE,DLL and delay chain" "0,1" rgroup.long 0x64++0x3 line.long 0x0 "DLL_STATUS,DLL Status" hexmask.long.byte 0x0 9.--15. 1. "DLL_STS_REF_SEL,Reference delay line select taps" newline hexmask.long.byte 0x0 2.--8. 1. "DLL_STS_SLV_SEL,Slave delay line select status" newline bitfld.long 0x0 1. "DLL_STS_REF_LOCK,Reference DLL lock status" "0,1" newline bitfld.long 0x0 0. "DLL_STS_SLV_LOCK,Slave delay-line lock status" "0,1" group.long 0x68++0x3 line.long 0x0 "CLK_TUNE_CTRL_STATUS,CLK Tuning Control and Status" rbitfld.long 0x0 31. "PRE_ERR,PRE error" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "TAP_SEL_PRE,TAP_SEL_PRE" newline hexmask.long.byte 0x0 20.--23. 1. "TAP_SEL_OUT,Delay cells added on the feedback clock between CLK_PRE and CLK_OUT" newline hexmask.long.byte 0x0 16.--19. 1. "TAP_SEL_POST,Delay cells added on the feedback clock between CLK_OUT and CLK_POST" newline rbitfld.long 0x0 15. "NXT_ERR,NXT error" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "DLY_CELL_SET_PRE,delay cells on the feedback clock between the feedback clock and CLK_PRE" newline hexmask.long.byte 0x0 4.--7. 1. "DLY_CELL_SET_OUT,Delay cells on the feedback clock between CLK_PRE and CLK_OUT" newline hexmask.long.byte 0x0 0.--3. 1. "DLY_CELL_SET_POST,Delay cells on the feedback clock between CLK_OUT and CLK_POST" group.long 0x70++0x3 line.long 0x0 "STROBE_DLL_CTRL,Strobe DLL control" hexmask.long.byte 0x0 28.--31. 1. "STROBE_DLL_CTRL_REF_UPDATE_INT,Strobe DLL control reference update interval" newline hexmask.long.byte 0x0 20.--27. 1. "STROBE_DLL_CTRL_SLV_UPDATE_INT,Strobe DLL control slave update interval" newline hexmask.long.byte 0x0 9.--15. 1. "STROBE_DLL_CTRL_SLV_OVERRIDE_VAL,Strobe DLL control slave Override value" newline bitfld.long 0x0 8. "STROBE_DLL_CTRL_SLV_OVERRIDE,Strobe DLL control slave override" "0,1" newline bitfld.long 0x0 7. "STROBE_DLL_CTRL_GATE_UPDATE,Strobe DLL control gate update" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "STROBE_DLL_CTRL_SLV_DLY_TARGET,Strobe DLL Control Slave Delay Target" newline bitfld.long 0x0 2. "STROBE_DLL_CTRL_SLV_FORCE_UPD,Strobe DLL control slave force updated" "0,1" newline bitfld.long 0x0 1. "STROBE_DLL_CTRL_RESET,Strobe DLL control reset" "0,1" newline bitfld.long 0x0 0. "STROBE_DLL_CTRL_ENABLE,Strobe DLL control enable" "0,1" rgroup.long 0x74++0x3 line.long 0x0 "STROBE_DLL_STATUS,Strobe DLL status" hexmask.long.byte 0x0 9.--15. 1. "STROBE_DLL_STS_REF_SEL,Strobe DLL status reference select" newline hexmask.long.byte 0x0 2.--8. 1. "STROBE_DLL_STS_SLV_SEL,Strobe DLL status slave select" newline bitfld.long 0x0 1. "STROBE_DLL_STS_REF_LOCK,Strobe DLL status reference lock" "0,1" newline bitfld.long 0x0 0. "STROBE_DLL_STS_SLV_LOCK,Strobe DLL status slave lock" "0,1" group.long 0xC0++0xF line.long 0x0 "VEND_SPEC,Vendor Specific Register" bitfld.long 0x0 31. "CMD_BYTE_EN,Register byte access for CMD_XFR_TYP" "0: Disable. MIX_CTRL[7:0] is read/write and..,1: Enable. MIX_CTRL[7:0] is read-only and.." newline bitfld.long 0x0 15. "CRC_CHK_DIS,CRC Check Disable" "0: Check CRC16 for every read data packet and check..,1: Ignore CRC16 check for every read data packet.." newline bitfld.long 0x0 8. "FRC_SDCLK_ON,Force CLK" "0: CLK active or inactive is fully controlled by..,1: Force CLK active" newline bitfld.long 0x0 3. "AC12_WR_CHKBUSY_EN,Check busy enable" "0: Do not check busy after auto CMD12 for write..,1: Check busy after auto CMD12 for write data packet" newline bitfld.long 0x0 1. "VSELECT,Voltage selection" "0: Change the voltage to high voltage range around..,1: Change the voltage to low voltage range around.." line.long 0x4 "MMC_BOOT,eMMC Boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_BLK_CNT,Stop At Block Gap value of automatic mode" newline bitfld.long 0x4 8. "DISABLE_TIME_OUT,Time out" "0: Enable time out,1: Disable time out" newline bitfld.long 0x4 7. "AUTO_SABG_EN,Auto stop at block gap" "0,1" newline bitfld.long 0x4 6. "BOOT_EN,Boot enable" "0: Fast boot disable,1: Fast boot enable" newline bitfld.long 0x4 5. "BOOT_MODE,Boot mode" "0: Normal boot,1: Alternative boot" newline bitfld.long 0x4 4. "BOOT_ACK,BOOT ACK" "0: No ack,1: Ack" newline hexmask.long.byte 0x4 0.--3. 1. "DTOCV_ACK,DTOCV_ACK" line.long 0x8 "VEND_SPEC2,Vendor Specific 2 Register" hexmask.long.word 0x8 16.--31. 1. "FBCLK_TAP_SEL,Enable extra delay on internal feedback clock" newline bitfld.long 0x8 15. "EN_32K_CLK,Enable 32khz clock for card detection" "0,1" newline bitfld.long 0x8 12. "ACMD23_ARGU2_EN,Argument2 register enable for ACMD23" "0: Disable,1: Argument2 register enable for ACMD23 sharing.." newline bitfld.long 0x8 11. "HS400_RD_CLK_STOP_EN,HS400 read clock stop enable" "0,1" newline bitfld.long 0x8 10. "HS400_WR_CLK_STOP_EN,HS400 write clock stop enable" "0,1" newline bitfld.long 0x8 6. "TUNING_CMD_EN,Tuning command enable" "0: Auto tuning circuit does not check the CMD line.,1: Auto tuning circuit checks the CMD line." newline bitfld.long 0x8 5. "TUNING_1bit_EN,Tuning 1bit enable" "0,1" newline bitfld.long 0x8 4. "TUNING_8bit_EN,Tuning 8bit enable" "0,1" newline bitfld.long 0x8 3. "CARD_INT_D3_TEST,Card interrupt detection test" "0: Check the card interrupt only when DATA3 is high.,1: Check the card interrupt by ignoring the status.." line.long 0xC "TUNING_CTRL,Tuning Control" bitfld.long 0xC 24. "STD_TUNING_EN,Standard tuning circuit and procedure enable" "0,1" newline bitfld.long 0xC 20.--22. "TUNING_WINDOW,Data window" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 16.--18. "TUNING_STEP,TUNING_STEP" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--15. 1. "TUNING_COUNTER,Tuning counter" newline bitfld.long 0xC 7. "DIS_CMD_CHK_FOR_STD_TUNING,Disable command check for standard tuning" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "TUNING_START_TAP,Tuning start" rgroup.long 0x100++0x3 line.long 0x0 "CQVER,Command Queuing Version" hexmask.long.byte 0x0 8.--11. 1. "MAJOR_VN,eMMC major version number" newline hexmask.long.byte 0x0 4.--7. 1. "MINOR_VN,eMMC minor version number" newline hexmask.long.byte 0x0 0.--3. 1. "VERSION_SUFFIX,eMMC version suffix" group.long 0x104++0x2B line.long 0x0 "CQCAP,Command Queuing Capabilities" hexmask.long.byte 0x0 12.--15. 1. "ITCFMUL,Internal timer clock frequency multiplier" newline hexmask.long.word 0x0 0.--9. 1. "ITCFVAL,Internal timer clock frequency value" line.long 0x4 "CQCFG,Command Queuing Configuration" bitfld.long 0x4 12. "DCMDE,Direct command (DCMD) enable" "0: Task descriptor in slot #31 is a Data Transfer..,1: Task descriptor in slot #31 is a DCMD Task.." newline bitfld.long 0x4 8. "TDS,Task descriptor size" "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits" newline bitfld.long 0x4 0. "CQUE,Command queuing enable" "0,1" line.long 0x8 "CQCTL,Command Queuing Control" bitfld.long 0x8 8. "CLEAR,Clear all tasks" "0,1" newline bitfld.long 0x8 0. "HALT,Halt" "0,1" line.long 0xC "CQIS,Command Queuing Interrupt Status" eventfld.long 0xC 3. "TCL,Task cleared" "0,1" newline eventfld.long 0xC 2. "RED,Response error detected interrupt" "0,1" newline eventfld.long 0xC 1. "TCC,Task complete interrupt" "0,1" newline eventfld.long 0xC 0. "HAC,Halt complete interrupt" "0,1" line.long 0x10 "CQISTE,Command Queuing Interrupt Status Enable" bitfld.long 0x10 3. "TCL_STE,Task cleared status enable" "0: CQIS[TCL] is disabled,1: CQIS[TCL] is set when its interrupt condition is.." newline bitfld.long 0x10 2. "RED_STE,Response error detected status enable" "0: CQIS[RED]is disabled,1: CQIS[RED] is set when its interrupt condition is.." newline bitfld.long 0x10 1. "TCC_STE,Task complete status enable" "0: CQIS[TCC] is disabled,1: CQIS[TCC] is set when its interrupt condition is.." newline bitfld.long 0x10 0. "HAC_STE,Halt complete status enable" "0: CQIS[HAC] is disabled,1: CQIS[HAC] is set when its interrupt condition is.." line.long 0x14 "CQISGE,Command Queuing Interrupt Signal Enable" bitfld.long 0x14 3. "TCL_SGE,Task cleared signal enable" "0,1" newline bitfld.long 0x14 2. "RED_SGE,Response error detected signal enable" "0,1" newline bitfld.long 0x14 1. "TCC_SGE,Task complete signal enable" "0,1" newline bitfld.long 0x14 0. "HAC_SGE,Halt complete signal enable" "0,1" line.long 0x18 "CQIC,Command Queuing Interrupt Coalescing" bitfld.long 0x18 31. "ICENDIS,Interrupt coalescing enable/disable" "0,1" newline rbitfld.long 0x18 20. "ICSB,Interrupt coalescing status" "0: No task completions have occurred since last..,1: At least one task completion has been counted.." newline bitfld.long 0x18 16. "ICCTR,Counter and timer reset" "0,1" newline bitfld.long 0x18 15. "ICCTHWEN,Interrupt coalescing counter threshold write enable" "0,1" newline hexmask.long.byte 0x18 8.--12. 1. "ICCTH,Interrupt coalescing counter threshold" newline bitfld.long 0x18 7. "ICTOVALWEN,Interrupt coalescing timeout value write enable" "0,1" newline hexmask.long.byte 0x18 0.--6. 1. "ICTOVAL,Interrupt coalescing timeout value" line.long 0x1C "CQTDLBA,Command Queuing Task Descriptor List Base Address" hexmask.long 0x1C 0.--31. 1. "TDLBA,Task descriptor list base address" line.long 0x20 "CQTDLBAU,Command Queuing Task Descriptor List Base Address Upper 32 Bits" hexmask.long 0x20 0.--31. 1. "TDLBAU,Task descriptor list base address" line.long 0x24 "CQTDBR,Command Queuing Task Doorbell" hexmask.long 0x24 0.--31. 1. "TDBR,Task doorbell" line.long 0x28 "CQTCN,Command Queuing Task Completion Notification" hexmask.long 0x28 0.--31. 1. "TCN,Task complete notification" rgroup.long 0x130++0x7 line.long 0x0 "CQDQS,Command Queuing Device Queue Status" hexmask.long 0x0 0.--31. 1. "DQS,Device queue status" line.long 0x4 "CQDPT,Command Queuing Device Pending Tasks" hexmask.long 0x4 0.--31. 1. "DPT,Device pending tasks" group.long 0x138++0x3 line.long 0x0 "CQTCLR,Command Queuing Task Clear" hexmask.long 0x0 0.--31. 1. "TCLR,Task clear" group.long 0x140++0x7 line.long 0x0 "CQSSC1,Command Queuing Send Status Configuration 1" hexmask.long.byte 0x0 16.--19. 1. "CBC,Send status command block counter" newline hexmask.long.word 0x0 0.--15. 1. "CIT,Send status command idle timer" line.long 0x4 "CQSSC2,Command Queuing Send Status Configuration 2" hexmask.long.word 0x4 0.--15. 1. "SSC2,Send queue status RCA" rgroup.long 0x148++0x3 line.long 0x0 "CQCRDCT,Command Queuing Command Response for Direct-Command Task" hexmask.long 0x0 0.--31. 1. "CRDCT,Direct command last response" group.long 0x150++0x3 line.long 0x0 "CQRMEM,Command Queuing Response Mode Error Mask" hexmask.long 0x0 0.--31. 1. "RMEM,Response mode error mask" rgroup.long 0x154++0xB line.long 0x0 "CQTERRI,Command Queuing Task Error Information" bitfld.long 0x0 31. "DTEFV,Data transfer error fields valid" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "DTETID,Data transfer error task ID" newline hexmask.long.byte 0x0 16.--21. 1. "DTECI,Data transfer error command index" newline bitfld.long 0x0 15. "RMEFV,Response mode error fields valid" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "RMETID,Response mode error task ID" newline hexmask.long.byte 0x0 0.--5. 1. "RMECI,Response mode error command index" line.long 0x4 "CQCRI,Command Queuing Command Response Index" hexmask.long.byte 0x4 0.--5. 1. "LCMDRI,Last command response index" line.long 0x8 "CQCRA,Command Queuing Command Response Argument" hexmask.long 0x8 0.--31. 1. "LCMDRA,Last command response argument" tree.end tree "WKPU (Wakeup Unit)" base ad:0x40090000 group.long 0x0++0x3 line.long 0x0 "NSR,NMI Status Flag Register" eventfld.long 0x0 31. "NIF0,NMI Status Flag 0" "0: No event has occurred on the pad,1: An event as defined by NREE0 and NFEE0 has.." eventfld.long 0x0 30. "NOVF0,NMI Overrun Status Flag 0" "0: No overrun has occurred on NMI input 0,1: An overrun has occurred on NMI input 0" group.long 0x8++0x3 line.long 0x0 "NCR,NMI Configuration Register" bitfld.long 0x0 31. "NLOCK0,NMI Configuration Lock Register 0" "0,1" bitfld.long 0x0 29.--30. "NDSS0,NMI Destination Source Select 0" "0: Non-maskable interrupt,?,?,?" newline bitfld.long 0x0 28. "NWRE0,NMI Wakeup Request Enable 0" "0: System wakeup requests from the corresponding..,1: Causes a system wakeup request when NIF0 = 1 or.." bitfld.long 0x0 26. "NREE0,NMI Rising-Edge Events Enable 0" "0: Rising-edge event is disabled,1: Rising-edge event is enabled" newline bitfld.long 0x0 25. "NFEE0,NMI Falling-edge Events Enable 0" "0,1" bitfld.long 0x0 24. "NFE0,NMI Filter Enable 0" "0: Filter is disabled,1: Filter is enabled" group.long 0x10++0xF line.long 0x0 "WBMSR,Wakeup Boot Mode Select Register" hexmask.long 0x0 0.--31. 1. "WBMS_32,Wakeup Short or Long Boot Select 0b - Short boot execution by boot software after wakeup from STANDBY mode 1b - Long boot execution by boot software after wakeup from STANDBY mode" line.long 0x4 "WISR,Wakeup/Interrupt Status Flag Register" hexmask.long 0x4 0.--31. 1. "EIF,External Wakeup/Interrupt Status Flag x" line.long 0x8 "IRER,Interrupt Request Enable Register" hexmask.long 0x8 0.--31. 1. "EIRE,External Interrupt Request Enable x" line.long 0xC "WRER,Wakeup Request Enable Register" hexmask.long 0xC 0.--31. 1. "WRE,External Wakeup Request Enable x" group.long 0x28++0xF line.long 0x0 "WIREER,Wakeup/Interrupt Rising-Edge Event Enable Register" hexmask.long 0x0 0.--31. 1. "IREE,External Interrupt Rising-edge Events Enable x" line.long 0x4 "WIFEER,Wakeup/Interrupt Falling-Edge Event Enable Register" hexmask.long 0x4 0.--31. 1. "IFEEx,External Interrupt Falling-edge Events Enable x" line.long 0x8 "WIFER,Wakeup/Interrupt Filter Enable Register" hexmask.long 0x8 0.--30. 1. "IFE,External Interrupt Filter Enable x" line.long 0xC "WIPUER_WIPDER,Wakeup/Interrupt Pull Enable Register" hexmask.long 0xC 0.--30. 1. "IPUE,External Interrupt Pull Enable x 0b - Pull is disabled. 1b - Pull is enabled." tree.end tree "XRDC (Extended Resource Domain Controller)" base ad:0x0 tree "XRDC_0" base ad:0x401A4000 group.long 0x0++0x3 line.long 0x0 "CR,Control" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" rbitfld.long 0x0 8. "VAW,Virtualization Aware" "0: Not virtualization-aware,1: Virtualization-aware" newline rbitfld.long 0x0 7. "MRF,Memory Region Format" "?,1: SMPU family format" hexmask.long.byte 0x0 1.--4. 1. "HRL,Hardware Revision Level" newline bitfld.long 0x0 0. "GVLD,Global Valid (XRDC Global Enable/Disable)" "0: Disables,1: Enables" rgroup.long 0xF0++0xB line.long 0x0 "HWCFG0,Hardware Configuration 0" hexmask.long.byte 0x0 28.--31. 1. "MID,Module ID" hexmask.long.byte 0x0 24.--27. 1. "NPAC,Number Of PACs" newline hexmask.long.byte 0x0 16.--23. 1. "NMRC,Number of MRCs" hexmask.long.byte 0x0 8.--15. 1. "NMSTR,Number Of Bus Masters" newline hexmask.long.byte 0x0 0.--7. 1. "NDID,Number Of DIDs" line.long 0x4 "HWCFG1,Hardware Configuration 1" hexmask.long.byte 0x4 0.--3. 1. "DID,Domain Identifier" line.long 0x8 "HWCFG2,Hardware Configuration 2" bitfld.long 0x8 31. "PIDP31,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 30. "PIDP30,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 29. "PIDP29,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 28. "PIDP28,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 27. "PIDP27,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 26. "PIDP26,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 25. "PIDP25,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 24. "PIDP24,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 23. "PIDP23,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 22. "PIDP22,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 21. "PIDP21,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 20. "PIDP20,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 19. "PIDP19,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 18. "PIDP18,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 17. "PIDP17,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 16. "PIDP16,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 15. "PIDP15,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 14. "PIDP14,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 13. "PIDP13,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 12. "PIDP12,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 11. "PIDP11,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 10. "PIDP10,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 9. "PIDP9,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 8. "PIDP8,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 7. "PIDP7,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 6. "PIDP6,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 5. "PIDP5,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 4. "PIDP4,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 3. "PIDP3,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 2. "PIDP2,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 1. "PIDP1,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 0. "PIDP0,Process Identifier Present" "0: Does not have PID register,1: Has PID register" rgroup.byte 0x100++0xC line.byte 0x0 "MDACFG0,Master Domain Assignment Configuration" bitfld.byte 0x0 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x0 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x1 "MDACFG1,Master Domain Assignment Configuration" bitfld.byte 0x1 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x1 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x2 "MDACFG2,Master Domain Assignment Configuration" bitfld.byte 0x2 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x2 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x3 "MDACFG3,Master Domain Assignment Configuration" bitfld.byte 0x3 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x3 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x4 "MDACFG4,Master Domain Assignment Configuration" bitfld.byte 0x4 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x4 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x5 "MDACFG5,Master Domain Assignment Configuration" bitfld.byte 0x5 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x5 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x6 "MDACFG6,Master Domain Assignment Configuration" bitfld.byte 0x6 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x6 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x7 "MDACFG7,Master Domain Assignment Configuration" bitfld.byte 0x7 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x7 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x8 "MDACFG8,Master Domain Assignment Configuration" bitfld.byte 0x8 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x8 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x9 "MDACFG9,Master Domain Assignment Configuration" bitfld.byte 0x9 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x9 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0xA "MDACFG10,Master Domain Assignment Configuration" bitfld.byte 0xA 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0xA 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0xB "MDACFG11,Master Domain Assignment Configuration" bitfld.byte 0xB 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0xB 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0xC "MDACFG12,Master Domain Assignment Configuration" bitfld.byte 0xC 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0xC 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" rgroup.byte 0x10F++0x6 line.byte 0x0 "MDACFG15,Master Domain Assignment Configuration" bitfld.byte 0x0 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x0 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x1 "MDACFG16,Master Domain Assignment Configuration" bitfld.byte 0x1 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x1 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x2 "MDACFG17,Master Domain Assignment Configuration" bitfld.byte 0x2 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x2 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x3 "MDACFG18,Master Domain Assignment Configuration" bitfld.byte 0x3 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x3 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x4 "MDACFG19,Master Domain Assignment Configuration" bitfld.byte 0x4 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x4 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x5 "MDACFG20,Master Domain Assignment Configuration" bitfld.byte 0x5 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x5 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x6 "MDACFG21,Master Domain Assignment Configuration" bitfld.byte 0x6 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x6 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" rgroup.byte 0x140++0x0 line.byte 0x0 "MRCFG0,Memory Region Configuration" hexmask.byte 0x0 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" rgroup.byte 0x142++0xB line.byte 0x0 "MRCFG2,Memory Region Configuration" hexmask.byte 0x0 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x1 "MRCFG3,Memory Region Configuration" hexmask.byte 0x1 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x2 "MRCFG4,Memory Region Configuration" hexmask.byte 0x2 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x3 "MRCFG5,Memory Region Configuration" hexmask.byte 0x3 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x4 "MRCFG6,Memory Region Configuration" hexmask.byte 0x4 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x5 "MRCFG7,Memory Region Configuration" hexmask.byte 0x5 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x6 "MRCFG8,Memory Region Configuration" hexmask.byte 0x6 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x7 "MRCFG9,Memory Region Configuration" hexmask.byte 0x7 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x8 "MRCFG10,Memory Region Configuration" hexmask.byte 0x8 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x9 "MRCFG11,Memory Region Configuration" hexmask.byte 0x9 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0xA "MRCFG12,Memory Region Configuration" hexmask.byte 0xA 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0xB "MRCFG13,Memory Region Configuration" hexmask.byte 0xB 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x200)++0x3 line.long 0x0 "DERRLOC[$1],Domain Error Location" hexmask.long.byte 0x0 16.--19. 1. "PACINST,PAC Instance" hexmask.long.word 0x0 0.--15. 1. "MRCINST,MRC Instance" repeat.end rgroup.long 0x400++0xB line.long 0x0 "DERR_W0_0,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_0,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_0,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x40C++0x3 line.long 0x0 "DERR_W3_0,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x420++0xB line.long 0x0 "DERR_W0_2,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_2,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_2,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x42C++0x3 line.long 0x0 "DERR_W3_2,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x430++0xB line.long 0x0 "DERR_W0_3,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_3,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_3,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x43C++0x3 line.long 0x0 "DERR_W3_3,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x440++0xB line.long 0x0 "DERR_W0_4,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_4,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_4,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x44C++0x3 line.long 0x0 "DERR_W3_4,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x450++0xB line.long 0x0 "DERR_W0_5,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_5,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_5,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x45C++0x3 line.long 0x0 "DERR_W3_5,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x460++0xB line.long 0x0 "DERR_W0_6,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_6,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_6,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x46C++0x3 line.long 0x0 "DERR_W3_6,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x470++0xB line.long 0x0 "DERR_W0_7,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_7,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_7,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x47C++0x3 line.long 0x0 "DERR_W3_7,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x480++0xB line.long 0x0 "DERR_W0_8,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_8,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_8,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x48C++0x3 line.long 0x0 "DERR_W3_8,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x490++0xB line.long 0x0 "DERR_W0_9,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_9,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_9,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x49C++0x3 line.long 0x0 "DERR_W3_9,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x4A0++0xB line.long 0x0 "DERR_W0_10,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_10,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_10,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x4AC++0x3 line.long 0x0 "DERR_W3_10,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x4B0++0xB line.long 0x0 "DERR_W0_11,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_11,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_11,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x4BC++0x3 line.long 0x0 "DERR_W3_11,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x4C0++0xB line.long 0x0 "DERR_W0_12,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_12,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_12,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x4CC++0x3 line.long 0x0 "DERR_W3_12,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x4D0++0xB line.long 0x0 "DERR_W0_13,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_13,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_13,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x4DC++0x3 line.long 0x0 "DERR_W3_13,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x500++0xB line.long 0x0 "DERR_W0_16,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_16,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_16,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x50C++0x3 line.long 0x0 "DERR_W3_16,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x510++0xB line.long 0x0 "DERR_W0_17,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_17,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_17,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x51C++0x3 line.long 0x0 "DERR_W3_17,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x520++0xB line.long 0x0 "DERR_W0_18,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_18,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_18,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x52C++0x3 line.long 0x0 "DERR_W3_18,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x530++0xB line.long 0x0 "DERR_W0_19,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_19,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_19,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x53C++0x3 line.long 0x0 "DERR_W3_19,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" group.long 0x700++0x7 line.long 0x0 "PID0,Process Identifier" bitfld.long 0x0 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x0 28. "TSM,Three-State Model" "0,1" newline rbitfld.long 0x0 24. "ELK22H,LK2 Special Handling Enable" "0: LK2 operates normally; LMNUM is reserved and..,1: If LK2 = 2 (10b) LMNUM indicates the master that.." hexmask.long.byte 0x0 16.--21. 1. "LMNUM,Locked Master Number" newline bitfld.long 0x0 5. "PID,Process Identifier Secure Attribute" "0: Secure,1: Nonsecure" line.long 0x4 "PID1,Process Identifier" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x4 28. "TSM,Three-State Model" "0,1" newline rbitfld.long 0x4 24. "ELK22H,LK2 Special Handling Enable" "0: LK2 operates normally; LMNUM is reserved and..,1: If LK2 = 2 (10b) LMNUM indicates the master that.." hexmask.long.byte 0x4 16.--21. 1. "LMNUM,Locked Master Number" newline bitfld.long 0x4 5. "PID,Process Identifier Secure Attribute" "0: Secure,1: Nonsecure" group.long 0x720++0xB line.long 0x0 "PID8,Process Identifier" bitfld.long 0x0 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x0 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "PID,Process Identifier" line.long 0x4 "PID9,Process Identifier" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x4 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "PID,Process Identifier" line.long 0x8 "PID10,Process Identifier" bitfld.long 0x8 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x8 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x8 0.--5. 1. "PID,Process Identifier" group.long 0x740++0xB line.long 0x0 "PID16,Process Identifier" bitfld.long 0x0 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x0 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "PID,Process Identifier" line.long 0x4 "PID17,Process Identifier" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x4 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "PID,Process Identifier" line.long 0x8 "PID18,Process Identifier" bitfld.long 0x8 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x8 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x8 0.--5. 1. "PID,Process Identifier" group.long 0x800++0x43 line.long 0x0 "MDA_W0_0_DFMT0,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x0 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x0 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x0 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x0 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x4 "MDA_W1_0_DFMT0,Master Domain Assignment" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x4 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x4 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x4 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x4 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x4 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x4 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x8 "MDA_W2_0_DFMT0,Master Domain Assignment" bitfld.long 0x8 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x8 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x8 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x8 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x8 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x8 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x8 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0xC "MDA_W3_0_DFMT0,Master Domain Assignment" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0xC 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0xC 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0xC 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0xC 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0xC 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0xC 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x10 "MDA_W4_0_DFMT0,Master Domain Assignment" bitfld.long 0x10 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x10 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x10 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x10 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x10 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x10 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x10 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x10 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x14 "MDA_W5_0_DFMT0,Master Domain Assignment" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x14 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x14 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x14 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x14 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x14 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x14 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x18 "MDA_W6_0_DFMT0,Master Domain Assignment" bitfld.long 0x18 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x18 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x18 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x18 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x18 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x18 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x18 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x18 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x1C "MDA_W7_0_DFMT0,Master Domain Assignment" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x1C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x1C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x1C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x1C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x1C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x1C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x20 "MDA_W0_1_DFMT0,Master Domain Assignment" bitfld.long 0x20 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x20 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x20 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x20 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x20 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x20 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x20 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x20 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x24 "MDA_W1_1_DFMT0,Master Domain Assignment" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x24 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x24 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x24 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x24 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x24 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x24 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x28 "MDA_W2_1_DFMT0,Master Domain Assignment" bitfld.long 0x28 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x28 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x28 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x28 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x28 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x28 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x28 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x28 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x2C "MDA_W3_1_DFMT0,Master Domain Assignment" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x2C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x2C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x2C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x2C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x2C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x2C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x30 "MDA_W4_1_DFMT0,Master Domain Assignment" bitfld.long 0x30 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x30 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x30 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x30 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x30 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x30 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x30 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x30 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x34 "MDA_W5_1_DFMT0,Master Domain Assignment" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x34 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x34 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x34 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x34 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x34 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x34 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x38 "MDA_W6_1_DFMT0,Master Domain Assignment" bitfld.long 0x38 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x38 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x38 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x38 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x38 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x38 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x38 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x38 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x3C "MDA_W7_1_DFMT0,Master Domain Assignment" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x3C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x3C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x3C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x3C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x3C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x3C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x40 "MDA_W0_2_DFMT1,Master Domain Assignment" bitfld.long 0x40 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x40 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x40 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x40 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x40 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x40 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x40 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x860++0x3 line.long 0x0 "MDA_W0_3_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x880++0x3 line.long 0x0 "MDA_W0_4_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x8A0++0x3 line.long 0x0 "MDA_W0_5_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x8C0++0x3 line.long 0x0 "MDA_W0_6_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x8E0++0x3 line.long 0x0 "MDA_W0_7_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x900++0x63 line.long 0x0 "MDA_W0_8_DFMT0,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x0 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x0 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x0 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x0 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x4 "MDA_W1_8_DFMT0,Master Domain Assignment" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x4 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x4 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x4 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x4 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x4 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x4 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x8 "MDA_W2_8_DFMT0,Master Domain Assignment" bitfld.long 0x8 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x8 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x8 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x8 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x8 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x8 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x8 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0xC "MDA_W3_8_DFMT0,Master Domain Assignment" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0xC 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0xC 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0xC 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0xC 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0xC 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0xC 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x10 "MDA_W4_8_DFMT0,Master Domain Assignment" bitfld.long 0x10 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x10 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x10 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x10 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x10 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x10 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x10 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x10 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x14 "MDA_W5_8_DFMT0,Master Domain Assignment" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x14 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x14 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x14 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x14 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x14 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x14 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x18 "MDA_W6_8_DFMT0,Master Domain Assignment" bitfld.long 0x18 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x18 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x18 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x18 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x18 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x18 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x18 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x18 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x1C "MDA_W7_8_DFMT0,Master Domain Assignment" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x1C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x1C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x1C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x1C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x1C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x1C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x20 "MDA_W0_9_DFMT0,Master Domain Assignment" bitfld.long 0x20 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x20 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x20 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x20 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x20 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x20 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x20 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x20 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x24 "MDA_W1_9_DFMT0,Master Domain Assignment" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x24 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x24 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x24 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x24 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x24 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x24 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x28 "MDA_W2_9_DFMT0,Master Domain Assignment" bitfld.long 0x28 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x28 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x28 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x28 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x28 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x28 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x28 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x28 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x2C "MDA_W3_9_DFMT0,Master Domain Assignment" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x2C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x2C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x2C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x2C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x2C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x2C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x30 "MDA_W4_9_DFMT0,Master Domain Assignment" bitfld.long 0x30 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x30 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x30 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x30 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x30 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x30 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x30 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x30 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x34 "MDA_W5_9_DFMT0,Master Domain Assignment" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x34 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x34 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x34 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x34 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x34 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x34 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x38 "MDA_W6_9_DFMT0,Master Domain Assignment" bitfld.long 0x38 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x38 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x38 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x38 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x38 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x38 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x38 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x38 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x3C "MDA_W7_9_DFMT0,Master Domain Assignment" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x3C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x3C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x3C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x3C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x3C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x3C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x40 "MDA_W0_10_DFMT0,Master Domain Assignment" bitfld.long 0x40 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x40 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x40 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x40 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x40 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x40 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x40 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x40 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x44 "MDA_W1_10_DFMT0,Master Domain Assignment" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x44 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x44 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x44 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x44 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x44 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x44 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x48 "MDA_W2_10_DFMT0,Master Domain Assignment" bitfld.long 0x48 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x48 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x48 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x48 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x48 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x48 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x48 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x48 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x4C "MDA_W3_10_DFMT0,Master Domain Assignment" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x4C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x4C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x4C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x4C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x4C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x4C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x50 "MDA_W4_10_DFMT0,Master Domain Assignment" bitfld.long 0x50 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x50 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x50 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x50 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x50 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x50 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x50 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x50 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x54 "MDA_W5_10_DFMT0,Master Domain Assignment" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x54 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x54 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x54 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x54 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x54 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x54 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x58 "MDA_W6_10_DFMT0,Master Domain Assignment" bitfld.long 0x58 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x58 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x58 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x58 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x58 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x58 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x58 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x58 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x5C "MDA_W7_10_DFMT0,Master Domain Assignment" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x5C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x5C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x5C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x5C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x5C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x5C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x60 "MDA_W0_11_DFMT1,Master Domain Assignment" bitfld.long 0x60 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x60 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x60 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x60 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x60 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x60 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x60 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x980++0x3 line.long 0x0 "MDA_W0_12_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x9E0++0x3 line.long 0x0 "MDA_W0_15_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0xA00++0x63 line.long 0x0 "MDA_W0_16_DFMT0,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x0 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x0 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x0 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x0 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x4 "MDA_W1_16_DFMT0,Master Domain Assignment" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x4 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x4 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x4 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x4 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x4 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x4 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x8 "MDA_W2_16_DFMT0,Master Domain Assignment" bitfld.long 0x8 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x8 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x8 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x8 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x8 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x8 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x8 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0xC "MDA_W3_16_DFMT0,Master Domain Assignment" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0xC 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0xC 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0xC 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0xC 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0xC 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0xC 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x10 "MDA_W4_16_DFMT0,Master Domain Assignment" bitfld.long 0x10 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x10 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x10 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x10 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x10 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x10 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x10 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x10 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x14 "MDA_W5_16_DFMT0,Master Domain Assignment" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x14 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x14 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x14 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x14 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x14 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x14 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x18 "MDA_W6_16_DFMT0,Master Domain Assignment" bitfld.long 0x18 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x18 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x18 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x18 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x18 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x18 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x18 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x18 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x1C "MDA_W7_16_DFMT0,Master Domain Assignment" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x1C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x1C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x1C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x1C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x1C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x1C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x20 "MDA_W0_17_DFMT0,Master Domain Assignment" bitfld.long 0x20 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x20 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x20 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x20 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x20 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x20 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x20 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x20 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x24 "MDA_W1_17_DFMT0,Master Domain Assignment" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x24 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x24 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x24 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x24 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x24 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x24 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x28 "MDA_W2_17_DFMT0,Master Domain Assignment" bitfld.long 0x28 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x28 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x28 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x28 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x28 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x28 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x28 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x28 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x2C "MDA_W3_17_DFMT0,Master Domain Assignment" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x2C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x2C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x2C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x2C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x2C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x2C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x30 "MDA_W4_17_DFMT0,Master Domain Assignment" bitfld.long 0x30 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x30 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x30 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x30 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x30 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x30 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x30 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x30 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x34 "MDA_W5_17_DFMT0,Master Domain Assignment" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x34 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x34 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x34 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x34 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x34 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x34 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x38 "MDA_W6_17_DFMT0,Master Domain Assignment" bitfld.long 0x38 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x38 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x38 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x38 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x38 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x38 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x38 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x38 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x3C "MDA_W7_17_DFMT0,Master Domain Assignment" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x3C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x3C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x3C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x3C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x3C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x3C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x40 "MDA_W0_18_DFMT0,Master Domain Assignment" bitfld.long 0x40 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x40 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x40 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x40 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x40 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x40 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x40 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x40 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x44 "MDA_W1_18_DFMT0,Master Domain Assignment" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x44 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x44 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x44 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x44 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x44 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x44 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x48 "MDA_W2_18_DFMT0,Master Domain Assignment" bitfld.long 0x48 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x48 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x48 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x48 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x48 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x48 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x48 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x48 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x4C "MDA_W3_18_DFMT0,Master Domain Assignment" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x4C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x4C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x4C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x4C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x4C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x4C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x50 "MDA_W4_18_DFMT0,Master Domain Assignment" bitfld.long 0x50 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x50 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x50 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x50 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x50 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x50 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x50 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x50 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x54 "MDA_W5_18_DFMT0,Master Domain Assignment" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x54 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x54 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x54 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x54 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x54 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x54 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x58 "MDA_W6_18_DFMT0,Master Domain Assignment" bitfld.long 0x58 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x58 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x58 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x58 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x58 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x58 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x58 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x58 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x5C "MDA_W7_18_DFMT0,Master Domain Assignment" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x5C 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x5C 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x5C 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x5C 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x5C 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x5C 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" line.long 0x60 "MDA_W0_19_DFMT1,Master Domain Assignment" bitfld.long 0x60 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x60 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x60 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x60 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x60 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x60 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x60 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0xA80++0x3 line.long 0x0 "MDA_W0_20_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0xAA0++0x3 line.long 0x0 "MDA_W0_21_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x1000++0xFF line.long 0x0 "PDAC_W0_0,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_0,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_1,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_1,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_2,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_2,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_3,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_3,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_4,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_4,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_5,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_5,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_6,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_6,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_7,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_7,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_8,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_8,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_9,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_9,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_10,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_10,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x58 "PDAC_W0_11,Peripheral Domain Access Control Word 0" bitfld.long 0x58 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x58 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x58 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x5C "PDAC_W1_11,Peripheral Domain Access Control Word 1" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x60 "PDAC_W0_12,Peripheral Domain Access Control Word 0" bitfld.long 0x60 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x60 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x60 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x64 "PDAC_W1_12,Peripheral Domain Access Control Word 1" bitfld.long 0x64 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x64 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x68 "PDAC_W0_13,Peripheral Domain Access Control Word 0" bitfld.long 0x68 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x68 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x68 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x6C "PDAC_W1_13,Peripheral Domain Access Control Word 1" bitfld.long 0x6C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x6C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x70 "PDAC_W0_14,Peripheral Domain Access Control Word 0" bitfld.long 0x70 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x70 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x70 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x74 "PDAC_W1_14,Peripheral Domain Access Control Word 1" bitfld.long 0x74 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x74 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x78 "PDAC_W0_15,Peripheral Domain Access Control Word 0" bitfld.long 0x78 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x78 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x78 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x7C "PDAC_W1_15,Peripheral Domain Access Control Word 1" bitfld.long 0x7C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x7C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x80 "PDAC_W0_16,Peripheral Domain Access Control Word 0" bitfld.long 0x80 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x80 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x80 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x84 "PDAC_W1_16,Peripheral Domain Access Control Word 1" bitfld.long 0x84 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x84 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x88 "PDAC_W0_17,Peripheral Domain Access Control Word 0" bitfld.long 0x88 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x88 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x88 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x8C "PDAC_W1_17,Peripheral Domain Access Control Word 1" bitfld.long 0x8C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x90 "PDAC_W0_18,Peripheral Domain Access Control Word 0" bitfld.long 0x90 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x90 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x90 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x94 "PDAC_W1_18,Peripheral Domain Access Control Word 1" bitfld.long 0x94 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x94 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x98 "PDAC_W0_19,Peripheral Domain Access Control Word 0" bitfld.long 0x98 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x98 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x98 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x9C "PDAC_W1_19,Peripheral Domain Access Control Word 1" bitfld.long 0x9C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x9C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA0 "PDAC_W0_20,Peripheral Domain Access Control Word 0" bitfld.long 0xA0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xA4 "PDAC_W1_20,Peripheral Domain Access Control Word 1" bitfld.long 0xA4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xA4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA8 "PDAC_W0_21,Peripheral Domain Access Control Word 0" bitfld.long 0xA8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xAC "PDAC_W1_21,Peripheral Domain Access Control Word 1" bitfld.long 0xAC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xAC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB0 "PDAC_W0_22,Peripheral Domain Access Control Word 0" bitfld.long 0xB0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xB4 "PDAC_W1_22,Peripheral Domain Access Control Word 1" bitfld.long 0xB4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xB4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB8 "PDAC_W0_23,Peripheral Domain Access Control Word 0" bitfld.long 0xB8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xBC "PDAC_W1_23,Peripheral Domain Access Control Word 1" bitfld.long 0xBC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xBC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC0 "PDAC_W0_24,Peripheral Domain Access Control Word 0" bitfld.long 0xC0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC4 "PDAC_W1_24,Peripheral Domain Access Control Word 1" bitfld.long 0xC4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC8 "PDAC_W0_25,Peripheral Domain Access Control Word 0" bitfld.long 0xC8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xCC "PDAC_W1_25,Peripheral Domain Access Control Word 1" bitfld.long 0xCC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xCC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD0 "PDAC_W0_26,Peripheral Domain Access Control Word 0" bitfld.long 0xD0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xD4 "PDAC_W1_26,Peripheral Domain Access Control Word 1" bitfld.long 0xD4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xD4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD8 "PDAC_W0_27,Peripheral Domain Access Control Word 0" bitfld.long 0xD8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xDC "PDAC_W1_27,Peripheral Domain Access Control Word 1" bitfld.long 0xDC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xDC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE0 "PDAC_W0_28,Peripheral Domain Access Control Word 0" bitfld.long 0xE0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xE4 "PDAC_W1_28,Peripheral Domain Access Control Word 1" bitfld.long 0xE4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xE4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE8 "PDAC_W0_29,Peripheral Domain Access Control Word 0" bitfld.long 0xE8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xEC "PDAC_W1_29,Peripheral Domain Access Control Word 1" bitfld.long 0xEC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xEC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF0 "PDAC_W0_30,Peripheral Domain Access Control Word 0" bitfld.long 0xF0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xF4 "PDAC_W1_30,Peripheral Domain Access Control Word 1" bitfld.long 0xF4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xF4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF8 "PDAC_W0_31,Peripheral Domain Access Control Word 0" bitfld.long 0xF8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xFC "PDAC_W1_31,Peripheral Domain Access Control Word 1" bitfld.long 0xFC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xFC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1400++0xFF line.long 0x0 "PDAC_W0_128,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_128,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_129,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_129,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_130,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_130,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_131,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_131,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_132,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_132,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_133,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_133,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_134,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_134,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_135,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_135,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_136,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_136,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_137,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_137,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_138,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_138,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x58 "PDAC_W0_139,Peripheral Domain Access Control Word 0" bitfld.long 0x58 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x58 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x58 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x5C "PDAC_W1_139,Peripheral Domain Access Control Word 1" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x60 "PDAC_W0_140,Peripheral Domain Access Control Word 0" bitfld.long 0x60 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x60 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x60 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x64 "PDAC_W1_140,Peripheral Domain Access Control Word 1" bitfld.long 0x64 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x64 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x68 "PDAC_W0_141,Peripheral Domain Access Control Word 0" bitfld.long 0x68 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x68 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x68 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x6C "PDAC_W1_141,Peripheral Domain Access Control Word 1" bitfld.long 0x6C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x6C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x70 "PDAC_W0_142,Peripheral Domain Access Control Word 0" bitfld.long 0x70 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x70 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x70 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x74 "PDAC_W1_142,Peripheral Domain Access Control Word 1" bitfld.long 0x74 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x74 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x78 "PDAC_W0_143,Peripheral Domain Access Control Word 0" bitfld.long 0x78 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x78 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x78 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x7C "PDAC_W1_143,Peripheral Domain Access Control Word 1" bitfld.long 0x7C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x7C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x80 "PDAC_W0_144,Peripheral Domain Access Control Word 0" bitfld.long 0x80 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x80 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x80 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x84 "PDAC_W1_144,Peripheral Domain Access Control Word 1" bitfld.long 0x84 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x84 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x88 "PDAC_W0_145,Peripheral Domain Access Control Word 0" bitfld.long 0x88 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x88 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x88 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x8C "PDAC_W1_145,Peripheral Domain Access Control Word 1" bitfld.long 0x8C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x90 "PDAC_W0_146,Peripheral Domain Access Control Word 0" bitfld.long 0x90 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x90 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x90 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x94 "PDAC_W1_146,Peripheral Domain Access Control Word 1" bitfld.long 0x94 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x94 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x98 "PDAC_W0_147,Peripheral Domain Access Control Word 0" bitfld.long 0x98 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x98 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x98 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x9C "PDAC_W1_147,Peripheral Domain Access Control Word 1" bitfld.long 0x9C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x9C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA0 "PDAC_W0_148,Peripheral Domain Access Control Word 0" bitfld.long 0xA0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xA4 "PDAC_W1_148,Peripheral Domain Access Control Word 1" bitfld.long 0xA4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xA4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA8 "PDAC_W0_149,Peripheral Domain Access Control Word 0" bitfld.long 0xA8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xAC "PDAC_W1_149,Peripheral Domain Access Control Word 1" bitfld.long 0xAC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xAC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB0 "PDAC_W0_150,Peripheral Domain Access Control Word 0" bitfld.long 0xB0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xB4 "PDAC_W1_150,Peripheral Domain Access Control Word 1" bitfld.long 0xB4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xB4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB8 "PDAC_W0_151,Peripheral Domain Access Control Word 0" bitfld.long 0xB8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xBC "PDAC_W1_151,Peripheral Domain Access Control Word 1" bitfld.long 0xBC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xBC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC0 "PDAC_W0_152,Peripheral Domain Access Control Word 0" bitfld.long 0xC0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC4 "PDAC_W1_152,Peripheral Domain Access Control Word 1" bitfld.long 0xC4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC8 "PDAC_W0_153,Peripheral Domain Access Control Word 0" bitfld.long 0xC8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xCC "PDAC_W1_153,Peripheral Domain Access Control Word 1" bitfld.long 0xCC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xCC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD0 "PDAC_W0_154,Peripheral Domain Access Control Word 0" bitfld.long 0xD0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xD4 "PDAC_W1_154,Peripheral Domain Access Control Word 1" bitfld.long 0xD4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xD4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD8 "PDAC_W0_155,Peripheral Domain Access Control Word 0" bitfld.long 0xD8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xDC "PDAC_W1_155,Peripheral Domain Access Control Word 1" bitfld.long 0xDC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xDC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE0 "PDAC_W0_156,Peripheral Domain Access Control Word 0" bitfld.long 0xE0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xE4 "PDAC_W1_156,Peripheral Domain Access Control Word 1" bitfld.long 0xE4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xE4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE8 "PDAC_W0_157,Peripheral Domain Access Control Word 0" bitfld.long 0xE8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xEC "PDAC_W1_157,Peripheral Domain Access Control Word 1" bitfld.long 0xEC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xEC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF0 "PDAC_W0_158,Peripheral Domain Access Control Word 0" bitfld.long 0xF0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xF4 "PDAC_W1_158,Peripheral Domain Access Control Word 1" bitfld.long 0xF4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xF4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF8 "PDAC_W0_159,Peripheral Domain Access Control Word 0" bitfld.long 0xF8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xFC "PDAC_W1_159,Peripheral Domain Access Control Word 1" bitfld.long 0xFC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xFC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1800++0xFF line.long 0x0 "PDAC_W0_256,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_256,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_257,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_257,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_258,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_258,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_259,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_259,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_260,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_260,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_261,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_261,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_262,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_262,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_263,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_263,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_264,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_264,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_265,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_265,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_266,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_266,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x58 "PDAC_W0_267,Peripheral Domain Access Control Word 0" bitfld.long 0x58 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x58 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x58 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x5C "PDAC_W1_267,Peripheral Domain Access Control Word 1" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x60 "PDAC_W0_268,Peripheral Domain Access Control Word 0" bitfld.long 0x60 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x60 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x60 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x64 "PDAC_W1_268,Peripheral Domain Access Control Word 1" bitfld.long 0x64 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x64 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x68 "PDAC_W0_269,Peripheral Domain Access Control Word 0" bitfld.long 0x68 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x68 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x68 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x6C "PDAC_W1_269,Peripheral Domain Access Control Word 1" bitfld.long 0x6C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x6C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x70 "PDAC_W0_270,Peripheral Domain Access Control Word 0" bitfld.long 0x70 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x70 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x70 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x74 "PDAC_W1_270,Peripheral Domain Access Control Word 1" bitfld.long 0x74 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x74 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x78 "PDAC_W0_271,Peripheral Domain Access Control Word 0" bitfld.long 0x78 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x78 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x78 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x7C "PDAC_W1_271,Peripheral Domain Access Control Word 1" bitfld.long 0x7C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x7C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x80 "PDAC_W0_272,Peripheral Domain Access Control Word 0" bitfld.long 0x80 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x80 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x80 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x84 "PDAC_W1_272,Peripheral Domain Access Control Word 1" bitfld.long 0x84 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x84 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x88 "PDAC_W0_273,Peripheral Domain Access Control Word 0" bitfld.long 0x88 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x88 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x88 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x8C "PDAC_W1_273,Peripheral Domain Access Control Word 1" bitfld.long 0x8C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x90 "PDAC_W0_274,Peripheral Domain Access Control Word 0" bitfld.long 0x90 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x90 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x90 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x94 "PDAC_W1_274,Peripheral Domain Access Control Word 1" bitfld.long 0x94 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x94 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x98 "PDAC_W0_275,Peripheral Domain Access Control Word 0" bitfld.long 0x98 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x98 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x98 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x9C "PDAC_W1_275,Peripheral Domain Access Control Word 1" bitfld.long 0x9C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x9C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA0 "PDAC_W0_276,Peripheral Domain Access Control Word 0" bitfld.long 0xA0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xA4 "PDAC_W1_276,Peripheral Domain Access Control Word 1" bitfld.long 0xA4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xA4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA8 "PDAC_W0_277,Peripheral Domain Access Control Word 0" bitfld.long 0xA8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xAC "PDAC_W1_277,Peripheral Domain Access Control Word 1" bitfld.long 0xAC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xAC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB0 "PDAC_W0_278,Peripheral Domain Access Control Word 0" bitfld.long 0xB0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xB4 "PDAC_W1_278,Peripheral Domain Access Control Word 1" bitfld.long 0xB4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xB4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB8 "PDAC_W0_279,Peripheral Domain Access Control Word 0" bitfld.long 0xB8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xBC "PDAC_W1_279,Peripheral Domain Access Control Word 1" bitfld.long 0xBC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xBC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC0 "PDAC_W0_280,Peripheral Domain Access Control Word 0" bitfld.long 0xC0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC4 "PDAC_W1_280,Peripheral Domain Access Control Word 1" bitfld.long 0xC4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC8 "PDAC_W0_281,Peripheral Domain Access Control Word 0" bitfld.long 0xC8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xCC "PDAC_W1_281,Peripheral Domain Access Control Word 1" bitfld.long 0xCC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xCC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD0 "PDAC_W0_282,Peripheral Domain Access Control Word 0" bitfld.long 0xD0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xD4 "PDAC_W1_282,Peripheral Domain Access Control Word 1" bitfld.long 0xD4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xD4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD8 "PDAC_W0_283,Peripheral Domain Access Control Word 0" bitfld.long 0xD8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xDC "PDAC_W1_283,Peripheral Domain Access Control Word 1" bitfld.long 0xDC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xDC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE0 "PDAC_W0_284,Peripheral Domain Access Control Word 0" bitfld.long 0xE0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xE4 "PDAC_W1_284,Peripheral Domain Access Control Word 1" bitfld.long 0xE4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xE4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE8 "PDAC_W0_285,Peripheral Domain Access Control Word 0" bitfld.long 0xE8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xEC "PDAC_W1_285,Peripheral Domain Access Control Word 1" bitfld.long 0xEC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xEC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF0 "PDAC_W0_286,Peripheral Domain Access Control Word 0" bitfld.long 0xF0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xF4 "PDAC_W1_286,Peripheral Domain Access Control Word 1" bitfld.long 0xF4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xF4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF8 "PDAC_W0_287,Peripheral Domain Access Control Word 0" bitfld.long 0xF8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xFC "PDAC_W1_287,Peripheral Domain Access Control Word 1" bitfld.long 0xFC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xFC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1C00++0x77 line.long 0x0 "PDAC_W0_384,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_384,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_385,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_385,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_386,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_386,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_387,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_387,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_388,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_388,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_389,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_389,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_390,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_390,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_391,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_391,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_392,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_392,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_393,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_393,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_394,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_394,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x58 "PDAC_W0_395,Peripheral Domain Access Control Word 0" bitfld.long 0x58 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x58 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x58 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x5C "PDAC_W1_395,Peripheral Domain Access Control Word 1" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x60 "PDAC_W0_396,Peripheral Domain Access Control Word 0" bitfld.long 0x60 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x60 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x60 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x64 "PDAC_W1_396,Peripheral Domain Access Control Word 1" bitfld.long 0x64 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x64 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x68 "PDAC_W0_397,Peripheral Domain Access Control Word 0" bitfld.long 0x68 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x68 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x68 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x6C "PDAC_W1_397,Peripheral Domain Access Control Word 1" bitfld.long 0x6C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x6C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x70 "PDAC_W0_398,Peripheral Domain Access Control Word 0" bitfld.long 0x70 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x70 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x70 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x74 "PDAC_W1_398,Peripheral Domain Access Control Word 1" bitfld.long 0x74 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x74 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1C80++0xF line.long 0x0 "PDAC_W0_400,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_400,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_401,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_401,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1CB0++0x17 line.long 0x0 "PDAC_W0_406,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_406,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_407,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_407,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_408,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_408,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x2000++0xF line.long 0x0 "MRGD_W0_0,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_0,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_0,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_0,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2020++0xF line.long 0x0 "MRGD_W0_1,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_1,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_1,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_1,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2040++0xF line.long 0x0 "MRGD_W0_2,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_2,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_2,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_2,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2060++0xF line.long 0x0 "MRGD_W0_3,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_3,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_3,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_3,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2080++0xF line.long 0x0 "MRGD_W0_4,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_4,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_4,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_4,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x20A0++0xF line.long 0x0 "MRGD_W0_5,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_5,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_5,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_5,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x20C0++0xF line.long 0x0 "MRGD_W0_6,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_6,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_6,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_6,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x20E0++0xF line.long 0x0 "MRGD_W0_7,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_7,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_7,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_7,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2100++0xF line.long 0x0 "MRGD_W0_8,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_8,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_8,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_8,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2120++0xF line.long 0x0 "MRGD_W0_9,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_9,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_9,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_9,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2140++0xF line.long 0x0 "MRGD_W0_10,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_10,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_10,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_10,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2160++0xF line.long 0x0 "MRGD_W0_11,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_11,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_11,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_11,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2180++0xF line.long 0x0 "MRGD_W0_12,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_12,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_12,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_12,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x21A0++0xF line.long 0x0 "MRGD_W0_13,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_13,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_13,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_13,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x21C0++0xF line.long 0x0 "MRGD_W0_14,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_14,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_14,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_14,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x21E0++0xF line.long 0x0 "MRGD_W0_15,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_15,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_15,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_15,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2400++0xF line.long 0x0 "MRGD_W0_32,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_32,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_32,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_32,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2420++0xF line.long 0x0 "MRGD_W0_33,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_33,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_33,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_33,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2440++0xF line.long 0x0 "MRGD_W0_34,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_34,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_34,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_34,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2460++0xF line.long 0x0 "MRGD_W0_35,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_35,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_35,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_35,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2480++0xF line.long 0x0 "MRGD_W0_36,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_36,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_36,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_36,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x24A0++0xF line.long 0x0 "MRGD_W0_37,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_37,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_37,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_37,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x24C0++0xF line.long 0x0 "MRGD_W0_38,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_38,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_38,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_38,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x24E0++0xF line.long 0x0 "MRGD_W0_39,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_39,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_39,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_39,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2500++0xF line.long 0x0 "MRGD_W0_40,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_40,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_40,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_40,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2520++0xF line.long 0x0 "MRGD_W0_41,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_41,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_41,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_41,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2540++0xF line.long 0x0 "MRGD_W0_42,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_42,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_42,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_42,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2560++0xF line.long 0x0 "MRGD_W0_43,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_43,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_43,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_43,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2580++0xF line.long 0x0 "MRGD_W0_44,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_44,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_44,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_44,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x25A0++0xF line.long 0x0 "MRGD_W0_45,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_45,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_45,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_45,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x25C0++0xF line.long 0x0 "MRGD_W0_46,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_46,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_46,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_46,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x25E0++0xF line.long 0x0 "MRGD_W0_47,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_47,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_47,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_47,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2600++0xF line.long 0x0 "MRGD_W0_48,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_48,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_48,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_48,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2620++0xF line.long 0x0 "MRGD_W0_49,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_49,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_49,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_49,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2640++0xF line.long 0x0 "MRGD_W0_50,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_50,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_50,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_50,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2660++0xF line.long 0x0 "MRGD_W0_51,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_51,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_51,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_51,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2680++0xF line.long 0x0 "MRGD_W0_52,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_52,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_52,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_52,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x26A0++0xF line.long 0x0 "MRGD_W0_53,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_53,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_53,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_53,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x26C0++0xF line.long 0x0 "MRGD_W0_54,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_54,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_54,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_54,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x26E0++0xF line.long 0x0 "MRGD_W0_55,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_55,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_55,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_55,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2700++0xF line.long 0x0 "MRGD_W0_56,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_56,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_56,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_56,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2720++0xF line.long 0x0 "MRGD_W0_57,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_57,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_57,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_57,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2740++0xF line.long 0x0 "MRGD_W0_58,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_58,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_58,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_58,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2760++0xF line.long 0x0 "MRGD_W0_59,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_59,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_59,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_59,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2780++0xF line.long 0x0 "MRGD_W0_60,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_60,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_60,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_60,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x27A0++0xF line.long 0x0 "MRGD_W0_61,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_61,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_61,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_61,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x27C0++0xF line.long 0x0 "MRGD_W0_62,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_62,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_62,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_62,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x27E0++0xF line.long 0x0 "MRGD_W0_63,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_63,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_63,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_63,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2800++0xF line.long 0x0 "MRGD_W0_64,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_64,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_64,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_64,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2820++0xF line.long 0x0 "MRGD_W0_65,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_65,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_65,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_65,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2840++0xF line.long 0x0 "MRGD_W0_66,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_66,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_66,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_66,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2860++0xF line.long 0x0 "MRGD_W0_67,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_67,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_67,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_67,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2880++0xF line.long 0x0 "MRGD_W0_68,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_68,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_68,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_68,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x28A0++0xF line.long 0x0 "MRGD_W0_69,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_69,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_69,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_69,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x28C0++0xF line.long 0x0 "MRGD_W0_70,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_70,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_70,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_70,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x28E0++0xF line.long 0x0 "MRGD_W0_71,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_71,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_71,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_71,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2900++0xF line.long 0x0 "MRGD_W0_72,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_72,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_72,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_72,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2920++0xF line.long 0x0 "MRGD_W0_73,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_73,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_73,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_73,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2940++0xF line.long 0x0 "MRGD_W0_74,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_74,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_74,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_74,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2960++0xF line.long 0x0 "MRGD_W0_75,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_75,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_75,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_75,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2980++0xF line.long 0x0 "MRGD_W0_76,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_76,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_76,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_76,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x29A0++0xF line.long 0x0 "MRGD_W0_77,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_77,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_77,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_77,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x29C0++0xF line.long 0x0 "MRGD_W0_78,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_78,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_78,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_78,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x29E0++0xF line.long 0x0 "MRGD_W0_79,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_79,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_79,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_79,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2A00++0xF line.long 0x0 "MRGD_W0_80,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_80,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_80,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_80,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2A20++0xF line.long 0x0 "MRGD_W0_81,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_81,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_81,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_81,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2A40++0xF line.long 0x0 "MRGD_W0_82,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_82,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_82,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_82,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2A60++0xF line.long 0x0 "MRGD_W0_83,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_83,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_83,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_83,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2A80++0xF line.long 0x0 "MRGD_W0_84,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_84,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_84,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_84,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2AA0++0xF line.long 0x0 "MRGD_W0_85,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_85,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_85,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_85,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2AC0++0xF line.long 0x0 "MRGD_W0_86,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_86,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_86,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_86,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2AE0++0xF line.long 0x0 "MRGD_W0_87,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_87,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_87,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_87,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2B00++0xF line.long 0x0 "MRGD_W0_88,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_88,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_88,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_88,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2B20++0xF line.long 0x0 "MRGD_W0_89,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_89,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_89,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_89,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2B40++0xF line.long 0x0 "MRGD_W0_90,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_90,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_90,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_90,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2B60++0xF line.long 0x0 "MRGD_W0_91,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_91,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_91,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_91,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2B80++0xF line.long 0x0 "MRGD_W0_92,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_92,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_92,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_92,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2BA0++0xF line.long 0x0 "MRGD_W0_93,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_93,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_93,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_93,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2BC0++0xF line.long 0x0 "MRGD_W0_94,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_94,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_94,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_94,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2BE0++0xF line.long 0x0 "MRGD_W0_95,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_95,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_95,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_95,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2C00++0xF line.long 0x0 "MRGD_W0_96,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_96,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_96,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_96,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2C20++0xF line.long 0x0 "MRGD_W0_97,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_97,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_97,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_97,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2C40++0xF line.long 0x0 "MRGD_W0_98,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_98,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_98,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_98,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2C60++0xF line.long 0x0 "MRGD_W0_99,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_99,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_99,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_99,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2C80++0xF line.long 0x0 "MRGD_W0_100,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_100,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_100,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_100,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2CA0++0xF line.long 0x0 "MRGD_W0_101,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_101,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_101,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_101,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2CC0++0xF line.long 0x0 "MRGD_W0_102,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_102,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_102,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_102,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2CE0++0xF line.long 0x0 "MRGD_W0_103,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_103,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_103,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_103,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2D00++0xF line.long 0x0 "MRGD_W0_104,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_104,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_104,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_104,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2D20++0xF line.long 0x0 "MRGD_W0_105,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_105,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_105,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_105,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2D40++0xF line.long 0x0 "MRGD_W0_106,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_106,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_106,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_106,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2D60++0xF line.long 0x0 "MRGD_W0_107,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_107,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_107,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_107,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2D80++0xF line.long 0x0 "MRGD_W0_108,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_108,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_108,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_108,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2DA0++0xF line.long 0x0 "MRGD_W0_109,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_109,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_109,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_109,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2DC0++0xF line.long 0x0 "MRGD_W0_110,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_110,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_110,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_110,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2DE0++0xF line.long 0x0 "MRGD_W0_111,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_111,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_111,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_111,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2E00++0xF line.long 0x0 "MRGD_W0_112,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_112,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_112,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_112,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2E20++0xF line.long 0x0 "MRGD_W0_113,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_113,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_113,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_113,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2E40++0xF line.long 0x0 "MRGD_W0_114,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_114,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_114,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_114,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2E60++0xF line.long 0x0 "MRGD_W0_115,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_115,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_115,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_115,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2E80++0xF line.long 0x0 "MRGD_W0_116,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_116,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_116,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_116,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2EA0++0xF line.long 0x0 "MRGD_W0_117,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_117,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_117,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_117,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2EC0++0xF line.long 0x0 "MRGD_W0_118,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_118,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_118,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_118,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2EE0++0xF line.long 0x0 "MRGD_W0_119,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_119,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_119,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_119,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2F00++0xF line.long 0x0 "MRGD_W0_120,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_120,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_120,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_120,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2F20++0xF line.long 0x0 "MRGD_W0_121,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_121,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_121,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_121,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2F40++0xF line.long 0x0 "MRGD_W0_122,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_122,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_122,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_122,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2F60++0xF line.long 0x0 "MRGD_W0_123,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_123,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_123,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_123,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2F80++0xF line.long 0x0 "MRGD_W0_124,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_124,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_124,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_124,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2FA0++0xF line.long 0x0 "MRGD_W0_125,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_125,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_125,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_125,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2FC0++0xF line.long 0x0 "MRGD_W0_126,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_126,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_126,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_126,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2FE0++0xF line.long 0x0 "MRGD_W0_127,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_127,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_127,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_127,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3000++0xF line.long 0x0 "MRGD_W0_128,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_128,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_128,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_128,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3020++0xF line.long 0x0 "MRGD_W0_129,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_129,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_129,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_129,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3040++0xF line.long 0x0 "MRGD_W0_130,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_130,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_130,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_130,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3060++0xF line.long 0x0 "MRGD_W0_131,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_131,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_131,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_131,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3080++0xF line.long 0x0 "MRGD_W0_132,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_132,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_132,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_132,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x30A0++0xF line.long 0x0 "MRGD_W0_133,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_133,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_133,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_133,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x30C0++0xF line.long 0x0 "MRGD_W0_134,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_134,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_134,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_134,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x30E0++0xF line.long 0x0 "MRGD_W0_135,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_135,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_135,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_135,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3100++0xF line.long 0x0 "MRGD_W0_136,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_136,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_136,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_136,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3120++0xF line.long 0x0 "MRGD_W0_137,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_137,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_137,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_137,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3140++0xF line.long 0x0 "MRGD_W0_138,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_138,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_138,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_138,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3160++0xF line.long 0x0 "MRGD_W0_139,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_139,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_139,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_139,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3180++0xF line.long 0x0 "MRGD_W0_140,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_140,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_140,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_140,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x31A0++0xF line.long 0x0 "MRGD_W0_141,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_141,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_141,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_141,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x31C0++0xF line.long 0x0 "MRGD_W0_142,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_142,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_142,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_142,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x31E0++0xF line.long 0x0 "MRGD_W0_143,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_143,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_143,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_143,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3200++0xF line.long 0x0 "MRGD_W0_144,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_144,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_144,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_144,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3220++0xF line.long 0x0 "MRGD_W0_145,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_145,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_145,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_145,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3240++0xF line.long 0x0 "MRGD_W0_146,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_146,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_146,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_146,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3260++0xF line.long 0x0 "MRGD_W0_147,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_147,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_147,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_147,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3280++0xF line.long 0x0 "MRGD_W0_148,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_148,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_148,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_148,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x32A0++0xF line.long 0x0 "MRGD_W0_149,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_149,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_149,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_149,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x32C0++0xF line.long 0x0 "MRGD_W0_150,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_150,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_150,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_150,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x32E0++0xF line.long 0x0 "MRGD_W0_151,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_151,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_151,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_151,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3300++0xF line.long 0x0 "MRGD_W0_152,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_152,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_152,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_152,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3320++0xF line.long 0x0 "MRGD_W0_153,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_153,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_153,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_153,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3340++0xF line.long 0x0 "MRGD_W0_154,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_154,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_154,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_154,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3360++0xF line.long 0x0 "MRGD_W0_155,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_155,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_155,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_155,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3380++0xF line.long 0x0 "MRGD_W0_156,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_156,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_156,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_156,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x33A0++0xF line.long 0x0 "MRGD_W0_157,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_157,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_157,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_157,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x33C0++0xF line.long 0x0 "MRGD_W0_158,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_158,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_158,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_158,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x33E0++0xF line.long 0x0 "MRGD_W0_159,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_159,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_159,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_159,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3400++0xF line.long 0x0 "MRGD_W0_160,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_160,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_160,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_160,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3420++0xF line.long 0x0 "MRGD_W0_161,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_161,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_161,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_161,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3440++0xF line.long 0x0 "MRGD_W0_162,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_162,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_162,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_162,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3460++0xF line.long 0x0 "MRGD_W0_163,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_163,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_163,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_163,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3480++0xF line.long 0x0 "MRGD_W0_164,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_164,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_164,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_164,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x34A0++0xF line.long 0x0 "MRGD_W0_165,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_165,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_165,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_165,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x34C0++0xF line.long 0x0 "MRGD_W0_166,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_166,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_166,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_166,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x34E0++0xF line.long 0x0 "MRGD_W0_167,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_167,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_167,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_167,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3500++0xF line.long 0x0 "MRGD_W0_168,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_168,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_168,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_168,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3520++0xF line.long 0x0 "MRGD_W0_169,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_169,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_169,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_169,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3540++0xF line.long 0x0 "MRGD_W0_170,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_170,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_170,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_170,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3560++0xF line.long 0x0 "MRGD_W0_171,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_171,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_171,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_171,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3580++0xF line.long 0x0 "MRGD_W0_172,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_172,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_172,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_172,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x35A0++0xF line.long 0x0 "MRGD_W0_173,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_173,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_173,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_173,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x35C0++0xF line.long 0x0 "MRGD_W0_174,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_174,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_174,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_174,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x35E0++0xF line.long 0x0 "MRGD_W0_175,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_175,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_175,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_175,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3600++0xF line.long 0x0 "MRGD_W0_176,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_176,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_176,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_176,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3620++0xF line.long 0x0 "MRGD_W0_177,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_177,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_177,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_177,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3640++0xF line.long 0x0 "MRGD_W0_178,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_178,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_178,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_178,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3660++0xF line.long 0x0 "MRGD_W0_179,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_179,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_179,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_179,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3680++0xF line.long 0x0 "MRGD_W0_180,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_180,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_180,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_180,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x36A0++0xF line.long 0x0 "MRGD_W0_181,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_181,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_181,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_181,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x36C0++0xF line.long 0x0 "MRGD_W0_182,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_182,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_182,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_182,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x36E0++0xF line.long 0x0 "MRGD_W0_183,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_183,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_183,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_183,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3700++0xF line.long 0x0 "MRGD_W0_184,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_184,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_184,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_184,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3720++0xF line.long 0x0 "MRGD_W0_185,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_185,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_185,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_185,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3740++0xF line.long 0x0 "MRGD_W0_186,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_186,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_186,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_186,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3760++0xF line.long 0x0 "MRGD_W0_187,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_187,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_187,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_187,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3800++0xF line.long 0x0 "MRGD_W0_192,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_192,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_192,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_192,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3820++0xF line.long 0x0 "MRGD_W0_193,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_193,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_193,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_193,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3840++0xF line.long 0x0 "MRGD_W0_194,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_194,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_194,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_194,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3860++0xF line.long 0x0 "MRGD_W0_195,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_195,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_195,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_195,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3A00++0xF line.long 0x0 "MRGD_W0_208,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_208,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_208,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_208,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3A20++0xF line.long 0x0 "MRGD_W0_209,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_209,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_209,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_209,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3A40++0xF line.long 0x0 "MRGD_W0_210,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_210,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_210,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_210,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3A60++0xF line.long 0x0 "MRGD_W0_211,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_211,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_211,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_211,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3A80++0xF line.long 0x0 "MRGD_W0_212,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_212,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_212,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_212,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3AA0++0xF line.long 0x0 "MRGD_W0_213,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_213,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_213,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_213,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3AC0++0xF line.long 0x0 "MRGD_W0_214,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_214,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_214,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_214,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3AE0++0xF line.long 0x0 "MRGD_W0_215,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_215,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_215,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_215,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3B00++0xF line.long 0x0 "MRGD_W0_216,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_216,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_216,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_216,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3B20++0xF line.long 0x0 "MRGD_W0_217,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_217,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_217,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_217,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3B40++0xF line.long 0x0 "MRGD_W0_218,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_218,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_218,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_218,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3B60++0xF line.long 0x0 "MRGD_W0_219,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_219,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_219,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_219,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3B80++0xF line.long 0x0 "MRGD_W0_220,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_220,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_220,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_220,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3BA0++0xF line.long 0x0 "MRGD_W0_221,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_221,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_221,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_221,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3BC0++0xF line.long 0x0 "MRGD_W0_222,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_222,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_222,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_222,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x3BE0++0xF line.long 0x0 "MRGD_W0_223,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_223,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_223,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_223,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" tree.end tree "XRDC_1" base ad:0x44004000 group.long 0x0++0x3 line.long 0x0 "CR,Control" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" rbitfld.long 0x0 8. "VAW,Virtualization Aware" "0: Not virtualization-aware,1: Virtualization-aware" newline rbitfld.long 0x0 7. "MRF,Memory Region Format" "?,1: SMPU family format" hexmask.long.byte 0x0 1.--4. 1. "HRL,Hardware Revision Level" newline bitfld.long 0x0 0. "GVLD,Global Valid (XRDC Global Enable/Disable)" "0: Disables,1: Enables" rgroup.long 0xF0++0xB line.long 0x0 "HWCFG0,Hardware Configuration 0" hexmask.long.byte 0x0 28.--31. 1. "MID,Module ID" hexmask.long.byte 0x0 24.--27. 1. "NPAC,Number Of PACs" newline hexmask.long.byte 0x0 16.--23. 1. "NMRC,Number of MRCs" hexmask.long.byte 0x0 8.--15. 1. "NMSTR,Number Of Bus Masters" newline hexmask.long.byte 0x0 0.--7. 1. "NDID,Number Of DIDs" line.long 0x4 "HWCFG1,Hardware Configuration 1" hexmask.long.byte 0x4 0.--3. 1. "DID,Domain Identifier" line.long 0x8 "HWCFG2,Hardware Configuration 2" bitfld.long 0x8 31. "PIDP31,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 30. "PIDP30,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 29. "PIDP29,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 28. "PIDP28,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 27. "PIDP27,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 26. "PIDP26,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 25. "PIDP25,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 24. "PIDP24,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 23. "PIDP23,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 22. "PIDP22,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 21. "PIDP21,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 20. "PIDP20,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 19. "PIDP19,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 18. "PIDP18,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 17. "PIDP17,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 16. "PIDP16,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 15. "PIDP15,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 14. "PIDP14,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 13. "PIDP13,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 12. "PIDP12,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 11. "PIDP11,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 10. "PIDP10,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 9. "PIDP9,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 8. "PIDP8,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 7. "PIDP7,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 6. "PIDP6,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 5. "PIDP5,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 4. "PIDP4,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 3. "PIDP3,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 2. "PIDP2,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 1. "PIDP1,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 0. "PIDP0,Process Identifier Present" "0: Does not have PID register,1: Has PID register" rgroup.byte 0x100++0x7 line.byte 0x0 "MDACFG0,Master Domain Assignment Configuration" bitfld.byte 0x0 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x0 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x1 "MDACFG1,Master Domain Assignment Configuration" bitfld.byte 0x1 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x1 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x2 "MDACFG2,Master Domain Assignment Configuration" bitfld.byte 0x2 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x2 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x3 "MDACFG3,Master Domain Assignment Configuration" bitfld.byte 0x3 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x3 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x4 "MDACFG4,Master Domain Assignment Configuration" bitfld.byte 0x4 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x4 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x5 "MDACFG5,Master Domain Assignment Configuration" bitfld.byte 0x5 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x5 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x6 "MDACFG6,Master Domain Assignment Configuration" bitfld.byte 0x6 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x6 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x7 "MDACFG7,Master Domain Assignment Configuration" bitfld.byte 0x7 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x7 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" rgroup.byte 0x140++0x5 line.byte 0x0 "MRCFG0,Memory Region Configuration" hexmask.byte 0x0 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x1 "MRCFG1,Memory Region Configuration" hexmask.byte 0x1 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x2 "MRCFG2,Memory Region Configuration" hexmask.byte 0x2 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x3 "MRCFG3,Memory Region Configuration" hexmask.byte 0x3 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x4 "MRCFG4,Memory Region Configuration" hexmask.byte 0x4 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x5 "MRCFG5,Memory Region Configuration" hexmask.byte 0x5 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x200)++0x3 line.long 0x0 "DERRLOC[$1],Domain Error Location" hexmask.long.byte 0x0 16.--19. 1. "PACINST,PAC Instance" hexmask.long.word 0x0 0.--15. 1. "MRCINST,MRC Instance" repeat.end rgroup.long 0x400++0xB line.long 0x0 "DERR_W0_0,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_0,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_0,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x40C++0x3 line.long 0x0 "DERR_W3_0,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x410++0xB line.long 0x0 "DERR_W0_1,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_1,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_1,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x41C++0x3 line.long 0x0 "DERR_W3_1,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x420++0xB line.long 0x0 "DERR_W0_2,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_2,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_2,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x42C++0x3 line.long 0x0 "DERR_W3_2,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x430++0xB line.long 0x0 "DERR_W0_3,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_3,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_3,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x43C++0x3 line.long 0x0 "DERR_W3_3,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x440++0xB line.long 0x0 "DERR_W0_4,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_4,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_4,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x44C++0x3 line.long 0x0 "DERR_W3_4,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x450++0xB line.long 0x0 "DERR_W0_5,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_5,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_5,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x45C++0x3 line.long 0x0 "DERR_W3_5,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x500++0xB line.long 0x0 "DERR_W0_16,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_16,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "EA40FMT,Error Address 40-bit Format" "0: 32-bit format,1: 40-bit format" bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" newline bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" line.long 0x8 "DERR_W2_16,Domain Error Word 2" hexmask.long.byte 0x8 0.--7. 1. "EADDR39_32,EADDR Bits 39-32" group.long 0x50C++0x3 line.long 0x0 "DERR_W3_16,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" group.long 0x800++0x3 line.long 0x0 "MDA_W0_0_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x820++0x3 line.long 0x0 "MDA_W0_1_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x840++0x3 line.long 0x0 "MDA_W0_2_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x860++0x3 line.long 0x0 "MDA_W0_3_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x880++0x3 line.long 0x0 "MDA_W0_4_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x8A0++0x3 line.long 0x0 "MDA_W0_5_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x8C0++0x3 line.long 0x0 "MDA_W0_6_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x8E0++0x3 line.long 0x0 "MDA_W0_7_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7F line.long 0x0 "PDAC_W0_0,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_0,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_1,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_1,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_2,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_2,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_3,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_3,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_4,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_4,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_5,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_5,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_6,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_6,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_7,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_7,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_8,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_8,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_9,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_9,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_10,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_10,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x58 "PDAC_W0_11,Peripheral Domain Access Control Word 0" bitfld.long 0x58 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x58 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x58 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x5C "PDAC_W1_11,Peripheral Domain Access Control Word 1" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x60 "PDAC_W0_12,Peripheral Domain Access Control Word 0" bitfld.long 0x60 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x60 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x60 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x64 "PDAC_W1_12,Peripheral Domain Access Control Word 1" bitfld.long 0x64 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x64 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x68 "PDAC_W0_13,Peripheral Domain Access Control Word 0" bitfld.long 0x68 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x68 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x68 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x6C "PDAC_W1_13,Peripheral Domain Access Control Word 1" bitfld.long 0x6C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x6C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x70 "PDAC_W0_14,Peripheral Domain Access Control Word 0" bitfld.long 0x70 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x70 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x70 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x74 "PDAC_W1_14,Peripheral Domain Access Control Word 1" bitfld.long 0x74 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x74 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x78 "PDAC_W0_15,Peripheral Domain Access Control Word 0" bitfld.long 0x78 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x78 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x78 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x7C "PDAC_W1_15,Peripheral Domain Access Control Word 1" bitfld.long 0x7C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x7C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x2000++0xF line.long 0x0 "MRGD_W0_0,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_0,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_0,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_0,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2020++0xF line.long 0x0 "MRGD_W0_1,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_1,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_1,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_1,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2040++0xF line.long 0x0 "MRGD_W0_2,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_2,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_2,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_2,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2060++0xF line.long 0x0 "MRGD_W0_3,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_3,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_3,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_3,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2200++0xF line.long 0x0 "MRGD_W0_16,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_16,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_16,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_16,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2220++0xF line.long 0x0 "MRGD_W0_17,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_17,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_17,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_17,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2240++0xF line.long 0x0 "MRGD_W0_18,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_18,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_18,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_18,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2260++0xF line.long 0x0 "MRGD_W0_19,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_19,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_19,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_19,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2400++0xF line.long 0x0 "MRGD_W0_32,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_32,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_32,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_32,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2420++0xF line.long 0x0 "MRGD_W0_33,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_33,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_33,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_33,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2440++0xF line.long 0x0 "MRGD_W0_34,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_34,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_34,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_34,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2460++0xF line.long 0x0 "MRGD_W0_35,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_35,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_35,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_35,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2480++0xF line.long 0x0 "MRGD_W0_36,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_36,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_36,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_36,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x24A0++0xF line.long 0x0 "MRGD_W0_37,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_37,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_37,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_37,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x24C0++0xF line.long 0x0 "MRGD_W0_38,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_38,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_38,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_38,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x24E0++0xF line.long 0x0 "MRGD_W0_39,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_39,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_39,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_39,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2500++0xF line.long 0x0 "MRGD_W0_40,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_40,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_40,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_40,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2520++0xF line.long 0x0 "MRGD_W0_41,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_41,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_41,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_41,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2540++0xF line.long 0x0 "MRGD_W0_42,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_42,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_42,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_42,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2560++0xF line.long 0x0 "MRGD_W0_43,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_43,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_43,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_43,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2580++0xF line.long 0x0 "MRGD_W0_44,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_44,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_44,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_44,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x25A0++0xF line.long 0x0 "MRGD_W0_45,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_45,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_45,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_45,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x25C0++0xF line.long 0x0 "MRGD_W0_46,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_46,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_46,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_46,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x25E0++0xF line.long 0x0 "MRGD_W0_47,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_47,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_47,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_47,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2600++0xF line.long 0x0 "MRGD_W0_48,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_48,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_48,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_48,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2620++0xF line.long 0x0 "MRGD_W0_49,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_49,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_49,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_49,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2640++0xF line.long 0x0 "MRGD_W0_50,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_50,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_50,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_50,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2660++0xF line.long 0x0 "MRGD_W0_51,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_51,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_51,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_51,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2800++0xF line.long 0x0 "MRGD_W0_64,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_64,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_64,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_64,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2820++0xF line.long 0x0 "MRGD_W0_65,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_65,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_65,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_65,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2840++0xF line.long 0x0 "MRGD_W0_66,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_66,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_66,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_66,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2860++0xF line.long 0x0 "MRGD_W0_67,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_67,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_67,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_67,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2A00++0xF line.long 0x0 "MRGD_W0_80,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_80,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_80,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_80,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2A20++0xF line.long 0x0 "MRGD_W0_81,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_81,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_81,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_81,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2A40++0xF line.long 0x0 "MRGD_W0_82,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_82,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_82,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_82,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2A60++0xF line.long 0x0 "MRGD_W0_83,Memory Region Descriptor Word 0" hexmask.long 0x0 1.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_83,Memory Region Descriptor Word 1" hexmask.long 0x4 1.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_83,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_83,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" tree.end tree.end AUTOINDENT.OFF