; -------------------------------------------------------------------------------- ; @Title: RP2040 On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2022-09-01 KRZ ; @Manufacturer: Raspberry Pi (Trading) Ltd. ; @Doc: SVD generated (SVD2PER 1.8.6), based on: rp2040.svd (Ver. 0.1) ; @Core: Cortex-M0+ ; @Chip: RP2040 ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perrp2040.per 15175 2022-09-01 11:21:47Z kwisniewski $ tree.close "Core Registers (Cortex-M0+)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end autoindent.on center tree tree "ADC (Analog to Digital Converter)" base ad:0x4004C000 group.long 0x00++0x03 line.long 0x00 "CS,ADC Control and Status" bitfld.long 0x00 16.--20. "RROBIN,Round-robin sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--14. "AINSEL,Select analog mux input" "0,1,2,3,4,5,6,7" eventfld.long 0x00 10. "ERR_STICKY,Some past ADC conversion encountered an error" "0,1" rbitfld.long 0x00 9. "ERR,The most recent ADC conversion encountered an error result is undefined or noisy" "0,1" rbitfld.long 0x00 8. "READY,1 if the ADC is ready to start a new conversion" "0,1" bitfld.long 0x00 3. "START_MANY,Continuously perform conversions whilst this bit is 1" "0,1" bitfld.long 0x00 2. "START_ONCE,Start a single conversion" "0,1" bitfld.long 0x00 1. "TS_EN,Power on temperature sensor" "0: disabled,1: enabled" bitfld.long 0x00 0. "EN,Power on ADC and enable its clock.\n" "0: disabled,1: enabled" group.long 0x04++0x03 line.long 0x00 "RESULT,Result of most recent ADC conversion" hexmask.long.word 0x00 0.--11. 1. "RESULT," group.long 0x08++0x03 line.long 0x00 "FCS,FIFO control and status" bitfld.long 0x00 24.--27. "THRESH,DREQ/IRQ asserted when level >= threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. "LEVEL,The number of conversion results currently waiting in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" eventfld.long 0x00 11. "OVER,1 if the FIFO has been overflowed" "0,1" eventfld.long 0x00 10. "UNDER,1 if the FIFO has been underflowed" "0,1" rbitfld.long 0x00 9. "FULL," "0,1" rbitfld.long 0x00 8. "EMPTY," "0,1" bitfld.long 0x00 3. "DREQ_EN,If" "0,1" bitfld.long 0x00 2. "ERR,If" "0,1" bitfld.long 0x00 1. "SHIFT,If" "0,1" newline bitfld.long 0x00 0. "EN,If" "0,1" group.long 0x0C++0x03 line.long 0x00 "FIFO,Conversion result FIFO" rbitfld.long 0x00 15. "ERR,1 if this particular sample experienced a conversion error" "0,1" hexmask.long.word 0x00 0.--11. 1. "VAL," group.long 0x10++0x03 line.long 0x00 "DIV,Clock divider" hexmask.long.word 0x00 8.--23. 1. "INT,Integer part of clock divisor" hexmask.long.byte 0x00 0.--7. 1. "FRAC,Fractional part of clock divisor" group.long 0x14++0x03 line.long 0x00 "INTR,Raw Interrupts" rbitfld.long 0x00 0. "FIFO,Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field" "0,1" group.long 0x18++0x03 line.long 0x00 "INTE,Interrupt Enable" bitfld.long 0x00 0. "FIFO,Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field" "0,1" group.long 0x1C++0x03 line.long 0x00 "INTF,Interrupt Force" bitfld.long 0x00 0. "FIFO,Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field" "0,1" group.long 0x20++0x03 line.long 0x00 "INTS,Interrupt status after masking & forcing" rbitfld.long 0x00 0. "FIFO,Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field" "0,1" tree.end tree "BUSCTRL (Bus Fabric)" base ad:0x40030000 group.long 0x00++0x03 line.long 0x00 "BUS_PRIORITY,Set the priority of each master for bus arbitration" bitfld.long 0x00 12. "DMA_W," "0,1" bitfld.long 0x00 8. "DMA_R," "0,1" bitfld.long 0x00 4. "PROC1," "0,1" bitfld.long 0x00 0. "PROC0," "0,1" group.long 0x04++0x03 line.long 0x00 "BUS_PRIORITY_ACK,Bus priority acknowledge" rbitfld.long 0x00 0. "BUS_PRIORITY_ACK,Goes to 1 once all arbiters have registered the new global priority levels.\n Arbiters update their local priority when servicing a new nonsequential access.\n In normal circumstances this will happen almost immediately" "0,1" group.long 0x08++0x03 line.long 0x00 "PERFCTR0,Bus fabric performance counter 0" hexmask.long.tbyte 0x00 0.--23. 1. "PERFCTR0,Busfabric saturating performance counter 0\n Count some event signal from the busfabric arbiters.\n Write any value to clear" group.long 0x0C++0x03 line.long 0x00 "PERFSEL0,Bus fabric performance event select for PERFCTR0" bitfld.long 0x00 0.--4. "PERFSEL0,Select an event for PERFCTR0" "0: apb_contested,1: UNKN_DESC,2: fastperi_contested,3: UNKN_DESC,4: sram5_contested,5: UNKN_DESC,6: sram4_contested,7: UNKN_DESC,8: sram3_contested,9: UNKN_DESC,10: sram2_contested,11: UNKN_DESC,12: sram1_contested,13: UNKN_DESC,14: sram0_contested,15: UNKN_DESC,16: xip_main_contested,17: UNKN_DESC,18: rom_contested,19: UNKN_DESC,?..." group.long 0x10++0x03 line.long 0x00 "PERFCTR1,Bus fabric performance counter 1" hexmask.long.tbyte 0x00 0.--23. 1. "PERFCTR1,Busfabric saturating performance counter 1\n Count some event signal from the busfabric arbiters.\n Write any value to clear" group.long 0x14++0x03 line.long 0x00 "PERFSEL1,Bus fabric performance event select for PERFCTR1" bitfld.long 0x00 0.--4. "PERFSEL1,Select an event for PERFCTR1" "0: apb_contested,1: UNKN_DESC,2: fastperi_contested,3: UNKN_DESC,4: sram5_contested,5: UNKN_DESC,6: sram4_contested,7: UNKN_DESC,8: sram3_contested,9: UNKN_DESC,10: sram2_contested,11: UNKN_DESC,12: sram1_contested,13: UNKN_DESC,14: sram0_contested,15: UNKN_DESC,16: xip_main_contested,17: UNKN_DESC,18: rom_contested,19: UNKN_DESC,?..." group.long 0x18++0x03 line.long 0x00 "PERFCTR2,Bus fabric performance counter 2" hexmask.long.tbyte 0x00 0.--23. 1. "PERFCTR2,Busfabric saturating performance counter 2\n Count some event signal from the busfabric arbiters.\n Write any value to clear" group.long 0x1C++0x03 line.long 0x00 "PERFSEL2,Bus fabric performance event select for PERFCTR2" bitfld.long 0x00 0.--4. "PERFSEL2,Select an event for PERFCTR2" "0: apb_contested,1: UNKN_DESC,2: fastperi_contested,3: UNKN_DESC,4: sram5_contested,5: UNKN_DESC,6: sram4_contested,7: UNKN_DESC,8: sram3_contested,9: UNKN_DESC,10: sram2_contested,11: UNKN_DESC,12: sram1_contested,13: UNKN_DESC,14: sram0_contested,15: UNKN_DESC,16: xip_main_contested,17: UNKN_DESC,18: rom_contested,19: UNKN_DESC,?..." group.long 0x20++0x03 line.long 0x00 "PERFCTR3,Bus fabric performance counter 3" hexmask.long.tbyte 0x00 0.--23. 1. "PERFCTR3,Busfabric saturating performance counter 3\n Count some event signal from the busfabric arbiters.\n Write any value to clear" group.long 0x24++0x03 line.long 0x00 "PERFSEL3,Bus fabric performance event select for PERFCTR3" bitfld.long 0x00 0.--4. "PERFSEL3,Select an event for PERFCTR3" "0: apb_contested,1: UNKN_DESC,2: fastperi_contested,3: UNKN_DESC,4: sram5_contested,5: UNKN_DESC,6: sram4_contested,7: UNKN_DESC,8: sram3_contested,9: UNKN_DESC,10: sram2_contested,11: UNKN_DESC,12: sram1_contested,13: UNKN_DESC,14: sram0_contested,15: UNKN_DESC,16: xip_main_contested,17: UNKN_DESC,18: rom_contested,19: UNKN_DESC,?..." tree.end tree "CLOCKS" base ad:0x40008000 group.long 0x00++0x03 line.long 0x00 "CLK_GPOUT0_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time" "0,1" bitfld.long 0x00 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect" "0,1,2,3" bitfld.long 0x00 12. "DC50,Enables duty cycle correction for odd divisors" "0,1" newline bitfld.long 0x00 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1" bitfld.long 0x00 10. "KILL,Asynchronously kills the clock generator" "0,1" bitfld.long 0x00 5.--8. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: clksrc_pll_sys,1: clksrc_gpin0,2: clksrc_gpin1,3: clksrc_pll_usb,4: rosc_clksrc,5: xosc_clksrc,6: UNKN_DESC,7: UNKN_DESC,8: UNKN_DESC,9: UNKN_DESC,10: UNKN_DESC,?..." group.long 0x04++0x03 line.long 0x00 "CLK_GPOUT0_DIV,Clock divisor can be changed on-the-fly" hexmask.long.tbyte 0x00 8.--31. 1. "INT,Integer component of the divisor 0 -> divide by 2^16" hexmask.long.byte 0x00 0.--7. 1. "FRAC,Fractional component of the divisor" rgroup.long 0x08++0x03 line.long 0x00 "CLK_GPOUT0_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1" group.long 0x0C++0x03 line.long 0x00 "CLK_GPOUT1_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time" "0,1" bitfld.long 0x00 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect" "0,1,2,3" bitfld.long 0x00 12. "DC50,Enables duty cycle correction for odd divisors" "0,1" newline bitfld.long 0x00 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1" bitfld.long 0x00 10. "KILL,Asynchronously kills the clock generator" "0,1" bitfld.long 0x00 5.--8. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: clksrc_pll_sys,1: clksrc_gpin0,2: clksrc_gpin1,3: clksrc_pll_usb,4: rosc_clksrc,5: xosc_clksrc,6: UNKN_DESC,7: UNKN_DESC,8: UNKN_DESC,9: UNKN_DESC,10: UNKN_DESC,?..." group.long 0x10++0x03 line.long 0x00 "CLK_GPOUT1_DIV,Clock divisor can be changed on-the-fly" hexmask.long.tbyte 0x00 8.--31. 1. "INT,Integer component of the divisor 0 -> divide by 2^16" hexmask.long.byte 0x00 0.--7. 1. "FRAC,Fractional component of the divisor" rgroup.long 0x14++0x03 line.long 0x00 "CLK_GPOUT1_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1" group.long 0x18++0x03 line.long 0x00 "CLK_GPOUT2_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time" "0,1" bitfld.long 0x00 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect" "0,1,2,3" bitfld.long 0x00 12. "DC50,Enables duty cycle correction for odd divisors" "0,1" newline bitfld.long 0x00 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1" bitfld.long 0x00 10. "KILL,Asynchronously kills the clock generator" "0,1" bitfld.long 0x00 5.--8. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: clksrc_pll_sys,1: clksrc_gpin0,2: clksrc_gpin1,3: clksrc_pll_usb,4: rosc_clksrc_ph,5: xosc_clksrc,6: UNKN_DESC,7: UNKN_DESC,8: UNKN_DESC,9: UNKN_DESC,10: UNKN_DESC,?..." group.long 0x1C++0x03 line.long 0x00 "CLK_GPOUT2_DIV,Clock divisor can be changed on-the-fly" hexmask.long.tbyte 0x00 8.--31. 1. "INT,Integer component of the divisor 0 -> divide by 2^16" hexmask.long.byte 0x00 0.--7. 1. "FRAC,Fractional component of the divisor" rgroup.long 0x20++0x03 line.long 0x00 "CLK_GPOUT2_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1" group.long 0x24++0x03 line.long 0x00 "CLK_GPOUT3_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time" "0,1" bitfld.long 0x00 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect" "0,1,2,3" bitfld.long 0x00 12. "DC50,Enables duty cycle correction for odd divisors" "0,1" newline bitfld.long 0x00 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1" bitfld.long 0x00 10. "KILL,Asynchronously kills the clock generator" "0,1" bitfld.long 0x00 5.--8. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: clksrc_pll_sys,1: clksrc_gpin0,2: clksrc_gpin1,3: clksrc_pll_usb,4: rosc_clksrc_ph,5: xosc_clksrc,6: UNKN_DESC,7: UNKN_DESC,8: UNKN_DESC,9: UNKN_DESC,10: UNKN_DESC,?..." group.long 0x28++0x03 line.long 0x00 "CLK_GPOUT3_DIV,Clock divisor can be changed on-the-fly" hexmask.long.tbyte 0x00 8.--31. 1. "INT,Integer component of the divisor 0 -> divide by 2^16" hexmask.long.byte 0x00 0.--7. 1. "FRAC,Fractional component of the divisor" rgroup.long 0x2C++0x03 line.long 0x00 "CLK_GPOUT3_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1" group.long 0x30++0x03 line.long 0x00 "CLK_REF_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 5.--6. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: clksrc_pll_usb,1: clksrc_gpin0,2: clksrc_gpin1,?..." bitfld.long 0x00 0.--1. "SRC,Selects the clock source glitchlessly can be changed on-the-fly" "0: rosc_clksrc_ph,1: clksrc_clk_ref_aux,2: xosc_clksrc,?..." group.long 0x34++0x03 line.long 0x00 "CLK_REF_DIV,Clock divisor can be changed on-the-fly" bitfld.long 0x00 8.--9. "INT,Integer component of the divisor 0 -> divide by 2^16" "0,1,2,3" rgroup.long 0x38++0x03 line.long 0x00 "CLK_REF_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n The glitchless multiplexer does not switch instantaneously (to avoid glitches) so software should poll this register to wait for the switch to complete" group.long 0x3C++0x03 line.long 0x00 "CLK_SYS_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: clksrc_pll_sys,1: clksrc_pll_usb,2: rosc_clksrc,3: xosc_clksrc,4: clksrc_gpin0,5: clksrc_gpin1,?..." bitfld.long 0x00 0. "SRC,Selects the clock source glitchlessly can be changed on-the-fly" "0: UNKN_DESC,1: clksrc_clk_sys_aux" group.long 0x40++0x03 line.long 0x00 "CLK_SYS_DIV,Clock divisor can be changed on-the-fly" hexmask.long.tbyte 0x00 8.--31. 1. "INT,Integer component of the divisor 0 -> divide by 2^16" hexmask.long.byte 0x00 0.--7. 1. "FRAC,Fractional component of the divisor" rgroup.long 0x44++0x03 line.long 0x00 "CLK_SYS_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n The glitchless multiplexer does not switch instantaneously (to avoid glitches) so software should poll this register to wait for the switch to complete" group.long 0x48++0x03 line.long 0x00 "CLK_PERI_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1" bitfld.long 0x00 10. "KILL,Asynchronously kills the clock generator" "0,1" bitfld.long 0x00 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: UNKN_DESC,1: clksrc_pll_sys,2: clksrc_pll_usb,3: rosc_clksrc_ph,4: xosc_clksrc,5: clksrc_gpin0,6: clksrc_gpin1,?..." rgroup.long 0x50++0x03 line.long 0x00 "CLK_PERI_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1" group.long 0x54++0x03 line.long 0x00 "CLK_USB_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time" "0,1" bitfld.long 0x00 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect" "0,1,2,3" bitfld.long 0x00 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1" newline bitfld.long 0x00 10. "KILL,Asynchronously kills the clock generator" "0,1" bitfld.long 0x00 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: clksrc_pll_usb,1: clksrc_pll_sys,2: rosc_clksrc_ph,3: xosc_clksrc,4: clksrc_gpin0,5: clksrc_gpin1,?..." group.long 0x58++0x03 line.long 0x00 "CLK_USB_DIV,Clock divisor can be changed on-the-fly" bitfld.long 0x00 8.--9. "INT,Integer component of the divisor 0 -> divide by 2^16" "0,1,2,3" rgroup.long 0x5C++0x03 line.long 0x00 "CLK_USB_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1" group.long 0x60++0x03 line.long 0x00 "CLK_ADC_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time" "0,1" bitfld.long 0x00 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect" "0,1,2,3" bitfld.long 0x00 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1" newline bitfld.long 0x00 10. "KILL,Asynchronously kills the clock generator" "0,1" bitfld.long 0x00 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: clksrc_pll_usb,1: clksrc_pll_sys,2: rosc_clksrc_ph,3: xosc_clksrc,4: clksrc_gpin0,5: clksrc_gpin1,?..." group.long 0x64++0x03 line.long 0x00 "CLK_ADC_DIV,Clock divisor can be changed on-the-fly" bitfld.long 0x00 8.--9. "INT,Integer component of the divisor 0 -> divide by 2^16" "0,1,2,3" rgroup.long 0x68++0x03 line.long 0x00 "CLK_ADC_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1" group.long 0x6C++0x03 line.long 0x00 "CLK_RTC_CTRL,Clock control can be changed on-the-fly (except for auxsrc)" bitfld.long 0x00 20. "NUDGE,An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time" "0,1" bitfld.long 0x00 16.--17. "PHASE,This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect" "0,1,2,3" bitfld.long 0x00 11. "ENABLE,Starts and stops the clock generator cleanly" "0,1" newline bitfld.long 0x00 10. "KILL,Asynchronously kills the clock generator" "0,1" bitfld.long 0x00 5.--7. "AUXSRC,Selects the auxiliary clock source will glitch when switching" "0: clksrc_pll_usb,1: clksrc_pll_sys,2: rosc_clksrc_ph,3: xosc_clksrc,4: clksrc_gpin0,5: clksrc_gpin1,?..." group.long 0x70++0x03 line.long 0x00 "CLK_RTC_DIV,Clock divisor can be changed on-the-fly" hexmask.long.tbyte 0x00 8.--31. 1. "INT,Integer component of the divisor 0 -> divide by 2^16" hexmask.long.byte 0x00 0.--7. 1. "FRAC,Fractional component of the divisor" rgroup.long 0x74++0x03 line.long 0x00 "CLK_RTC_SELECTED,Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present not SRC) so this register is hardwired to 0x1" group.long 0x78++0x03 line.long 0x00 "CLK_SYS_RESUS_CTRL," bitfld.long 0x00 16. "CLEAR,For clearing the resus after the fault that triggered it has been corrected" "0,1" bitfld.long 0x00 12. "FRCE,Force a resus for test purposes only" "0,1" bitfld.long 0x00 8. "ENABLE,Enable resus" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TIMEOUT,This is expressed as a number of clk_ref cycles\n and must be >= 2x clk_ref_freq/min_clk_tst_freq" group.long 0x7C++0x03 line.long 0x00 "CLK_SYS_RESUS_STATUS," rbitfld.long 0x00 0. "RESUSSED,Clock has been resuscitated correct the error then send ctrl_clear=1" "0,1" group.long 0x80++0x03 line.long 0x00 "FC0_REF_KHZ,Reference clock frequency in kHz" hexmask.long.tbyte 0x00 0.--19. 1. "FC0_REF_KHZ," group.long 0x84++0x03 line.long 0x00 "FC0_MIN_KHZ,Minimum pass frequency in kHz" hexmask.long 0x00 0.--24. 1. "FC0_MIN_KHZ," group.long 0x88++0x03 line.long 0x00 "FC0_MAX_KHZ,Maximum pass frequency in kHz" hexmask.long 0x00 0.--24. 1. "FC0_MAX_KHZ," group.long 0x8C++0x03 line.long 0x00 "FC0_DELAY,Delays the start of frequency counting to allow the mux to settle\n Delay is measured in multiples of the reference clock period" bitfld.long 0x00 0.--2. "FC0_DELAY," "0,1,2,3,4,5,6,7" group.long 0x90++0x03 line.long 0x00 "FC0_INTERVAL,The test interval is 0.98us * 2**interval but let's call it 1us * 2**interval\n The default gives a test interval of 250us" bitfld.long 0x00 0.--3. "FC0_INTERVAL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x94++0x03 line.long 0x00 "FC0_SRC,Clock sent to frequency counter set to 0 when not required\n Writing to this register initiates the frequency count" hexmask.long.byte 0x00 0.--7. 1. "FC0_SRC," group.long 0x98++0x03 line.long 0x00 "FC0_STATUS,Frequency counter status" rbitfld.long 0x00 28. "DIED,Test clock stopped during test" "0,1" rbitfld.long 0x00 24. "FAST,Test clock faster than expected only valid when status_done=1" "0,1" rbitfld.long 0x00 20. "SLOW,Test clock slower than expected only valid when status_done=1" "0,1" newline rbitfld.long 0x00 16. "FAIL,Test failed" "0,1" rbitfld.long 0x00 12. "WAITING,Waiting for test clock to start" "0,1" rbitfld.long 0x00 8. "RUNNING,Test running" "0,1" newline rbitfld.long 0x00 4. "DONE,Test complete" "0,1" rbitfld.long 0x00 0. "PASS,Test passed" "0,1" group.long 0x9C++0x03 line.long 0x00 "FC0_RESULT,Result of frequency measurement only valid when status_done=1" hexmask.long 0x00 5.--29. 1. "KHZ," rbitfld.long 0x00 0.--4. "FRAC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA0++0x03 line.long 0x00 "WAKE_EN0,enable clock in wake mode" bitfld.long 0x00 31. "clk_sys_sram3," "0,1" bitfld.long 0x00 30. "clk_sys_sram2," "0,1" bitfld.long 0x00 29. "clk_sys_sram1," "0,1" newline bitfld.long 0x00 28. "clk_sys_sram0," "0,1" bitfld.long 0x00 27. "clk_sys_spi1," "0,1" bitfld.long 0x00 26. "clk_peri_spi1," "0,1" newline bitfld.long 0x00 25. "clk_sys_spi0," "0,1" bitfld.long 0x00 24. "clk_peri_spi0," "0,1" bitfld.long 0x00 23. "clk_sys_sio," "0,1" newline bitfld.long 0x00 22. "clk_sys_rtc," "0,1" bitfld.long 0x00 21. "clk_rtc_rtc," "0,1" bitfld.long 0x00 20. "clk_sys_rosc," "0,1" newline bitfld.long 0x00 19. "clk_sys_rom," "0,1" bitfld.long 0x00 18. "clk_sys_resets," "0,1" bitfld.long 0x00 17. "clk_sys_pwm," "0,1" newline bitfld.long 0x00 16. "clk_sys_psm," "0,1" bitfld.long 0x00 15. "clk_sys_pll_usb," "0,1" bitfld.long 0x00 14. "clk_sys_pll_sys," "0,1" newline bitfld.long 0x00 13. "clk_sys_pio1," "0,1" bitfld.long 0x00 12. "clk_sys_pio0," "0,1" bitfld.long 0x00 11. "clk_sys_pads," "0,1" newline bitfld.long 0x00 10. "clk_sys_vreg_and_chip_reset," "0,1" bitfld.long 0x00 9. "clk_sys_jtag," "0,1" bitfld.long 0x00 8. "clk_sys_io," "0,1" newline bitfld.long 0x00 7. "clk_sys_i2c1," "0,1" bitfld.long 0x00 6. "clk_sys_i2c0," "0,1" bitfld.long 0x00 5. "clk_sys_dma," "0,1" newline bitfld.long 0x00 4. "clk_sys_busfabric," "0,1" bitfld.long 0x00 3. "clk_sys_busctrl," "0,1" bitfld.long 0x00 2. "clk_sys_adc," "0,1" newline bitfld.long 0x00 1. "clk_adc_adc," "0,1" bitfld.long 0x00 0. "clk_sys_clocks," "0,1" group.long 0xA4++0x03 line.long 0x00 "WAKE_EN1,enable clock in wake mode" bitfld.long 0x00 14. "clk_sys_xosc," "0,1" bitfld.long 0x00 13. "clk_sys_xip," "0,1" bitfld.long 0x00 12. "clk_sys_watchdog," "0,1" newline bitfld.long 0x00 11. "clk_usb_usbctrl," "0,1" bitfld.long 0x00 10. "clk_sys_usbctrl," "0,1" bitfld.long 0x00 9. "clk_sys_uart1," "0,1" newline bitfld.long 0x00 8. "clk_peri_uart1," "0,1" bitfld.long 0x00 7. "clk_sys_uart0," "0,1" bitfld.long 0x00 6. "clk_peri_uart0," "0,1" newline bitfld.long 0x00 5. "clk_sys_timer," "0,1" bitfld.long 0x00 4. "clk_sys_tbman," "0,1" bitfld.long 0x00 3. "clk_sys_sysinfo," "0,1" newline bitfld.long 0x00 2. "clk_sys_syscfg," "0,1" bitfld.long 0x00 1. "clk_sys_sram5," "0,1" bitfld.long 0x00 0. "clk_sys_sram4," "0,1" group.long 0xA8++0x03 line.long 0x00 "SLEEP_EN0,enable clock in sleep mode" bitfld.long 0x00 31. "clk_sys_sram3," "0,1" bitfld.long 0x00 30. "clk_sys_sram2," "0,1" bitfld.long 0x00 29. "clk_sys_sram1," "0,1" newline bitfld.long 0x00 28. "clk_sys_sram0," "0,1" bitfld.long 0x00 27. "clk_sys_spi1," "0,1" bitfld.long 0x00 26. "clk_peri_spi1," "0,1" newline bitfld.long 0x00 25. "clk_sys_spi0," "0,1" bitfld.long 0x00 24. "clk_peri_spi0," "0,1" bitfld.long 0x00 23. "clk_sys_sio," "0,1" newline bitfld.long 0x00 22. "clk_sys_rtc," "0,1" bitfld.long 0x00 21. "clk_rtc_rtc," "0,1" bitfld.long 0x00 20. "clk_sys_rosc," "0,1" newline bitfld.long 0x00 19. "clk_sys_rom," "0,1" bitfld.long 0x00 18. "clk_sys_resets," "0,1" bitfld.long 0x00 17. "clk_sys_pwm," "0,1" newline bitfld.long 0x00 16. "clk_sys_psm," "0,1" bitfld.long 0x00 15. "clk_sys_pll_usb," "0,1" bitfld.long 0x00 14. "clk_sys_pll_sys," "0,1" newline bitfld.long 0x00 13. "clk_sys_pio1," "0,1" bitfld.long 0x00 12. "clk_sys_pio0," "0,1" bitfld.long 0x00 11. "clk_sys_pads," "0,1" newline bitfld.long 0x00 10. "clk_sys_vreg_and_chip_reset," "0,1" bitfld.long 0x00 9. "clk_sys_jtag," "0,1" bitfld.long 0x00 8. "clk_sys_io," "0,1" newline bitfld.long 0x00 7. "clk_sys_i2c1," "0,1" bitfld.long 0x00 6. "clk_sys_i2c0," "0,1" bitfld.long 0x00 5. "clk_sys_dma," "0,1" newline bitfld.long 0x00 4. "clk_sys_busfabric," "0,1" bitfld.long 0x00 3. "clk_sys_busctrl," "0,1" bitfld.long 0x00 2. "clk_sys_adc," "0,1" newline bitfld.long 0x00 1. "clk_adc_adc," "0,1" bitfld.long 0x00 0. "clk_sys_clocks," "0,1" group.long 0xAC++0x03 line.long 0x00 "SLEEP_EN1,enable clock in sleep mode" bitfld.long 0x00 14. "clk_sys_xosc," "0,1" bitfld.long 0x00 13. "clk_sys_xip," "0,1" bitfld.long 0x00 12. "clk_sys_watchdog," "0,1" newline bitfld.long 0x00 11. "clk_usb_usbctrl," "0,1" bitfld.long 0x00 10. "clk_sys_usbctrl," "0,1" bitfld.long 0x00 9. "clk_sys_uart1," "0,1" newline bitfld.long 0x00 8. "clk_peri_uart1," "0,1" bitfld.long 0x00 7. "clk_sys_uart0," "0,1" bitfld.long 0x00 6. "clk_peri_uart0," "0,1" newline bitfld.long 0x00 5. "clk_sys_timer," "0,1" bitfld.long 0x00 4. "clk_sys_tbman," "0,1" bitfld.long 0x00 3. "clk_sys_sysinfo," "0,1" newline bitfld.long 0x00 2. "clk_sys_syscfg," "0,1" bitfld.long 0x00 1. "clk_sys_sram5," "0,1" bitfld.long 0x00 0. "clk_sys_sram4," "0,1" group.long 0xB0++0x03 line.long 0x00 "ENABLED0,indicates the state of the clock enable" rbitfld.long 0x00 31. "clk_sys_sram3," "0,1" rbitfld.long 0x00 30. "clk_sys_sram2," "0,1" rbitfld.long 0x00 29. "clk_sys_sram1," "0,1" newline rbitfld.long 0x00 28. "clk_sys_sram0," "0,1" rbitfld.long 0x00 27. "clk_sys_spi1," "0,1" rbitfld.long 0x00 26. "clk_peri_spi1," "0,1" newline rbitfld.long 0x00 25. "clk_sys_spi0," "0,1" rbitfld.long 0x00 24. "clk_peri_spi0," "0,1" rbitfld.long 0x00 23. "clk_sys_sio," "0,1" newline rbitfld.long 0x00 22. "clk_sys_rtc," "0,1" rbitfld.long 0x00 21. "clk_rtc_rtc," "0,1" rbitfld.long 0x00 20. "clk_sys_rosc," "0,1" newline rbitfld.long 0x00 19. "clk_sys_rom," "0,1" rbitfld.long 0x00 18. "clk_sys_resets," "0,1" rbitfld.long 0x00 17. "clk_sys_pwm," "0,1" newline rbitfld.long 0x00 16. "clk_sys_psm," "0,1" rbitfld.long 0x00 15. "clk_sys_pll_usb," "0,1" rbitfld.long 0x00 14. "clk_sys_pll_sys," "0,1" newline rbitfld.long 0x00 13. "clk_sys_pio1," "0,1" rbitfld.long 0x00 12. "clk_sys_pio0," "0,1" rbitfld.long 0x00 11. "clk_sys_pads," "0,1" newline rbitfld.long 0x00 10. "clk_sys_vreg_and_chip_reset," "0,1" rbitfld.long 0x00 9. "clk_sys_jtag," "0,1" rbitfld.long 0x00 8. "clk_sys_io," "0,1" newline rbitfld.long 0x00 7. "clk_sys_i2c1," "0,1" rbitfld.long 0x00 6. "clk_sys_i2c0," "0,1" rbitfld.long 0x00 5. "clk_sys_dma," "0,1" newline rbitfld.long 0x00 4. "clk_sys_busfabric," "0,1" rbitfld.long 0x00 3. "clk_sys_busctrl," "0,1" rbitfld.long 0x00 2. "clk_sys_adc," "0,1" newline rbitfld.long 0x00 1. "clk_adc_adc," "0,1" rbitfld.long 0x00 0. "clk_sys_clocks," "0,1" group.long 0xB4++0x03 line.long 0x00 "ENABLED1,indicates the state of the clock enable" rbitfld.long 0x00 14. "clk_sys_xosc," "0,1" rbitfld.long 0x00 13. "clk_sys_xip," "0,1" rbitfld.long 0x00 12. "clk_sys_watchdog," "0,1" newline rbitfld.long 0x00 11. "clk_usb_usbctrl," "0,1" rbitfld.long 0x00 10. "clk_sys_usbctrl," "0,1" rbitfld.long 0x00 9. "clk_sys_uart1," "0,1" newline rbitfld.long 0x00 8. "clk_peri_uart1," "0,1" rbitfld.long 0x00 7. "clk_sys_uart0," "0,1" rbitfld.long 0x00 6. "clk_peri_uart0," "0,1" newline rbitfld.long 0x00 5. "clk_sys_timer," "0,1" rbitfld.long 0x00 4. "clk_sys_tbman," "0,1" rbitfld.long 0x00 3. "clk_sys_sysinfo," "0,1" newline rbitfld.long 0x00 2. "clk_sys_syscfg," "0,1" rbitfld.long 0x00 1. "clk_sys_sram5," "0,1" rbitfld.long 0x00 0. "clk_sys_sram4," "0,1" group.long 0xB8++0x03 line.long 0x00 "INTR,Raw Interrupts" rbitfld.long 0x00 0. "CLK_SYS_RESUS," "0,1" group.long 0xBC++0x03 line.long 0x00 "INTE,Interrupt Enable" bitfld.long 0x00 0. "CLK_SYS_RESUS," "0,1" group.long 0xC0++0x03 line.long 0x00 "INTF,Interrupt Force" bitfld.long 0x00 0. "CLK_SYS_RESUS," "0,1" group.long 0xC4++0x03 line.long 0x00 "INTS,Interrupt status after masking & forcing" rbitfld.long 0x00 0. "CLK_SYS_RESUS," "0,1" tree.end tree "DMA (Direct Memory Access)" base ad:0x50000000 group.long 0x00++0x03 line.long 0x00 "CH0_READ_ADDR,DMA Channel 0 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x04++0x03 line.long 0x00 "CH0_WRITE_ADDR,DMA Channel 0 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x08++0x03 line.long 0x00 "CH0_TRANS_COUNT,DMA Channel 0 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x0C++0x03 line.long 0x00 "CH0_CTRL_TRIG,DMA Channel 0 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x10++0x03 line.long 0x00 "CH0_AL1_CTRL,Alias for channel 0 CTRL register" group.long 0x14++0x03 line.long 0x00 "CH0_AL1_READ_ADDR,Alias for channel 0 READ_ADDR register" group.long 0x18++0x03 line.long 0x00 "CH0_AL1_WRITE_ADDR,Alias for channel 0 WRITE_ADDR register" group.long 0x1C++0x03 line.long 0x00 "CH0_AL1_TRANS_COUNT_TRIG,Alias for channel 0 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x20++0x03 line.long 0x00 "CH0_AL2_CTRL,Alias for channel 0 CTRL register" group.long 0x24++0x03 line.long 0x00 "CH0_AL2_TRANS_COUNT,Alias for channel 0 TRANS_COUNT register" group.long 0x28++0x03 line.long 0x00 "CH0_AL2_READ_ADDR,Alias for channel 0 READ_ADDR register" group.long 0x2C++0x03 line.long 0x00 "CH0_AL2_WRITE_ADDR_TRIG,Alias for channel 0 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x30++0x03 line.long 0x00 "CH0_AL3_CTRL,Alias for channel 0 CTRL register" group.long 0x34++0x03 line.long 0x00 "CH0_AL3_WRITE_ADDR,Alias for channel 0 WRITE_ADDR register" group.long 0x38++0x03 line.long 0x00 "CH0_AL3_TRANS_COUNT,Alias for channel 0 TRANS_COUNT register" group.long 0x3C++0x03 line.long 0x00 "CH0_AL3_READ_ADDR_TRIG,Alias for channel 0 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x40++0x03 line.long 0x00 "CH1_READ_ADDR,DMA Channel 1 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x44++0x03 line.long 0x00 "CH1_WRITE_ADDR,DMA Channel 1 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x48++0x03 line.long 0x00 "CH1_TRANS_COUNT,DMA Channel 1 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x4C++0x03 line.long 0x00 "CH1_CTRL_TRIG,DMA Channel 1 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x50++0x03 line.long 0x00 "CH1_AL1_CTRL,Alias for channel 1 CTRL register" group.long 0x54++0x03 line.long 0x00 "CH1_AL1_READ_ADDR,Alias for channel 1 READ_ADDR register" group.long 0x58++0x03 line.long 0x00 "CH1_AL1_WRITE_ADDR,Alias for channel 1 WRITE_ADDR register" group.long 0x5C++0x03 line.long 0x00 "CH1_AL1_TRANS_COUNT_TRIG,Alias for channel 1 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x60++0x03 line.long 0x00 "CH1_AL2_CTRL,Alias for channel 1 CTRL register" group.long 0x64++0x03 line.long 0x00 "CH1_AL2_TRANS_COUNT,Alias for channel 1 TRANS_COUNT register" group.long 0x68++0x03 line.long 0x00 "CH1_AL2_READ_ADDR,Alias for channel 1 READ_ADDR register" group.long 0x6C++0x03 line.long 0x00 "CH1_AL2_WRITE_ADDR_TRIG,Alias for channel 1 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x70++0x03 line.long 0x00 "CH1_AL3_CTRL,Alias for channel 1 CTRL register" group.long 0x74++0x03 line.long 0x00 "CH1_AL3_WRITE_ADDR,Alias for channel 1 WRITE_ADDR register" group.long 0x78++0x03 line.long 0x00 "CH1_AL3_TRANS_COUNT,Alias for channel 1 TRANS_COUNT register" group.long 0x7C++0x03 line.long 0x00 "CH1_AL3_READ_ADDR_TRIG,Alias for channel 1 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x80++0x03 line.long 0x00 "CH2_READ_ADDR,DMA Channel 2 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x84++0x03 line.long 0x00 "CH2_WRITE_ADDR,DMA Channel 2 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x88++0x03 line.long 0x00 "CH2_TRANS_COUNT,DMA Channel 2 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x8C++0x03 line.long 0x00 "CH2_CTRL_TRIG,DMA Channel 2 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x90++0x03 line.long 0x00 "CH2_AL1_CTRL,Alias for channel 2 CTRL register" group.long 0x94++0x03 line.long 0x00 "CH2_AL1_READ_ADDR,Alias for channel 2 READ_ADDR register" group.long 0x98++0x03 line.long 0x00 "CH2_AL1_WRITE_ADDR,Alias for channel 2 WRITE_ADDR register" group.long 0x9C++0x03 line.long 0x00 "CH2_AL1_TRANS_COUNT_TRIG,Alias for channel 2 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0xA0++0x03 line.long 0x00 "CH2_AL2_CTRL,Alias for channel 2 CTRL register" group.long 0xA4++0x03 line.long 0x00 "CH2_AL2_TRANS_COUNT,Alias for channel 2 TRANS_COUNT register" group.long 0xA8++0x03 line.long 0x00 "CH2_AL2_READ_ADDR,Alias for channel 2 READ_ADDR register" group.long 0xAC++0x03 line.long 0x00 "CH2_AL2_WRITE_ADDR_TRIG,Alias for channel 2 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0xB0++0x03 line.long 0x00 "CH2_AL3_CTRL,Alias for channel 2 CTRL register" group.long 0xB4++0x03 line.long 0x00 "CH2_AL3_WRITE_ADDR,Alias for channel 2 WRITE_ADDR register" group.long 0xB8++0x03 line.long 0x00 "CH2_AL3_TRANS_COUNT,Alias for channel 2 TRANS_COUNT register" group.long 0xBC++0x03 line.long 0x00 "CH2_AL3_READ_ADDR_TRIG,Alias for channel 2 READ_ADDR register\n This is a trigger register (0xc)" group.long 0xC0++0x03 line.long 0x00 "CH3_READ_ADDR,DMA Channel 3 Read Address pointer\n This register updates automatically each time a read completes" group.long 0xC4++0x03 line.long 0x00 "CH3_WRITE_ADDR,DMA Channel 3 Write Address pointer\n This register updates automatically each time a write completes" group.long 0xC8++0x03 line.long 0x00 "CH3_TRANS_COUNT,DMA Channel 3 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0xCC++0x03 line.long 0x00 "CH3_CTRL_TRIG,DMA Channel 3 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0xD0++0x03 line.long 0x00 "CH3_AL1_CTRL,Alias for channel 3 CTRL register" group.long 0xD4++0x03 line.long 0x00 "CH3_AL1_READ_ADDR,Alias for channel 3 READ_ADDR register" group.long 0xD8++0x03 line.long 0x00 "CH3_AL1_WRITE_ADDR,Alias for channel 3 WRITE_ADDR register" group.long 0xDC++0x03 line.long 0x00 "CH3_AL1_TRANS_COUNT_TRIG,Alias for channel 3 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0xE0++0x03 line.long 0x00 "CH3_AL2_CTRL,Alias for channel 3 CTRL register" group.long 0xE4++0x03 line.long 0x00 "CH3_AL2_TRANS_COUNT,Alias for channel 3 TRANS_COUNT register" group.long 0xE8++0x03 line.long 0x00 "CH3_AL2_READ_ADDR,Alias for channel 3 READ_ADDR register" group.long 0xEC++0x03 line.long 0x00 "CH3_AL2_WRITE_ADDR_TRIG,Alias for channel 3 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0xF0++0x03 line.long 0x00 "CH3_AL3_CTRL,Alias for channel 3 CTRL register" group.long 0xF4++0x03 line.long 0x00 "CH3_AL3_WRITE_ADDR,Alias for channel 3 WRITE_ADDR register" group.long 0xF8++0x03 line.long 0x00 "CH3_AL3_TRANS_COUNT,Alias for channel 3 TRANS_COUNT register" group.long 0xFC++0x03 line.long 0x00 "CH3_AL3_READ_ADDR_TRIG,Alias for channel 3 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x100++0x03 line.long 0x00 "CH4_READ_ADDR,DMA Channel 4 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x104++0x03 line.long 0x00 "CH4_WRITE_ADDR,DMA Channel 4 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x108++0x03 line.long 0x00 "CH4_TRANS_COUNT,DMA Channel 4 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x10C++0x03 line.long 0x00 "CH4_CTRL_TRIG,DMA Channel 4 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x110++0x03 line.long 0x00 "CH4_AL1_CTRL,Alias for channel 4 CTRL register" group.long 0x114++0x03 line.long 0x00 "CH4_AL1_READ_ADDR,Alias for channel 4 READ_ADDR register" group.long 0x118++0x03 line.long 0x00 "CH4_AL1_WRITE_ADDR,Alias for channel 4 WRITE_ADDR register" group.long 0x11C++0x03 line.long 0x00 "CH4_AL1_TRANS_COUNT_TRIG,Alias for channel 4 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x120++0x03 line.long 0x00 "CH4_AL2_CTRL,Alias for channel 4 CTRL register" group.long 0x124++0x03 line.long 0x00 "CH4_AL2_TRANS_COUNT,Alias for channel 4 TRANS_COUNT register" group.long 0x128++0x03 line.long 0x00 "CH4_AL2_READ_ADDR,Alias for channel 4 READ_ADDR register" group.long 0x12C++0x03 line.long 0x00 "CH4_AL2_WRITE_ADDR_TRIG,Alias for channel 4 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x130++0x03 line.long 0x00 "CH4_AL3_CTRL,Alias for channel 4 CTRL register" group.long 0x134++0x03 line.long 0x00 "CH4_AL3_WRITE_ADDR,Alias for channel 4 WRITE_ADDR register" group.long 0x138++0x03 line.long 0x00 "CH4_AL3_TRANS_COUNT,Alias for channel 4 TRANS_COUNT register" group.long 0x13C++0x03 line.long 0x00 "CH4_AL3_READ_ADDR_TRIG,Alias for channel 4 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x140++0x03 line.long 0x00 "CH5_READ_ADDR,DMA Channel 5 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x144++0x03 line.long 0x00 "CH5_WRITE_ADDR,DMA Channel 5 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x148++0x03 line.long 0x00 "CH5_TRANS_COUNT,DMA Channel 5 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x14C++0x03 line.long 0x00 "CH5_CTRL_TRIG,DMA Channel 5 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x150++0x03 line.long 0x00 "CH5_AL1_CTRL,Alias for channel 5 CTRL register" group.long 0x154++0x03 line.long 0x00 "CH5_AL1_READ_ADDR,Alias for channel 5 READ_ADDR register" group.long 0x158++0x03 line.long 0x00 "CH5_AL1_WRITE_ADDR,Alias for channel 5 WRITE_ADDR register" group.long 0x15C++0x03 line.long 0x00 "CH5_AL1_TRANS_COUNT_TRIG,Alias for channel 5 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x160++0x03 line.long 0x00 "CH5_AL2_CTRL,Alias for channel 5 CTRL register" group.long 0x164++0x03 line.long 0x00 "CH5_AL2_TRANS_COUNT,Alias for channel 5 TRANS_COUNT register" group.long 0x168++0x03 line.long 0x00 "CH5_AL2_READ_ADDR,Alias for channel 5 READ_ADDR register" group.long 0x16C++0x03 line.long 0x00 "CH5_AL2_WRITE_ADDR_TRIG,Alias for channel 5 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x170++0x03 line.long 0x00 "CH5_AL3_CTRL,Alias for channel 5 CTRL register" group.long 0x174++0x03 line.long 0x00 "CH5_AL3_WRITE_ADDR,Alias for channel 5 WRITE_ADDR register" group.long 0x178++0x03 line.long 0x00 "CH5_AL3_TRANS_COUNT,Alias for channel 5 TRANS_COUNT register" group.long 0x17C++0x03 line.long 0x00 "CH5_AL3_READ_ADDR_TRIG,Alias for channel 5 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x180++0x03 line.long 0x00 "CH6_READ_ADDR,DMA Channel 6 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x184++0x03 line.long 0x00 "CH6_WRITE_ADDR,DMA Channel 6 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x188++0x03 line.long 0x00 "CH6_TRANS_COUNT,DMA Channel 6 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x18C++0x03 line.long 0x00 "CH6_CTRL_TRIG,DMA Channel 6 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x190++0x03 line.long 0x00 "CH6_AL1_CTRL,Alias for channel 6 CTRL register" group.long 0x194++0x03 line.long 0x00 "CH6_AL1_READ_ADDR,Alias for channel 6 READ_ADDR register" group.long 0x198++0x03 line.long 0x00 "CH6_AL1_WRITE_ADDR,Alias for channel 6 WRITE_ADDR register" group.long 0x19C++0x03 line.long 0x00 "CH6_AL1_TRANS_COUNT_TRIG,Alias for channel 6 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x1A0++0x03 line.long 0x00 "CH6_AL2_CTRL,Alias for channel 6 CTRL register" group.long 0x1A4++0x03 line.long 0x00 "CH6_AL2_TRANS_COUNT,Alias for channel 6 TRANS_COUNT register" group.long 0x1A8++0x03 line.long 0x00 "CH6_AL2_READ_ADDR,Alias for channel 6 READ_ADDR register" group.long 0x1AC++0x03 line.long 0x00 "CH6_AL2_WRITE_ADDR_TRIG,Alias for channel 6 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x1B0++0x03 line.long 0x00 "CH6_AL3_CTRL,Alias for channel 6 CTRL register" group.long 0x1B4++0x03 line.long 0x00 "CH6_AL3_WRITE_ADDR,Alias for channel 6 WRITE_ADDR register" group.long 0x1B8++0x03 line.long 0x00 "CH6_AL3_TRANS_COUNT,Alias for channel 6 TRANS_COUNT register" group.long 0x1BC++0x03 line.long 0x00 "CH6_AL3_READ_ADDR_TRIG,Alias for channel 6 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x1C0++0x03 line.long 0x00 "CH7_READ_ADDR,DMA Channel 7 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x1C4++0x03 line.long 0x00 "CH7_WRITE_ADDR,DMA Channel 7 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x1C8++0x03 line.long 0x00 "CH7_TRANS_COUNT,DMA Channel 7 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x1CC++0x03 line.long 0x00 "CH7_CTRL_TRIG,DMA Channel 7 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x1D0++0x03 line.long 0x00 "CH7_AL1_CTRL,Alias for channel 7 CTRL register" group.long 0x1D4++0x03 line.long 0x00 "CH7_AL1_READ_ADDR,Alias for channel 7 READ_ADDR register" group.long 0x1D8++0x03 line.long 0x00 "CH7_AL1_WRITE_ADDR,Alias for channel 7 WRITE_ADDR register" group.long 0x1DC++0x03 line.long 0x00 "CH7_AL1_TRANS_COUNT_TRIG,Alias for channel 7 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x1E0++0x03 line.long 0x00 "CH7_AL2_CTRL,Alias for channel 7 CTRL register" group.long 0x1E4++0x03 line.long 0x00 "CH7_AL2_TRANS_COUNT,Alias for channel 7 TRANS_COUNT register" group.long 0x1E8++0x03 line.long 0x00 "CH7_AL2_READ_ADDR,Alias for channel 7 READ_ADDR register" group.long 0x1EC++0x03 line.long 0x00 "CH7_AL2_WRITE_ADDR_TRIG,Alias for channel 7 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x1F0++0x03 line.long 0x00 "CH7_AL3_CTRL,Alias for channel 7 CTRL register" group.long 0x1F4++0x03 line.long 0x00 "CH7_AL3_WRITE_ADDR,Alias for channel 7 WRITE_ADDR register" group.long 0x1F8++0x03 line.long 0x00 "CH7_AL3_TRANS_COUNT,Alias for channel 7 TRANS_COUNT register" group.long 0x1FC++0x03 line.long 0x00 "CH7_AL3_READ_ADDR_TRIG,Alias for channel 7 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x200++0x03 line.long 0x00 "CH8_READ_ADDR,DMA Channel 8 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x204++0x03 line.long 0x00 "CH8_WRITE_ADDR,DMA Channel 8 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x208++0x03 line.long 0x00 "CH8_TRANS_COUNT,DMA Channel 8 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x20C++0x03 line.long 0x00 "CH8_CTRL_TRIG,DMA Channel 8 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x210++0x03 line.long 0x00 "CH8_AL1_CTRL,Alias for channel 8 CTRL register" group.long 0x214++0x03 line.long 0x00 "CH8_AL1_READ_ADDR,Alias for channel 8 READ_ADDR register" group.long 0x218++0x03 line.long 0x00 "CH8_AL1_WRITE_ADDR,Alias for channel 8 WRITE_ADDR register" group.long 0x21C++0x03 line.long 0x00 "CH8_AL1_TRANS_COUNT_TRIG,Alias for channel 8 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x220++0x03 line.long 0x00 "CH8_AL2_CTRL,Alias for channel 8 CTRL register" group.long 0x224++0x03 line.long 0x00 "CH8_AL2_TRANS_COUNT,Alias for channel 8 TRANS_COUNT register" group.long 0x228++0x03 line.long 0x00 "CH8_AL2_READ_ADDR,Alias for channel 8 READ_ADDR register" group.long 0x22C++0x03 line.long 0x00 "CH8_AL2_WRITE_ADDR_TRIG,Alias for channel 8 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x230++0x03 line.long 0x00 "CH8_AL3_CTRL,Alias for channel 8 CTRL register" group.long 0x234++0x03 line.long 0x00 "CH8_AL3_WRITE_ADDR,Alias for channel 8 WRITE_ADDR register" group.long 0x238++0x03 line.long 0x00 "CH8_AL3_TRANS_COUNT,Alias for channel 8 TRANS_COUNT register" group.long 0x23C++0x03 line.long 0x00 "CH8_AL3_READ_ADDR_TRIG,Alias for channel 8 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x240++0x03 line.long 0x00 "CH9_READ_ADDR,DMA Channel 9 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x244++0x03 line.long 0x00 "CH9_WRITE_ADDR,DMA Channel 9 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x248++0x03 line.long 0x00 "CH9_TRANS_COUNT,DMA Channel 9 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x24C++0x03 line.long 0x00 "CH9_CTRL_TRIG,DMA Channel 9 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x250++0x03 line.long 0x00 "CH9_AL1_CTRL,Alias for channel 9 CTRL register" group.long 0x254++0x03 line.long 0x00 "CH9_AL1_READ_ADDR,Alias for channel 9 READ_ADDR register" group.long 0x258++0x03 line.long 0x00 "CH9_AL1_WRITE_ADDR,Alias for channel 9 WRITE_ADDR register" group.long 0x25C++0x03 line.long 0x00 "CH9_AL1_TRANS_COUNT_TRIG,Alias for channel 9 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x260++0x03 line.long 0x00 "CH9_AL2_CTRL,Alias for channel 9 CTRL register" group.long 0x264++0x03 line.long 0x00 "CH9_AL2_TRANS_COUNT,Alias for channel 9 TRANS_COUNT register" group.long 0x268++0x03 line.long 0x00 "CH9_AL2_READ_ADDR,Alias for channel 9 READ_ADDR register" group.long 0x26C++0x03 line.long 0x00 "CH9_AL2_WRITE_ADDR_TRIG,Alias for channel 9 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x270++0x03 line.long 0x00 "CH9_AL3_CTRL,Alias for channel 9 CTRL register" group.long 0x274++0x03 line.long 0x00 "CH9_AL3_WRITE_ADDR,Alias for channel 9 WRITE_ADDR register" group.long 0x278++0x03 line.long 0x00 "CH9_AL3_TRANS_COUNT,Alias for channel 9 TRANS_COUNT register" group.long 0x27C++0x03 line.long 0x00 "CH9_AL3_READ_ADDR_TRIG,Alias for channel 9 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x280++0x03 line.long 0x00 "CH10_READ_ADDR,DMA Channel 10 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x284++0x03 line.long 0x00 "CH10_WRITE_ADDR,DMA Channel 10 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x288++0x03 line.long 0x00 "CH10_TRANS_COUNT,DMA Channel 10 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x28C++0x03 line.long 0x00 "CH10_CTRL_TRIG,DMA Channel 10 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x290++0x03 line.long 0x00 "CH10_AL1_CTRL,Alias for channel 10 CTRL register" group.long 0x294++0x03 line.long 0x00 "CH10_AL1_READ_ADDR,Alias for channel 10 READ_ADDR register" group.long 0x298++0x03 line.long 0x00 "CH10_AL1_WRITE_ADDR,Alias for channel 10 WRITE_ADDR register" group.long 0x29C++0x03 line.long 0x00 "CH10_AL1_TRANS_COUNT_TRIG,Alias for channel 10 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x2A0++0x03 line.long 0x00 "CH10_AL2_CTRL,Alias for channel 10 CTRL register" group.long 0x2A4++0x03 line.long 0x00 "CH10_AL2_TRANS_COUNT,Alias for channel 10 TRANS_COUNT register" group.long 0x2A8++0x03 line.long 0x00 "CH10_AL2_READ_ADDR,Alias for channel 10 READ_ADDR register" group.long 0x2AC++0x03 line.long 0x00 "CH10_AL2_WRITE_ADDR_TRIG,Alias for channel 10 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x2B0++0x03 line.long 0x00 "CH10_AL3_CTRL,Alias for channel 10 CTRL register" group.long 0x2B4++0x03 line.long 0x00 "CH10_AL3_WRITE_ADDR,Alias for channel 10 WRITE_ADDR register" group.long 0x2B8++0x03 line.long 0x00 "CH10_AL3_TRANS_COUNT,Alias for channel 10 TRANS_COUNT register" group.long 0x2BC++0x03 line.long 0x00 "CH10_AL3_READ_ADDR_TRIG,Alias for channel 10 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x2C0++0x03 line.long 0x00 "CH11_READ_ADDR,DMA Channel 11 Read Address pointer\n This register updates automatically each time a read completes" group.long 0x2C4++0x03 line.long 0x00 "CH11_WRITE_ADDR,DMA Channel 11 Write Address pointer\n This register updates automatically each time a write completes" group.long 0x2C8++0x03 line.long 0x00 "CH11_TRANS_COUNT,DMA Channel 11 Transfer Count\n Program the number of bus transfers a channel will perform before halting" group.long 0x2CC++0x03 line.long 0x00 "CH11_CTRL_TRIG,DMA Channel 11 Control and Status" rbitfld.long 0x00 31. "AHB_ERROR,Logical OR of the READ_ERROR and WRITE_ERROR flags" "0,1" eventfld.long 0x00 30. "READ_ERROR,If 1 the channel received a read bus error" "0,1" newline eventfld.long 0x00 29. "WRITE_ERROR,If 1 the channel received a write bus error" "0,1" rbitfld.long 0x00 24. "BUSY,This flag goes high when the channel starts a new transfer sequence and low when the last transfer of that sequence completes" "0,1" newline bitfld.long 0x00 23. "SNIFF_EN,If 1 this channel's data transfers are visible to the sniff hardware and each transfer will advance the state of the checksum" "0,1" bitfld.long 0x00 22. "BSWAP,Apply byte-swap transformation to DMA data.\n For byte data this has no effect" "0,1" newline bitfld.long 0x00 21. "IRQ_QUIET,In QUIET mode the channel does not generate IRQs at the end of every transfer block" "0,1" bitfld.long 0x00 15.--20. "TREQ_SEL,Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,59: Select Timer 0 as TREQ,60: Select Timer 1 as TREQ,61: Select Timer 2 as TREQ (Optional),62: Select Timer 3 as TREQ (Optional),63: Permanent request for unpaced transfers" newline bitfld.long 0x00 11.--14. "CHAIN_TO,When this channel completes it will trigger the channel indicated by CHAIN_TO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "RING_SEL,Select whether RING_SIZE applies to read or write addresses.\n If 0 read addresses are wrapped on a (1 << RING_SIZE) boundary" "0,1" newline bitfld.long 0x00 6.--9. "RING_SIZE,Size of address wrap region" "0: RING_NONE,?..." bitfld.long 0x00 5. "INCR_WRITE,If 1 the write address increments with each transfer" "0,1" newline bitfld.long 0x00 4. "INCR_READ,If 1 the read address increments with each transfer" "0,1" bitfld.long 0x00 2.--3. "DATA_SIZE,Set the size of each bus transfer (byte/halfword/word)" "0: SIZE_BYTE,1: SIZE_HALFWORD,2: SIZE_WORD,?..." newline bitfld.long 0x00 1. "HIGH_PRIORITY,HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round all high priority channels are considered first and then only a single low priority channel before returning to the high priority.." "0,1" bitfld.long 0x00 0. "EN,DMA Channel Enable.\n When 1 the channel will respond to triggering events which will cause it to become BUSY and start transferring data" "0,1" group.long 0x2D0++0x03 line.long 0x00 "CH11_AL1_CTRL,Alias for channel 11 CTRL register" group.long 0x2D4++0x03 line.long 0x00 "CH11_AL1_READ_ADDR,Alias for channel 11 READ_ADDR register" group.long 0x2D8++0x03 line.long 0x00 "CH11_AL1_WRITE_ADDR,Alias for channel 11 WRITE_ADDR register" group.long 0x2DC++0x03 line.long 0x00 "CH11_AL1_TRANS_COUNT_TRIG,Alias for channel 11 TRANS_COUNT register\n This is a trigger register (0xc)" group.long 0x2E0++0x03 line.long 0x00 "CH11_AL2_CTRL,Alias for channel 11 CTRL register" group.long 0x2E4++0x03 line.long 0x00 "CH11_AL2_TRANS_COUNT,Alias for channel 11 TRANS_COUNT register" group.long 0x2E8++0x03 line.long 0x00 "CH11_AL2_READ_ADDR,Alias for channel 11 READ_ADDR register" group.long 0x2EC++0x03 line.long 0x00 "CH11_AL2_WRITE_ADDR_TRIG,Alias for channel 11 WRITE_ADDR register\n This is a trigger register (0xc)" group.long 0x2F0++0x03 line.long 0x00 "CH11_AL3_CTRL,Alias for channel 11 CTRL register" group.long 0x2F4++0x03 line.long 0x00 "CH11_AL3_WRITE_ADDR,Alias for channel 11 WRITE_ADDR register" group.long 0x2F8++0x03 line.long 0x00 "CH11_AL3_TRANS_COUNT,Alias for channel 11 TRANS_COUNT register" group.long 0x2FC++0x03 line.long 0x00 "CH11_AL3_READ_ADDR_TRIG,Alias for channel 11 READ_ADDR register\n This is a trigger register (0xc)" group.long 0x400++0x03 line.long 0x00 "INTR,Interrupt Status (raw)" hexmask.long.word 0x00 0.--15. 1. "INTR,Raw interrupt status for DMA Channels 0..15" group.long 0x404++0x03 line.long 0x00 "INTE0,Interrupt Enables for IRQ 0" hexmask.long.word 0x00 0.--15. 1. "INTE0,Set bit n to pass interrupts from channel n to DMA IRQ 0" group.long 0x408++0x03 line.long 0x00 "INTF0,Force Interrupts" hexmask.long.word 0x00 0.--15. 1. "INTF0,Write 1s to force the corresponding bits in INTE0" group.long 0x40C++0x03 line.long 0x00 "INTS0,Interrupt Status for IRQ 0" hexmask.long.word 0x00 0.--15. 1. "INTS0,Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n Channel interrupts can be cleared by writing a bit mask here" group.long 0x414++0x03 line.long 0x00 "INTE1,Interrupt Enables for IRQ 1" hexmask.long.word 0x00 0.--15. 1. "INTE1,Set bit n to pass interrupts from channel n to DMA IRQ 1" group.long 0x418++0x03 line.long 0x00 "INTF1,Force Interrupts for IRQ 1" hexmask.long.word 0x00 0.--15. 1. "INTF1,Write 1s to force the corresponding bits in INTE0" group.long 0x41C++0x03 line.long 0x00 "INTS1,Interrupt Status (masked) for IRQ 1" hexmask.long.word 0x00 0.--15. 1. "INTS1,Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n Channel interrupts can be cleared by writing a bit mask here" repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x420)++0x03 line.long 0x00 "TIMER$1,Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk)" hexmask.long.word 0x00 16.--31. 1. "X,Pacing Timer Dividend" hexmask.long.word 0x00 0.--15. 1. "Y,Pacing Timer Divisor" repeat.end group.long 0x430++0x03 line.long 0x00 "MULTI_CHAN_TRIGGER,Trigger one or more channels simultaneously" hexmask.long.word 0x00 0.--15. 1. "MULTI_CHAN_TRIGGER,Each bit in this register corresponds to a DMA channel" group.long 0x434++0x03 line.long 0x00 "SNIFF_CTRL,Sniffer Control" bitfld.long 0x00 11. "OUT_INV,If set the result appears inverted (bitwise complement) when" "0,1" bitfld.long 0x00 10. "OUT_REV,If set the result appears bit-reversed when" "0,1" newline bitfld.long 0x00 9. "BSWAP,Locally perform a byte reverse on the sniffed data before feeding into checksum.\n\n Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled.." "0,1" bitfld.long 0x00 5.--8. "CALC," "0: Calculate a CRC-32 (IEEE802.3 polynomial),1: Calculate a CRC-32 (IEEE802.3 polynomial)..,2: Calculate a CRC-16-CCITT,3: Calculate a CRC-16-CCITT with bit reversed data,?,?,?,?,?,?,?,?,?,?,14: XOR reduction over all data,15: Calculate a simple 32-bit checksum (addition.." newline bitfld.long 0x00 1.--4. "DMACH,DMA channel for Sniffer to observe" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "EN,Enable sniffer" "0,1" group.long 0x438++0x03 line.long 0x00 "SNIFF_DATA,Data accumulator for sniff hardware\n Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH" group.long 0x440++0x03 line.long 0x00 "FIFO_LEVELS,Debug RAF WAF TDF levels" hexmask.long.byte 0x00 16.--23. 1. "RAF_LVL,Current Read-Address-FIFO fill level" hexmask.long.byte 0x00 8.--15. 1. "WAF_LVL,Current Write-Address-FIFO fill level" newline hexmask.long.byte 0x00 0.--7. 1. "TDF_LVL,Current Transfer-Data-FIFO fill level" group.long 0x444++0x03 line.long 0x00 "CHAN_ABORT,Abort an in-progress transfer sequence on one or more channels" hexmask.long.word 0x00 0.--15. 1. "CHAN_ABORT,Each bit corresponds to a channel" group.long 0x448++0x03 line.long 0x00 "N_CHANNELS,The number of channels this DMA instance is equipped with" rbitfld.long 0x00 0.--4. "N_CHANNELS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x800++0x03 line.long 0x00 "CH0_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH0_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x804++0x03 line.long 0x00 "CH0_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0x840++0x03 line.long 0x00 "CH1_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH1_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x844++0x03 line.long 0x00 "CH1_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0x880++0x03 line.long 0x00 "CH2_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH2_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x884++0x03 line.long 0x00 "CH2_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0x8C0++0x03 line.long 0x00 "CH3_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH3_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x8C4++0x03 line.long 0x00 "CH3_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0x900++0x03 line.long 0x00 "CH4_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH4_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x904++0x03 line.long 0x00 "CH4_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0x940++0x03 line.long 0x00 "CH5_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH5_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x944++0x03 line.long 0x00 "CH5_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0x980++0x03 line.long 0x00 "CH6_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH6_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x984++0x03 line.long 0x00 "CH6_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0x9C0++0x03 line.long 0x00 "CH7_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH7_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x9C4++0x03 line.long 0x00 "CH7_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0xA00++0x03 line.long 0x00 "CH8_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH8_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xA04++0x03 line.long 0x00 "CH8_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0xA40++0x03 line.long 0x00 "CH9_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH9_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xA44++0x03 line.long 0x00 "CH9_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0xA80++0x03 line.long 0x00 "CH10_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH10_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xA84++0x03 line.long 0x00 "CH10_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" group.long 0xAC0++0x03 line.long 0x00 "CH11_DBG_CTDREQ,Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter and cause channel to re-initiate DREQ handshake" eventfld.long 0x00 0.--5. "CH11_DBG_CTDREQ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0xAC4++0x03 line.long 0x00 "CH11_DBG_TCR,Read to get channel TRANS_COUNT reload value i.e" tree.end tree "I2C (Inter-Integrated Circuit)" repeat 2. (list 0. 1.) (list ad:0x40044000 ad:0x40048000) tree "I2C$1" base $2 group.long 0x00++0x03 line.long 0x00 "IC_CON,I2C Control Register" rbitfld.long 0x00 10. "STOP_DET_IF_MASTER_ACTIVE,Master issues the STOP_DET interrupt irrespective of whether master is active or not" "0,1" newline bitfld.long 0x00 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n Reset value: 0x0" "0: Overflow when RX_FIFO is full,1: Hold bus when RX_FIFO is full" newline bitfld.long 0x00 8. "TX_EMPTY_CTRL,This bit controls the generation of the TX_EMPTY interrupt as described in the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0: Default behaviour of TX_EMPTY interrupt,1: Controlled generation of TX_EMPTY interrupt" newline bitfld.long 0x00 7. "STOP_DET_IFADDRESSED,In slave mode" "0: slave issues STOP_DET intr always,1: slave issues STOP_DET intr only if addressed" newline bitfld.long 0x00 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled which means once the presetn signal is applied then this bit is set and the slave is disabled.\n\n If this bit is set (slave is disabled) DW_apb_i2c functions only as a master and.." "0: Slave mode is enabled,1: Slave mode is disabled" newline bitfld.long 0x00 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master" "0: Master restart disabled,1: Master restart enabled" newline bitfld.long 0x00 4. "IC_10BITADDR_MASTER,Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master" "0: Master 7Bit addressing mode,1: Master 10Bit addressing mode" newline bitfld.long 0x00 3. "IC_10BITADDR_SLAVE,When acting as a slave this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses" "0: Slave 7Bit addressing,1: Slave 10Bit addressing" newline bitfld.long 0x00 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates its setting is relevant only if one is operating the DW_apb_i2c in master mode" "?,1: Standard Speed mode of operation,2: Fast or Fast Plus mode of operation,3: High Speed mode of operation" newline bitfld.long 0x00 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled.\n\n NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'" "0: Master mode is disabled,1: Master mode is enabled" group.long 0x04++0x03 line.long 0x00 "IC_TAR,I2C Target Address Register\n\n This register is 12 bits wide and bits 31:12 are reserved" bitfld.long 0x00 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or START BYTE command" "0: Disables programming of GENERAL_CALL or..,1: Enables programming of GENERAL_CALL or.." newline bitfld.long 0x00 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0 then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c" "0: GENERAL_CALL byte transmission,1: START byte transmission" newline hexmask.long.word 0x00 0.--9. 1. "IC_TAR,This is the target address for any master transaction" group.long 0x08++0x03 line.long 0x00 "IC_SAR,I2C Slave Address Register" hexmask.long.word 0x00 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave" group.long 0x10++0x03 line.long 0x00 "IC_DATA_CMD,I2C Rx/Tx Data Buffer and Command Register this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n The size of the register changes as follows:\n\n Write: - 11 bits when.." rbitfld.long 0x00 11. "FIRST_DATA_BYTE,Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n Reset value : 0x0\n\n NOTE: In case of APB_DATA_WIDTH=8 \n\n 1" "0: Sequential data byte received,1: Non sequential data byte received" newline bitfld.long 0x00 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received.\n\n" "0: Don't Issue RESTART before this command,1: Issue RESTART before this command" newline bitfld.long 0x00 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received.\n\n" "0: Don't Issue STOP after this command,1: Issue STOP after this command" newline bitfld.long 0x00 8. "CMD,This bit controls whether a read or a write is performed" "0: Master Write Command,1: Master Read Command" newline hexmask.long.byte 0x00 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus" group.long 0x14++0x03 line.long 0x00 "IC_SS_SCL_HCNT,Standard Speed I2C Clock SCL High Count Register" hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing" group.long 0x18++0x03 line.long 0x00 "IC_SS_SCL_LCNT,Standard Speed I2C Clock SCL Low Count Register" hexmask.long.word 0x00 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing" group.long 0x1C++0x03 line.long 0x00 "IC_FS_SCL_HCNT,Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register" hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing" group.long 0x20++0x03 line.long 0x00 "IC_FS_SCL_LCNT,Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register" hexmask.long.word 0x00 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing" group.long 0x2C++0x03 line.long 0x00 "IC_INTR_STAT,I2C Interrupt Status Register\n\n Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register" rbitfld.long 0x00 12. "R_RESTART_DET,See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n Reset value: 0x0" "0: R_RESTART_DET interrupt is inactive,1: R_RESTART_DET interrupt is active" newline rbitfld.long 0x00 11. "R_GEN_CALL,See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n Reset value: 0x0" "0: R_GEN_CALL interrupt is inactive,1: R_GEN_CALL interrupt is active" newline rbitfld.long 0x00 10. "R_START_DET,See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n Reset value: 0x0" "0: R_START_DET interrupt is inactive,1: R_START_DET interrupt is active" newline rbitfld.long 0x00 9. "R_STOP_DET,See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n Reset value: 0x0" "0: R_STOP_DET interrupt is inactive,1: R_STOP_DET interrupt is active" newline rbitfld.long 0x00 8. "R_ACTIVITY,See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n Reset value: 0x0" "0: R_ACTIVITY interrupt is inactive,1: R_ACTIVITY interrupt is active" newline rbitfld.long 0x00 7. "R_RX_DONE,See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n Reset value: 0x0" "0: R_RX_DONE interrupt is inactive,1: R_RX_DONE interrupt is active" newline rbitfld.long 0x00 6. "R_TX_ABRT,See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n Reset value: 0x0" "0: R_TX_ABRT interrupt is inactive,1: R_TX_ABRT interrupt is active" newline rbitfld.long 0x00 5. "R_RD_REQ,See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n Reset value: 0x0" "0: R_RD_REQ interrupt is inactive,1: R_RD_REQ interrupt is active" newline rbitfld.long 0x00 4. "R_TX_EMPTY,See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n Reset value: 0x0" "0: R_TX_EMPTY interrupt is inactive,1: R_TX_EMPTY interrupt is active" newline rbitfld.long 0x00 3. "R_TX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n Reset value: 0x0" "0: R_TX_OVER interrupt is inactive,1: R_TX_OVER interrupt is active" newline rbitfld.long 0x00 2. "R_RX_FULL,See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n Reset value: 0x0" "0: R_RX_FULL interrupt is inactive,1: R_RX_FULL interrupt is active" newline rbitfld.long 0x00 1. "R_RX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n Reset value: 0x0" "0: R_RX_OVER interrupt is inactive,1: R_RX_OVER interrupt is active" newline rbitfld.long 0x00 0. "R_RX_UNDER,See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n Reset value: 0x0" "0: RX_UNDER interrupt is inactive,1: RX_UNDER interrupt is active" group.long 0x30++0x03 line.long 0x00 "IC_INTR_MASK,I2C Interrupt Mask Register.\n\n These bits mask their corresponding interrupt status bits" bitfld.long 0x00 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0" "0: RESTART_DET interrupt is masked,1: RESTART_DET interrupt is unmasked" newline bitfld.long 0x00 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1" "0: GEN_CALL interrupt is masked,1: GEN_CALL interrupt is unmasked" newline bitfld.long 0x00 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0" "0: START_DET interrupt is masked,1: START_DET interrupt is unmasked" newline bitfld.long 0x00 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0" "0: STOP_DET interrupt is masked,1: STOP_DET interrupt is unmasked" newline bitfld.long 0x00 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0" "0: ACTIVITY interrupt is masked,1: ACTIVITY interrupt is unmasked" newline bitfld.long 0x00 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1" "0: RX_DONE interrupt is masked,1: RX_DONE interrupt is unmasked" newline bitfld.long 0x00 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1" "0: TX_ABORT interrupt is masked,1: TX_ABORT interrupt is unmasked" newline bitfld.long 0x00 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1" "0: RD_REQ interrupt is masked,1: RD_REQ interrupt is unmasked" newline bitfld.long 0x00 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1" "0: TX_EMPTY interrupt is masked,1: TX_EMPTY interrupt is unmasked" newline bitfld.long 0x00 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1" "0: TX_OVER interrupt is masked,1: TX_OVER interrupt is unmasked" newline bitfld.long 0x00 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1" "0: RX_FULL interrupt is masked,1: RX_FULL interrupt is unmasked" newline bitfld.long 0x00 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1" "0: RX_OVER interrupt is masked,1: RX_OVER interrupt is unmasked" newline bitfld.long 0x00 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1" "0: RX_UNDER interrupt is masked,1: RX_UNDER interrupt is unmasked" group.long 0x34++0x03 line.long 0x00 "IC_RAW_INTR_STAT,I2C Raw Interrupt Status Register\n\n Unlike the IC_INTR_STAT register these bits are not masked so they always show the true status of the DW_apb_i2c" rbitfld.long 0x00 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed" "0: RESTART_DET interrupt is inactive,1: RESTART_DET interrupt is active" newline rbitfld.long 0x00 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged" "0: GEN_CALL interrupt is inactive,1: GEN_CALL interrupt is active" newline rbitfld.long 0x00 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n Reset value: 0x0" "0: START_DET interrupt is inactive,1: START_DET interrupt is active" newline rbitfld.long 0x00 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED) the STOP_DET interrupt will be issued only.." "0: STOP_DET interrupt is inactive,1: STOP_DET interrupt is active" newline rbitfld.long 0x00 8. "ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared" "0: RAW_INTR_ACTIVITY interrupt is inactive,1: RAW_INTR_ACTIVITY interrupt is active" newline rbitfld.long 0x00 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte" "0: RX_DONE interrupt is inactive,1: RX_DONE interrupt is active" newline rbitfld.long 0x00 6. "TX_ABRT,This bit indicates if DW_apb_i2c as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO" "0: TX_ABRT interrupt is inactive,1: TX_ABRT interrupt is active" newline rbitfld.long 0x00 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c" "0: RD_REQ interrupt is inactive,1: RD_REQ interrupt is active" newline rbitfld.long 0x00 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register" "0: TX_EMPTY interrupt is inactive,1: TX_EMPTY interrupt is active" newline rbitfld.long 0x00 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register" "0: TX_OVER interrupt is inactive,1: TX_OVER interrupt is active" newline rbitfld.long 0x00 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register" "0: RX_FULL interrupt is inactive,1: RX_FULL interrupt is active" newline rbitfld.long 0x00 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device" "0: RX_OVER interrupt is inactive,1: RX_OVER interrupt is active" newline rbitfld.long 0x00 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register" "0: RX_UNDER interrupt is inactive,1: RX_UNDER interrupt is active" group.long 0x38++0x03 line.long 0x00 "IC_RX_TL,I2C Receive FIFO Threshold Register" hexmask.long.byte 0x00 0.--7. 1. "RX_TL,Receive FIFO Threshold Level.\n\n Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register)" group.long 0x3C++0x03 line.long 0x00 "IC_TX_TL,I2C Transmit FIFO Threshold Register" hexmask.long.byte 0x00 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level.\n\n Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register)" group.long 0x40++0x03 line.long 0x00 "IC_CLR_INTR,Clear Combined and Individual Interrupt Register" rbitfld.long 0x00 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the IC_TX_ABRT_SOURCE register" "0,1" group.long 0x44++0x03 line.long 0x00 "IC_CLR_RX_UNDER,Clear RX_UNDER Interrupt Register" rbitfld.long 0x00 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0,1" group.long 0x48++0x03 line.long 0x00 "IC_CLR_RX_OVER,Clear RX_OVER Interrupt Register" rbitfld.long 0x00 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0,1" group.long 0x4C++0x03 line.long 0x00 "IC_CLR_TX_OVER,Clear TX_OVER Interrupt Register" rbitfld.long 0x00 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0,1" group.long 0x50++0x03 line.long 0x00 "IC_CLR_RD_REQ,Clear RD_REQ Interrupt Register" rbitfld.long 0x00 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0,1" group.long 0x54++0x03 line.long 0x00 "IC_CLR_TX_ABRT,Clear TX_ABRT Interrupt Register" rbitfld.long 0x00 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the IC_TX_ABRT_SOURCE register" "0,1" group.long 0x58++0x03 line.long 0x00 "IC_CLR_RX_DONE,Clear RX_DONE Interrupt Register" rbitfld.long 0x00 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0,1" group.long 0x5C++0x03 line.long 0x00 "IC_CLR_ACTIVITY,Clear ACTIVITY Interrupt Register" rbitfld.long 0x00 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore" "0,1" group.long 0x60++0x03 line.long 0x00 "IC_CLR_STOP_DET,Clear STOP_DET Interrupt Register" rbitfld.long 0x00 0. "CLR_STOP_DET,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0,1" group.long 0x64++0x03 line.long 0x00 "IC_CLR_START_DET,Clear START_DET Interrupt Register" rbitfld.long 0x00 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0,1" group.long 0x68++0x03 line.long 0x00 "IC_CLR_GEN_CALL,Clear GEN_CALL Interrupt Register" rbitfld.long 0x00 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0,1" group.long 0x6C++0x03 line.long 0x00 "IC_ENABLE,I2C Enable Register" bitfld.long 0x00 2. "TX_CMD_BLOCK,In Master mode" "0: Tx Command execution not blocked,1: Tx Command execution blocked" newline bitfld.long 0x00 1. "ABORT,When set the controller initiates the transfer abort" "0: ABORT operation not in progress,1: ABORT operation in progress" newline bitfld.long 0x00 0. "ENABLE,Controls whether the DW_apb_i2c is enabled" "0: I2C is disabled,1: I2C is enabled" group.long 0x70++0x03 line.long 0x00 "IC_STATUS,I2C Status Register\n\n This is a read-only register used to indicate the current transfer status and FIFO status" rbitfld.long 0x00 6. "SLV_ACTIVITY,Slave FSM Activity Status" "0: Slave is idle,1: Slave not idle" newline rbitfld.long 0x00 5. "MST_ACTIVITY,Master FSM Activity Status" "0: Master is idle,1: Master not idle" newline rbitfld.long 0x00 4. "RFF,Receive FIFO Completely Full" "0: Rx FIFO not full,1: Rx FIFO is full" newline rbitfld.long 0x00 3. "RFNE,Receive FIFO Not Empty" "0: Rx FIFO is empty,1: Rx FIFO not empty" newline rbitfld.long 0x00 2. "TFE,Transmit FIFO Completely Empty" "0: Tx FIFO not empty,1: Tx FIFO is empty" newline rbitfld.long 0x00 1. "TFNF,Transmit FIFO Not Full" "0: Tx FIFO is full,1: Tx FIFO not full" newline rbitfld.long 0x00 0. "ACTIVITY,I2C Activity Status" "0: I2C is idle,1: I2C is active" group.long 0x74++0x03 line.long 0x00 "IC_TXFLR,I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer" rbitfld.long 0x00 0.--4. "TXFLR,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x78++0x03 line.long 0x00 "IC_RXFLR,I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer" rbitfld.long 0x00 0.--4. "RXFLR,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7C++0x03 line.long 0x00 "IC_SDA_HOLD,I2C SDA Hold Time Length Register\n\n The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n The bits [23:16] of this register are used.." hexmask.long.byte 0x00 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a receiver.\n\n Reset value: IC_DEFAULT_SDA_HOLD[23:16]" newline hexmask.long.word 0x00 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a transmitter.\n\n Reset value: IC_DEFAULT_SDA_HOLD[15:0]" group.long 0x80++0x03 line.long 0x00 "IC_TX_ABRT_SOURCE,I2C Transmit Abort Source Register\n\n This register has 32 bits that indicate the source of the TX_ABRT bit" hexmask.long.word 0x00 23.--31. 1. "TX_FLUSH_CNT,This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt" newline rbitfld.long 0x00 16. "ABRT_USER_ABRT,This is a master-mode-only bit" "0: Transfer abort detected by master- scenario..,1: Transfer abort detected by master" newline rbitfld.long 0x00 15. "ABRT_SLVRD_INTX," "0: Slave trying to transmit to remote master in..,1: Slave trying to transmit to remote master in.." newline rbitfld.long 0x00 14. "ABRT_SLV_ARBLOST,This field indicates that a Slave has lost the bus while transmitting data to a remote master" "0: Slave lost arbitration to remote master-..,1: Slave lost arbitration to remote master" newline rbitfld.long 0x00 13. "ABRT_SLVFLUSH_TXFIFO,This field specifies that the Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter" "0: Slave flushes existing data in TX-FIFO upon..,1: Slave flushes existing data in TX-FIFO upon.." newline rbitfld.long 0x00 12. "ARB_LOST,This field specifies that the Master has lost arbitration or if IC_TX_ABRT_SOURCE[14] is also set then the slave transmitter has lost arbitration.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter" "0: Master or Slave-Transmitter lost arbitration-..,1: Master or Slave-Transmitter lost arbitration" newline rbitfld.long 0x00 11. "ABRT_MASTER_DIS,This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver" "0: User initiating master operation when MASTER..,1: User initiating master operation when MASTER.." newline rbitfld.long 0x00 10. "ABRT_10B_RD_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Receiver" "0: Master not trying to read in 10Bit addressing..,1: Master trying to read in 10Bit addressing.." newline rbitfld.long 0x00 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (IC_CON[5]=1) the SPECIAL bit must be cleared (IC_TAR[11]) or the GC_OR_START bit must be cleared (IC_TAR[10])" "0: User trying to send START byte when RESTART..,1: User trying to send START byte when RESTART.." newline rbitfld.long 0x00 8. "ABRT_HS_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or.." "0: User trying to switch Master to HS mode when..,1: User trying to switch Master to HS mode when.." newline rbitfld.long 0x00 7. "ABRT_SBYTE_ACKDET,This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master" "0: ACK detected for START byte- scenario not..,1: ABRT_SBYTE_ACKDET_GENERATED" newline rbitfld.long 0x00 6. "ABRT_HS_ACKDET,This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master" "0: HS Master code ACKed in HS Mode- scenario not..,1: HS Master code ACKed in HS Mode" newline rbitfld.long 0x00 5. "ABRT_GCALL_READ,This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n Reset value: 0x0\n\n Role of.." "0: GCALL is followed by read from bus-scenario..,1: GCALL is followed by read from bus" newline rbitfld.long 0x00 4. "ABRT_GCALL_NOACK,This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter" "0: GCALL not ACKed by any slave-scenario not..,1: GCALL not ACKed by any slave" newline rbitfld.long 0x00 3. "ABRT_TXDATA_NOACK,This field indicates the master-mode only bit" "0: Transmitted data non-ACKed by addressed..,1: Transmitted data not ACKed by addressed slave" newline rbitfld.long 0x00 2. "ABRT_10ADDR2_NOACK,This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver" "0: This abort is not generated,1: Byte 2 of 10Bit Address not ACKed by any slave" newline rbitfld.long 0x00 1. "ABRT_10ADDR1_NOACK,This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver" "0: This abort is not generated,1: Byte 1 of 10Bit Address not ACKed by any slave" newline rbitfld.long 0x00 0. "ABRT_7B_ADDR_NOACK,This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver" "0: This abort is not generated,1: This abort is generated because of NOACK for.." group.long 0x84++0x03 line.long 0x00 "IC_SLV_DATA_NACK_ONLY,Generate Slave Data NACK Register\n\n The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver" bitfld.long 0x00 0. "NACK,Generate NACK" "0: Slave receiver generates NACK normally,1: Slave receiver generates NACK upon data.." group.long 0x88++0x03 line.long 0x00 "IC_DMA_CR,DMA Control Register\n\n The register is used to enable the DMA Controller interface operation" bitfld.long 0x00 1. "TDMAE,Transmit DMA Enable" "0: transmit FIFO DMA channel disabled,1: Transmit FIFO DMA channel enabled" newline bitfld.long 0x00 0. "RDMAE,Receive DMA Enable" "0: Receive FIFO DMA channel disabled,1: Receive FIFO DMA channel enabled" group.long 0x8C++0x03 line.long 0x00 "IC_DMA_TDLR,DMA Transmit Data Level Register" bitfld.long 0x00 0.--3. "DMATDL,Transmit Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x03 line.long 0x00 "IC_DMA_RDLR,I2C Receive Data Level Register" bitfld.long 0x00 0.--3. "DMARDL,Receive Data Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x94++0x03 line.long 0x00 "IC_SDA_SETUP,I2C SDA Setup Register\n\n This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a.." hexmask.long.byte 0x00 0.--7. 1. "SDA_SETUP,SDA Setup" group.long 0x98++0x03 line.long 0x00 "IC_ACK_GENERAL_CALL,I2C ACK General Call Register\n\n The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n This register is applicable only when the DW_apb_i2c is in slave mode" bitfld.long 0x00 0. "ACK_GEN_CALL,ACK General Call" "0: Generate NACK for a General Call,1: Generate ACK for a General Call" group.long 0x9C++0x03 line.long 0x00 "IC_ENABLE_STATUS,I2C Enable Status Register\n\n The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0 that is when DW_apb_i2c is disabled.\n\n If IC_ENABLE[0] has been set to 1 bits 2:1 are.." rbitfld.long 0x00 2. "SLV_RX_DATA_LOST,Slave Received Data Lost" "0: Slave RX Data is not lost,1: Slave RX Data is lost" newline rbitfld.long 0x00 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive)" "0: Slave is disabled when it is idle,1: Slave is disabled when it is active" newline rbitfld.long 0x00 0. "IC_EN,ic_en Status" "0: I2C disabled,1: I2C enabled" group.long 0xA0++0x03 line.long 0x00 "IC_FS_SPKLEN,I2C SS FS or FM+ spike suppression limit\n\n This register is used to store the duration measured in ic_clk cycles of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS FS or FM+ modes" hexmask.long.byte 0x00 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation" group.long 0xA8++0x03 line.long 0x00 "IC_CLR_RESTART_DET,Clear RESTART_DET Interrupt Register" rbitfld.long 0x00 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n Reset value: 0x0" "0,1" group.long 0xF4++0x03 line.long 0x00 "IC_COMP_PARAM_1,Component Parameter Register 1\n\n Note This register is not implemented and therefore reads as 0" hexmask.long.byte 0x00 16.--23. 1. "TX_BUFFER_DEPTH,TX Buffer Depth = 16" newline hexmask.long.byte 0x00 8.--15. 1. "RX_BUFFER_DEPTH,RX Buffer Depth = 16" newline rbitfld.long 0x00 7. "ADD_ENCODED_PARAMS,Encoded parameters not visible" "0,1" newline rbitfld.long 0x00 6. "HAS_DMA,DMA handshaking signals are enabled" "0,1" newline rbitfld.long 0x00 5. "INTR_IO,COMBINED Interrupt outputs" "0,1" newline rbitfld.long 0x00 4. "HC_COUNT_VALUES,Programmable count values for each mode" "0,1" newline rbitfld.long 0x00 2.--3. "MAX_SPEED_MODE,MAX SPEED MODE = FAST MODE" "0,1,2,3" newline rbitfld.long 0x00 0.--1. "APB_DATA_WIDTH,APB data bus width is 32 bits" "0,1,2,3" group.long 0xF8++0x03 line.long 0x00 "IC_COMP_VERSION,I2C Component Version Register" hexmask.long 0x00 0.--31. 1. "IC_COMP_VERSION," group.long 0xFC++0x03 line.long 0x00 "IC_COMP_TYPE,I2C Component Type Register" hexmask.long 0x00 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number = 0x44_57_01_40" tree.end repeat.end tree.end tree "IO_BANK0" base ad:0x40014000 group.long 0x00++0x03 line.long 0x00 "GPIO0_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x04++0x03 line.long 0x00 "GPIO0_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x08++0x03 line.long 0x00 "GPIO1_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x0C++0x03 line.long 0x00 "GPIO1_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,1: spi0_ss_n,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x10++0x03 line.long 0x00 "GPIO2_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x14++0x03 line.long 0x00 "GPIO2_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,1: spi0_sclk,2: uart0_cts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x18++0x03 line.long 0x00 "GPIO3_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x1C++0x03 line.long 0x00 "GPIO3_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,1: UNKN_DESC,2: uart0_rts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x20++0x03 line.long 0x00 "GPIO4_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x24++0x03 line.long 0x00 "GPIO4_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x28++0x03 line.long 0x00 "GPIO5_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x2C++0x03 line.long 0x00 "GPIO5_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi0_ss_n,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x30++0x03 line.long 0x00 "GPIO6_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x34++0x03 line.long 0x00 "GPIO6_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi0_sclk,2: uart1_cts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_extphy_softcon,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x38++0x03 line.long 0x00 "GPIO7_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x3C++0x03 line.long 0x00 "GPIO7_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: uart1_rts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_extphy_oe_n,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x40++0x03 line.long 0x00 "GPIO8_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x44++0x03 line.long 0x00 "GPIO8_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_extphy_rcv,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x48++0x03 line.long 0x00 "GPIO9_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x4C++0x03 line.long 0x00 "GPIO9_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi1_ss_n,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_extphy_vp,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x50++0x03 line.long 0x00 "GPIO10_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x54++0x03 line.long 0x00 "GPIO10_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi1_sclk,2: uart1_cts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_extphy_vm,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x58++0x03 line.long 0x00 "GPIO11_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x5C++0x03 line.long 0x00 "GPIO11_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: uart1_rts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_extphy_suspnd,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x60++0x03 line.long 0x00 "GPIO12_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x64++0x03 line.long 0x00 "GPIO12_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_extphy_speed,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x68++0x03 line.long 0x00 "GPIO13_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x6C++0x03 line.long 0x00 "GPIO13_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi1_ss_n,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_extphy_vpo,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x70++0x03 line.long 0x00 "GPIO14_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x74++0x03 line.long 0x00 "GPIO14_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi1_sclk,2: uart0_cts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_extphy_vmo,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x78++0x03 line.long 0x00 "GPIO15_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x7C++0x03 line.long 0x00 "GPIO15_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: uart0_rts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_digital_dp,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x80++0x03 line.long 0x00 "GPIO16_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x84++0x03 line.long 0x00 "GPIO16_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: usb_muxing_digital_dm,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x88++0x03 line.long 0x00 "GPIO17_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x8C++0x03 line.long 0x00 "GPIO17_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi0_ss_n,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x90++0x03 line.long 0x00 "GPIO18_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x94++0x03 line.long 0x00 "GPIO18_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi0_sclk,2: uart0_cts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x98++0x03 line.long 0x00 "GPIO19_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x9C++0x03 line.long 0x00 "GPIO19_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: uart0_rts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xA0++0x03 line.long 0x00 "GPIO20_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xA4++0x03 line.long 0x00 "GPIO20_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: clocks_gpin_0,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xA8++0x03 line.long 0x00 "GPIO21_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xAC++0x03 line.long 0x00 "GPIO21_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi0_ss_n,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: clocks_gpout_0,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xB0++0x03 line.long 0x00 "GPIO22_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xB4++0x03 line.long 0x00 "GPIO22_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi0_sclk,2: uart1_cts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: clocks_gpin_1,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xB8++0x03 line.long 0x00 "GPIO23_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xBC++0x03 line.long 0x00 "GPIO23_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: uart1_rts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: clocks_gpout_1,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xC0++0x03 line.long 0x00 "GPIO24_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xC4++0x03 line.long 0x00 "GPIO24_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: clocks_gpout_2,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xC8++0x03 line.long 0x00 "GPIO25_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xCC++0x03 line.long 0x00 "GPIO25_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi1_ss_n,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,8: clocks_gpout_3,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xD0++0x03 line.long 0x00 "GPIO26_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xD4++0x03 line.long 0x00 "GPIO26_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi1_sclk,2: uart1_cts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xD8++0x03 line.long 0x00 "GPIO27_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xDC++0x03 line.long 0x00 "GPIO27_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: uart1_rts,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_overcurr_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xE0++0x03 line.long 0x00 "GPIO28_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xE4++0x03 line.long 0x00 "GPIO28_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_vbus_detect,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xE8++0x03 line.long 0x00 "GPIO29_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0xEC++0x03 line.long 0x00 "GPIO29_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "?,1: spi1_ss_n,2: UNKN_DESC,3: UNKN_DESC,4: UNKN_DESC,5: UNKN_DESC,6: UNKN_DESC,7: UNKN_DESC,?,9: usb_muxing_vbus_en,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0xF0++0x03 line.long 0x00 "INTR0,Raw Interrupts" eventfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" eventfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline eventfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" eventfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline eventfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" eventfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline eventfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" eventfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline eventfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" eventfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline eventfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" eventfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline eventfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" eventfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline eventfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" eventfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0xF4++0x03 line.long 0x00 "INTR1,Raw Interrupts" eventfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" eventfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline eventfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" eventfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline eventfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" eventfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline eventfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" eventfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline eventfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" eventfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline eventfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" eventfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline eventfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" eventfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline eventfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" eventfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0xF8++0x03 line.long 0x00 "INTR2,Raw Interrupts" eventfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" eventfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline eventfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" eventfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline eventfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" eventfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline eventfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" eventfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline eventfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" eventfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline eventfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" eventfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline eventfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" eventfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline eventfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" eventfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0xFC++0x03 line.long 0x00 "INTR3,Raw Interrupts" eventfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" eventfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline eventfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" eventfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline eventfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" eventfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline eventfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" eventfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline eventfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" eventfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline eventfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" eventfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" group.long 0x100++0x03 line.long 0x00 "PROC0_INTE0,Interrupt Enable for proc0" bitfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0x104++0x03 line.long 0x00 "PROC0_INTE1,Interrupt Enable for proc0" bitfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0x108++0x03 line.long 0x00 "PROC0_INTE2,Interrupt Enable for proc0" bitfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0x10C++0x03 line.long 0x00 "PROC0_INTE3,Interrupt Enable for proc0" bitfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" group.long 0x110++0x03 line.long 0x00 "PROC0_INTF0,Interrupt Force for proc0" bitfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0x114++0x03 line.long 0x00 "PROC0_INTF1,Interrupt Force for proc0" bitfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0x118++0x03 line.long 0x00 "PROC0_INTF2,Interrupt Force for proc0" bitfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0x11C++0x03 line.long 0x00 "PROC0_INTF3,Interrupt Force for proc0" bitfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" group.long 0x120++0x03 line.long 0x00 "PROC0_INTS0,Interrupt status after masking & forcing for proc0" rbitfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" rbitfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" rbitfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0x124++0x03 line.long 0x00 "PROC0_INTS1,Interrupt status after masking & forcing for proc0" rbitfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" rbitfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" rbitfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0x128++0x03 line.long 0x00 "PROC0_INTS2,Interrupt status after masking & forcing for proc0" rbitfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" rbitfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" rbitfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0x12C++0x03 line.long 0x00 "PROC0_INTS3,Interrupt status after masking & forcing for proc0" rbitfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" group.long 0x130++0x03 line.long 0x00 "PROC1_INTE0,Interrupt Enable for proc1" bitfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0x134++0x03 line.long 0x00 "PROC1_INTE1,Interrupt Enable for proc1" bitfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0x138++0x03 line.long 0x00 "PROC1_INTE2,Interrupt Enable for proc1" bitfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0x13C++0x03 line.long 0x00 "PROC1_INTE3,Interrupt Enable for proc1" bitfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" group.long 0x140++0x03 line.long 0x00 "PROC1_INTF0,Interrupt Force for proc1" bitfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0x144++0x03 line.long 0x00 "PROC1_INTF1,Interrupt Force for proc1" bitfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0x148++0x03 line.long 0x00 "PROC1_INTF2,Interrupt Force for proc1" bitfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0x14C++0x03 line.long 0x00 "PROC1_INTF3,Interrupt Force for proc1" bitfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" group.long 0x150++0x03 line.long 0x00 "PROC1_INTS0,Interrupt status after masking & forcing for proc1" rbitfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" rbitfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" rbitfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0x154++0x03 line.long 0x00 "PROC1_INTS1,Interrupt status after masking & forcing for proc1" rbitfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" rbitfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" rbitfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0x158++0x03 line.long 0x00 "PROC1_INTS2,Interrupt status after masking & forcing for proc1" rbitfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" rbitfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" rbitfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0x15C++0x03 line.long 0x00 "PROC1_INTS3,Interrupt status after masking & forcing for proc1" rbitfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" group.long 0x160++0x03 line.long 0x00 "DORMANT_WAKE_INTE0,Interrupt Enable for dormant_wake" bitfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0x164++0x03 line.long 0x00 "DORMANT_WAKE_INTE1,Interrupt Enable for dormant_wake" bitfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0x168++0x03 line.long 0x00 "DORMANT_WAKE_INTE2,Interrupt Enable for dormant_wake" bitfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0x16C++0x03 line.long 0x00 "DORMANT_WAKE_INTE3,Interrupt Enable for dormant_wake" bitfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" group.long 0x170++0x03 line.long 0x00 "DORMANT_WAKE_INTF0,Interrupt Force for dormant_wake" bitfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0x174++0x03 line.long 0x00 "DORMANT_WAKE_INTF1,Interrupt Force for dormant_wake" bitfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0x178++0x03 line.long 0x00 "DORMANT_WAKE_INTF2,Interrupt Force for dormant_wake" bitfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" bitfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline bitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" bitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline bitfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" bitfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline bitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" bitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline bitfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0x17C++0x03 line.long 0x00 "DORMANT_WAKE_INTF3,Interrupt Force for dormant_wake" bitfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" bitfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" bitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" bitfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" bitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" bitfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" bitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" bitfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" bitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" bitfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" bitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" bitfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" bitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" group.long 0x180++0x03 line.long 0x00 "DORMANT_WAKE_INTS0,Interrupt status after masking & forcing for dormant_wake" rbitfld.long 0x00 31. "GPIO7_EDGE_HIGH," "0,1" rbitfld.long 0x00 30. "GPIO7_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO7_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO7_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 27. "GPIO6_EDGE_HIGH," "0,1" rbitfld.long 0x00 26. "GPIO6_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO6_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO6_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 23. "GPIO5_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO5_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO5_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO5_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO4_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO4_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO4_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO4_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO3_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO3_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO3_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO3_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO2_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO2_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO2_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO2_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO1_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO1_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO1_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO1_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO0_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO0_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO0_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO0_LEVEL_LOW," "0,1" group.long 0x184++0x03 line.long 0x00 "DORMANT_WAKE_INTS1,Interrupt status after masking & forcing for dormant_wake" rbitfld.long 0x00 31. "GPIO15_EDGE_HIGH," "0,1" rbitfld.long 0x00 30. "GPIO15_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO15_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO15_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 27. "GPIO14_EDGE_HIGH," "0,1" rbitfld.long 0x00 26. "GPIO14_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO14_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO14_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 23. "GPIO13_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO13_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO13_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO13_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO12_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO12_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO12_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO12_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO11_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO11_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO11_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO11_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO10_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO10_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO10_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO10_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO9_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO9_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO9_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO9_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO8_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO8_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO8_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO8_LEVEL_LOW," "0,1" group.long 0x188++0x03 line.long 0x00 "DORMANT_WAKE_INTS2,Interrupt status after masking & forcing for dormant_wake" rbitfld.long 0x00 31. "GPIO23_EDGE_HIGH," "0,1" rbitfld.long 0x00 30. "GPIO23_EDGE_LOW," "0,1" newline rbitfld.long 0x00 29. "GPIO23_LEVEL_HIGH," "0,1" rbitfld.long 0x00 28. "GPIO23_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 27. "GPIO22_EDGE_HIGH," "0,1" rbitfld.long 0x00 26. "GPIO22_EDGE_LOW," "0,1" newline rbitfld.long 0x00 25. "GPIO22_LEVEL_HIGH," "0,1" rbitfld.long 0x00 24. "GPIO22_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 23. "GPIO21_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO21_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO21_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO21_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO20_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO20_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO20_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO20_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO19_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO19_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO19_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO19_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO18_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO18_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO18_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO18_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO17_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO17_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO17_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO17_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO16_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO16_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO16_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO16_LEVEL_LOW," "0,1" group.long 0x18C++0x03 line.long 0x00 "DORMANT_WAKE_INTS3,Interrupt status after masking & forcing for dormant_wake" rbitfld.long 0x00 23. "GPIO29_EDGE_HIGH," "0,1" rbitfld.long 0x00 22. "GPIO29_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO29_LEVEL_HIGH," "0,1" rbitfld.long 0x00 20. "GPIO29_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO28_EDGE_HIGH," "0,1" rbitfld.long 0x00 18. "GPIO28_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO28_LEVEL_HIGH," "0,1" rbitfld.long 0x00 16. "GPIO28_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO27_EDGE_HIGH," "0,1" rbitfld.long 0x00 14. "GPIO27_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO27_LEVEL_HIGH," "0,1" rbitfld.long 0x00 12. "GPIO27_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO26_EDGE_HIGH," "0,1" rbitfld.long 0x00 10. "GPIO26_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO26_LEVEL_HIGH," "0,1" rbitfld.long 0x00 8. "GPIO26_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO25_EDGE_HIGH," "0,1" rbitfld.long 0x00 6. "GPIO25_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO25_LEVEL_HIGH," "0,1" rbitfld.long 0x00 4. "GPIO25_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO24_EDGE_HIGH," "0,1" rbitfld.long 0x00 2. "GPIO24_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO24_LEVEL_HIGH," "0,1" rbitfld.long 0x00 0. "GPIO24_LEVEL_LOW," "0,1" tree.end tree "IO_QSPI" base ad:0x40018000 group.long 0x00++0x03 line.long 0x00 "GPIO_QSPI_SCLK_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" newline rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" newline rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" newline rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" newline rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x04++0x03 line.long 0x00 "GPIO_QSPI_SCLK_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" newline bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" newline bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,?,?,?,?,5: UNKN_DESC,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x08++0x03 line.long 0x00 "GPIO_QSPI_SS_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" newline rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" newline rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" newline rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" newline rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x0C++0x03 line.long 0x00 "GPIO_QSPI_SS_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" newline bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" newline bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,?,?,?,?,5: UNKN_DESC,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x10++0x03 line.long 0x00 "GPIO_QSPI_SD0_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" newline rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" newline rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" newline rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" newline rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x14++0x03 line.long 0x00 "GPIO_QSPI_SD0_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" newline bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" newline bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,?,?,?,?,5: UNKN_DESC,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x18++0x03 line.long 0x00 "GPIO_QSPI_SD1_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" newline rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" newline rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" newline rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" newline rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x1C++0x03 line.long 0x00 "GPIO_QSPI_SD1_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" newline bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" newline bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,?,?,?,?,5: UNKN_DESC,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x20++0x03 line.long 0x00 "GPIO_QSPI_SD2_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" newline rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" newline rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" newline rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" newline rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x24++0x03 line.long 0x00 "GPIO_QSPI_SD2_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" newline bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" newline bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,?,?,?,?,5: UNKN_DESC,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x28++0x03 line.long 0x00 "GPIO_QSPI_SD3_STATUS,GPIO status" rbitfld.long 0x00 26. "IRQTOPROC,interrupt to processors after override is applied" "0,1" newline rbitfld.long 0x00 24. "IRQFROMPAD,interrupt from pad before override is applied" "0,1" newline rbitfld.long 0x00 19. "INTOPERI,input signal to peripheral after override is applied" "0,1" newline rbitfld.long 0x00 17. "INFROMPAD,input signal from pad before override is applied" "0,1" newline rbitfld.long 0x00 13. "OETOPAD,output enable to pad after register override is applied" "0,1" newline rbitfld.long 0x00 12. "OEFROMPERI,output enable from selected peripheral before register override is applied" "0,1" newline rbitfld.long 0x00 9. "OUTTOPAD,output signal to pad after register override is applied" "0,1" newline rbitfld.long 0x00 8. "OUTFROMPERI,output signal from selected peripheral before register override is applied" "0,1" group.long 0x2C++0x03 line.long 0x00 "GPIO_QSPI_SD3_CTRL,GPIO control including function select and overrides" bitfld.long 0x00 28.--29. "IRQOVER," "0: don't invert the interrupt,1: invert the interrupt,2: drive interrupt low,3: drive interrupt high" newline bitfld.long 0x00 16.--17. "INOVER," "0: don't invert the peri input,1: invert the peri input,2: drive peri input low,3: drive peri input high" newline bitfld.long 0x00 12.--13. "OEOVER," "0: drive output enable from peripheral signal..,1: drive output enable from inverse of..,2: disable output,3: enable output" newline bitfld.long 0x00 8.--9. "OUTOVER," "0: drive output from peripheral signal selected..,1: drive output from inverse of peripheral..,2: drive output low,3: drive output high" newline bitfld.long 0x00 0.--4. "FUNCSEL,0-31 -> selects pin function according to the gpio table\n" "0: UNKN_DESC,?,?,?,?,5: UNKN_DESC,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: UNKN_DESC" group.long 0x30++0x03 line.long 0x00 "INTR,Raw Interrupts" eventfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline eventfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline eventfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline eventfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline eventfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline eventfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline eventfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline eventfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline eventfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline eventfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline eventfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline eventfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" group.long 0x34++0x03 line.long 0x00 "PROC0_INTE,Interrupt Enable for proc0" bitfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline bitfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline bitfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline bitfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline bitfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline bitfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline bitfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" group.long 0x38++0x03 line.long 0x00 "PROC0_INTF,Interrupt Force for proc0" bitfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline bitfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline bitfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline bitfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline bitfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline bitfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline bitfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" group.long 0x3C++0x03 line.long 0x00 "PROC0_INTS,Interrupt status after masking & forcing for proc0" rbitfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" group.long 0x40++0x03 line.long 0x00 "PROC1_INTE,Interrupt Enable for proc1" bitfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline bitfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline bitfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline bitfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline bitfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline bitfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline bitfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" group.long 0x44++0x03 line.long 0x00 "PROC1_INTF,Interrupt Force for proc1" bitfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline bitfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline bitfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline bitfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline bitfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline bitfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline bitfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" group.long 0x48++0x03 line.long 0x00 "PROC1_INTS,Interrupt status after masking & forcing for proc1" rbitfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" group.long 0x4C++0x03 line.long 0x00 "DORMANT_WAKE_INTE,Interrupt Enable for dormant_wake" bitfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline bitfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline bitfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline bitfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline bitfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline bitfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline bitfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" group.long 0x50++0x03 line.long 0x00 "DORMANT_WAKE_INTF,Interrupt Force for dormant_wake" bitfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline bitfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline bitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline bitfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline bitfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline bitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline bitfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline bitfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline bitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline bitfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline bitfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline bitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline bitfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline bitfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline bitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline bitfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline bitfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline bitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline bitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" group.long 0x54++0x03 line.long 0x00 "DORMANT_WAKE_INTS,Interrupt status after masking & forcing for dormant_wake" rbitfld.long 0x00 23. "GPIO_QSPI_SD3_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 22. "GPIO_QSPI_SD3_EDGE_LOW," "0,1" newline rbitfld.long 0x00 21. "GPIO_QSPI_SD3_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 20. "GPIO_QSPI_SD3_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 19. "GPIO_QSPI_SD2_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 18. "GPIO_QSPI_SD2_EDGE_LOW," "0,1" newline rbitfld.long 0x00 17. "GPIO_QSPI_SD2_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 16. "GPIO_QSPI_SD2_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 15. "GPIO_QSPI_SD1_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 14. "GPIO_QSPI_SD1_EDGE_LOW," "0,1" newline rbitfld.long 0x00 13. "GPIO_QSPI_SD1_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 12. "GPIO_QSPI_SD1_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 11. "GPIO_QSPI_SD0_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 10. "GPIO_QSPI_SD0_EDGE_LOW," "0,1" newline rbitfld.long 0x00 9. "GPIO_QSPI_SD0_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 8. "GPIO_QSPI_SD0_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 7. "GPIO_QSPI_SS_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 6. "GPIO_QSPI_SS_EDGE_LOW," "0,1" newline rbitfld.long 0x00 5. "GPIO_QSPI_SS_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 4. "GPIO_QSPI_SS_LEVEL_LOW," "0,1" newline rbitfld.long 0x00 3. "GPIO_QSPI_SCLK_EDGE_HIGH," "0,1" newline rbitfld.long 0x00 2. "GPIO_QSPI_SCLK_EDGE_LOW," "0,1" newline rbitfld.long 0x00 1. "GPIO_QSPI_SCLK_LEVEL_HIGH," "0,1" newline rbitfld.long 0x00 0. "GPIO_QSPI_SCLK_LEVEL_LOW," "0,1" tree.end tree "PADS_BANK0" base ad:0x4001C000 group.long 0x00++0x03 line.long 0x00 "VOLTAGE_SELECT,Voltage select" bitfld.long 0x00 0. "VOLTAGE_SELECT," "0: Set voltage to 3.3V (DVDD >= 2V5),1: Set voltage to 1.8V (DVDD <= 1V8)" repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x04)++0x03 line.long 0x00 "GPIO$1,Pad control register" bitfld.long 0x00 7. "OD,Output disable" "0,1" bitfld.long 0x00 6. "IE,Input enable" "0,1" bitfld.long 0x00 4.--5. "DRIVE,Drive strength" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 3. "PUE,Pull up enable" "0,1" bitfld.long 0x00 2. "PDE,Pull down enable" "0,1" newline bitfld.long 0x00 1. "SCHMITT,Enable schmitt trigger" "0,1" bitfld.long 0x00 0. "SLEWFAST,Slew rate control" "0: Slow,1: Fast" repeat.end repeat 14. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 ) group.long ($2+0x44)++0x03 line.long 0x00 "GPIO$1,Pad control register" bitfld.long 0x00 7. "OD,Output disable" "0,1" bitfld.long 0x00 6. "IE,Input enable" "0,1" bitfld.long 0x00 4.--5. "DRIVE,Drive strength" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 3. "PUE,Pull up enable" "0,1" bitfld.long 0x00 2. "PDE,Pull down enable" "0,1" newline bitfld.long 0x00 1. "SCHMITT,Enable schmitt trigger" "0,1" bitfld.long 0x00 0. "SLEWFAST,Slew rate control" "0: Slow,1: Fast" repeat.end group.long 0x7C++0x03 line.long 0x00 "SWCLK,Pad control register" bitfld.long 0x00 7. "OD,Output disable" "0,1" bitfld.long 0x00 6. "IE,Input enable" "0,1" bitfld.long 0x00 4.--5. "DRIVE,Drive strength" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 3. "PUE,Pull up enable" "0,1" bitfld.long 0x00 2. "PDE,Pull down enable" "0,1" newline bitfld.long 0x00 1. "SCHMITT,Enable schmitt trigger" "0,1" bitfld.long 0x00 0. "SLEWFAST,Slew rate control" "0: Slow,1: Fast" group.long 0x80++0x03 line.long 0x00 "SWD,Pad control register" bitfld.long 0x00 7. "OD,Output disable" "0,1" bitfld.long 0x00 6. "IE,Input enable" "0,1" bitfld.long 0x00 4.--5. "DRIVE,Drive strength" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 3. "PUE,Pull up enable" "0,1" bitfld.long 0x00 2. "PDE,Pull down enable" "0,1" newline bitfld.long 0x00 1. "SCHMITT,Enable schmitt trigger" "0,1" bitfld.long 0x00 0. "SLEWFAST,Slew rate control" "0: Slow,1: Fast" tree.end tree "PADS_QSPI" base ad:0x40020000 group.long 0x00++0x03 line.long 0x00 "VOLTAGE_SELECT,Voltage select" bitfld.long 0x00 0. "VOLTAGE_SELECT," "0: Set voltage to 3.3V (DVDD >= 2V5),1: Set voltage to 1.8V (DVDD <= 1V8)" group.long 0x04++0x03 line.long 0x00 "GPIO_QSPI_SCLK,Pad control register" bitfld.long 0x00 7. "OD,Output disable" "0,1" bitfld.long 0x00 6. "IE,Input enable" "0,1" bitfld.long 0x00 4.--5. "DRIVE,Drive strength" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 3. "PUE,Pull up enable" "0,1" bitfld.long 0x00 2. "PDE,Pull down enable" "0,1" newline bitfld.long 0x00 1. "SCHMITT,Enable schmitt trigger" "0,1" bitfld.long 0x00 0. "SLEWFAST,Slew rate control" "0: Slow,1: Fast" repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x08)++0x03 line.long 0x00 "GPIO_QSPI_SD$1,Pad control register" bitfld.long 0x00 7. "OD,Output disable" "0,1" bitfld.long 0x00 6. "IE,Input enable" "0,1" bitfld.long 0x00 4.--5. "DRIVE,Drive strength" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 3. "PUE,Pull up enable" "0,1" bitfld.long 0x00 2. "PDE,Pull down enable" "0,1" newline bitfld.long 0x00 1. "SCHMITT,Enable schmitt trigger" "0,1" bitfld.long 0x00 0. "SLEWFAST,Slew rate control" "0: Slow,1: Fast" repeat.end group.long 0x18++0x03 line.long 0x00 "GPIO_QSPI_SS,Pad control register" bitfld.long 0x00 7. "OD,Output disable" "0,1" bitfld.long 0x00 6. "IE,Input enable" "0,1" bitfld.long 0x00 4.--5. "DRIVE,Drive strength" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 3. "PUE,Pull up enable" "0,1" bitfld.long 0x00 2. "PDE,Pull down enable" "0,1" newline bitfld.long 0x00 1. "SCHMITT,Enable schmitt trigger" "0,1" bitfld.long 0x00 0. "SLEWFAST,Slew rate control" "0: Slow,1: Fast" tree.end tree "PIO (Programmable IO block)" repeat 2. (list 0. 1.) (list ad:0x50200000 ad:0x50300000) tree "PIO$1" base $2 group.long 0x00++0x03 line.long 0x00 "CTRL,PIO control register" bitfld.long 0x00 8.--11. "CLKDIV_RESTART,Restart a state machine's clock divider from an initial phase of 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SM_RESTART,Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n Specifically the following are cleared: input and output shift counters the contents of the input shift register the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SM_ENABLE,Enable/disable each of the four state machines by writing 1/0 to each of these four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x04++0x03 line.long 0x00 "FSTAT,FIFO status register" rbitfld.long 0x00 24.--27. "TXEMPTY,State machine TX FIFO is empty" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. "TXFULL,State machine TX FIFO is full" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. "RXEMPTY,State machine RX FIFO is empty" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "RXFULL,State machine RX FIFO is full" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x08++0x03 line.long 0x00 "FDEBUG,FIFO debug register" eventfld.long 0x00 24.--27. "TXSTALL,State machine has stalled on empty TX FIFO during a blocking PULL or an OUT with autopull enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" eventfld.long 0x00 16.--19. "TXOVER,TX FIFO overflow (i.e. write-on-full by the system) has occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" eventfld.long 0x00 8.--11. "RXUNDER,RX FIFO underflow (i.e. read-on-empty by the system) has occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" eventfld.long 0x00 0.--3. "RXSTALL,State machine has stalled on full RX FIFO during a blocking PUSH or an IN with autopush enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x0C++0x03 line.long 0x00 "FLEVEL,FIFO levels" rbitfld.long 0x00 28.--31. "RX3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--27. "TX3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 20.--23. "RX2," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. "TX2," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 12.--15. "RX1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. "TX1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. "RX0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "TX0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC ) wgroup.long ($2+0x10)++0x03 line.long 0x00 "TXF$1,Direct write access to the TX FIFO for this state machine" repeat.end repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC ) rgroup.long ($2+0x20)++0x03 line.long 0x00 "RXF$1,Direct read access to the RX FIFO for this state machine" repeat.end group.long 0x30++0x03 line.long 0x00 "IRQ,State machine IRQ flags register" hexmask.long.byte 0x00 0.--7. 1. "IRQ," group.long 0x34++0x03 line.long 0x00 "IRQ_FORCE,Writing a 1 to each of these bits will forcibly assert the corresponding IRQ" hexmask.long.byte 0x00 0.--7. 1. "IRQ_FORCE," group.long 0x38++0x03 line.long 0x00 "INPUT_SYNC_BYPASS,There is a 2-flipflop synchronizer on each GPIO input which protects PIO logic from metastabilities" rgroup.long 0x3C++0x03 line.long 0x00 "DBG_PADOUT,Read to sample the pad output values PIO is currently driving to the GPIOs" rgroup.long 0x40++0x03 line.long 0x00 "DBG_PADOE,Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs" group.long 0x44++0x03 line.long 0x00 "DBG_CFGINFO,The PIO hardware has some free parameters that may vary between chip products.\n These should be provided in the chip datasheet but are also exposed here" rbitfld.long 0x00 16.--21. "IMEM_SIZE,The size of the instruction memory measured in units of one instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 8.--11. "SM_COUNT,The number of state machines this PIO instance is equipped with" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--5. "FIFO_DEPTH,The depth of the state machine TX/RX FIFOs measured in words.\n Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n this depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x48++0x03 line.long 0x00 "INSTR_MEM0,Write-only access to instruction memory location 0" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM0," group.long 0x4C++0x03 line.long 0x00 "INSTR_MEM1,Write-only access to instruction memory location 1" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM1," group.long 0x50++0x03 line.long 0x00 "INSTR_MEM2,Write-only access to instruction memory location 2" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM2," group.long 0x54++0x03 line.long 0x00 "INSTR_MEM3,Write-only access to instruction memory location 3" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM3," group.long 0x58++0x03 line.long 0x00 "INSTR_MEM4,Write-only access to instruction memory location 4" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM4," group.long 0x5C++0x03 line.long 0x00 "INSTR_MEM5,Write-only access to instruction memory location 5" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM5," group.long 0x60++0x03 line.long 0x00 "INSTR_MEM6,Write-only access to instruction memory location 6" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM6," group.long 0x64++0x03 line.long 0x00 "INSTR_MEM7,Write-only access to instruction memory location 7" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM7," group.long 0x68++0x03 line.long 0x00 "INSTR_MEM8,Write-only access to instruction memory location 8" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM8," group.long 0x6C++0x03 line.long 0x00 "INSTR_MEM9,Write-only access to instruction memory location 9" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM9," group.long 0x70++0x03 line.long 0x00 "INSTR_MEM10,Write-only access to instruction memory location 10" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM10," group.long 0x74++0x03 line.long 0x00 "INSTR_MEM11,Write-only access to instruction memory location 11" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM11," group.long 0x78++0x03 line.long 0x00 "INSTR_MEM12,Write-only access to instruction memory location 12" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM12," group.long 0x7C++0x03 line.long 0x00 "INSTR_MEM13,Write-only access to instruction memory location 13" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM13," group.long 0x80++0x03 line.long 0x00 "INSTR_MEM14,Write-only access to instruction memory location 14" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM14," group.long 0x84++0x03 line.long 0x00 "INSTR_MEM15,Write-only access to instruction memory location 15" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM15," group.long 0x88++0x03 line.long 0x00 "INSTR_MEM16,Write-only access to instruction memory location 16" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM16," group.long 0x8C++0x03 line.long 0x00 "INSTR_MEM17,Write-only access to instruction memory location 17" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM17," group.long 0x90++0x03 line.long 0x00 "INSTR_MEM18,Write-only access to instruction memory location 18" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM18," group.long 0x94++0x03 line.long 0x00 "INSTR_MEM19,Write-only access to instruction memory location 19" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM19," group.long 0x98++0x03 line.long 0x00 "INSTR_MEM20,Write-only access to instruction memory location 20" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM20," group.long 0x9C++0x03 line.long 0x00 "INSTR_MEM21,Write-only access to instruction memory location 21" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM21," group.long 0xA0++0x03 line.long 0x00 "INSTR_MEM22,Write-only access to instruction memory location 22" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM22," group.long 0xA4++0x03 line.long 0x00 "INSTR_MEM23,Write-only access to instruction memory location 23" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM23," group.long 0xA8++0x03 line.long 0x00 "INSTR_MEM24,Write-only access to instruction memory location 24" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM24," group.long 0xAC++0x03 line.long 0x00 "INSTR_MEM25,Write-only access to instruction memory location 25" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM25," group.long 0xB0++0x03 line.long 0x00 "INSTR_MEM26,Write-only access to instruction memory location 26" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM26," group.long 0xB4++0x03 line.long 0x00 "INSTR_MEM27,Write-only access to instruction memory location 27" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM27," group.long 0xB8++0x03 line.long 0x00 "INSTR_MEM28,Write-only access to instruction memory location 28" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM28," group.long 0xBC++0x03 line.long 0x00 "INSTR_MEM29,Write-only access to instruction memory location 29" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM29," group.long 0xC0++0x03 line.long 0x00 "INSTR_MEM30,Write-only access to instruction memory location 30" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM30," group.long 0xC4++0x03 line.long 0x00 "INSTR_MEM31,Write-only access to instruction memory location 31" hexmask.long.word 0x00 0.--15. 1. "INSTR_MEM31," group.long 0xC8++0x03 line.long 0x00 "SM0_CLKDIV,Clock divisor register for state machine 0\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)" hexmask.long.word 0x00 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256).\n Value of 0 is interpreted as 65536" hexmask.long.byte 0x00 8.--15. 1. "FRAC,Fractional part of clock divisor" group.long 0xCC++0x03 line.long 0x00 "SM0_EXECCTRL,Execution/behavioural settings for state machine 0" rbitfld.long 0x00 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine" "0,1" bitfld.long 0x00 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit" "0,1" bitfld.long 0x00 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1" bitfld.long 0x00 24.--28. "JMP_PIN,The GPIO number to use as condition for JMP PIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19.--23. "OUT_EN_SEL,Which data bit to use for inline OUT enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY writes with an enable of 0 will\n deassert the latest pin" "0,1" bitfld.long 0x00 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1" bitfld.long 0x00 12.--16. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom.\n If the instruction is a jump and the jump condition is true the jump takes priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--11. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "STATUS_SEL,Comparison used for the MOV x STATUS instruction" "0: All-ones if TX FIFO level < N otherwise..,1: All-ones if RX FIFO level < N otherwise.." bitfld.long 0x00 0.--3. "STATUS_N,Comparison level for the MOV x STATUS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD0++0x03 line.long 0x00 "SM0_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 0" bitfld.long 0x00 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed" "0,1" bitfld.long 0x00 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed" "0,1" bitfld.long 0x00 25.--29. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place.\n Write 0 for value of 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place.\n Write 0 for value of 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19. "OUT_SHIFTDIR," "0,1" bitfld.long 0x00 18. "IN_SHIFTDIR," "0,1" bitfld.long 0x00 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e" "0,1" bitfld.long 0x00 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e" "0,1" group.long 0xD4++0x03 line.long 0x00 "SM0_ADDR,Current instruction address of state machine 0" rbitfld.long 0x00 0.--4. "SM0_ADDR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD8++0x03 line.long 0x00 "SM0_INSTR,Read to see the instruction currently addressed by state machine 0's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution" hexmask.long.word 0x00 0.--15. 1. "SM0_INSTR," group.long 0xDC++0x03 line.long 0x00 "SM0_PINCTRL,State machine pin control" bitfld.long 0x00 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "SET_COUNT,The number of pins asserted by a SET" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--25. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15.--19. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE0++0x03 line.long 0x00 "SM1_CLKDIV,Clock divisor register for state machine 1\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)" hexmask.long.word 0x00 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256).\n Value of 0 is interpreted as 65536" hexmask.long.byte 0x00 8.--15. 1. "FRAC,Fractional part of clock divisor" group.long 0xE4++0x03 line.long 0x00 "SM1_EXECCTRL,Execution/behavioural settings for state machine 1" rbitfld.long 0x00 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine" "0,1" bitfld.long 0x00 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit" "0,1" bitfld.long 0x00 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1" bitfld.long 0x00 24.--28. "JMP_PIN,The GPIO number to use as condition for JMP PIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19.--23. "OUT_EN_SEL,Which data bit to use for inline OUT enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY writes with an enable of 0 will\n deassert the latest pin" "0,1" bitfld.long 0x00 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1" bitfld.long 0x00 12.--16. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom.\n If the instruction is a jump and the jump condition is true the jump takes priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--11. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "STATUS_SEL,Comparison used for the MOV x STATUS instruction" "0: All-ones if TX FIFO level < N otherwise..,1: All-ones if RX FIFO level < N otherwise.." bitfld.long 0x00 0.--3. "STATUS_N,Comparison level for the MOV x STATUS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE8++0x03 line.long 0x00 "SM1_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 1" bitfld.long 0x00 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed" "0,1" bitfld.long 0x00 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed" "0,1" bitfld.long 0x00 25.--29. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place.\n Write 0 for value of 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place.\n Write 0 for value of 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19. "OUT_SHIFTDIR," "0,1" bitfld.long 0x00 18. "IN_SHIFTDIR," "0,1" bitfld.long 0x00 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e" "0,1" bitfld.long 0x00 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e" "0,1" group.long 0xEC++0x03 line.long 0x00 "SM1_ADDR,Current instruction address of state machine 1" rbitfld.long 0x00 0.--4. "SM1_ADDR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF0++0x03 line.long 0x00 "SM1_INSTR,Read to see the instruction currently addressed by state machine 1's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution" hexmask.long.word 0x00 0.--15. 1. "SM1_INSTR," group.long 0xF4++0x03 line.long 0x00 "SM1_PINCTRL,State machine pin control" bitfld.long 0x00 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "SET_COUNT,The number of pins asserted by a SET" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--25. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15.--19. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF8++0x03 line.long 0x00 "SM2_CLKDIV,Clock divisor register for state machine 2\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)" hexmask.long.word 0x00 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256).\n Value of 0 is interpreted as 65536" hexmask.long.byte 0x00 8.--15. 1. "FRAC,Fractional part of clock divisor" group.long 0xFC++0x03 line.long 0x00 "SM2_EXECCTRL,Execution/behavioural settings for state machine 2" rbitfld.long 0x00 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine" "0,1" bitfld.long 0x00 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit" "0,1" bitfld.long 0x00 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1" bitfld.long 0x00 24.--28. "JMP_PIN,The GPIO number to use as condition for JMP PIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19.--23. "OUT_EN_SEL,Which data bit to use for inline OUT enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY writes with an enable of 0 will\n deassert the latest pin" "0,1" bitfld.long 0x00 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1" bitfld.long 0x00 12.--16. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom.\n If the instruction is a jump and the jump condition is true the jump takes priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--11. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "STATUS_SEL,Comparison used for the MOV x STATUS instruction" "0: All-ones if TX FIFO level < N otherwise..,1: All-ones if RX FIFO level < N otherwise.." bitfld.long 0x00 0.--3. "STATUS_N,Comparison level for the MOV x STATUS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x03 line.long 0x00 "SM2_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 2" bitfld.long 0x00 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed" "0,1" bitfld.long 0x00 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed" "0,1" bitfld.long 0x00 25.--29. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place.\n Write 0 for value of 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place.\n Write 0 for value of 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19. "OUT_SHIFTDIR," "0,1" bitfld.long 0x00 18. "IN_SHIFTDIR," "0,1" bitfld.long 0x00 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e" "0,1" bitfld.long 0x00 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e" "0,1" group.long 0x104++0x03 line.long 0x00 "SM2_ADDR,Current instruction address of state machine 2" rbitfld.long 0x00 0.--4. "SM2_ADDR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x108++0x03 line.long 0x00 "SM2_INSTR,Read to see the instruction currently addressed by state machine 2's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution" hexmask.long.word 0x00 0.--15. 1. "SM2_INSTR," group.long 0x10C++0x03 line.long 0x00 "SM2_PINCTRL,State machine pin control" bitfld.long 0x00 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "SET_COUNT,The number of pins asserted by a SET" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--25. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15.--19. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SM3_CLKDIV,Clock divisor register for state machine 3\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)" hexmask.long.word 0x00 16.--31. 1. "INT,Effective frequency is sysclk/(int + frac/256).\n Value of 0 is interpreted as 65536" hexmask.long.byte 0x00 8.--15. 1. "FRAC,Fractional part of clock divisor" group.long 0x114++0x03 line.long 0x00 "SM3_EXECCTRL,Execution/behavioural settings for state machine 3" rbitfld.long 0x00 31. "EXEC_STALLED,If 1 an instruction written to SMx_INSTR is stalled and latched by the state machine" "0,1" bitfld.long 0x00 30. "SIDE_EN,If 1 the MSB of the Delay/Side-set instruction field is used as side-set enable rather than a side-set data bit" "0,1" bitfld.long 0x00 29. "SIDE_PINDIR,If 1 side-set data is asserted to pin directions instead of pin values" "0,1" bitfld.long 0x00 24.--28. "JMP_PIN,The GPIO number to use as condition for JMP PIN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19.--23. "OUT_EN_SEL,Which data bit to use for inline OUT enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. "INLINE_OUT_EN,If 1 use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY writes with an enable of 0 will\n deassert the latest pin" "0,1" bitfld.long 0x00 17. "OUT_STICKY,Continuously assert the most recent OUT/SET to the pins" "0,1" bitfld.long 0x00 12.--16. "WRAP_TOP,After reaching this address execution is wrapped to wrap_bottom.\n If the instruction is a jump and the jump condition is true the jump takes priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--11. "WRAP_BOTTOM,After reaching wrap_top execution is wrapped to this address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "STATUS_SEL,Comparison used for the MOV x STATUS instruction" "0: All-ones if TX FIFO level < N otherwise..,1: All-ones if RX FIFO level < N otherwise.." bitfld.long 0x00 0.--3. "STATUS_N,Comparison level for the MOV x STATUS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x118++0x03 line.long 0x00 "SM3_SHIFTCTRL,Control behaviour of the input/output shift registers for state machine 3" bitfld.long 0x00 31. "FJOIN_RX,When 1 RX FIFO steals the TX FIFO's storage and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed" "0,1" bitfld.long 0x00 30. "FJOIN_TX,When 1 TX FIFO steals the RX FIFO's storage and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed" "0,1" bitfld.long 0x00 25.--29. "PULL_THRESH,Number of bits shifted out of OSR before autopull or conditional pull (PULL IFEMPTY) will take place.\n Write 0 for value of 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. "PUSH_THRESH,Number of bits shifted into ISR before autopush or conditional push (PUSH IFFULL) will take place.\n Write 0 for value of 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19. "OUT_SHIFTDIR," "0,1" bitfld.long 0x00 18. "IN_SHIFTDIR," "0,1" bitfld.long 0x00 17. "AUTOPULL,Pull automatically when the output shift register is emptied i.e" "0,1" bitfld.long 0x00 16. "AUTOPUSH,Push automatically when the input shift register is filled i.e" "0,1" group.long 0x11C++0x03 line.long 0x00 "SM3_ADDR,Current instruction address of state machine 3" rbitfld.long 0x00 0.--4. "SM3_ADDR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x120++0x03 line.long 0x00 "SM3_INSTR,Read to see the instruction currently addressed by state machine 3's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution" hexmask.long.word 0x00 0.--15. 1. "SM3_INSTR," group.long 0x124++0x03 line.long 0x00 "SM3_PINCTRL,State machine pin control" bitfld.long 0x00 29.--31. "SIDESET_COUNT,The number of MSBs of the Delay/Side-set instruction field which are used for side-set" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "SET_COUNT,The number of pins asserted by a SET" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--25. "OUT_COUNT,The number of pins asserted by an OUT PINS OUT PINDIRS or MOV PINS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15.--19. "IN_BASE,The pin which is mapped to the least-significant bit of a state machine's IN data bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. "SIDESET_BASE,The lowest-numbered pin that will be affected by a side-set operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "SET_BASE,The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "OUT_BASE,The lowest-numbered pin that will be affected by an OUT PINS OUT PINDIRS or MOV PINS instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x128++0x03 line.long 0x00 "INTR,Raw Interrupts" rbitfld.long 0x00 11. "SM3," "0,1" rbitfld.long 0x00 10. "SM2," "0,1" rbitfld.long 0x00 9. "SM1," "0,1" rbitfld.long 0x00 8. "SM0," "0,1" newline rbitfld.long 0x00 7. "SM3_TXNFULL," "0,1" rbitfld.long 0x00 6. "SM2_TXNFULL," "0,1" rbitfld.long 0x00 5. "SM1_TXNFULL," "0,1" rbitfld.long 0x00 4. "SM0_TXNFULL," "0,1" newline rbitfld.long 0x00 3. "SM3_RXNEMPTY," "0,1" rbitfld.long 0x00 2. "SM2_RXNEMPTY," "0,1" rbitfld.long 0x00 1. "SM1_RXNEMPTY," "0,1" rbitfld.long 0x00 0. "SM0_RXNEMPTY," "0,1" group.long 0x12C++0x03 line.long 0x00 "IRQ0_INTE,Interrupt Enable for irq0" bitfld.long 0x00 11. "SM3," "0,1" bitfld.long 0x00 10. "SM2," "0,1" bitfld.long 0x00 9. "SM1," "0,1" bitfld.long 0x00 8. "SM0," "0,1" newline bitfld.long 0x00 7. "SM3_TXNFULL," "0,1" bitfld.long 0x00 6. "SM2_TXNFULL," "0,1" bitfld.long 0x00 5. "SM1_TXNFULL," "0,1" bitfld.long 0x00 4. "SM0_TXNFULL," "0,1" newline bitfld.long 0x00 3. "SM3_RXNEMPTY," "0,1" bitfld.long 0x00 2. "SM2_RXNEMPTY," "0,1" bitfld.long 0x00 1. "SM1_RXNEMPTY," "0,1" bitfld.long 0x00 0. "SM0_RXNEMPTY," "0,1" group.long 0x130++0x03 line.long 0x00 "IRQ0_INTF,Interrupt Force for irq0" bitfld.long 0x00 11. "SM3," "0,1" bitfld.long 0x00 10. "SM2," "0,1" bitfld.long 0x00 9. "SM1," "0,1" bitfld.long 0x00 8. "SM0," "0,1" newline bitfld.long 0x00 7. "SM3_TXNFULL," "0,1" bitfld.long 0x00 6. "SM2_TXNFULL," "0,1" bitfld.long 0x00 5. "SM1_TXNFULL," "0,1" bitfld.long 0x00 4. "SM0_TXNFULL," "0,1" newline bitfld.long 0x00 3. "SM3_RXNEMPTY," "0,1" bitfld.long 0x00 2. "SM2_RXNEMPTY," "0,1" bitfld.long 0x00 1. "SM1_RXNEMPTY," "0,1" bitfld.long 0x00 0. "SM0_RXNEMPTY," "0,1" group.long 0x134++0x03 line.long 0x00 "IRQ0_INTS,Interrupt status after masking & forcing for irq0" rbitfld.long 0x00 11. "SM3," "0,1" rbitfld.long 0x00 10. "SM2," "0,1" rbitfld.long 0x00 9. "SM1," "0,1" rbitfld.long 0x00 8. "SM0," "0,1" newline rbitfld.long 0x00 7. "SM3_TXNFULL," "0,1" rbitfld.long 0x00 6. "SM2_TXNFULL," "0,1" rbitfld.long 0x00 5. "SM1_TXNFULL," "0,1" rbitfld.long 0x00 4. "SM0_TXNFULL," "0,1" newline rbitfld.long 0x00 3. "SM3_RXNEMPTY," "0,1" rbitfld.long 0x00 2. "SM2_RXNEMPTY," "0,1" rbitfld.long 0x00 1. "SM1_RXNEMPTY," "0,1" rbitfld.long 0x00 0. "SM0_RXNEMPTY," "0,1" group.long 0x138++0x03 line.long 0x00 "IRQ1_INTE,Interrupt Enable for irq1" bitfld.long 0x00 11. "SM3," "0,1" bitfld.long 0x00 10. "SM2," "0,1" bitfld.long 0x00 9. "SM1," "0,1" bitfld.long 0x00 8. "SM0," "0,1" newline bitfld.long 0x00 7. "SM3_TXNFULL," "0,1" bitfld.long 0x00 6. "SM2_TXNFULL," "0,1" bitfld.long 0x00 5. "SM1_TXNFULL," "0,1" bitfld.long 0x00 4. "SM0_TXNFULL," "0,1" newline bitfld.long 0x00 3. "SM3_RXNEMPTY," "0,1" bitfld.long 0x00 2. "SM2_RXNEMPTY," "0,1" bitfld.long 0x00 1. "SM1_RXNEMPTY," "0,1" bitfld.long 0x00 0. "SM0_RXNEMPTY," "0,1" group.long 0x13C++0x03 line.long 0x00 "IRQ1_INTF,Interrupt Force for irq1" bitfld.long 0x00 11. "SM3," "0,1" bitfld.long 0x00 10. "SM2," "0,1" bitfld.long 0x00 9. "SM1," "0,1" bitfld.long 0x00 8. "SM0," "0,1" newline bitfld.long 0x00 7. "SM3_TXNFULL," "0,1" bitfld.long 0x00 6. "SM2_TXNFULL," "0,1" bitfld.long 0x00 5. "SM1_TXNFULL," "0,1" bitfld.long 0x00 4. "SM0_TXNFULL," "0,1" newline bitfld.long 0x00 3. "SM3_RXNEMPTY," "0,1" bitfld.long 0x00 2. "SM2_RXNEMPTY," "0,1" bitfld.long 0x00 1. "SM1_RXNEMPTY," "0,1" bitfld.long 0x00 0. "SM0_RXNEMPTY," "0,1" group.long 0x140++0x03 line.long 0x00 "IRQ1_INTS,Interrupt status after masking & forcing for irq1" rbitfld.long 0x00 11. "SM3," "0,1" rbitfld.long 0x00 10. "SM2," "0,1" rbitfld.long 0x00 9. "SM1," "0,1" rbitfld.long 0x00 8. "SM0," "0,1" newline rbitfld.long 0x00 7. "SM3_TXNFULL," "0,1" rbitfld.long 0x00 6. "SM2_TXNFULL," "0,1" rbitfld.long 0x00 5. "SM1_TXNFULL," "0,1" rbitfld.long 0x00 4. "SM0_TXNFULL," "0,1" newline rbitfld.long 0x00 3. "SM3_RXNEMPTY," "0,1" rbitfld.long 0x00 2. "SM2_RXNEMPTY," "0,1" rbitfld.long 0x00 1. "SM1_RXNEMPTY," "0,1" rbitfld.long 0x00 0. "SM0_RXNEMPTY," "0,1" tree.end repeat.end tree.end tree "PLL_SYS" base ad:0x40028000 group.long 0x00++0x03 line.long 0x00 "CS,Control and Status\n GENERAL CONSTRAINTS:\n Reference clock frequency min=5MHz max=800MHz\n Feedback divider min=16 max=320\n VCO frequency min=750MHz max=1600MHz" rbitfld.long 0x00 31. "LOCK,PLL is locked" "0,1" bitfld.long 0x00 8. "BYPASS,Passes the reference clock to the output instead of the divided VCO" "0,1" bitfld.long 0x00 0.--5. "REFDIV,Divides the PLL input reference clock.\n Behaviour is undefined for div=0.\n PLL output will be unpredictable during refdiv changes wait for lock=1 before using it" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "PWR,Controls the PLL power modes" bitfld.long 0x00 5. "VCOPD,PLL VCO powerdown\n To save power set high when PLL output not required or bypass=1" "0,1" bitfld.long 0x00 3. "POSTDIVPD,PLL post divider powerdown\n To save power set high when PLL output not required or bypass=1" "0,1" bitfld.long 0x00 2. "DSMPD,PLL DSM powerdown\n Nothing is achieved by setting this low" "0,1" bitfld.long 0x00 0. "PD,PLL powerdown\n To save power set high when PLL output not required" "0,1" group.long 0x08++0x03 line.long 0x00 "FBDIV_INT,Feedback divisor\n (note: this PLL does not support fractional division)" hexmask.long.word 0x00 0.--11. 1. "FBDIV_INT,see ctrl reg description for constraints" group.long 0x0C++0x03 line.long 0x00 "PRIM,Controls the PLL post dividers for the primary output\n (note: this PLL does not have a secondary output)\n the primary output is driven from VCO divided by postdiv1*postdiv2" bitfld.long 0x00 16.--18. "POSTDIV1,divide by 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "POSTDIV2,divide by 1-7" "0,1,2,3,4,5,6,7" tree.end tree "PLL_USB" base ad:0x4002C000 group.long 0x00++0x03 line.long 0x00 "CS,Control and Status\n GENERAL CONSTRAINTS:\n Reference clock frequency min=5MHz max=800MHz\n Feedback divider min=16 max=320\n VCO frequency min=750MHz max=1600MHz" rbitfld.long 0x00 31. "LOCK,PLL is locked" "0,1" bitfld.long 0x00 8. "BYPASS,Passes the reference clock to the output instead of the divided VCO" "0,1" bitfld.long 0x00 0.--5. "REFDIV,Divides the PLL input reference clock.\n Behaviour is undefined for div=0.\n PLL output will be unpredictable during refdiv changes wait for lock=1 before using it" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "PWR,Controls the PLL power modes" bitfld.long 0x00 5. "VCOPD,PLL VCO powerdown\n To save power set high when PLL output not required or bypass=1" "0,1" bitfld.long 0x00 3. "POSTDIVPD,PLL post divider powerdown\n To save power set high when PLL output not required or bypass=1" "0,1" bitfld.long 0x00 2. "DSMPD,PLL DSM powerdown\n Nothing is achieved by setting this low" "0,1" bitfld.long 0x00 0. "PD,PLL powerdown\n To save power set high when PLL output not required" "0,1" group.long 0x08++0x03 line.long 0x00 "FBDIV_INT,Feedback divisor\n (note: this PLL does not support fractional division)" hexmask.long.word 0x00 0.--11. 1. "FBDIV_INT,see ctrl reg description for constraints" group.long 0x0C++0x03 line.long 0x00 "PRIM,Controls the PLL post dividers for the primary output\n (note: this PLL does not have a secondary output)\n the primary output is driven from VCO divided by postdiv1*postdiv2" bitfld.long 0x00 16.--18. "POSTDIV1,divide by 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "POSTDIV2,divide by 1-7" "0,1,2,3,4,5,6,7" tree.end tree "PPB" base ad:0xE0000000 group.long 0xE010++0x03 line.long 0x00 "SYST_CSR,Use the SysTick Control and Status Register to enable the SysTick features" rbitfld.long 0x00 16. "COUNTFLAG,Returns 1 if timer counted to 0 since last time this was" "0,1" bitfld.long 0x00 2. "CLKSOURCE,SysTick clock source" "0: External reference clock,1: Processor clock" newline bitfld.long 0x00 1. "TICKINT,Enables SysTick exception request:\n" "0: Counting down to zero does not assert the,1: Counting down to zero to asserts the SysTick" bitfld.long 0x00 0. "ENABLE,Enable SysTick counter:\n" "0: Counter disabled,1: Counter enabled" group.long 0xE014++0x03 line.long 0x00 "SYST_RVR,Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0" hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register when the counter reaches 0" group.long 0xE018++0x03 line.long 0x00 "SYST_CVR,Use the SysTick Current Value Register to find the current value in the register" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,Reads return the current value of the SysTick counter" group.long 0xE01C++0x03 line.long 0x00 "SYST_CALIB,Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply" rbitfld.long 0x00 31. "NOREF,If reads as 1 the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0" "0,1" rbitfld.long 0x00 30. "SKEW,If reads as 1 the calibration value for 10ms is inexact (due to clock frequency)" "0,1" newline hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,An optional Reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" group.long 0xE100++0x03 line.long 0x00 "NVIC_ISER,Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled If a pending interrupt is enabled the NVIC activates the interrupt based on its priority" abitfld.long 0x00 0.--31. "SETENA,Interrupt set-enable bits Write:\n" "0x00000000=0: Interrupt disabled,0x00000001=1: Interrupt enabled" group.long 0xE180++0x03 line.long 0x00 "NVIC_ICER,Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled" abitfld.long 0x00 0.--31. "CLRENA,Interrupt clear-enable bits Write:\n" "0x00000000=0: Interrupt disabled,0x00000001=1: Interrupt enabled" group.long 0xE200++0x03 line.long 0x00 "NVIC_ISPR,The NVIC_ISPR forces interrupts into the pending state and shows which interrupts are pending" abitfld.long 0x00 0.--31. "SETPEND,Interrupt set-pending bits Write:\n" "0x00000000=0: Interrupt is not pending,0x00000001=1: Interrupt is pending" group.long 0xE280++0x03 line.long 0x00 "NVIC_ICPR,Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending" abitfld.long 0x00 0.--31. "CLRPEND,Interrupt clear-pending bits Write:\n" "0x00000000=0: Interrupt is not pending,0x00000001=1: Interrupt is pending" group.long 0xE400++0x03 line.long 0x00 "NVIC_IPR0,Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts" bitfld.long 0x00 30.--31. "IP_3,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. "IP_2,Priority of interrupt 2" "0,1,2,3" newline bitfld.long 0x00 14.--15. "IP_1,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. "IP_0,Priority of interrupt 0" "0,1,2,3" group.long 0xE404++0x03 line.long 0x00 "NVIC_IPR1,Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts" bitfld.long 0x00 30.--31. "IP_7,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x00 22.--23. "IP_6,Priority of interrupt 6" "0,1,2,3" newline bitfld.long 0x00 14.--15. "IP_5,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x00 6.--7. "IP_4,Priority of interrupt 4" "0,1,2,3" group.long 0xE408++0x03 line.long 0x00 "NVIC_IPR2,Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts" bitfld.long 0x00 30.--31. "IP_11,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x00 22.--23. "IP_10,Priority of interrupt 10" "0,1,2,3" newline bitfld.long 0x00 14.--15. "IP_9,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x00 6.--7. "IP_8,Priority of interrupt 8" "0,1,2,3" group.long 0xE40C++0x03 line.long 0x00 "NVIC_IPR3,Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts" bitfld.long 0x00 30.--31. "IP_15,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x00 22.--23. "IP_14,Priority of interrupt 14" "0,1,2,3" newline bitfld.long 0x00 14.--15. "IP_13,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x00 6.--7. "IP_12,Priority of interrupt 12" "0,1,2,3" group.long 0xE410++0x03 line.long 0x00 "NVIC_IPR4,Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts" bitfld.long 0x00 30.--31. "IP_19,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x00 22.--23. "IP_18,Priority of interrupt 18" "0,1,2,3" newline bitfld.long 0x00 14.--15. "IP_17,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x00 6.--7. "IP_16,Priority of interrupt 16" "0,1,2,3" group.long 0xE414++0x03 line.long 0x00 "NVIC_IPR5,Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts" bitfld.long 0x00 30.--31. "IP_23,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x00 22.--23. "IP_22,Priority of interrupt 22" "0,1,2,3" newline bitfld.long 0x00 14.--15. "IP_21,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x00 6.--7. "IP_20,Priority of interrupt 20" "0,1,2,3" group.long 0xE418++0x03 line.long 0x00 "NVIC_IPR6,Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts" bitfld.long 0x00 30.--31. "IP_27,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x00 22.--23. "IP_26,Priority of interrupt 26" "0,1,2,3" newline bitfld.long 0x00 14.--15. "IP_25,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x00 6.--7. "IP_24,Priority of interrupt 24" "0,1,2,3" group.long 0xE41C++0x03 line.long 0x00 "NVIC_IPR7,Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts" bitfld.long 0x00 30.--31. "IP_31,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x00 22.--23. "IP_30,Priority of interrupt 30" "0,1,2,3" newline bitfld.long 0x00 14.--15. "IP_29,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x00 6.--7. "IP_28,Priority of interrupt 28" "0,1,2,3" group.long 0xED00++0x03 line.long 0x00 "CPUID,Read the CPU ID Base Register to determine: the ID number of the processor core the version number of the processor core the implementation details of the processor core" hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementor code" rbitfld.long 0x00 20.--23. "VARIANT,Major revision number n in the rnpm revision status:\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 16.--19. "ARCHITECTURE,Constant that defines the architecture of the processor:\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 4.--15. 1. "PARTNO,Number of processor within family" newline rbitfld.long 0x00 0.--3. "REVISION,Minor revision number m in the rnpm revision status:\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xED04++0x03 line.long 0x00 "ICSR,Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI) set or clear a pending PendSV set or clear a pending SysTick check for pending exceptions check the vector number of the highest priority pended exception check.." bitfld.long 0x00 31. "NMIPENDSET,Setting this bit will activate an NMI" "0: NMI exception is not pending,1: NMI exception is pending Because NMI is the" bitfld.long 0x00 28. "PENDSVSET,PendSV set-pending bit Write:\n" "0: PendSV exception is not pending,1: PendSV exception is pending Writing 1 to.." newline bitfld.long 0x00 27. "PENDSVCLR,PendSV clear-pending bit Write:\n" "0: No effect,1: Removes the pending state from the" bitfld.long 0x00 26. "PENDSTSET,SysTick exception set-pending bit Write:\n" "0: SysTick exception is not pending,1: SysTick exception is pending" newline bitfld.long 0x00 25. "PENDSTCLR,SysTick exception clear-pending bit Write:\n" "0: No effect,1: Removes the pending state from the" rbitfld.long 0x00 23. "ISRPREEMPT,The system can only access this bit when the core is halted" "0,1" newline rbitfld.long 0x00 22. "ISRPENDING,External interrupt pending flag" "0,1" hexmask.long.word 0x00 12.--20. 1. "VECTPENDING,Indicates the exception number for the highest priority pending exception" newline hexmask.long.word 0x00 0.--8. 1. "VECTACTIVE,Active exception number field" group.long 0xED08++0x03 line.long 0x00 "VTOR,The VTOR holds the vector table offset address" hexmask.long.tbyte 0x00 8.--31. 1. "TBLOFF,Bits [31:8] of the indicate the vector table offset address" group.long 0xED0C++0x03 line.long 0x00 "AIRCR,Use the Application Interrupt and Reset Control Register to: determine data endianness clear all active state information from debug halt mode request a system reset" hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Register key:\n Reads as Unknown\n On writes write 0x05FA to VECTKEY otherwise the write is ignored" rbitfld.long 0x00 15. "ENDIANESS,Data endianness implemented:\n" "0,1" newline bitfld.long 0x00 2. "SYSRESETREQ,Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset" "0,1" bitfld.long 0x00 1. "VECTCLRACTIVE,Clears all active state information for fixed and configurable exceptions" "0,1" group.long 0xED10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending bit:\n" "0: Only enabled interrupts or events can wakeup..,1: Enabled events and all interrupts including" bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low power mode:\n" "0: Sleep,1: Deep sleep" newline bitfld.long 0x00 1. "SLEEPONEXIT,Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR" group.long 0xED14++0x03 line.long 0x00 "CCR,The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault" rbitfld.long 0x00 9. "STKALIGN,Always reads as one indicates 8-byte stack alignment on exception entry" "0,1" rbitfld.long 0x00 3. "UNALIGN_TRP,Always reads as one indicates that all unaligned accesses generate a HardFault" "0,1" group.long 0xED1C++0x03 line.long 0x00 "SHPR2,System handlers are a special class of exception handler that can have their priority set to any of the priority levels" bitfld.long 0x00 30.--31. "PRI_11,Priority of system handler 11 SVCall" "0,1,2,3" group.long 0xED20++0x03 line.long 0x00 "SHPR3,System handlers are a special class of exception handler that can have their priority set to any of the priority levels" bitfld.long 0x00 30.--31. "PRI_15,Priority of system handler 15 SysTick" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_14,Priority of system handler 14 PendSV" "0,1,2,3" group.long 0xED24++0x03 line.long 0x00 "SHCSR,Use the System Handler Control and State Register to determine or clear the pending status of SVCall" bitfld.long 0x00 15. "SVCALLPENDED,Reads as 1 if SVCall is Pending" "0,1" group.long 0xED90++0x03 line.long 0x00 "MPU_TYPE,Read the MPU Type Register to determine if the processor implements an MPU and how many regions the MPU supports" hexmask.long.byte 0x00 16.--23. 1. "IREGION,Instruction region" hexmask.long.byte 0x00 8.--15. 1. "DREGION,Number of regions supported by the MPU" newline rbitfld.long 0x00 0. "SEPARATE,Indicates support for separate instruction and data address maps" "0,1" group.long 0xED94++0x03 line.long 0x00 "MPU_CTRL,Use the MPU Control Register to enable and disable the MPU and to control whether the default memory map is enabled as a background region for privileged accesses and whether the MPU is enabled for HardFaults and NMIs" bitfld.long 0x00 2. "PRIVDEFENA,Controls whether the default memory map is enabled as a background region for privileged accesses" "0: If the MPU is enabled disables use of the,1: If the MPU is enabled enables use of the.." bitfld.long 0x00 1. "HFNMIENA,Controls the use of the MPU for HardFaults and NMIs" "0: MPU is disabled during HardFault and NMI,1: the MPU is enabled during HardFault and NMI" newline bitfld.long 0x00 0. "ENABLE,Enables the MPU" "0: MPU disabled,1: MPU enabled" group.long 0xED98++0x03 line.long 0x00 "MPU_RNR,Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR" bitfld.long 0x00 0.--3. "REGION,Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers The MPU supports 8 memory regions so the permitted values of this field are 0-7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xED9C++0x03 line.long 0x00 "MPU_RBAR,Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR" hexmask.long.tbyte 0x00 8.--31. 1. "ADDR,Base address of the region" bitfld.long 0x00 4. "VALID,On writes indicates whether the write must update the base address of the region identified by the REGION field updating the MPU_RNR to indicate this new region Write:\n" "0: MPU_RNR not changed and the processor,1: The processor" newline bitfld.long 0x00 0.--3. "REGION,On writes specifies the number of the region whose base address to update provided VALID is set written as 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEDA0++0x03 line.long 0x00 "MPU_RASR,Use the MPU Region Attribute and Size Register to define the size access behaviour and memory type of the region identified by MPU_RNR and enable that region" abitfld.long 0x00 16.--31. "ATTRS,The MPU Region Attribute field" "0x0000=0: Instruction fetches enabled,0x0001=1: Instruction fetches disabled 26:24..,0x0010=16: B,0x0011=17: C,0x0012=18: S,0x001C=28: XN" hexmask.long.byte 0x00 8.--15. 1. "SRD,Subregion Disable" newline bitfld.long 0x00 1.--5. "SIZE,Indicates the region size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. "ENABLE,Enables the region" "0,1" tree.end tree "PSM (Power-On State Machine)" base ad:0x40010000 group.long 0x00++0x03 line.long 0x00 "FRCE_ON,Force block out of reset (i.e. power it on)" bitfld.long 0x00 16. "proc1," "0,1" bitfld.long 0x00 15. "proc0," "0,1" bitfld.long 0x00 14. "sio," "0,1" bitfld.long 0x00 13. "vreg_and_chip_reset," "0,1" bitfld.long 0x00 12. "xip," "0,1" bitfld.long 0x00 11. "sram5," "0,1" newline bitfld.long 0x00 10. "sram4," "0,1" bitfld.long 0x00 9. "sram3," "0,1" bitfld.long 0x00 8. "sram2," "0,1" bitfld.long 0x00 7. "sram1," "0,1" bitfld.long 0x00 6. "sram0," "0,1" bitfld.long 0x00 5. "rom," "0,1" newline bitfld.long 0x00 4. "busfabric," "0,1" bitfld.long 0x00 3. "resets," "0,1" bitfld.long 0x00 2. "clocks," "0,1" bitfld.long 0x00 1. "xosc," "0,1" bitfld.long 0x00 0. "rosc," "0,1" group.long 0x04++0x03 line.long 0x00 "FRCE_OFF,Force into reset (i.e. power it off)" bitfld.long 0x00 16. "proc1," "0,1" bitfld.long 0x00 15. "proc0," "0,1" bitfld.long 0x00 14. "sio," "0,1" bitfld.long 0x00 13. "vreg_and_chip_reset," "0,1" bitfld.long 0x00 12. "xip," "0,1" bitfld.long 0x00 11. "sram5," "0,1" newline bitfld.long 0x00 10. "sram4," "0,1" bitfld.long 0x00 9. "sram3," "0,1" bitfld.long 0x00 8. "sram2," "0,1" bitfld.long 0x00 7. "sram1," "0,1" bitfld.long 0x00 6. "sram0," "0,1" bitfld.long 0x00 5. "rom," "0,1" newline bitfld.long 0x00 4. "busfabric," "0,1" bitfld.long 0x00 3. "resets," "0,1" bitfld.long 0x00 2. "clocks," "0,1" bitfld.long 0x00 1. "xosc," "0,1" bitfld.long 0x00 0. "rosc," "0,1" group.long 0x08++0x03 line.long 0x00 "WDSEL,Set to 1 if this peripheral should be reset when the watchdog fires" bitfld.long 0x00 16. "proc1," "0,1" bitfld.long 0x00 15. "proc0," "0,1" bitfld.long 0x00 14. "sio," "0,1" bitfld.long 0x00 13. "vreg_and_chip_reset," "0,1" bitfld.long 0x00 12. "xip," "0,1" bitfld.long 0x00 11. "sram5," "0,1" newline bitfld.long 0x00 10. "sram4," "0,1" bitfld.long 0x00 9. "sram3," "0,1" bitfld.long 0x00 8. "sram2," "0,1" bitfld.long 0x00 7. "sram1," "0,1" bitfld.long 0x00 6. "sram0," "0,1" bitfld.long 0x00 5. "rom," "0,1" newline bitfld.long 0x00 4. "busfabric," "0,1" bitfld.long 0x00 3. "resets," "0,1" bitfld.long 0x00 2. "clocks," "0,1" bitfld.long 0x00 1. "xosc," "0,1" bitfld.long 0x00 0. "rosc," "0,1" group.long 0x0C++0x03 line.long 0x00 "DONE,Indicates the peripheral's registers are ready to access" rbitfld.long 0x00 16. "proc1," "0,1" rbitfld.long 0x00 15. "proc0," "0,1" rbitfld.long 0x00 14. "sio," "0,1" rbitfld.long 0x00 13. "vreg_and_chip_reset," "0,1" rbitfld.long 0x00 12. "xip," "0,1" rbitfld.long 0x00 11. "sram5," "0,1" newline rbitfld.long 0x00 10. "sram4," "0,1" rbitfld.long 0x00 9. "sram3," "0,1" rbitfld.long 0x00 8. "sram2," "0,1" rbitfld.long 0x00 7. "sram1," "0,1" rbitfld.long 0x00 6. "sram0," "0,1" rbitfld.long 0x00 5. "rom," "0,1" newline rbitfld.long 0x00 4. "busfabric," "0,1" rbitfld.long 0x00 3. "resets," "0,1" rbitfld.long 0x00 2. "clocks," "0,1" rbitfld.long 0x00 1. "xosc," "0,1" rbitfld.long 0x00 0. "rosc," "0,1" tree.end tree "PWM (Pulse-Width Modulator)" base ad:0x40050000 group.long 0x00++0x03 line.long 0x00 "CH0_CSR,Control and status register" bitfld.long 0x00 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 6. "PH_RET,Retard the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 4.--5. "DIVMODE," "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of.." bitfld.long 0x00 3. "B_INV,Invert output B" "0,1" bitfld.long 0x00 2. "A_INV,Invert output A" "0,1" bitfld.long 0x00 1. "PH_CORRECT," "0,1" bitfld.long 0x00 0. "EN,Enable the PWM channel" "0,1" group.long 0x04++0x03 line.long 0x00 "CH0_DIV,INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta" hexmask.long.byte 0x00 4.--11. 1. "INT," bitfld.long 0x00 0.--3. "FRAC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x08++0x03 line.long 0x00 "CH0_CTR,Direct access to the PWM counter" hexmask.long.word 0x00 0.--15. 1. "CH0_CTR," group.long 0x0C++0x03 line.long 0x00 "CH0_CC,Counter compare values" hexmask.long.word 0x00 16.--31. 1. "B," hexmask.long.word 0x00 0.--15. 1. "A," group.long 0x10++0x03 line.long 0x00 "CH0_TOP,Counter wrap value" hexmask.long.word 0x00 0.--15. 1. "CH0_TOP," group.long 0x14++0x03 line.long 0x00 "CH1_CSR,Control and status register" bitfld.long 0x00 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 6. "PH_RET,Retard the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 4.--5. "DIVMODE," "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of.." bitfld.long 0x00 3. "B_INV,Invert output B" "0,1" bitfld.long 0x00 2. "A_INV,Invert output A" "0,1" bitfld.long 0x00 1. "PH_CORRECT," "0,1" bitfld.long 0x00 0. "EN,Enable the PWM channel" "0,1" group.long 0x18++0x03 line.long 0x00 "CH1_DIV,INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta" hexmask.long.byte 0x00 4.--11. 1. "INT," bitfld.long 0x00 0.--3. "FRAC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "CH1_CTR,Direct access to the PWM counter" hexmask.long.word 0x00 0.--15. 1. "CH1_CTR," group.long 0x20++0x03 line.long 0x00 "CH1_CC,Counter compare values" hexmask.long.word 0x00 16.--31. 1. "B," hexmask.long.word 0x00 0.--15. 1. "A," group.long 0x24++0x03 line.long 0x00 "CH1_TOP,Counter wrap value" hexmask.long.word 0x00 0.--15. 1. "CH1_TOP," group.long 0x28++0x03 line.long 0x00 "CH2_CSR,Control and status register" bitfld.long 0x00 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 6. "PH_RET,Retard the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 4.--5. "DIVMODE," "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of.." bitfld.long 0x00 3. "B_INV,Invert output B" "0,1" bitfld.long 0x00 2. "A_INV,Invert output A" "0,1" bitfld.long 0x00 1. "PH_CORRECT," "0,1" bitfld.long 0x00 0. "EN,Enable the PWM channel" "0,1" group.long 0x2C++0x03 line.long 0x00 "CH2_DIV,INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta" hexmask.long.byte 0x00 4.--11. 1. "INT," bitfld.long 0x00 0.--3. "FRAC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x03 line.long 0x00 "CH2_CTR,Direct access to the PWM counter" hexmask.long.word 0x00 0.--15. 1. "CH2_CTR," group.long 0x34++0x03 line.long 0x00 "CH2_CC,Counter compare values" hexmask.long.word 0x00 16.--31. 1. "B," hexmask.long.word 0x00 0.--15. 1. "A," group.long 0x38++0x03 line.long 0x00 "CH2_TOP,Counter wrap value" hexmask.long.word 0x00 0.--15. 1. "CH2_TOP," group.long 0x3C++0x03 line.long 0x00 "CH3_CSR,Control and status register" bitfld.long 0x00 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 6. "PH_RET,Retard the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 4.--5. "DIVMODE," "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of.." bitfld.long 0x00 3. "B_INV,Invert output B" "0,1" bitfld.long 0x00 2. "A_INV,Invert output A" "0,1" bitfld.long 0x00 1. "PH_CORRECT," "0,1" bitfld.long 0x00 0. "EN,Enable the PWM channel" "0,1" group.long 0x40++0x03 line.long 0x00 "CH3_DIV,INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta" hexmask.long.byte 0x00 4.--11. 1. "INT," bitfld.long 0x00 0.--3. "FRAC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x44++0x03 line.long 0x00 "CH3_CTR,Direct access to the PWM counter" hexmask.long.word 0x00 0.--15. 1. "CH3_CTR," group.long 0x48++0x03 line.long 0x00 "CH3_CC,Counter compare values" hexmask.long.word 0x00 16.--31. 1. "B," hexmask.long.word 0x00 0.--15. 1. "A," group.long 0x4C++0x03 line.long 0x00 "CH3_TOP,Counter wrap value" hexmask.long.word 0x00 0.--15. 1. "CH3_TOP," group.long 0x50++0x03 line.long 0x00 "CH4_CSR,Control and status register" bitfld.long 0x00 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 6. "PH_RET,Retard the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 4.--5. "DIVMODE," "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of.." bitfld.long 0x00 3. "B_INV,Invert output B" "0,1" bitfld.long 0x00 2. "A_INV,Invert output A" "0,1" bitfld.long 0x00 1. "PH_CORRECT," "0,1" bitfld.long 0x00 0. "EN,Enable the PWM channel" "0,1" group.long 0x54++0x03 line.long 0x00 "CH4_DIV,INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta" hexmask.long.byte 0x00 4.--11. 1. "INT," bitfld.long 0x00 0.--3. "FRAC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x58++0x03 line.long 0x00 "CH4_CTR,Direct access to the PWM counter" hexmask.long.word 0x00 0.--15. 1. "CH4_CTR," group.long 0x5C++0x03 line.long 0x00 "CH4_CC,Counter compare values" hexmask.long.word 0x00 16.--31. 1. "B," hexmask.long.word 0x00 0.--15. 1. "A," group.long 0x60++0x03 line.long 0x00 "CH4_TOP,Counter wrap value" hexmask.long.word 0x00 0.--15. 1. "CH4_TOP," group.long 0x64++0x03 line.long 0x00 "CH5_CSR,Control and status register" bitfld.long 0x00 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 6. "PH_RET,Retard the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 4.--5. "DIVMODE," "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of.." bitfld.long 0x00 3. "B_INV,Invert output B" "0,1" bitfld.long 0x00 2. "A_INV,Invert output A" "0,1" bitfld.long 0x00 1. "PH_CORRECT," "0,1" bitfld.long 0x00 0. "EN,Enable the PWM channel" "0,1" group.long 0x68++0x03 line.long 0x00 "CH5_DIV,INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta" hexmask.long.byte 0x00 4.--11. 1. "INT," bitfld.long 0x00 0.--3. "FRAC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x6C++0x03 line.long 0x00 "CH5_CTR,Direct access to the PWM counter" hexmask.long.word 0x00 0.--15. 1. "CH5_CTR," group.long 0x70++0x03 line.long 0x00 "CH5_CC,Counter compare values" hexmask.long.word 0x00 16.--31. 1. "B," hexmask.long.word 0x00 0.--15. 1. "A," group.long 0x74++0x03 line.long 0x00 "CH5_TOP,Counter wrap value" hexmask.long.word 0x00 0.--15. 1. "CH5_TOP," group.long 0x78++0x03 line.long 0x00 "CH6_CSR,Control and status register" bitfld.long 0x00 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 6. "PH_RET,Retard the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 4.--5. "DIVMODE," "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of.." bitfld.long 0x00 3. "B_INV,Invert output B" "0,1" bitfld.long 0x00 2. "A_INV,Invert output A" "0,1" bitfld.long 0x00 1. "PH_CORRECT," "0,1" bitfld.long 0x00 0. "EN,Enable the PWM channel" "0,1" group.long 0x7C++0x03 line.long 0x00 "CH6_DIV,INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta" hexmask.long.byte 0x00 4.--11. 1. "INT," bitfld.long 0x00 0.--3. "FRAC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x03 line.long 0x00 "CH6_CTR,Direct access to the PWM counter" hexmask.long.word 0x00 0.--15. 1. "CH6_CTR," group.long 0x84++0x03 line.long 0x00 "CH6_CC,Counter compare values" hexmask.long.word 0x00 16.--31. 1. "B," hexmask.long.word 0x00 0.--15. 1. "A," group.long 0x88++0x03 line.long 0x00 "CH6_TOP,Counter wrap value" hexmask.long.word 0x00 0.--15. 1. "CH6_TOP," group.long 0x8C++0x03 line.long 0x00 "CH7_CSR,Control and status register" bitfld.long 0x00 7. "PH_ADV,Advance the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 6. "PH_RET,Retard the phase of the counter by 1 count while it is running.\n Self-clearing" "0,1" bitfld.long 0x00 4.--5. "DIVMODE," "0: Free-running counting at rate dictated by..,1: Fractional divider operation is gated by the..,2: Counter advances with each rising edge of the..,3: Counter advances with each falling edge of.." bitfld.long 0x00 3. "B_INV,Invert output B" "0,1" bitfld.long 0x00 2. "A_INV,Invert output A" "0,1" bitfld.long 0x00 1. "PH_CORRECT," "0,1" bitfld.long 0x00 0. "EN,Enable the PWM channel" "0,1" group.long 0x90++0x03 line.long 0x00 "CH7_DIV,INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta" hexmask.long.byte 0x00 4.--11. 1. "INT," bitfld.long 0x00 0.--3. "FRAC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x94++0x03 line.long 0x00 "CH7_CTR,Direct access to the PWM counter" hexmask.long.word 0x00 0.--15. 1. "CH7_CTR," group.long 0x98++0x03 line.long 0x00 "CH7_CC,Counter compare values" hexmask.long.word 0x00 16.--31. 1. "B," hexmask.long.word 0x00 0.--15. 1. "A," group.long 0x9C++0x03 line.long 0x00 "CH7_TOP,Counter wrap value" hexmask.long.word 0x00 0.--15. 1. "CH7_TOP," group.long 0xA0++0x03 line.long 0x00 "EN,This register aliases the CSR_EN bits for all channels.\n Writing to this register allows multiple channels to be enabled\n or disabled simultaneously so they can run in perfect sync.\n For each channel there is only one physical EN register bit \n.." bitfld.long 0x00 7. "CH7," "0,1" bitfld.long 0x00 6. "CH6," "0,1" bitfld.long 0x00 5. "CH5," "0,1" bitfld.long 0x00 4. "CH4," "0,1" bitfld.long 0x00 3. "CH3," "0,1" bitfld.long 0x00 2. "CH2," "0,1" bitfld.long 0x00 1. "CH1," "0,1" newline bitfld.long 0x00 0. "CH0," "0,1" group.long 0xA4++0x03 line.long 0x00 "INTR,Raw Interrupts" eventfld.long 0x00 7. "CH7," "0,1" eventfld.long 0x00 6. "CH6," "0,1" eventfld.long 0x00 5. "CH5," "0,1" eventfld.long 0x00 4. "CH4," "0,1" eventfld.long 0x00 3. "CH3," "0,1" eventfld.long 0x00 2. "CH2," "0,1" eventfld.long 0x00 1. "CH1," "0,1" newline eventfld.long 0x00 0. "CH0," "0,1" group.long 0xA8++0x03 line.long 0x00 "INTE,Interrupt Enable" bitfld.long 0x00 7. "CH7," "0,1" bitfld.long 0x00 6. "CH6," "0,1" bitfld.long 0x00 5. "CH5," "0,1" bitfld.long 0x00 4. "CH4," "0,1" bitfld.long 0x00 3. "CH3," "0,1" bitfld.long 0x00 2. "CH2," "0,1" bitfld.long 0x00 1. "CH1," "0,1" newline bitfld.long 0x00 0. "CH0," "0,1" group.long 0xAC++0x03 line.long 0x00 "INTF,Interrupt Force" bitfld.long 0x00 7. "CH7," "0,1" bitfld.long 0x00 6. "CH6," "0,1" bitfld.long 0x00 5. "CH5," "0,1" bitfld.long 0x00 4. "CH4," "0,1" bitfld.long 0x00 3. "CH3," "0,1" bitfld.long 0x00 2. "CH2," "0,1" bitfld.long 0x00 1. "CH1," "0,1" newline bitfld.long 0x00 0. "CH0," "0,1" group.long 0xB0++0x03 line.long 0x00 "INTS,Interrupt status after masking & forcing" rbitfld.long 0x00 7. "CH7," "0,1" rbitfld.long 0x00 6. "CH6," "0,1" rbitfld.long 0x00 5. "CH5," "0,1" rbitfld.long 0x00 4. "CH4," "0,1" rbitfld.long 0x00 3. "CH3," "0,1" rbitfld.long 0x00 2. "CH2," "0,1" rbitfld.long 0x00 1. "CH1," "0,1" newline rbitfld.long 0x00 0. "CH0," "0,1" tree.end tree "RESETS" base ad:0x4000C000 group.long 0x00++0x03 line.long 0x00 "RESET,Reset control" bitfld.long 0x00 24. "usbctrl," "0,1" bitfld.long 0x00 23. "uart1," "0,1" bitfld.long 0x00 22. "uart0," "0,1" bitfld.long 0x00 21. "timer," "0,1" bitfld.long 0x00 20. "tbman," "0,1" bitfld.long 0x00 19. "sysinfo," "0,1" bitfld.long 0x00 18. "syscfg," "0,1" bitfld.long 0x00 17. "spi1," "0,1" bitfld.long 0x00 16. "spi0," "0,1" bitfld.long 0x00 15. "rtc," "0,1" newline bitfld.long 0x00 14. "pwm," "0,1" bitfld.long 0x00 13. "pll_usb," "0,1" bitfld.long 0x00 12. "pll_sys," "0,1" bitfld.long 0x00 11. "pio1," "0,1" bitfld.long 0x00 10. "pio0," "0,1" bitfld.long 0x00 9. "pads_qspi," "0,1" bitfld.long 0x00 8. "pads_bank0," "0,1" bitfld.long 0x00 7. "jtag," "0,1" bitfld.long 0x00 6. "io_qspi," "0,1" bitfld.long 0x00 5. "io_bank0," "0,1" newline bitfld.long 0x00 4. "i2c1," "0,1" bitfld.long 0x00 3. "i2c0," "0,1" bitfld.long 0x00 2. "dma," "0,1" bitfld.long 0x00 1. "busctrl," "0,1" bitfld.long 0x00 0. "adc," "0,1" group.long 0x04++0x03 line.long 0x00 "WDSEL,Watchdog select" bitfld.long 0x00 24. "usbctrl," "0,1" bitfld.long 0x00 23. "uart1," "0,1" bitfld.long 0x00 22. "uart0," "0,1" bitfld.long 0x00 21. "timer," "0,1" bitfld.long 0x00 20. "tbman," "0,1" bitfld.long 0x00 19. "sysinfo," "0,1" bitfld.long 0x00 18. "syscfg," "0,1" bitfld.long 0x00 17. "spi1," "0,1" bitfld.long 0x00 16. "spi0," "0,1" bitfld.long 0x00 15. "rtc," "0,1" newline bitfld.long 0x00 14. "pwm," "0,1" bitfld.long 0x00 13. "pll_usb," "0,1" bitfld.long 0x00 12. "pll_sys," "0,1" bitfld.long 0x00 11. "pio1," "0,1" bitfld.long 0x00 10. "pio0," "0,1" bitfld.long 0x00 9. "pads_qspi," "0,1" bitfld.long 0x00 8. "pads_bank0," "0,1" bitfld.long 0x00 7. "jtag," "0,1" bitfld.long 0x00 6. "io_qspi," "0,1" bitfld.long 0x00 5. "io_bank0," "0,1" newline bitfld.long 0x00 4. "i2c1," "0,1" bitfld.long 0x00 3. "i2c0," "0,1" bitfld.long 0x00 2. "dma," "0,1" bitfld.long 0x00 1. "busctrl," "0,1" bitfld.long 0x00 0. "adc," "0,1" group.long 0x08++0x03 line.long 0x00 "RESET_DONE,Reset done" rbitfld.long 0x00 24. "usbctrl," "0,1" rbitfld.long 0x00 23. "uart1," "0,1" rbitfld.long 0x00 22. "uart0," "0,1" rbitfld.long 0x00 21. "timer," "0,1" rbitfld.long 0x00 20. "tbman," "0,1" rbitfld.long 0x00 19. "sysinfo," "0,1" rbitfld.long 0x00 18. "syscfg," "0,1" rbitfld.long 0x00 17. "spi1," "0,1" rbitfld.long 0x00 16. "spi0," "0,1" rbitfld.long 0x00 15. "rtc," "0,1" newline rbitfld.long 0x00 14. "pwm," "0,1" rbitfld.long 0x00 13. "pll_usb," "0,1" rbitfld.long 0x00 12. "pll_sys," "0,1" rbitfld.long 0x00 11. "pio1," "0,1" rbitfld.long 0x00 10. "pio0," "0,1" rbitfld.long 0x00 9. "pads_qspi," "0,1" rbitfld.long 0x00 8. "pads_bank0," "0,1" rbitfld.long 0x00 7. "jtag," "0,1" rbitfld.long 0x00 6. "io_qspi," "0,1" rbitfld.long 0x00 5. "io_bank0," "0,1" newline rbitfld.long 0x00 4. "i2c1," "0,1" rbitfld.long 0x00 3. "i2c0," "0,1" rbitfld.long 0x00 2. "dma," "0,1" rbitfld.long 0x00 1. "busctrl," "0,1" rbitfld.long 0x00 0. "adc," "0,1" tree.end tree "ROSC (Ring Oscillator)" base ad:0x40060000 group.long 0x00++0x03 line.long 0x00 "CTRL,Ring Oscillator control" hexmask.long.word 0x00 12.--23. 1. "ENABLE,On power-up this field is initialised to ENABLE\n The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n The 12-bit code is intended to give some protection against accidental.." hexmask.long.word 0x00 0.--11. 1. "FREQ_RANGE,Controls the number of delay stages in the ROSC ring\n LOW uses stages 0 to 7\n MEDIUM uses stages 0 to 5\n HIGH uses stages 0 to 3\n TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n The.." group.long 0x04++0x03 line.long 0x00 "FREQA,The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage\n The drive strength has 4 levels determined by the number of bits set\n Increasing the number of bits set increases the drive strength and increases.." hexmask.long.word 0x00 16.--31. 1. "PASSWD,Set to 0x9696 to apply the settings\n Any other value in this field will set all drive strengths to 0" bitfld.long 0x00 12.--14. "DS3,Stage 3 drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "DS2,Stage 2 drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "DS1,Stage 1 drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "DS0,Stage 0 drive strength" "0,1,2,3,4,5,6,7" group.long 0x08++0x03 line.long 0x00 "FREQB,For a detailed description see freqa register" hexmask.long.word 0x00 16.--31. 1. "PASSWD,Set to 0x9696 to apply the settings\n Any other value in this field will set all drive strengths to 0" bitfld.long 0x00 12.--14. "DS7,Stage 7 drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "DS6,Stage 6 drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "DS5,Stage 5 drive strength" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "DS4,Stage 4 drive strength" "0,1,2,3,4,5,6,7" group.long 0x0C++0x03 line.long 0x00 "DORMANT,Ring Oscillator pause control\n This is used to save power by pausing the ROSC\n On power-up this field is initialised to WAKE\n An invalid write will also select WAKE\n Warning: setup the irq before selecting dormant mode" group.long 0x10++0x03 line.long 0x00 "DIV,Controls the output divider" hexmask.long.word 0x00 0.--11. 1. "DIV,set to 0xaa0 + div where\n div = 0 divides by 32\n div = 1-31 divides by div\n any other value sets div=31\n this register resets to div=16" group.long 0x14++0x03 line.long 0x00 "PHASE,Controls the phase shifted output" hexmask.long.byte 0x00 4.--11. 1. "PASSWD,set to 0xaa\n any other value enables the output with shift=0" bitfld.long 0x00 3. "ENABLE,enable the phase-shifted output\n this can be changed on-the-fly" "0,1" bitfld.long 0x00 2. "FLIP,invert the phase-shifted output\n this is ignored when div=1" "0,1" bitfld.long 0x00 0.--1. "SHIFT,phase shift the phase-shifted output by SHIFT input clocks\n this can be changed on-the-fly\n must be set to 0 before setting div=1" "0,1,2,3" group.long 0x18++0x03 line.long 0x00 "STATUS,Ring Oscillator Status" rbitfld.long 0x00 31. "STABLE,Oscillator is running and stable" "0,1" eventfld.long 0x00 24. "BADWRITE,An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT" "0,1" rbitfld.long 0x00 16. "DIV_RUNNING,post-divider is running\n this resets to 0 but transitions to 1 during chip startup" "0,1" rbitfld.long 0x00 12. "ENABLED,Oscillator is enabled but not necessarily running and stable\n this resets to 0 but transitions to 1 during chip startup" "0,1" group.long 0x1C++0x03 line.long 0x00 "RANDOMBIT,This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency" rbitfld.long 0x00 0. "RANDOMBIT," "0,1" group.long 0x20++0x03 line.long 0x00 "COUNT,A down counter running at the ROSC frequency which counts to zero and stops.\n To start the counter write a non-zero value.\n Can be used for short software pauses when setting up time sensitive hardware" hexmask.long.byte 0x00 0.--7. 1. "COUNT," tree.end tree "RTC (Real-time Counter)" base ad:0x4005C000 group.long 0x00++0x03 line.long 0x00 "CLKDIV_M1,Divider minus 1 for the 1 second counter" hexmask.long.word 0x00 0.--15. 1. "CLKDIV_M1," group.long 0x04++0x03 line.long 0x00 "SETUP_0,RTC setup register 0" hexmask.long.word 0x00 12.--23. 1. "YEAR,Year" bitfld.long 0x00 8.--11. "MONTH,Month (1..12)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. "DAY,Day of the month (1..31)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x08++0x03 line.long 0x00 "SETUP_1,RTC setup register 1" bitfld.long 0x00 24.--26. "DOTW,Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "HOUR,Hours" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. "MIN,Minutes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "SEC,Seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x0C++0x03 line.long 0x00 "CTRL,RTC Control and status" bitfld.long 0x00 8. "FORCE_NOTLEAPYEAR,If set leapyear is forced off.\n Useful for years divisible by 100 but not by 400" "0,1" bitfld.long 0x00 4. "LOAD,Load RTC" "0,1" rbitfld.long 0x00 1. "RTC_ACTIVE,RTC enabled (running)" "0,1" bitfld.long 0x00 0. "RTC_ENABLE,Enable RTC" "0,1" group.long 0x10++0x03 line.long 0x00 "IRQ_SETUP_0,Interrupt setup register 0" rbitfld.long 0x00 29. "MATCH_ACTIVE," "0,1" bitfld.long 0x00 28. "MATCH_ENA,Global match enable" "0,1" bitfld.long 0x00 26. "YEAR_ENA,Enable year matching" "0,1" bitfld.long 0x00 25. "MONTH_ENA,Enable month matching" "0,1" bitfld.long 0x00 24. "DAY_ENA,Enable day matching" "0,1" hexmask.long.word 0x00 12.--23. 1. "YEAR,Year" newline bitfld.long 0x00 8.--11. "MONTH,Month (1..12)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. "DAY,Day of the month (1..31)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14++0x03 line.long 0x00 "IRQ_SETUP_1,Interrupt setup register 1" bitfld.long 0x00 31. "DOTW_ENA,Enable day of the week matching" "0,1" bitfld.long 0x00 30. "HOUR_ENA,Enable hour matching" "0,1" bitfld.long 0x00 29. "MIN_ENA,Enable minute matching" "0,1" bitfld.long 0x00 28. "SEC_ENA,Enable second matching" "0,1" bitfld.long 0x00 24.--26. "DOTW,Day of the week" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "HOUR,Hours" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--13. "MIN,Minutes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "SEC,Seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x18++0x03 line.long 0x00 "RTC_1,RTC register 1" hexmask.long.word 0x00 12.--23. 1. "YEAR,Year" rbitfld.long 0x00 8.--11. "MONTH,Month (1..12)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--4. "DAY,Day of the month (1..31)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C++0x03 line.long 0x00 "RTC_0,RTC register 0\n Read this before RTC 1!" rbitfld.long 0x00 24.--26. "DOTW,Day of the week" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 16.--20. "HOUR,Hours" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 8.--13. "MIN,Minutes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0.--5. "SEC,Seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x03 line.long 0x00 "INTR,Raw Interrupts" rbitfld.long 0x00 0. "RTC," "0,1" group.long 0x24++0x03 line.long 0x00 "INTE,Interrupt Enable" bitfld.long 0x00 0. "RTC," "0,1" group.long 0x28++0x03 line.long 0x00 "INTF,Interrupt Force" bitfld.long 0x00 0. "RTC," "0,1" group.long 0x2C++0x03 line.long 0x00 "INTS,Interrupt status after masking & forcing" rbitfld.long 0x00 0. "RTC," "0,1" tree.end tree "SIO (SuperIO Controller)" base ad:0xD0000000 rgroup.long 0x00++0x03 line.long 0x00 "CPUID,Processor core identifier\n Value is 0 when read from processor core 0 and 1 when read from processor core 1" group.long 0x04++0x03 line.long 0x00 "GPIO_IN,Input value for GPIO pins" hexmask.long 0x00 0.--29. 1. "GPIO_IN,Input value for GPIO0...29" group.long 0x08++0x03 line.long 0x00 "GPIO_HI_IN,Input value for QSPI pins" rbitfld.long 0x00 0.--5. "GPIO_HI_IN,Input value on QSPI IO in order 0..5: SCLK SSn SD0 SD1 SD2 SD3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "GPIO_OUT,GPIO output value" hexmask.long 0x00 0.--29. 1. "GPIO_OUT,Set output level (1/0 -> high/low) for GPIO0...29.\n Reading back gives the last value written NOT the input value from the pins.\n If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias) \n the result is as.." group.long 0x14++0x03 line.long 0x00 "GPIO_OUT_SET,GPIO output value set" hexmask.long 0x00 0.--29. 1. "GPIO_OUT_SET,Perform an atomic bit-set on GPIO_OUT i.e" group.long 0x18++0x03 line.long 0x00 "GPIO_OUT_CLR,GPIO output value clear" hexmask.long 0x00 0.--29. 1. "GPIO_OUT_CLR,Perform an atomic bit-clear on GPIO_OUT i.e" group.long 0x1C++0x03 line.long 0x00 "GPIO_OUT_XOR,GPIO output value XOR" hexmask.long 0x00 0.--29. 1. "GPIO_OUT_XOR,Perform an atomic bitwise XOR on GPIO_OUT i.e" group.long 0x20++0x03 line.long 0x00 "GPIO_OE,GPIO output enable" hexmask.long 0x00 0.--29. 1. "GPIO_OE,Set output enable (1/0 -> output/input) for GPIO0...29.\n Reading back gives the last value written.\n If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias) \n the result is as though the write from core 0 took.." group.long 0x24++0x03 line.long 0x00 "GPIO_OE_SET,GPIO output enable set" hexmask.long 0x00 0.--29. 1. "GPIO_OE_SET,Perform an atomic bit-set on GPIO_OE i.e" group.long 0x28++0x03 line.long 0x00 "GPIO_OE_CLR,GPIO output enable clear" hexmask.long 0x00 0.--29. 1. "GPIO_OE_CLR,Perform an atomic bit-clear on GPIO_OE i.e" group.long 0x2C++0x03 line.long 0x00 "GPIO_OE_XOR,GPIO output enable XOR" hexmask.long 0x00 0.--29. 1. "GPIO_OE_XOR,Perform an atomic bitwise XOR on GPIO_OE i.e" group.long 0x30++0x03 line.long 0x00 "GPIO_HI_OUT,QSPI output value" bitfld.long 0x00 0.--5. "GPIO_HI_OUT,Set output level (1/0 -> high/low) for QSPI IO0...5.\n Reading back gives the last value written NOT the input value from the pins.\n If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias) \n the result is.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x34++0x03 line.long 0x00 "GPIO_HI_OUT_SET,QSPI output value set" bitfld.long 0x00 0.--5. "GPIO_HI_OUT_SET,Perform an atomic bit-set on GPIO_HI_OUT i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x38++0x03 line.long 0x00 "GPIO_HI_OUT_CLR,QSPI output value clear" bitfld.long 0x00 0.--5. "GPIO_HI_OUT_CLR,Perform an atomic bit-clear on GPIO_HI_OUT i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x3C++0x03 line.long 0x00 "GPIO_HI_OUT_XOR,QSPI output value XOR" bitfld.long 0x00 0.--5. "GPIO_HI_OUT_XOR,Perform an atomic bitwise XOR on GPIO_HI_OUT i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x40++0x03 line.long 0x00 "GPIO_HI_OE,QSPI output enable" bitfld.long 0x00 0.--5. "GPIO_HI_OE,Set output enable (1/0 -> output/input) for QSPI IO0...5.\n Reading back gives the last value written.\n If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias) \n the result is as though the write from core 0.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x03 line.long 0x00 "GPIO_HI_OE_SET,QSPI output enable set" bitfld.long 0x00 0.--5. "GPIO_HI_OE_SET,Perform an atomic bit-set on GPIO_HI_OE i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x48++0x03 line.long 0x00 "GPIO_HI_OE_CLR,QSPI output enable clear" bitfld.long 0x00 0.--5. "GPIO_HI_OE_CLR,Perform an atomic bit-clear on GPIO_HI_OE i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4C++0x03 line.long 0x00 "GPIO_HI_OE_XOR,QSPI output enable XOR" bitfld.long 0x00 0.--5. "GPIO_HI_OE_XOR,Perform an atomic bitwise XOR on GPIO_HI_OE i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x50++0x03 line.long 0x00 "FIFO_ST,Status register for inter-core FIFOs (mailboxes).\n There is one FIFO in the core 0 -> core 1 direction and one core 1 -> core 0" eventfld.long 0x00 3. "ROE,Sticky flag indicating the RX FIFO was read when empty" "0,1" eventfld.long 0x00 2. "WOF,Sticky flag indicating the TX FIFO was written when full" "0,1" rbitfld.long 0x00 1. "RDY,Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)" "0,1" rbitfld.long 0x00 0. "VLD,Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)" "0,1" wgroup.long 0x54++0x03 line.long 0x00 "FIFO_WR,Write access to this core's TX FIFO" rgroup.long 0x58++0x03 line.long 0x00 "FIFO_RD,Read access to this core's RX FIFO" rgroup.long 0x5C++0x03 line.long 0x00 "SPINLOCK_ST,Spinlock state\n A bitmap containing the state of all 32 spinlocks (1=locked).\n Mainly intended for debugging" group.long 0x60++0x03 line.long 0x00 "DIV_UDIVIDEND,Divider unsigned dividend\n Write to the DIVIDEND operand of the divider i.e" group.long 0x64++0x03 line.long 0x00 "DIV_UDIVISOR,Divider unsigned divisor\n Write to the DIVISOR operand of the divider i.e" group.long 0x68++0x03 line.long 0x00 "DIV_SDIVIDEND,Divider signed dividend\n The same as UDIVIDEND but starts a signed calculation rather than unsigned" group.long 0x6C++0x03 line.long 0x00 "DIV_SDIVISOR,Divider signed divisor\n The same as UDIVISOR but starts a signed calculation rather than unsigned" group.long 0x70++0x03 line.long 0x00 "DIV_QUOTIENT,Divider result quotient\n The result of `DIVIDEND / DIVISOR` (division)" group.long 0x74++0x03 line.long 0x00 "DIV_REMAINDER,Divider result remainder\n The result of `DIVIDEND % DIVISOR` (modulo)" group.long 0x78++0x03 line.long 0x00 "DIV_CSR,Control and status register for divider" rbitfld.long 0x00 1. "DIRTY,Changes to 1 when any register is written and back to 0 when QUOTIENT is read.\n Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n If the flag is used in this way it's recommended to either read QUOTIENT only \n.." "0,1" rbitfld.long 0x00 0. "READY,Reads as 0 when a calculation is in progress 1 otherwise.\n Writing an operand (xDIVIDEND xDIVISOR) will immediately start a new calculation no\n matter if one is already in progress.\n Writing to a result register will immediately terminate any.." "0,1" repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0x80)++0x03 line.long 0x00 "INTERP0_ACCUM$1,Read/write access to accumulator $1" repeat.end group.long 0x88++0x03 line.long 0x00 "INTERP0_BASE0,Read/write access to BASE0 register" group.long 0x8C++0x03 line.long 0x00 "INTERP0_BASE1,Read/write access to BASE1 register" group.long 0x90++0x03 line.long 0x00 "INTERP0_BASE2,Read/write access to BASE2 register" rgroup.long 0x94++0x03 line.long 0x00 "INTERP0_POP_LANE0,Read LANE0 result and simultaneously write lane results to both accumulators (POP)" rgroup.long 0x98++0x03 line.long 0x00 "INTERP0_POP_LANE1,Read LANE1 result and simultaneously write lane results to both accumulators (POP)" rgroup.long 0x9C++0x03 line.long 0x00 "INTERP0_POP_FULL,Read FULL result and simultaneously write lane results to both accumulators (POP)" rgroup.long 0xA0++0x03 line.long 0x00 "INTERP0_PEEK_LANE0,Read LANE0 result without altering any internal state (PEEK)" rgroup.long 0xA4++0x03 line.long 0x00 "INTERP0_PEEK_LANE1,Read LANE1 result without altering any internal state (PEEK)" rgroup.long 0xA8++0x03 line.long 0x00 "INTERP0_PEEK_FULL,Read FULL result without altering any internal state (PEEK)" group.long 0xAC++0x03 line.long 0x00 "INTERP0_CTRL_LANE0,Control register for lane 0" rbitfld.long 0x00 25. "OVERF,Set if either OVERF0 or OVERF1 is set" "0,1" rbitfld.long 0x00 24. "OVERF1,Indicates if any masked-off MSBs in ACCUM1 are set" "0,1" rbitfld.long 0x00 23. "OVERF0,Indicates if any masked-off MSBs in ACCUM0 are set" "0,1" bitfld.long 0x00 21. "BLEND,Only present on INTERP0 on each core" "0,1" bitfld.long 0x00 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath" "0,1,2,3" newline bitfld.long 0x00 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE0 result" "0,1" bitfld.long 0x00 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP" "0,1" bitfld.long 0x00 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)" "0,1" bitfld.long 0x00 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE0 and LANE0 PEEK/POP appear extended to 32 bits when read by processor" "0,1" bitfld.long 0x00 10.--14. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SHIFT,Logical right-shift applied to accumulator before masking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB0++0x03 line.long 0x00 "INTERP0_CTRL_LANE1,Control register for lane 1" bitfld.long 0x00 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath" "0,1,2,3" bitfld.long 0x00 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE1 result" "0,1" bitfld.long 0x00 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP" "0,1" bitfld.long 0x00 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)" "0,1" bitfld.long 0x00 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE1 and LANE1 PEEK/POP appear extended to 32 bits when read by processor" "0,1" newline bitfld.long 0x00 10.--14. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SHIFT,Logical right-shift applied to accumulator before masking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB4++0x03 line.long 0x00 "INTERP0_ACCUM0_ADD,Values written here are atomically added to ACCUM0\n Reading yields lane 0's raw shift and mask value (BASE0 not added)" hexmask.long.tbyte 0x00 0.--23. 1. "INTERP0_ACCUM0_ADD," group.long 0xB8++0x03 line.long 0x00 "INTERP0_ACCUM1_ADD,Values written here are atomically added to ACCUM1\n Reading yields lane 1's raw shift and mask value (BASE1 not added)" hexmask.long.tbyte 0x00 0.--23. 1. "INTERP0_ACCUM1_ADD," wgroup.long 0xBC++0x03 line.long 0x00 "INTERP0_BASE_1AND0,On write the lower 16 bits go to BASE0 upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane's SIGNED flag is set" repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0xC0)++0x03 line.long 0x00 "INTERP1_ACCUM$1,Read/write access to accumulator $1" repeat.end group.long 0xC8++0x03 line.long 0x00 "INTERP1_BASE0,Read/write access to BASE0 register" group.long 0xCC++0x03 line.long 0x00 "INTERP1_BASE1,Read/write access to BASE1 register" group.long 0xD0++0x03 line.long 0x00 "INTERP1_BASE2,Read/write access to BASE2 register" rgroup.long 0xD4++0x03 line.long 0x00 "INTERP1_POP_LANE0,Read LANE0 result and simultaneously write lane results to both accumulators (POP)" rgroup.long 0xD8++0x03 line.long 0x00 "INTERP1_POP_LANE1,Read LANE1 result and simultaneously write lane results to both accumulators (POP)" rgroup.long 0xDC++0x03 line.long 0x00 "INTERP1_POP_FULL,Read FULL result and simultaneously write lane results to both accumulators (POP)" rgroup.long 0xE0++0x03 line.long 0x00 "INTERP1_PEEK_LANE0,Read LANE0 result without altering any internal state (PEEK)" rgroup.long 0xE4++0x03 line.long 0x00 "INTERP1_PEEK_LANE1,Read LANE1 result without altering any internal state (PEEK)" rgroup.long 0xE8++0x03 line.long 0x00 "INTERP1_PEEK_FULL,Read FULL result without altering any internal state (PEEK)" group.long 0xEC++0x03 line.long 0x00 "INTERP1_CTRL_LANE0,Control register for lane 0" rbitfld.long 0x00 25. "OVERF,Set if either OVERF0 or OVERF1 is set" "0,1" rbitfld.long 0x00 24. "OVERF1,Indicates if any masked-off MSBs in ACCUM1 are set" "0,1" rbitfld.long 0x00 23. "OVERF0,Indicates if any masked-off MSBs in ACCUM0 are set" "0,1" bitfld.long 0x00 22. "CLAMP,Only present on INTERP1 on each core" "0,1" bitfld.long 0x00 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath" "0,1,2,3" newline bitfld.long 0x00 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE0 result" "0,1" bitfld.long 0x00 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP" "0,1" bitfld.long 0x00 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)" "0,1" bitfld.long 0x00 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE0 and LANE0 PEEK/POP appear extended to 32 bits when read by processor" "0,1" bitfld.long 0x00 10.--14. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SHIFT,Logical right-shift applied to accumulator before masking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF0++0x03 line.long 0x00 "INTERP1_CTRL_LANE1,Control register for lane 1" bitfld.long 0x00 19.--20. "FORCE_MSB,ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath" "0,1,2,3" bitfld.long 0x00 18. "ADD_RAW,If 1 mask + shift is bypassed for LANE1 result" "0,1" bitfld.long 0x00 17. "CROSS_RESULT,If 1 feed the opposite lane's result into this lane's accumulator on POP" "0,1" bitfld.long 0x00 16. "CROSS_INPUT,If 1 feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)" "0,1" bitfld.long 0x00 15. "SIGNED,If SIGNED is set the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE1 and LANE1 PEEK/POP appear extended to 32 bits when read by processor" "0,1" newline bitfld.long 0x00 10.--14. "MASK_MSB,The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "MASK_LSB,The least-significant bit allowed to pass by the mask (inclusive)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SHIFT,Logical right-shift applied to accumulator before masking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF4++0x03 line.long 0x00 "INTERP1_ACCUM0_ADD,Values written here are atomically added to ACCUM0\n Reading yields lane 0's raw shift and mask value (BASE0 not added)" hexmask.long.tbyte 0x00 0.--23. 1. "INTERP1_ACCUM0_ADD," group.long 0xF8++0x03 line.long 0x00 "INTERP1_ACCUM1_ADD,Values written here are atomically added to ACCUM1\n Reading yields lane 1's raw shift and mask value (BASE1 not added)" hexmask.long.tbyte 0x00 0.--23. 1. "INTERP1_ACCUM1_ADD," wgroup.long 0xFC++0x03 line.long 0x00 "INTERP1_BASE_1AND0,On write the lower 16 bits go to BASE0 upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane's SIGNED flag is set" repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x100)++0x03 line.long 0x00 "SPINLOCK$1,Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock.." repeat.end repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x140)++0x03 line.long 0x00 "SPINLOCK$1,Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock.." repeat.end tree.end tree "SPI (Serial Peripheral Interface)" repeat 2. (list 0. 1.) (list ad:0x4003C000 ad:0x40040000) tree "SPI$1" base $2 group.long 0x00++0x03 line.long 0x00 "SSPCR0,Control register 0 SSPCR0 on page 3-4" hexmask.long.byte 0x00 8.--15. 1. "SCR,Serial clock rate" bitfld.long 0x00 7. "SPH,SSPCLKOUT phase applicable to Motorola SPI frame format only" "0,1" bitfld.long 0x00 6. "SPO,SSPCLKOUT polarity applicable to Motorola SPI frame format only" "0,1" bitfld.long 0x00 4.--5. "FRF,Frame format: 00 Motorola SPI frame format" "0,1,2,3" bitfld.long 0x00 0.--3. "DSS,Data Size Select: 0000 Reserved undefined operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x04++0x03 line.long 0x00 "SSPCR1,Control register 1 SSPCR1 on page 3-5" bitfld.long 0x00 3. "SOD,Slave-mode output disable" "0,1" bitfld.long 0x00 2. "MS,Master or slave mode select" "0,1" bitfld.long 0x00 1. "SSE,Synchronous serial port enable: 0 SSP operation disabled" "0,1" bitfld.long 0x00 0. "LBM,Loop back mode: 0 Normal serial port operation enabled" "0,1" group.long 0x08++0x03 line.long 0x00 "SSPDR,Data register SSPDR on page 3-6" hexmask.long.word 0x00 0.--15. 1. "DATA,Transmit/Receive FIFO: Read Receive FIFO" group.long 0x0C++0x03 line.long 0x00 "SSPSR,Status register SSPSR on page 3-7" rbitfld.long 0x00 4. "BSY,PrimeCell SSP busy flag RO: 0 SSP is idle" "0,1" rbitfld.long 0x00 3. "RFF,Receive FIFO full RO: 0 Receive FIFO is not full" "0,1" rbitfld.long 0x00 2. "RNE,Receive FIFO not empty RO: 0 Receive FIFO is empty" "0,1" rbitfld.long 0x00 1. "TNF,Transmit FIFO not full RO: 0 Transmit FIFO is full" "0,1" rbitfld.long 0x00 0. "TFE,Transmit FIFO empty RO: 0 Transmit FIFO is not empty" "0,1" group.long 0x10++0x03 line.long 0x00 "SSPCPSR,Clock prescale register SSPCPSR on page 3-8" hexmask.long.byte 0x00 0.--7. 1. "CPSDVSR,Clock prescale divisor" group.long 0x14++0x03 line.long 0x00 "SSPIMSC,Interrupt mask set or clear register SSPIMSC on page 3-9" bitfld.long 0x00 3. "TXIM,Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked" "0,1" bitfld.long 0x00 2. "RXIM,Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked" "0,1" bitfld.long 0x00 1. "RTIM,Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked" "0,1" bitfld.long 0x00 0. "RORIM,Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked" "0,1" group.long 0x18++0x03 line.long 0x00 "SSPRIS,Raw interrupt status register SSPRIS on page 3-10" rbitfld.long 0x00 3. "TXRIS,Gives the raw interrupt state prior to masking of the SSPTXINTR interrupt" "0,1" rbitfld.long 0x00 2. "RXRIS,Gives the raw interrupt state prior to masking of the SSPRXINTR interrupt" "0,1" rbitfld.long 0x00 1. "RTRIS,Gives the raw interrupt state prior to masking of the SSPRTINTR interrupt" "0,1" rbitfld.long 0x00 0. "RORRIS,Gives the raw interrupt state prior to masking of the SSPRORINTR interrupt" "0,1" group.long 0x1C++0x03 line.long 0x00 "SSPMIS,Masked interrupt status register SSPMIS on page 3-11" rbitfld.long 0x00 3. "TXMIS,Gives the transmit FIFO masked interrupt state after masking of the SSPTXINTR interrupt" "0,1" rbitfld.long 0x00 2. "RXMIS,Gives the receive FIFO masked interrupt state after masking of the SSPRXINTR interrupt" "0,1" rbitfld.long 0x00 1. "RTMIS,Gives the receive timeout masked interrupt state after masking of the SSPRTINTR interrupt" "0,1" rbitfld.long 0x00 0. "RORMIS,Gives the receive over run masked interrupt status after masking of the SSPRORINTR interrupt" "0,1" group.long 0x20++0x03 line.long 0x00 "SSPICR,Interrupt clear register SSPICR on page 3-11" eventfld.long 0x00 1. "RTIC,Clears the SSPRTINTR interrupt" "0,1" eventfld.long 0x00 0. "RORIC,Clears the SSPRORINTR interrupt" "0,1" group.long 0x24++0x03 line.long 0x00 "SSPDMACR,DMA control register SSPDMACR on page 3-12" bitfld.long 0x00 1. "TXDMAE,Transmit DMA Enable" "0,1" bitfld.long 0x00 0. "RXDMAE,Receive DMA Enable" "0,1" group.long 0xFE0++0x03 line.long 0x00 "SSPPERIPHID0,Peripheral identification registers SSPPeriphID0-3 on page 3-13" hexmask.long.byte 0x00 0.--7. 1. "PARTNUMBER0,These bits read back as 0x22" group.long 0xFE4++0x03 line.long 0x00 "SSPPERIPHID1,Peripheral identification registers SSPPeriphID0-3 on page 3-13" rbitfld.long 0x00 4.--7. "DESIGNER0,These bits read back as 0x1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PARTNUMBER1,These bits read back as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFE8++0x03 line.long 0x00 "SSPPERIPHID2,Peripheral identification registers SSPPeriphID0-3 on page 3-13" rbitfld.long 0x00 4.--7. "REVISION,These bits return the peripheral revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "DESIGNER1,These bits read back as 0x4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFEC++0x03 line.long 0x00 "SSPPERIPHID3,Peripheral identification registers SSPPeriphID0-3 on page 3-13" hexmask.long.byte 0x00 0.--7. 1. "CONFIGURATION,These bits read back as 0x00" group.long 0xFF0++0x03 line.long 0x00 "SSPPCELLID0,PrimeCell identification registers SSPPCellID0-3 on page 3-16" hexmask.long.byte 0x00 0.--7. 1. "SSPPCELLID0,These bits read back as 0x0D" group.long 0xFF4++0x03 line.long 0x00 "SSPPCELLID1,PrimeCell identification registers SSPPCellID0-3 on page 3-16" hexmask.long.byte 0x00 0.--7. 1. "SSPPCELLID1,These bits read back as 0xF0" group.long 0xFF8++0x03 line.long 0x00 "SSPPCELLID2,PrimeCell identification registers SSPPCellID0-3 on page 3-16" hexmask.long.byte 0x00 0.--7. 1. "SSPPCELLID2,These bits read back as 0x05" group.long 0xFFC++0x03 line.long 0x00 "SSPPCELLID3,PrimeCell identification registers SSPPCellID0-3 on page 3-16" hexmask.long.byte 0x00 0.--7. 1. "SSPPCELLID3,These bits read back as 0xB1" tree.end repeat.end tree.end tree "SYSCFG (System Config)" base ad:0x40004000 group.long 0x00++0x03 line.long 0x00 "PROC0_NMI_MASK,Processor core 0 NMI source mask\n Set a bit high to enable NMI from that IRQ" group.long 0x04++0x03 line.long 0x00 "PROC1_NMI_MASK,Processor core 1 NMI source mask\n Set a bit high to enable NMI from that IRQ" group.long 0x08++0x03 line.long 0x00 "PROC_CONFIG,Configuration for processors" bitfld.long 0x00 28.--31. "PROC1_DAP_INSTID,Configure proc1 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "PROC0_DAP_INSTID,Configure proc0 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "PROC1_HALTED,Indication that proc1 has halted" "0,1" rbitfld.long 0x00 0. "PROC0_HALTED,Indication that proc0 has halted" "0,1" group.long 0x0C++0x03 line.long 0x00 "PROC_IN_SYNC_BYPASS,For each bit if 1 bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO" hexmask.long 0x00 0.--29. 1. "PROC_IN_SYNC_BYPASS," group.long 0x10++0x03 line.long 0x00 "PROC_IN_SYNC_BYPASS_HI,For each bit if 1 bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO" bitfld.long 0x00 0.--5. "PROC_IN_SYNC_BYPASS_HI," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x14++0x03 line.long 0x00 "DBGFORCE,Directly control the SWD debug port of either processor" bitfld.long 0x00 7. "PROC1_ATTACH,Attach processor 1 debug port to syscfg controls and disconnect it from external SWD pads" "0,1" bitfld.long 0x00 6. "PROC1_SWCLK,Directly drive processor 1 SWCLK if PROC1_ATTACH is set" "0,1" bitfld.long 0x00 5. "PROC1_SWDI,Directly drive processor 1 SWDIO input if PROC1_ATTACH is set" "0,1" rbitfld.long 0x00 4. "PROC1_SWDO,Observe the value of processor 1 SWDIO output" "0,1" newline bitfld.long 0x00 3. "PROC0_ATTACH,Attach processor 0 debug port to syscfg controls and disconnect it from external SWD pads" "0,1" bitfld.long 0x00 2. "PROC0_SWCLK,Directly drive processor 0 SWCLK if PROC0_ATTACH is set" "0,1" bitfld.long 0x00 1. "PROC0_SWDI,Directly drive processor 0 SWDIO input if PROC0_ATTACH is set" "0,1" rbitfld.long 0x00 0. "PROC0_SWDO,Observe the value of processor 0 SWDIO output" "0,1" group.long 0x18++0x03 line.long 0x00 "MEMPOWERDOWN,Control power downs to memories" bitfld.long 0x00 7. "ROM," "0,1" bitfld.long 0x00 6. "USB," "0,1" bitfld.long 0x00 5. "SRAM5," "0,1" bitfld.long 0x00 4. "SRAM4," "0,1" newline bitfld.long 0x00 3. "SRAM3," "0,1" bitfld.long 0x00 2. "SRAM2," "0,1" bitfld.long 0x00 1. "SRAM1," "0,1" bitfld.long 0x00 0. "SRAM0," "0,1" tree.end tree "SYSINFO (System Info)" base ad:0x40000000 group.long 0x00++0x03 line.long 0x00 "CHIP_ID,JEDEC JEP-106 compliant chip identifier" rbitfld.long 0x00 28.--31. "REVISION," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 12.--27. 1. "PART," hexmask.long.word 0x00 0.--11. 1. "MANUFACTURER," group.long 0x04++0x03 line.long 0x00 "PLATFORM,Platform register" rbitfld.long 0x00 1. "ASIC," "0,1" rbitfld.long 0x00 0. "FPGA," "0,1" rgroup.long 0x40++0x03 line.long 0x00 "GITREF_RP2040,Git hash of the chip source" tree.end tree "TBMAN (Testbench Manager)" base ad:0x4006C000 group.long 0x00++0x03 line.long 0x00 "PLATFORM,Indicates the type of platform in use" rbitfld.long 0x00 1. "FPGA,Indicates the platform is an FPGA" "0,1" rbitfld.long 0x00 0. "ASIC,Indicates the platform is an ASIC" "0,1" tree.end tree "TIMER (Timer/Counter)" base ad:0x40054000 wgroup.long 0x00++0x03 line.long 0x00 "TIMEHW,Write to bits 63:32 of time\n always write timelw before timehw" wgroup.long 0x04++0x03 line.long 0x00 "TIMELW,Write to bits 31:0 of time\n writes do not get copied to time until timehw is written" rgroup.long 0x08++0x03 line.long 0x00 "TIMEHR,Read from bits 63:32 of time\n always read timelr before timehr" rgroup.long 0x0C++0x03 line.long 0x00 "TIMELR,Read from bits 31:0 of time" group.long 0x10++0x03 line.long 0x00 "ALARM0,Arm alarm 0 and configure the time it will fire.\n Once armed the alarm fires when TIMER_ALARM0 == TIMELR.\n The alarm will disarm itself once it fires and can\n be disarmed early using the ARMED status register" group.long 0x14++0x03 line.long 0x00 "ALARM1,Arm alarm 1 and configure the time it will fire.\n Once armed the alarm fires when TIMER_ALARM1 == TIMELR.\n The alarm will disarm itself once it fires and can\n be disarmed early using the ARMED status register" group.long 0x18++0x03 line.long 0x00 "ALARM2,Arm alarm 2 and configure the time it will fire.\n Once armed the alarm fires when TIMER_ALARM2 == TIMELR.\n The alarm will disarm itself once it fires and can\n be disarmed early using the ARMED status register" group.long 0x1C++0x03 line.long 0x00 "ALARM3,Arm alarm 3 and configure the time it will fire.\n Once armed the alarm fires when TIMER_ALARM3 == TIMELR.\n The alarm will disarm itself once it fires and can\n be disarmed early using the ARMED status register" group.long 0x20++0x03 line.long 0x00 "ARMED,Indicates the armed/disarmed status of each alarm.\n A write to the corresponding ALARMx register arms the alarm.\n Alarms automatically disarm upon firing but writing ones here\n will disarm immediately without waiting to fire" eventfld.long 0x00 0.--3. "ARMED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x24++0x03 line.long 0x00 "TIMERAWH,Raw read from bits 63:32 of time (no side effects)" rgroup.long 0x28++0x03 line.long 0x00 "TIMERAWL,Raw read from bits 31:0 of time (no side effects)" group.long 0x2C++0x03 line.long 0x00 "DBGPAUSE,Set bits high to enable pause when the corresponding debug ports are active" bitfld.long 0x00 2. "DBG1,Pause when processor 1 is in debug mode" "0,1" bitfld.long 0x00 1. "DBG0,Pause when processor 0 is in debug mode" "0,1" group.long 0x30++0x03 line.long 0x00 "PAUSE,Set high to pause the timer" bitfld.long 0x00 0. "PAUSE," "0,1" group.long 0x34++0x03 line.long 0x00 "INTR,Raw Interrupts" eventfld.long 0x00 3. "ALARM_3," "0,1" eventfld.long 0x00 2. "ALARM_2," "0,1" eventfld.long 0x00 1. "ALARM_1," "0,1" eventfld.long 0x00 0. "ALARM_0," "0,1" group.long 0x38++0x03 line.long 0x00 "INTE,Interrupt Enable" bitfld.long 0x00 3. "ALARM_3," "0,1" bitfld.long 0x00 2. "ALARM_2," "0,1" bitfld.long 0x00 1. "ALARM_1," "0,1" bitfld.long 0x00 0. "ALARM_0," "0,1" group.long 0x3C++0x03 line.long 0x00 "INTF,Interrupt Force" bitfld.long 0x00 3. "ALARM_3," "0,1" bitfld.long 0x00 2. "ALARM_2," "0,1" bitfld.long 0x00 1. "ALARM_1," "0,1" bitfld.long 0x00 0. "ALARM_0," "0,1" group.long 0x40++0x03 line.long 0x00 "INTS,Interrupt status after masking & forcing" rbitfld.long 0x00 3. "ALARM_3," "0,1" rbitfld.long 0x00 2. "ALARM_2," "0,1" rbitfld.long 0x00 1. "ALARM_1," "0,1" rbitfld.long 0x00 0. "ALARM_0," "0,1" tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" repeat 2. (list 0. 1.) (list ad:0x40034000 ad:0x40038000) tree "UART$1" base $2 group.long 0x00++0x03 line.long 0x00 "UARTDR,Data Register UARTDR" rbitfld.long 0x00 11. "OE,Overrun error" "0,1" rbitfld.long 0x00 10. "BE,Break error" "0,1" newline rbitfld.long 0x00 9. "PE,Parity error" "0,1" rbitfld.long 0x00 8. "FE,Framing error" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive (read) data character" group.long 0x04++0x03 line.long 0x00 "UARTRSR,Receive Status Register/Error Clear Register UARTRSR/UARTECR" eventfld.long 0x00 3. "OE,Overrun error" "0,1" eventfld.long 0x00 2. "BE,Break error" "0,1" newline eventfld.long 0x00 1. "PE,Parity error" "0,1" eventfld.long 0x00 0. "FE,Framing error" "0,1" group.long 0x18++0x03 line.long 0x00 "UARTFR,Flag Register UARTFR" rbitfld.long 0x00 8. "RI,Ring indicator" "0,1" rbitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1" newline rbitfld.long 0x00 6. "RXFF,Receive FIFO full" "0,1" rbitfld.long 0x00 5. "TXFF,Transmit FIFO full" "0,1" newline rbitfld.long 0x00 4. "RXFE,Receive FIFO empty" "0,1" rbitfld.long 0x00 3. "BUSY,UART busy" "0,1" newline rbitfld.long 0x00 2. "DCD,Data carrier detect" "0,1" rbitfld.long 0x00 1. "DSR,Data set ready" "0,1" newline rbitfld.long 0x00 0. "CTS,Clear to send" "0,1" group.long 0x20++0x03 line.long 0x00 "UARTILPR,IrDA Low-Power Counter Register UARTILPR" hexmask.long.byte 0x00 0.--7. 1. "ILPDVSR,8-bit low-power divisor value" group.long 0x24++0x03 line.long 0x00 "UARTIBRD,Integer Baud Rate Register UARTIBRD" hexmask.long.word 0x00 0.--15. 1. "BAUD_DIVINT,The integer baud rate divisor" group.long 0x28++0x03 line.long 0x00 "UARTFBRD,Fractional Baud Rate Register UARTFBRD" bitfld.long 0x00 0.--5. "BAUD_DIVFRAC,The fractional baud rate divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2C++0x03 line.long 0x00 "UARTLCR_H,Line Control Register UARTLCR_H" bitfld.long 0x00 7. "SPS,Stick parity select" "0: stick parity is disabled,1: either" bitfld.long 0x00 5.--6. "WLEN,Word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits" newline bitfld.long 0x00 4. "FEN,Enable FIFOs" "0: FIFOs are disabled (character mode) that is the,1: transmit and receive FIFO buffers are enabled" bitfld.long 0x00 3. "STP2,Two stop bits select" "0,1" newline bitfld.long 0x00 2. "EPS,Even parity select" "0: odd parity,1: even parity" bitfld.long 0x00 1. "PEN,Parity enable" "0: parity is disabled and no parity bit added to,1: parity checking and generation is enabled" newline bitfld.long 0x00 0. "BRK,Send break" "0,1" group.long 0x30++0x03 line.long 0x00 "UARTCR,Control Register UARTCR" bitfld.long 0x00 15. "CTSEN,CTS hardware flow control enable" "0,1" bitfld.long 0x00 14. "RTSEN,RTS hardware flow control enable" "0,1" newline bitfld.long 0x00 13. "OUT2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output" "0,1" bitfld.long 0x00 12. "OUT1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output" "0,1" newline bitfld.long 0x00 11. "RTS,Request to send" "0,1" bitfld.long 0x00 10. "DTR,Data transmit ready" "0,1" newline bitfld.long 0x00 9. "RXE,Receive enable" "0,1" bitfld.long 0x00 8. "TXE,Transmit enable" "0,1" newline bitfld.long 0x00 7. "LBE,Loopback enable" "0,1" bitfld.long 0x00 2. "SIRLP,SIR low-power IrDA mode" "0,1" newline bitfld.long 0x00 1. "SIREN,SIR enable" "0: IrDA SIR ENDEC is disabled,1: IrDA SIR ENDEC is enabled" bitfld.long 0x00 0. "UARTEN,UART enable" "0: UART is disabled,1: the UART is enabled" group.long 0x34++0x03 line.long 0x00 "UARTIFLS,Interrupt FIFO Level Select Register UARTIFLS" bitfld.long 0x00 3.--5. "RXIFLSEL,Receive interrupt FIFO level select" "0: Receive FIFO becomes >= 1 / 8 full,1: Receive FIFO becomes >= 1 / 4 full,2: Receive FIFO becomes >= 1 / 2 full,3: Receive FIFO becomes >= 3 / 4 full,4: Receive FIFO becomes >= 7 / 8 full b101-b111 =,?..." bitfld.long 0x00 0.--2. "TXIFLSEL,Transmit interrupt FIFO level select" "0: Transmit FIFO becomes <= 1 / 8 full,1: Transmit FIFO becomes <= 1 / 4 full,2: Transmit FIFO becomes <= 1 / 2 full,3: Transmit FIFO becomes <= 3 / 4 full,4: Transmit FIFO becomes <= 7 / 8 full b101-b111 =,?..." group.long 0x38++0x03 line.long 0x00 "UARTIMSC,Interrupt Mask Set/Clear Register UARTIMSC" bitfld.long 0x00 10. "OEIM,Overrun error interrupt mask" "0,1" bitfld.long 0x00 9. "BEIM,Break error interrupt mask" "0,1" newline bitfld.long 0x00 8. "PEIM,Parity error interrupt mask" "0,1" bitfld.long 0x00 7. "FEIM,Framing error interrupt mask" "0,1" newline bitfld.long 0x00 6. "RTIM,Receive timeout interrupt mask" "0,1" bitfld.long 0x00 5. "TXIM,Transmit interrupt mask" "0,1" newline bitfld.long 0x00 4. "RXIM,Receive interrupt mask" "0,1" bitfld.long 0x00 3. "DSRMIM,nUARTDSR modem interrupt mask" "0,1" newline bitfld.long 0x00 2. "DCDMIM,nUARTDCD modem interrupt mask" "0,1" bitfld.long 0x00 1. "CTSMIM,nUARTCTS modem interrupt mask" "0,1" newline bitfld.long 0x00 0. "RIMIM,nUARTRI modem interrupt mask" "0,1" group.long 0x3C++0x03 line.long 0x00 "UARTRIS,Raw Interrupt Status Register UARTRIS" rbitfld.long 0x00 10. "OERIS,Overrun error interrupt status" "0,1" rbitfld.long 0x00 9. "BERIS,Break error interrupt status" "0,1" newline rbitfld.long 0x00 8. "PERIS,Parity error interrupt status" "0,1" rbitfld.long 0x00 7. "FERIS,Framing error interrupt status" "0,1" newline rbitfld.long 0x00 6. "RTRIS,Receive timeout interrupt status" "0,1" rbitfld.long 0x00 5. "TXRIS,Transmit interrupt status" "0,1" newline rbitfld.long 0x00 4. "RXRIS,Receive interrupt status" "0,1" rbitfld.long 0x00 3. "DSRRMIS,nUARTDSR modem interrupt status" "0,1" newline rbitfld.long 0x00 2. "DCDRMIS,nUARTDCD modem interrupt status" "0,1" rbitfld.long 0x00 1. "CTSRMIS,nUARTCTS modem interrupt status" "0,1" newline rbitfld.long 0x00 0. "RIRMIS,nUARTRI modem interrupt status" "0,1" group.long 0x40++0x03 line.long 0x00 "UARTMIS,Masked Interrupt Status Register UARTMIS" rbitfld.long 0x00 10. "OEMIS,Overrun error masked interrupt status" "0,1" rbitfld.long 0x00 9. "BEMIS,Break error masked interrupt status" "0,1" newline rbitfld.long 0x00 8. "PEMIS,Parity error masked interrupt status" "0,1" rbitfld.long 0x00 7. "FEMIS,Framing error masked interrupt status" "0,1" newline rbitfld.long 0x00 6. "RTMIS,Receive timeout masked interrupt status" "0,1" rbitfld.long 0x00 5. "TXMIS,Transmit masked interrupt status" "0,1" newline rbitfld.long 0x00 4. "RXMIS,Receive masked interrupt status" "0,1" rbitfld.long 0x00 3. "DSRMMIS,nUARTDSR modem masked interrupt status" "0,1" newline rbitfld.long 0x00 2. "DCDMMIS,nUARTDCD modem masked interrupt status" "0,1" rbitfld.long 0x00 1. "CTSMMIS,nUARTCTS modem masked interrupt status" "0,1" newline rbitfld.long 0x00 0. "RIMMIS,nUARTRI modem masked interrupt status" "0,1" group.long 0x44++0x03 line.long 0x00 "UARTICR,Interrupt Clear Register UARTICR" eventfld.long 0x00 10. "OEIC,Overrun error interrupt clear" "0,1" eventfld.long 0x00 9. "BEIC,Break error interrupt clear" "0,1" newline eventfld.long 0x00 8. "PEIC,Parity error interrupt clear" "0,1" eventfld.long 0x00 7. "FEIC,Framing error interrupt clear" "0,1" newline eventfld.long 0x00 6. "RTIC,Receive timeout interrupt clear" "0,1" eventfld.long 0x00 5. "TXIC,Transmit interrupt clear" "0,1" newline eventfld.long 0x00 4. "RXIC,Receive interrupt clear" "0,1" eventfld.long 0x00 3. "DSRMIC,nUARTDSR modem interrupt clear" "0,1" newline eventfld.long 0x00 2. "DCDMIC,nUARTDCD modem interrupt clear" "0,1" eventfld.long 0x00 1. "CTSMIC,nUARTCTS modem interrupt clear" "0,1" newline eventfld.long 0x00 0. "RIMIC,nUARTRI modem interrupt clear" "0,1" group.long 0x48++0x03 line.long 0x00 "UARTDMACR,DMA Control Register UARTDMACR" bitfld.long 0x00 2. "DMAONERR,DMA on error" "0,1" bitfld.long 0x00 1. "TXDMAE,Transmit DMA enable" "0,1" newline bitfld.long 0x00 0. "RXDMAE,Receive DMA enable" "0,1" group.long 0xFE0++0x03 line.long 0x00 "UARTPERIPHID0,UARTPeriphID0 Register" hexmask.long.byte 0x00 0.--7. 1. "PARTNUMBER0,These bits read back as 0x11" group.long 0xFE4++0x03 line.long 0x00 "UARTPERIPHID1,UARTPeriphID1 Register" rbitfld.long 0x00 4.--7. "DESIGNER0,These bits read back as 0x1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "PARTNUMBER1,These bits read back as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFE8++0x03 line.long 0x00 "UARTPERIPHID2,UARTPeriphID2 Register" rbitfld.long 0x00 4.--7. "REVISION,This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "DESIGNER1,These bits read back as 0x4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFEC++0x03 line.long 0x00 "UARTPERIPHID3,UARTPeriphID3 Register" hexmask.long.byte 0x00 0.--7. 1. "CONFIGURATION,These bits read back as 0x00" group.long 0xFF0++0x03 line.long 0x00 "UARTPCELLID0,UARTPCellID0 Register" hexmask.long.byte 0x00 0.--7. 1. "UARTPCELLID0,These bits read back as 0x0D" group.long 0xFF4++0x03 line.long 0x00 "UARTPCELLID1,UARTPCellID1 Register" hexmask.long.byte 0x00 0.--7. 1. "UARTPCELLID1,These bits read back as 0xF0" group.long 0xFF8++0x03 line.long 0x00 "UARTPCELLID2,UARTPCellID2 Register" hexmask.long.byte 0x00 0.--7. 1. "UARTPCELLID2,These bits read back as 0x05" group.long 0xFFC++0x03 line.long 0x00 "UARTPCELLID3,UARTPCellID3 Register" hexmask.long.byte 0x00 0.--7. 1. "UARTPCELLID3,These bits read back as 0xB1" tree.end repeat.end tree.end tree "USBCTRL_DPRAM (DPRAM Layout for USB)" base ad:0x50100000 group.long 0x00++0x03 line.long 0x00 "SETUP_PACKET_LOW,Bytes 0-3 of the SETUP packet from the host" hexmask.long.word 0x00 16.--31. 1. "WVALUE," hexmask.long.byte 0x00 8.--15. 1. "BREQUEST," hexmask.long.byte 0x00 0.--7. 1. "BMREQUESTTYPE," group.long 0x04++0x03 line.long 0x00 "SETUP_PACKET_HIGH,Bytes 4-7 of the setup packet from the host" hexmask.long.word 0x00 16.--31. 1. "WLENGTH," hexmask.long.word 0x00 0.--15. 1. "WINDEX," group.long 0x08++0x03 line.long 0x00 "EP1_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x0C++0x03 line.long 0x00 "EP1_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x10++0x03 line.long 0x00 "EP2_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x14++0x03 line.long 0x00 "EP2_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x18++0x03 line.long 0x00 "EP3_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x1C++0x03 line.long 0x00 "EP3_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x20++0x03 line.long 0x00 "EP4_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x24++0x03 line.long 0x00 "EP4_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x28++0x03 line.long 0x00 "EP5_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x2C++0x03 line.long 0x00 "EP5_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x30++0x03 line.long 0x00 "EP6_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x34++0x03 line.long 0x00 "EP6_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x38++0x03 line.long 0x00 "EP7_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x3C++0x03 line.long 0x00 "EP7_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x40++0x03 line.long 0x00 "EP8_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x44++0x03 line.long 0x00 "EP8_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x48++0x03 line.long 0x00 "EP9_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x4C++0x03 line.long 0x00 "EP9_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x50++0x03 line.long 0x00 "EP10_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x54++0x03 line.long 0x00 "EP10_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x58++0x03 line.long 0x00 "EP11_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x5C++0x03 line.long 0x00 "EP11_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x60++0x03 line.long 0x00 "EP12_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x64++0x03 line.long 0x00 "EP12_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x68++0x03 line.long 0x00 "EP13_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x6C++0x03 line.long 0x00 "EP13_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x70++0x03 line.long 0x00 "EP14_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x74++0x03 line.long 0x00 "EP14_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x78++0x03 line.long 0x00 "EP15_IN_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x7C++0x03 line.long 0x00 "EP15_OUT_CONTROL," bitfld.long 0x00 31. "ENABLE,Enable this endpoint" "0,1" bitfld.long 0x00 30. "DOUBLE_BUFFERED,This endpoint is double buffered" "0,1" bitfld.long 0x00 29. "INTERRUPT_PER_BUFF,Trigger an interrupt each time a buffer is done" "0,1" newline bitfld.long 0x00 28. "INTERRUPT_PER_DOUBLE_BUFF,Trigger an interrupt each time both buffers are done" "0,1" bitfld.long 0x00 26.--27. "ENDPOINT_TYPE," "0: UNKN_DESC,1: Isochronous,2: UNKN_DESC,3: Interrupt" bitfld.long 0x00 17. "INTERRUPT_ON_STALL,Trigger an interrupt if a STALL is sent" "0,1" newline bitfld.long 0x00 16. "INTERRUPT_ON_NAK,Trigger an interrupt if a NAK is sent" "0,1" hexmask.long.word 0x00 0.--15. 1. "BUFFER_ADDRESS,64 byte aligned buffer address for this EP (bits 0-5 are ignored)" group.long 0x80++0x03 line.long 0x00 "EP0_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0x84++0x03 line.long 0x00 "EP0_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0x88++0x03 line.long 0x00 "EP1_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0x8C++0x03 line.long 0x00 "EP1_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0x90++0x03 line.long 0x00 "EP2_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0x94++0x03 line.long 0x00 "EP2_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0x98++0x03 line.long 0x00 "EP3_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0x9C++0x03 line.long 0x00 "EP3_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xA0++0x03 line.long 0x00 "EP4_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xA4++0x03 line.long 0x00 "EP4_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xA8++0x03 line.long 0x00 "EP5_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xAC++0x03 line.long 0x00 "EP5_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xB0++0x03 line.long 0x00 "EP6_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xB4++0x03 line.long 0x00 "EP6_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xB8++0x03 line.long 0x00 "EP7_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xBC++0x03 line.long 0x00 "EP7_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xC0++0x03 line.long 0x00 "EP8_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xC4++0x03 line.long 0x00 "EP8_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xC8++0x03 line.long 0x00 "EP9_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xCC++0x03 line.long 0x00 "EP9_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xD0++0x03 line.long 0x00 "EP10_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xD4++0x03 line.long 0x00 "EP10_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xD8++0x03 line.long 0x00 "EP11_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xDC++0x03 line.long 0x00 "EP11_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xE0++0x03 line.long 0x00 "EP12_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xE4++0x03 line.long 0x00 "EP12_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xE8++0x03 line.long 0x00 "EP13_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xEC++0x03 line.long 0x00 "EP13_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xF0++0x03 line.long 0x00 "EP14_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xF4++0x03 line.long 0x00 "EP14_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xF8++0x03 line.long 0x00 "EP15_IN_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" group.long 0xFC++0x03 line.long 0x00 "EP15_OUT_BUFFER_CONTROL,Buffer control for both buffers of an endpoint" bitfld.long 0x00 31. "FULL_1,Buffer 1 is full" "0,1" bitfld.long 0x00 30. "LAST_1,Buffer 1 is the last buffer of the transfer" "0,1" bitfld.long 0x00 29. "PID_1,The data pid of buffer 1" "0,1" newline bitfld.long 0x00 27.--28. "DOUBLE_BUFFER_ISO_OFFSET,The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode" "0: UNKN_DESC,1: UNKN_DESC,2: UNKN_DESC,3: UNKN_DESC" bitfld.long 0x00 26. "AVAILABLE_1,Buffer 1 is available" "0,1" hexmask.long.word 0x00 16.--25. 1. "LENGTH_1,The length of the data in buffer 1" newline bitfld.long 0x00 15. "FULL_0,Buffer 0 is full" "0,1" bitfld.long 0x00 14. "LAST_0,Buffer 0 is the last buffer of the transfer" "0,1" bitfld.long 0x00 13. "PID_0,The data pid of buffer 0" "0,1" newline bitfld.long 0x00 12. "RESET,Reset the buffer selector to buffer 0" "0,1" bitfld.long 0x00 11. "STALL,Reply with a stall (valid for both buffers)" "0,1" bitfld.long 0x00 10. "AVAILABLE_0,Buffer 0 is available" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "LENGTH_0,The length of the data in buffer 0" tree.end tree "USBCTRL_REGS (USB FS/LS Controller)" base ad:0x50110000 group.long 0x00++0x03 line.long 0x00 "ADDR_ENDP,Device address and endpoint control" bitfld.long 0x00 16.--19. "ENDPOINT,Device endpoint to send data to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,In device mode the address that the device should respond to" group.long 0x04++0x03 line.long 0x00 "ADDR_ENDP1,Interrupt endpoint 1" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x08++0x03 line.long 0x00 "ADDR_ENDP2,Interrupt endpoint 2" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x0C++0x03 line.long 0x00 "ADDR_ENDP3,Interrupt endpoint 3" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x10++0x03 line.long 0x00 "ADDR_ENDP4,Interrupt endpoint 4" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x14++0x03 line.long 0x00 "ADDR_ENDP5,Interrupt endpoint 5" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x18++0x03 line.long 0x00 "ADDR_ENDP6,Interrupt endpoint 6" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x1C++0x03 line.long 0x00 "ADDR_ENDP7,Interrupt endpoint 7" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x20++0x03 line.long 0x00 "ADDR_ENDP8,Interrupt endpoint 8" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x24++0x03 line.long 0x00 "ADDR_ENDP9,Interrupt endpoint 9" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x28++0x03 line.long 0x00 "ADDR_ENDP10,Interrupt endpoint 10" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x2C++0x03 line.long 0x00 "ADDR_ENDP11,Interrupt endpoint 11" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x30++0x03 line.long 0x00 "ADDR_ENDP12,Interrupt endpoint 12" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x34++0x03 line.long 0x00 "ADDR_ENDP13,Interrupt endpoint 13" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x38++0x03 line.long 0x00 "ADDR_ENDP14,Interrupt endpoint 14" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x3C++0x03 line.long 0x00 "ADDR_ENDP15,Interrupt endpoint 15" bitfld.long 0x00 26. "INTEP_PREAMBLE,Interrupt EP requires preamble (is a low speed device on a full speed hub)" "0,1" bitfld.long 0x00 25. "INTEP_DIR,Direction of the interrupt endpoint" "0,1" newline bitfld.long 0x00 16.--19. "ENDPOINT,Endpoint number of the interrupt endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. "ADDRESS,Device address" group.long 0x40++0x03 line.long 0x00 "MAIN_CTRL,Main control register" bitfld.long 0x00 31. "SIM_TIMING,Reduced timings for simulation" "0,1" bitfld.long 0x00 1. "HOST_NDEVICE,Device mode = 0 Host mode = 1" "0,1" newline bitfld.long 0x00 0. "CONTROLLER_EN,Enable controller" "0,1" group.long 0x44++0x03 line.long 0x00 "SOF_WR,Set the SOF (Start of Frame) frame number in the host controller" hexmask.long.word 0x00 0.--10. 1. "COUNT," group.long 0x48++0x03 line.long 0x00 "SOF_RD,Read the last SOF (Start of Frame) frame number seen" hexmask.long.word 0x00 0.--10. 1. "COUNT," group.long 0x4C++0x03 line.long 0x00 "SIE_CTRL,SIE control register" bitfld.long 0x00 31. "EP0_INT_STALL,Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL" "0,1" bitfld.long 0x00 30. "EP0_DOUBLE_BUF,Device: EP0 single buffered = 0 double buffered = 1" "0,1" newline bitfld.long 0x00 29. "EP0_INT_1BUF,Device: Set bit in BUFF_STATUS for every buffer completed on EP0" "0,1" bitfld.long 0x00 28. "EP0_INT_2BUF,Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0" "0,1" newline bitfld.long 0x00 27. "EP0_INT_NAK,Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK" "0,1" bitfld.long 0x00 26. "DIRECT_EN,Direct bus drive enable" "0,1" newline bitfld.long 0x00 25. "DIRECT_DP,Direct control of DP" "0,1" bitfld.long 0x00 24. "DIRECT_DM,Direct control of DM" "0,1" newline bitfld.long 0x00 18. "TRANSCEIVER_PD,Power down bus transceiver" "0,1" bitfld.long 0x00 17. "RPU_OPT,Device: Pull-up strength (0=1K2 1=2k3)" "0,1" newline bitfld.long 0x00 16. "PULLUP_EN,Device: Enable pull up resistor" "0,1" bitfld.long 0x00 15. "PULLDOWN_EN,Host: Enable pull down resistors" "0,1" newline bitfld.long 0x00 13. "RESET_BUS,Host: Reset bus" "0,1" bitfld.long 0x00 12. "RESUME,Device: Remote wakeup" "0,1" newline bitfld.long 0x00 11. "VBUS_EN,Host: Enable VBUS" "0,1" bitfld.long 0x00 10. "KEEP_ALIVE_EN,Host: Enable keep alive packet (for low speed bus)" "0,1" newline bitfld.long 0x00 9. "SOF_EN,Host: Enable SOF generation (for full speed bus)" "0,1" bitfld.long 0x00 8. "SOF_SYNC,Host: Delay packet(s) until after SOF" "0,1" newline bitfld.long 0x00 6. "PREAMBLE_EN,Host: Preable enable for LS device on FS hub" "0,1" bitfld.long 0x00 4. "STOP_TRANS,Host: Stop transaction" "0,1" newline bitfld.long 0x00 3. "RECEIVE_DATA,Host: Receive transaction (IN to host)" "0,1" bitfld.long 0x00 2. "SEND_DATA,Host: Send transaction (OUT from host)" "0,1" newline bitfld.long 0x00 1. "SEND_SETUP,Host: Send Setup packet" "0,1" bitfld.long 0x00 0. "START_TRANS,Host: Start transaction" "0,1" group.long 0x50++0x03 line.long 0x00 "SIE_STATUS,SIE status register" eventfld.long 0x00 31. "DATA_SEQ_ERROR,Data Sequence Error.\n\n The device can raise a sequence error in the following conditions:\n\n * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but.." "0,1" eventfld.long 0x00 30. "ACK_REC,ACK received" "0,1" newline eventfld.long 0x00 29. "STALL_REC,Host: STALL received" "0,1" eventfld.long 0x00 28. "NAK_REC,Host: NAK received" "0,1" newline eventfld.long 0x00 27. "RX_TIMEOUT,RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec" "0,1" eventfld.long 0x00 26. "RX_OVERFLOW,RX overflow is raised by the Serial RX engine if the incoming data is too fast" "0,1" newline eventfld.long 0x00 25. "BIT_STUFF_ERROR,Bit Stuff Error" "0,1" eventfld.long 0x00 24. "CRC_ERROR,CRC Error" "0,1" newline eventfld.long 0x00 19. "BUS_RESET,Device: bus reset received" "0,1" eventfld.long 0x00 18. "TRANS_COMPLETE,Transaction complete.\n\n Raised by device if:\n\n * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n Raised by host if:\n\n * A setup packet is sent when no data in or data out transaction.." "0,1" newline eventfld.long 0x00 17. "SETUP_REC,Device: Setup packet received" "0,1" eventfld.long 0x00 16. "CONNECTED,Device: connected" "0,1" newline eventfld.long 0x00 11. "RESUME,Host: Device has initiated a remote resume" "0,1" rbitfld.long 0x00 10. "VBUS_OVER_CURR,VBUS over current detected" "0,1" newline eventfld.long 0x00 8.--9. "SPEED,Host: device speed" "0,1,2,3" eventfld.long 0x00 4. "SUSPENDED,Bus in suspended state" "0,1" newline rbitfld.long 0x00 2.--3. "LINE_STATE,USB bus line state" "0,1,2,3" rbitfld.long 0x00 0. "VBUS_DETECTED,Device: VBUS Detected" "0,1" group.long 0x54++0x03 line.long 0x00 "INT_EP_CTRL,interrupt endpoint control register" hexmask.long.word 0x00 1.--15. 1. "INT_EP_ACTIVE,Host: Enable interrupt endpoint 1 -> 15" group.long 0x58++0x03 line.long 0x00 "BUFF_STATUS,Buffer status register" eventfld.long 0x00 31. "EP15_OUT," "0,1" eventfld.long 0x00 30. "EP15_IN," "0,1" newline eventfld.long 0x00 29. "EP14_OUT," "0,1" eventfld.long 0x00 28. "EP14_IN," "0,1" newline eventfld.long 0x00 27. "EP13_OUT," "0,1" eventfld.long 0x00 26. "EP13_IN," "0,1" newline eventfld.long 0x00 25. "EP12_OUT," "0,1" eventfld.long 0x00 24. "EP12_IN," "0,1" newline eventfld.long 0x00 23. "EP11_OUT," "0,1" eventfld.long 0x00 22. "EP11_IN," "0,1" newline eventfld.long 0x00 21. "EP10_OUT," "0,1" eventfld.long 0x00 20. "EP10_IN," "0,1" newline eventfld.long 0x00 19. "EP9_OUT," "0,1" eventfld.long 0x00 18. "EP9_IN," "0,1" newline eventfld.long 0x00 17. "EP8_OUT," "0,1" eventfld.long 0x00 16. "EP8_IN," "0,1" newline eventfld.long 0x00 15. "EP7_OUT," "0,1" eventfld.long 0x00 14. "EP7_IN," "0,1" newline eventfld.long 0x00 13. "EP6_OUT," "0,1" eventfld.long 0x00 12. "EP6_IN," "0,1" newline eventfld.long 0x00 11. "EP5_OUT," "0,1" eventfld.long 0x00 10. "EP5_IN," "0,1" newline eventfld.long 0x00 9. "EP4_OUT," "0,1" eventfld.long 0x00 8. "EP4_IN," "0,1" newline eventfld.long 0x00 7. "EP3_OUT," "0,1" eventfld.long 0x00 6. "EP3_IN," "0,1" newline eventfld.long 0x00 5. "EP2_OUT," "0,1" eventfld.long 0x00 4. "EP2_IN," "0,1" newline eventfld.long 0x00 3. "EP1_OUT," "0,1" eventfld.long 0x00 2. "EP1_IN," "0,1" newline eventfld.long 0x00 1. "EP0_OUT," "0,1" eventfld.long 0x00 0. "EP0_IN," "0,1" group.long 0x5C++0x03 line.long 0x00 "BUFF_CPU_SHOULD_HANDLE,Which of the double buffers should be handled" rbitfld.long 0x00 31. "EP15_OUT," "0,1" rbitfld.long 0x00 30. "EP15_IN," "0,1" newline rbitfld.long 0x00 29. "EP14_OUT," "0,1" rbitfld.long 0x00 28. "EP14_IN," "0,1" newline rbitfld.long 0x00 27. "EP13_OUT," "0,1" rbitfld.long 0x00 26. "EP13_IN," "0,1" newline rbitfld.long 0x00 25. "EP12_OUT," "0,1" rbitfld.long 0x00 24. "EP12_IN," "0,1" newline rbitfld.long 0x00 23. "EP11_OUT," "0,1" rbitfld.long 0x00 22. "EP11_IN," "0,1" newline rbitfld.long 0x00 21. "EP10_OUT," "0,1" rbitfld.long 0x00 20. "EP10_IN," "0,1" newline rbitfld.long 0x00 19. "EP9_OUT," "0,1" rbitfld.long 0x00 18. "EP9_IN," "0,1" newline rbitfld.long 0x00 17. "EP8_OUT," "0,1" rbitfld.long 0x00 16. "EP8_IN," "0,1" newline rbitfld.long 0x00 15. "EP7_OUT," "0,1" rbitfld.long 0x00 14. "EP7_IN," "0,1" newline rbitfld.long 0x00 13. "EP6_OUT," "0,1" rbitfld.long 0x00 12. "EP6_IN," "0,1" newline rbitfld.long 0x00 11. "EP5_OUT," "0,1" rbitfld.long 0x00 10. "EP5_IN," "0,1" newline rbitfld.long 0x00 9. "EP4_OUT," "0,1" rbitfld.long 0x00 8. "EP4_IN," "0,1" newline rbitfld.long 0x00 7. "EP3_OUT," "0,1" rbitfld.long 0x00 6. "EP3_IN," "0,1" newline rbitfld.long 0x00 5. "EP2_OUT," "0,1" rbitfld.long 0x00 4. "EP2_IN," "0,1" newline rbitfld.long 0x00 3. "EP1_OUT," "0,1" rbitfld.long 0x00 2. "EP1_IN," "0,1" newline rbitfld.long 0x00 1. "EP0_OUT," "0,1" rbitfld.long 0x00 0. "EP0_IN," "0,1" group.long 0x60++0x03 line.long 0x00 "EP_ABORT,Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer" bitfld.long 0x00 31. "EP15_OUT," "0,1" bitfld.long 0x00 30. "EP15_IN," "0,1" newline bitfld.long 0x00 29. "EP14_OUT," "0,1" bitfld.long 0x00 28. "EP14_IN," "0,1" newline bitfld.long 0x00 27. "EP13_OUT," "0,1" bitfld.long 0x00 26. "EP13_IN," "0,1" newline bitfld.long 0x00 25. "EP12_OUT," "0,1" bitfld.long 0x00 24. "EP12_IN," "0,1" newline bitfld.long 0x00 23. "EP11_OUT," "0,1" bitfld.long 0x00 22. "EP11_IN," "0,1" newline bitfld.long 0x00 21. "EP10_OUT," "0,1" bitfld.long 0x00 20. "EP10_IN," "0,1" newline bitfld.long 0x00 19. "EP9_OUT," "0,1" bitfld.long 0x00 18. "EP9_IN," "0,1" newline bitfld.long 0x00 17. "EP8_OUT," "0,1" bitfld.long 0x00 16. "EP8_IN," "0,1" newline bitfld.long 0x00 15. "EP7_OUT," "0,1" bitfld.long 0x00 14. "EP7_IN," "0,1" newline bitfld.long 0x00 13. "EP6_OUT," "0,1" bitfld.long 0x00 12. "EP6_IN," "0,1" newline bitfld.long 0x00 11. "EP5_OUT," "0,1" bitfld.long 0x00 10. "EP5_IN," "0,1" newline bitfld.long 0x00 9. "EP4_OUT," "0,1" bitfld.long 0x00 8. "EP4_IN," "0,1" newline bitfld.long 0x00 7. "EP3_OUT," "0,1" bitfld.long 0x00 6. "EP3_IN," "0,1" newline bitfld.long 0x00 5. "EP2_OUT," "0,1" bitfld.long 0x00 4. "EP2_IN," "0,1" newline bitfld.long 0x00 3. "EP1_OUT," "0,1" bitfld.long 0x00 2. "EP1_IN," "0,1" newline bitfld.long 0x00 1. "EP0_OUT," "0,1" bitfld.long 0x00 0. "EP0_IN," "0,1" group.long 0x64++0x03 line.long 0x00 "EP_ABORT_DONE,Device only: Used in conjunction with `EP_ABORT`" eventfld.long 0x00 31. "EP15_OUT," "0,1" eventfld.long 0x00 30. "EP15_IN," "0,1" newline eventfld.long 0x00 29. "EP14_OUT," "0,1" eventfld.long 0x00 28. "EP14_IN," "0,1" newline eventfld.long 0x00 27. "EP13_OUT," "0,1" eventfld.long 0x00 26. "EP13_IN," "0,1" newline eventfld.long 0x00 25. "EP12_OUT," "0,1" eventfld.long 0x00 24. "EP12_IN," "0,1" newline eventfld.long 0x00 23. "EP11_OUT," "0,1" eventfld.long 0x00 22. "EP11_IN," "0,1" newline eventfld.long 0x00 21. "EP10_OUT," "0,1" eventfld.long 0x00 20. "EP10_IN," "0,1" newline eventfld.long 0x00 19. "EP9_OUT," "0,1" eventfld.long 0x00 18. "EP9_IN," "0,1" newline eventfld.long 0x00 17. "EP8_OUT," "0,1" eventfld.long 0x00 16. "EP8_IN," "0,1" newline eventfld.long 0x00 15. "EP7_OUT," "0,1" eventfld.long 0x00 14. "EP7_IN," "0,1" newline eventfld.long 0x00 13. "EP6_OUT," "0,1" eventfld.long 0x00 12. "EP6_IN," "0,1" newline eventfld.long 0x00 11. "EP5_OUT," "0,1" eventfld.long 0x00 10. "EP5_IN," "0,1" newline eventfld.long 0x00 9. "EP4_OUT," "0,1" eventfld.long 0x00 8. "EP4_IN," "0,1" newline eventfld.long 0x00 7. "EP3_OUT," "0,1" eventfld.long 0x00 6. "EP3_IN," "0,1" newline eventfld.long 0x00 5. "EP2_OUT," "0,1" eventfld.long 0x00 4. "EP2_IN," "0,1" newline eventfld.long 0x00 3. "EP1_OUT," "0,1" eventfld.long 0x00 2. "EP1_IN," "0,1" newline eventfld.long 0x00 1. "EP0_OUT," "0,1" eventfld.long 0x00 0. "EP0_IN," "0,1" group.long 0x68++0x03 line.long 0x00 "EP_STALL_ARM,Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0" bitfld.long 0x00 1. "EP0_OUT," "0,1" bitfld.long 0x00 0. "EP0_IN," "0,1" group.long 0x6C++0x03 line.long 0x00 "NAK_POLL,Used by the host controller" hexmask.long.word 0x00 16.--25. 1. "DELAY_FS,NAK polling interval for a full speed device" hexmask.long.word 0x00 0.--9. 1. "DELAY_LS,NAK polling interval for a low speed device" group.long 0x70++0x03 line.long 0x00 "EP_STATUS_STALL_NAK,Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set" eventfld.long 0x00 31. "EP15_OUT," "0,1" eventfld.long 0x00 30. "EP15_IN," "0,1" newline eventfld.long 0x00 29. "EP14_OUT," "0,1" eventfld.long 0x00 28. "EP14_IN," "0,1" newline eventfld.long 0x00 27. "EP13_OUT," "0,1" eventfld.long 0x00 26. "EP13_IN," "0,1" newline eventfld.long 0x00 25. "EP12_OUT," "0,1" eventfld.long 0x00 24. "EP12_IN," "0,1" newline eventfld.long 0x00 23. "EP11_OUT," "0,1" eventfld.long 0x00 22. "EP11_IN," "0,1" newline eventfld.long 0x00 21. "EP10_OUT," "0,1" eventfld.long 0x00 20. "EP10_IN," "0,1" newline eventfld.long 0x00 19. "EP9_OUT," "0,1" eventfld.long 0x00 18. "EP9_IN," "0,1" newline eventfld.long 0x00 17. "EP8_OUT," "0,1" eventfld.long 0x00 16. "EP8_IN," "0,1" newline eventfld.long 0x00 15. "EP7_OUT," "0,1" eventfld.long 0x00 14. "EP7_IN," "0,1" newline eventfld.long 0x00 13. "EP6_OUT," "0,1" eventfld.long 0x00 12. "EP6_IN," "0,1" newline eventfld.long 0x00 11. "EP5_OUT," "0,1" eventfld.long 0x00 10. "EP5_IN," "0,1" newline eventfld.long 0x00 9. "EP4_OUT," "0,1" eventfld.long 0x00 8. "EP4_IN," "0,1" newline eventfld.long 0x00 7. "EP3_OUT," "0,1" eventfld.long 0x00 6. "EP3_IN," "0,1" newline eventfld.long 0x00 5. "EP2_OUT," "0,1" eventfld.long 0x00 4. "EP2_IN," "0,1" newline eventfld.long 0x00 3. "EP1_OUT," "0,1" eventfld.long 0x00 2. "EP1_IN," "0,1" newline eventfld.long 0x00 1. "EP0_OUT," "0,1" eventfld.long 0x00 0. "EP0_IN," "0,1" group.long 0x74++0x03 line.long 0x00 "USB_MUXING,Where to connect the USB controller" bitfld.long 0x00 3. "SOFTCON," "0,1" bitfld.long 0x00 2. "TO_DIGITAL_PAD," "0,1" newline bitfld.long 0x00 1. "TO_EXTPHY," "0,1" bitfld.long 0x00 0. "TO_PHY," "0,1" group.long 0x78++0x03 line.long 0x00 "USB_PWR,Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO" bitfld.long 0x00 5. "OVERCURR_DETECT_EN," "0,1" bitfld.long 0x00 4. "OVERCURR_DETECT," "0,1" newline bitfld.long 0x00 3. "VBUS_DETECT_OVERRIDE_EN," "0,1" bitfld.long 0x00 2. "VBUS_DETECT," "0,1" newline bitfld.long 0x00 1. "VBUS_EN_OVERRIDE_EN," "0,1" bitfld.long 0x00 0. "VBUS_EN," "0,1" group.long 0x7C++0x03 line.long 0x00 "USBPHY_DIRECT,This register allows for direct control of the USB phy" rbitfld.long 0x00 22. "DM_OVV,DM over voltage" "0,1" rbitfld.long 0x00 21. "DP_OVV,DP over voltage" "0,1" newline rbitfld.long 0x00 20. "DM_OVCN,DM overcurrent" "0,1" rbitfld.long 0x00 19. "DP_OVCN,DP overcurrent" "0,1" newline rbitfld.long 0x00 18. "RX_DM,DPM pin state" "0,1" rbitfld.long 0x00 17. "RX_DP,DPP pin state" "0,1" newline rbitfld.long 0x00 16. "RX_DD,Differential RX" "0,1" bitfld.long 0x00 15. "TX_DIFFMODE,TX_DIFFMODE=0: Single ended mode\n TX_DIFFMODE=1: Differential drive mode (TX_DM TX_DM_OE ignored)" "0,1" newline bitfld.long 0x00 14. "TX_FSSLEW,TX_FSSLEW=0: Low speed slew rate\n TX_FSSLEW=1: Full speed slew rate" "0,1" bitfld.long 0x00 13. "TX_PD,TX power down override (if override enable is set)" "0,1" newline bitfld.long 0x00 12. "RX_PD,RX power down override (if override enable is set)" "0,1" bitfld.long 0x00 11. "TX_DM,Output data" "0,1" newline bitfld.long 0x00 10. "TX_DP,Output data" "0,1" bitfld.long 0x00 9. "TX_DM_OE,Output enable" "0: DPM in Hi-Z state,1: DPM driving" newline bitfld.long 0x00 8. "TX_DP_OE,Output enable" "0: DPP in Hi-Z state,1: DPP driving" bitfld.long 0x00 6. "DM_PULLDN_EN,DM pull down enable" "0,1" newline bitfld.long 0x00 5. "DM_PULLUP_EN,DM pull up enable" "0,1" bitfld.long 0x00 4. "DM_PULLUP_HISEL,Enable the second DM pull up resistor" "0: Pull = Rpu2,1: Pull = Rpu1 + Rpu2" newline bitfld.long 0x00 2. "DP_PULLDN_EN,DP pull down enable" "0,1" bitfld.long 0x00 1. "DP_PULLUP_EN,DP pull up enable" "0,1" newline bitfld.long 0x00 0. "DP_PULLUP_HISEL,Enable the second DP pull up resistor" "0: Pull = Rpu2,1: Pull = Rpu1 + Rpu2" group.long 0x80++0x03 line.long 0x00 "USBPHY_DIRECT_OVERRIDE,Override enable for each control in usbphy_direct" bitfld.long 0x00 15. "TX_DIFFMODE_OVERRIDE_EN," "0,1" bitfld.long 0x00 12. "DM_PULLUP_OVERRIDE_EN," "0,1" newline bitfld.long 0x00 11. "TX_FSSLEW_OVERRIDE_EN," "0,1" bitfld.long 0x00 10. "TX_PD_OVERRIDE_EN," "0,1" newline bitfld.long 0x00 9. "RX_PD_OVERRIDE_EN," "0,1" bitfld.long 0x00 8. "TX_DM_OVERRIDE_EN," "0,1" newline bitfld.long 0x00 7. "TX_DP_OVERRIDE_EN," "0,1" bitfld.long 0x00 6. "TX_DM_OE_OVERRIDE_EN," "0,1" newline bitfld.long 0x00 5. "TX_DP_OE_OVERRIDE_EN," "0,1" bitfld.long 0x00 4. "DM_PULLDN_EN_OVERRIDE_EN," "0,1" newline bitfld.long 0x00 3. "DP_PULLDN_EN_OVERRIDE_EN," "0,1" bitfld.long 0x00 2. "DP_PULLUP_EN_OVERRIDE_EN," "0,1" newline bitfld.long 0x00 1. "DM_PULLUP_HISEL_OVERRIDE_EN," "0,1" bitfld.long 0x00 0. "DP_PULLUP_HISEL_OVERRIDE_EN," "0,1" group.long 0x84++0x03 line.long 0x00 "USBPHY_TRIM,Used to adjust trim values of USB phy pull down resistors" bitfld.long 0x00 8.--12. "DM_PULLDN_TRIM,Value to drive to USB PHY\n DM pulldown resistor trim control\n Experimental data suggests that the reset value will work but this register allows adjustment if required" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "DP_PULLDN_TRIM,Value to drive to USB PHY\n DP pulldown resistor trim control\n Experimental data suggests that the reset value will work but this register allows adjustment if required" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x03 line.long 0x00 "INTR,Raw Interrupts" rbitfld.long 0x00 19. "EP_STALL_NAK,Raised when any bit in EP_STATUS_STALL_NAK is set" "0,1" rbitfld.long 0x00 18. "ABORT_DONE,Raised when any bit in ABORT_DONE is set" "0,1" newline rbitfld.long 0x00 17. "DEV_SOF,Set every time the device receives a SOF (Start of Frame) packet" "0,1" rbitfld.long 0x00 16. "SETUP_REQ,Device" "0,1" newline rbitfld.long 0x00 15. "DEV_RESUME_FROM_HOST,Set when the device receives a resume from the host" "0,1" rbitfld.long 0x00 14. "DEV_SUSPEND,Set when the device suspend state changes" "0,1" newline rbitfld.long 0x00 13. "DEV_CONN_DIS,Set when the device connection state changes" "0,1" rbitfld.long 0x00 12. "BUS_RESET,Source: SIE_STATUS.BUS_RESET" "0,1" newline rbitfld.long 0x00 11. "VBUS_DETECT,Source: SIE_STATUS.VBUS_DETECTED" "0,1" rbitfld.long 0x00 10. "STALL,Source: SIE_STATUS.STALL_REC" "0,1" newline rbitfld.long 0x00 9. "ERROR_CRC,Source: SIE_STATUS.CRC_ERROR" "0,1" rbitfld.long 0x00 8. "ERROR_BIT_STUFF,Source: SIE_STATUS.BIT_STUFF_ERROR" "0,1" newline rbitfld.long 0x00 7. "ERROR_RX_OVERFLOW,Source: SIE_STATUS.RX_OVERFLOW" "0,1" rbitfld.long 0x00 6. "ERROR_RX_TIMEOUT,Source: SIE_STATUS.RX_TIMEOUT" "0,1" newline rbitfld.long 0x00 5. "ERROR_DATA_SEQ,Source: SIE_STATUS.DATA_SEQ_ERROR" "0,1" rbitfld.long 0x00 4. "BUFF_STATUS,Raised when any bit in BUFF_STATUS is set" "0,1" newline rbitfld.long 0x00 3. "TRANS_COMPLETE,Raised every time SIE_STATUS.TRANS_COMPLETE is set" "0,1" rbitfld.long 0x00 2. "HOST_SOF,Host: raised every time the host sends a SOF (Start of Frame)" "0,1" newline rbitfld.long 0x00 1. "HOST_RESUME,Host: raised when a device wakes up the host" "0,1" rbitfld.long 0x00 0. "HOST_CONN_DIS,Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes)" "0,1" group.long 0x90++0x03 line.long 0x00 "INTE,Interrupt Enable" bitfld.long 0x00 19. "EP_STALL_NAK,Raised when any bit in EP_STATUS_STALL_NAK is set" "0,1" bitfld.long 0x00 18. "ABORT_DONE,Raised when any bit in ABORT_DONE is set" "0,1" newline bitfld.long 0x00 17. "DEV_SOF,Set every time the device receives a SOF (Start of Frame) packet" "0,1" bitfld.long 0x00 16. "SETUP_REQ,Device" "0,1" newline bitfld.long 0x00 15. "DEV_RESUME_FROM_HOST,Set when the device receives a resume from the host" "0,1" bitfld.long 0x00 14. "DEV_SUSPEND,Set when the device suspend state changes" "0,1" newline bitfld.long 0x00 13. "DEV_CONN_DIS,Set when the device connection state changes" "0,1" bitfld.long 0x00 12. "BUS_RESET,Source: SIE_STATUS.BUS_RESET" "0,1" newline bitfld.long 0x00 11. "VBUS_DETECT,Source: SIE_STATUS.VBUS_DETECTED" "0,1" bitfld.long 0x00 10. "STALL,Source: SIE_STATUS.STALL_REC" "0,1" newline bitfld.long 0x00 9. "ERROR_CRC,Source: SIE_STATUS.CRC_ERROR" "0,1" bitfld.long 0x00 8. "ERROR_BIT_STUFF,Source: SIE_STATUS.BIT_STUFF_ERROR" "0,1" newline bitfld.long 0x00 7. "ERROR_RX_OVERFLOW,Source: SIE_STATUS.RX_OVERFLOW" "0,1" bitfld.long 0x00 6. "ERROR_RX_TIMEOUT,Source: SIE_STATUS.RX_TIMEOUT" "0,1" newline bitfld.long 0x00 5. "ERROR_DATA_SEQ,Source: SIE_STATUS.DATA_SEQ_ERROR" "0,1" bitfld.long 0x00 4. "BUFF_STATUS,Raised when any bit in BUFF_STATUS is set" "0,1" newline bitfld.long 0x00 3. "TRANS_COMPLETE,Raised every time SIE_STATUS.TRANS_COMPLETE is set" "0,1" bitfld.long 0x00 2. "HOST_SOF,Host: raised every time the host sends a SOF (Start of Frame)" "0,1" newline bitfld.long 0x00 1. "HOST_RESUME,Host: raised when a device wakes up the host" "0,1" bitfld.long 0x00 0. "HOST_CONN_DIS,Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes)" "0,1" group.long 0x94++0x03 line.long 0x00 "INTF,Interrupt Force" bitfld.long 0x00 19. "EP_STALL_NAK,Raised when any bit in EP_STATUS_STALL_NAK is set" "0,1" bitfld.long 0x00 18. "ABORT_DONE,Raised when any bit in ABORT_DONE is set" "0,1" newline bitfld.long 0x00 17. "DEV_SOF,Set every time the device receives a SOF (Start of Frame) packet" "0,1" bitfld.long 0x00 16. "SETUP_REQ,Device" "0,1" newline bitfld.long 0x00 15. "DEV_RESUME_FROM_HOST,Set when the device receives a resume from the host" "0,1" bitfld.long 0x00 14. "DEV_SUSPEND,Set when the device suspend state changes" "0,1" newline bitfld.long 0x00 13. "DEV_CONN_DIS,Set when the device connection state changes" "0,1" bitfld.long 0x00 12. "BUS_RESET,Source: SIE_STATUS.BUS_RESET" "0,1" newline bitfld.long 0x00 11. "VBUS_DETECT,Source: SIE_STATUS.VBUS_DETECTED" "0,1" bitfld.long 0x00 10. "STALL,Source: SIE_STATUS.STALL_REC" "0,1" newline bitfld.long 0x00 9. "ERROR_CRC,Source: SIE_STATUS.CRC_ERROR" "0,1" bitfld.long 0x00 8. "ERROR_BIT_STUFF,Source: SIE_STATUS.BIT_STUFF_ERROR" "0,1" newline bitfld.long 0x00 7. "ERROR_RX_OVERFLOW,Source: SIE_STATUS.RX_OVERFLOW" "0,1" bitfld.long 0x00 6. "ERROR_RX_TIMEOUT,Source: SIE_STATUS.RX_TIMEOUT" "0,1" newline bitfld.long 0x00 5. "ERROR_DATA_SEQ,Source: SIE_STATUS.DATA_SEQ_ERROR" "0,1" bitfld.long 0x00 4. "BUFF_STATUS,Raised when any bit in BUFF_STATUS is set" "0,1" newline bitfld.long 0x00 3. "TRANS_COMPLETE,Raised every time SIE_STATUS.TRANS_COMPLETE is set" "0,1" bitfld.long 0x00 2. "HOST_SOF,Host: raised every time the host sends a SOF (Start of Frame)" "0,1" newline bitfld.long 0x00 1. "HOST_RESUME,Host: raised when a device wakes up the host" "0,1" bitfld.long 0x00 0. "HOST_CONN_DIS,Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes)" "0,1" group.long 0x98++0x03 line.long 0x00 "INTS,Interrupt status after masking & forcing" rbitfld.long 0x00 19. "EP_STALL_NAK,Raised when any bit in EP_STATUS_STALL_NAK is set" "0,1" rbitfld.long 0x00 18. "ABORT_DONE,Raised when any bit in ABORT_DONE is set" "0,1" newline rbitfld.long 0x00 17. "DEV_SOF,Set every time the device receives a SOF (Start of Frame) packet" "0,1" rbitfld.long 0x00 16. "SETUP_REQ,Device" "0,1" newline rbitfld.long 0x00 15. "DEV_RESUME_FROM_HOST,Set when the device receives a resume from the host" "0,1" rbitfld.long 0x00 14. "DEV_SUSPEND,Set when the device suspend state changes" "0,1" newline rbitfld.long 0x00 13. "DEV_CONN_DIS,Set when the device connection state changes" "0,1" rbitfld.long 0x00 12. "BUS_RESET,Source: SIE_STATUS.BUS_RESET" "0,1" newline rbitfld.long 0x00 11. "VBUS_DETECT,Source: SIE_STATUS.VBUS_DETECTED" "0,1" rbitfld.long 0x00 10. "STALL,Source: SIE_STATUS.STALL_REC" "0,1" newline rbitfld.long 0x00 9. "ERROR_CRC,Source: SIE_STATUS.CRC_ERROR" "0,1" rbitfld.long 0x00 8. "ERROR_BIT_STUFF,Source: SIE_STATUS.BIT_STUFF_ERROR" "0,1" newline rbitfld.long 0x00 7. "ERROR_RX_OVERFLOW,Source: SIE_STATUS.RX_OVERFLOW" "0,1" rbitfld.long 0x00 6. "ERROR_RX_TIMEOUT,Source: SIE_STATUS.RX_TIMEOUT" "0,1" newline rbitfld.long 0x00 5. "ERROR_DATA_SEQ,Source: SIE_STATUS.DATA_SEQ_ERROR" "0,1" rbitfld.long 0x00 4. "BUFF_STATUS,Raised when any bit in BUFF_STATUS is set" "0,1" newline rbitfld.long 0x00 3. "TRANS_COMPLETE,Raised every time SIE_STATUS.TRANS_COMPLETE is set" "0,1" rbitfld.long 0x00 2. "HOST_SOF,Host: raised every time the host sends a SOF (Start of Frame)" "0,1" newline rbitfld.long 0x00 1. "HOST_RESUME,Host: raised when a device wakes up the host" "0,1" rbitfld.long 0x00 0. "HOST_CONN_DIS,Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes)" "0,1" tree.end tree "VREG_AND_CHIP_RESET (Voltage Regulator and Chip Level Reset)" base ad:0x40064000 group.long 0x00++0x03 line.long 0x00 "VREG,Voltage regulator control and status" rbitfld.long 0x00 12. "ROK,regulation status\n" "0: not in regulation,1: in regulation" bitfld.long 0x00 4.--7. "VSEL,output voltage select\n 0000 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "HIZ,high impedance mode select\n" "0: not in high impedance mode,1: in high impedance mode" newline bitfld.long 0x00 0. "EN,enable\n" "0: not enabled,1: enabled" group.long 0x04++0x03 line.long 0x00 "BOD,brown-out detection control" bitfld.long 0x00 4.--7. "VSEL,threshold select\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "EN,enable\n" "0: not enabled,1: enabled" group.long 0x08++0x03 line.long 0x00 "CHIP_RESET,Chip reset control and status" eventfld.long 0x00 24. "PSM_RESTART_FLAG,This is set by psm_restart from the debugger.\n Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n In the safe mode the debugger can repair the boot.." "0,1" rbitfld.long 0x00 20. "HAD_PSM_RESTART,Last reset was from the debug port" "0,1" rbitfld.long 0x00 16. "HAD_RUN,Last reset was from the RUN pin" "0,1" newline rbitfld.long 0x00 8. "HAD_POR,Last reset was from the power-on reset or brown-out detection blocks" "0,1" tree.end tree "WATCHDOG" base ad:0x40058000 group.long 0x00++0x03 line.long 0x00 "CTRL,Watchdog control\n The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n The watchdog can be triggered in software" bitfld.long 0x00 31. "TRIGGER,Trigger a watchdog reset" "0,1" bitfld.long 0x00 30. "ENABLE,When not enabled the watchdog timer is paused" "0,1" bitfld.long 0x00 26. "PAUSE_DBG1,Pause the watchdog timer when processor 1 is in debug mode" "0,1" bitfld.long 0x00 25. "PAUSE_DBG0,Pause the watchdog timer when processor 0 is in debug mode" "0,1" bitfld.long 0x00 24. "PAUSE_JTAG,Pause the watchdog timer when JTAG is accessing the bus fabric" "0,1" hexmask.long.tbyte 0x00 0.--23. 1. "TIME,Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered" group.long 0x04++0x03 line.long 0x00 "LOAD,Load the watchdog timer" hexmask.long.tbyte 0x00 0.--23. 1. "LOAD," group.long 0x08++0x03 line.long 0x00 "REASON,Logs the reason for the last reset" rbitfld.long 0x00 1. "FORCE," "0,1" rbitfld.long 0x00 0. "TIMER," "0,1" repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.long ($2+0x0C)++0x03 line.long 0x00 "SCRATCH$1,Scratch register" repeat.end group.long 0x2C++0x03 line.long 0x00 "TICK,Controls the tick generator" hexmask.long.word 0x00 11.--19. 1. "COUNT,Count down timer: the remaining number clk_tick cycles before the next tick is generated" rbitfld.long 0x00 10. "RUNNING,Is the tick generator running?" "0,1" bitfld.long 0x00 9. "ENABLE,start / stop tick generation" "0,1" hexmask.long.word 0x00 0.--8. 1. "CYCLES,Total number of clk_tick cycles before the next tick" tree.end tree "XIP_CTRL (Execute-In-Place QSPI Flash)" base ad:0x14000000 group.long 0x00++0x03 line.long 0x00 "CTRL,Cache control" bitfld.long 0x00 3. "POWER_DOWN,When 1 the cache memories are powered down" "0,1" bitfld.long 0x00 1. "ERR_BADWRITE,When 1 writes to any alias other than 0x0 (caching allocating)\n will produce a bus fault" "0,1" bitfld.long 0x00 0. "EN,When 1 enable the cache" "0,1" group.long 0x04++0x03 line.long 0x00 "FLUSH,Cache Flush control" bitfld.long 0x00 0. "FLUSH,Write 1 to flush the cache" "0,1" group.long 0x08++0x03 line.long 0x00 "STAT,Cache Status" rbitfld.long 0x00 2. "FIFO_FULL,When 1 indicates the XIP streaming FIFO is completely full.\n The streaming FIFO is 2 entries deep so the full and empty\n flag allow its level to be ascertained" "0,1" rbitfld.long 0x00 1. "FIFO_EMPTY,When 1 indicates the XIP streaming FIFO is completely empty" "0,1" rbitfld.long 0x00 0. "FLUSH_READY,Reads as 0 while a cache flush is in progress and 1 otherwise.\n The cache is flushed whenever the XIP block is reset and also\n when requested via the FLUSH register" "0,1" group.long 0x0C++0x03 line.long 0x00 "CTR_HIT,Cache Hit counter\n A 32 bit saturating counter that increments upon each cache hit \n i.e" group.long 0x10++0x03 line.long 0x00 "CTR_ACC,Cache Access counter\n A 32 bit saturating counter that increments upon each XIP access \n whether the cache is hit or not" group.long 0x14++0x03 line.long 0x00 "STREAM_ADDR,FIFO stream address" hexmask.long 0x00 2.--31. 1. "STREAM_ADDR,The address of the next word to be streamed from flash to the streaming FIFO.\n Increments automatically after each flash access.\n Write the initial access address here before starting a streaming" group.long 0x18++0x03 line.long 0x00 "STREAM_CTR,FIFO stream control" hexmask.long.tbyte 0x00 0.--21. 1. "STREAM_CTR,Write a nonzero value to start a streaming" rgroup.long 0x1C++0x03 line.long 0x00 "STREAM_FIFO,FIFO stream data\n Streamed data is buffered here for retrieval by the system DMA.\n This FIFO can also be accessed via the XIP_AUX slave to avoid exposing\n the DMA to bus stalls caused by other XIP traffic" tree.end tree "XIP_SSI (Execute-In-Place Synchronous Serial Interface)" base ad:0x18000000 group.long 0x00++0x03 line.long 0x00 "CTRLR0,Control register 0" bitfld.long 0x00 24. "SSTE,Slave select toggle enable" "0,1" bitfld.long 0x00 21.--22. "SPI_FRF,SPI frame format" "0: Standard 1-bit SPI frame format 1 bit per SCK..,1: Dual-SPI frame format two bits per SCK..,2: Quad-SPI frame format four bits per SCK..,?..." newline bitfld.long 0x00 16.--20. "DFS_32,Data frame size in 32b transfer mode\n Value of n -> n+1 clocks per frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--15. "CFS,Control frame size\n Value of n -> n+1 clocks per frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 11. "SRL,Shift register loop (test mode)" "0,1" bitfld.long 0x00 10. "SLV_OE,Slave output enable" "0,1" newline bitfld.long 0x00 8.--9. "TMOD,Transfer mode" "0: Both transmit and receive,1: Transmit only (not for FRF == 0 standard SPI..,2: Receive only (not for FRF == 0 standard SPI..,3: EEPROM read mode (TX then RX RX starts after.." bitfld.long 0x00 7. "SCPOL,Serial clock polarity" "0,1" newline bitfld.long 0x00 6. "SCPH,Serial clock phase" "0,1" bitfld.long 0x00 4.--5. "FRF,Frame format" "0,1,2,3" newline bitfld.long 0x00 0.--3. "DFS,Data frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x04++0x03 line.long 0x00 "CTRLR1,Master Control register 1" hexmask.long.word 0x00 0.--15. 1. "NDF,Number of data frames" group.long 0x08++0x03 line.long 0x00 "SSIENR,SSI Enable" bitfld.long 0x00 0. "SSI_EN,SSI enable" "0,1" group.long 0x0C++0x03 line.long 0x00 "MWCR,Microwire Control" bitfld.long 0x00 2. "MHS,Microwire handshaking" "0,1" bitfld.long 0x00 1. "MDD,Microwire control" "0,1" newline bitfld.long 0x00 0. "MWMOD,Microwire transfer mode" "0,1" group.long 0x10++0x03 line.long 0x00 "SER,Slave enable" bitfld.long 0x00 0. "SER,For each bit:\n 0 -> slave not selected\n 1 -> slave selected" "0,1" group.long 0x14++0x03 line.long 0x00 "BAUDR,Baud rate" hexmask.long.word 0x00 0.--15. 1. "SCKDV,SSI clock divider" group.long 0x18++0x03 line.long 0x00 "TXFTLR,TX FIFO threshold level" hexmask.long.byte 0x00 0.--7. 1. "TFT,Transmit FIFO threshold" group.long 0x1C++0x03 line.long 0x00 "RXFTLR,RX FIFO threshold level" hexmask.long.byte 0x00 0.--7. 1. "RFT,Receive FIFO threshold" group.long 0x20++0x03 line.long 0x00 "TXFLR,TX FIFO level" hexmask.long.byte 0x00 0.--7. 1. "TFTFL,Transmit FIFO level" group.long 0x24++0x03 line.long 0x00 "RXFLR,RX FIFO level" hexmask.long.byte 0x00 0.--7. 1. "RXTFL,Receive FIFO level" group.long 0x28++0x03 line.long 0x00 "SR,Status register" rbitfld.long 0x00 6. "DCOL,Data collision error" "0,1" rbitfld.long 0x00 5. "TXE,Transmission error" "0,1" newline rbitfld.long 0x00 4. "RFF,Receive FIFO full" "0,1" rbitfld.long 0x00 3. "RFNE,Receive FIFO not empty" "0,1" newline rbitfld.long 0x00 2. "TFE,Transmit FIFO empty" "0,1" rbitfld.long 0x00 1. "TFNF,Transmit FIFO not full" "0,1" newline rbitfld.long 0x00 0. "BUSY,SSI busy flag" "0,1" group.long 0x2C++0x03 line.long 0x00 "IMR,Interrupt mask" bitfld.long 0x00 5. "MSTIM,Multi-master contention interrupt mask" "0,1" bitfld.long 0x00 4. "RXFIM,Receive FIFO full interrupt mask" "0,1" newline bitfld.long 0x00 3. "RXOIM,Receive FIFO overflow interrupt mask" "0,1" bitfld.long 0x00 2. "RXUIM,Receive FIFO underflow interrupt mask" "0,1" newline bitfld.long 0x00 1. "TXOIM,Transmit FIFO overflow interrupt mask" "0,1" bitfld.long 0x00 0. "TXEIM,Transmit FIFO empty interrupt mask" "0,1" group.long 0x30++0x03 line.long 0x00 "ISR,Interrupt status" rbitfld.long 0x00 5. "MSTIS,Multi-master contention interrupt status" "0,1" rbitfld.long 0x00 4. "RXFIS,Receive FIFO full interrupt status" "0,1" newline rbitfld.long 0x00 3. "RXOIS,Receive FIFO overflow interrupt status" "0,1" rbitfld.long 0x00 2. "RXUIS,Receive FIFO underflow interrupt status" "0,1" newline rbitfld.long 0x00 1. "TXOIS,Transmit FIFO overflow interrupt status" "0,1" rbitfld.long 0x00 0. "TXEIS,Transmit FIFO empty interrupt status" "0,1" group.long 0x34++0x03 line.long 0x00 "RISR,Raw interrupt status" rbitfld.long 0x00 5. "MSTIR,Multi-master contention raw interrupt status" "0,1" rbitfld.long 0x00 4. "RXFIR,Receive FIFO full raw interrupt status" "0,1" newline rbitfld.long 0x00 3. "RXOIR,Receive FIFO overflow raw interrupt status" "0,1" rbitfld.long 0x00 2. "RXUIR,Receive FIFO underflow raw interrupt status" "0,1" newline rbitfld.long 0x00 1. "TXOIR,Transmit FIFO overflow raw interrupt status" "0,1" rbitfld.long 0x00 0. "TXEIR,Transmit FIFO empty raw interrupt status" "0,1" group.long 0x38++0x03 line.long 0x00 "TXOICR,TX FIFO overflow interrupt clear" rbitfld.long 0x00 0. "TXOICR,Clear-on-read transmit FIFO overflow interrupt" "0,1" group.long 0x3C++0x03 line.long 0x00 "RXOICR,RX FIFO overflow interrupt clear" rbitfld.long 0x00 0. "RXOICR,Clear-on-read receive FIFO overflow interrupt" "0,1" group.long 0x40++0x03 line.long 0x00 "RXUICR,RX FIFO underflow interrupt clear" rbitfld.long 0x00 0. "RXUICR,Clear-on-read receive FIFO underflow interrupt" "0,1" group.long 0x44++0x03 line.long 0x00 "MSTICR,Multi-master interrupt clear" rbitfld.long 0x00 0. "MSTICR,Clear-on-read multi-master contention interrupt" "0,1" group.long 0x48++0x03 line.long 0x00 "ICR,Interrupt clear" rbitfld.long 0x00 0. "ICR,Clear-on-read all active interrupts" "0,1" group.long 0x4C++0x03 line.long 0x00 "DMACR,DMA control" bitfld.long 0x00 1. "TDMAE,Transmit DMA enable" "0,1" bitfld.long 0x00 0. "RDMAE,Receive DMA enable" "0,1" group.long 0x50++0x03 line.long 0x00 "DMATDLR,DMA TX data level" hexmask.long.byte 0x00 0.--7. 1. "DMATDL,Transmit data watermark level" group.long 0x54++0x03 line.long 0x00 "DMARDLR,DMA RX data level" hexmask.long.byte 0x00 0.--7. 1. "DMARDL,Receive data watermark level (DMARDLR+1)" group.long 0x58++0x03 line.long 0x00 "IDR,Identification register" hexmask.long 0x00 0.--31. 1. "IDCODE,Peripheral dentification code" group.long 0x5C++0x03 line.long 0x00 "SSI_VERSION_ID,Version ID" hexmask.long 0x00 0.--31. 1. "SSI_COMP_VERSION,SNPS component version (format X.YY)" group.long 0x60++0x03 line.long 0x00 "DR0,Data Register 0 (of 36)" hexmask.long 0x00 0.--31. 1. "DR,First data register of 36" group.long 0xF0++0x03 line.long 0x00 "RX_SAMPLE_DLY,RX sample delay" hexmask.long.byte 0x00 0.--7. 1. "RSD,RXD sample delay (in SCLK cycles)" group.long 0xF4++0x03 line.long 0x00 "SPI_CTRLR0,SPI control" hexmask.long.byte 0x00 24.--31. 1. "XIP_CMD,SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)" bitfld.long 0x00 18. "SPI_RXDS_EN,Read data strobe enable" "0,1" newline bitfld.long 0x00 17. "INST_DDR_EN,Instruction DDR transfer enable" "0,1" bitfld.long 0x00 16. "SPI_DDR_EN,SPI DDR transfer enable" "0,1" newline bitfld.long 0x00 11.--15. "WAIT_CYCLES,Wait cycles between control frame transmit and data reception (in SCLK cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. "INST_L,Instruction length (0/4/8/16b)" "0: No instruction,1: 4-bit instruction,2: 8-bit instruction,3: 16-bit instruction" newline bitfld.long 0x00 2.--5. "ADDR_L,Address length (0b-60b in 4b increments)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TRANS_TYPE,Address and instruction transfer format" "0: Command and address both in standard SPI..,1: Command in standard SPI format address in..,2: Command and address both in format specified..,?..." group.long 0xF8++0x03 line.long 0x00 "TXD_DRIVE_EDGE,TX drive edge" hexmask.long.byte 0x00 0.--7. 1. "TDE,TXD drive edge" tree.end tree "XOSC (Crystal Oscillator)" base ad:0x40024000 group.long 0x00++0x03 line.long 0x00 "CTRL,Crystal Oscillator Control" hexmask.long.word 0x00 12.--23. 1. "ENABLE,On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip" hexmask.long.word 0x00 0.--11. 1. "FREQ_RANGE,Frequency range" group.long 0x04++0x03 line.long 0x00 "STATUS,Crystal Oscillator Status" rbitfld.long 0x00 31. "STABLE,Oscillator is running and stable" "0,1" eventfld.long 0x00 24. "BADWRITE,An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT" "0,1" rbitfld.long 0x00 12. "ENABLED,Oscillator is enabled but not necessarily running and stable resets to 0" "0,1" rbitfld.long 0x00 0.--1. "FREQ_RANGE,The current frequency range setting always reads 0" "0: UNKN_DESC,1: RESERVED_1,2: RESERVED_2,3: RESERVED_3" group.long 0x08++0x03 line.long 0x00 "DORMANT,Crystal Oscillator pause control\n This is used to save power by pausing the XOSC\n On power-up this field is initialised to WAKE\n An invalid write will also select WAKE\n WARNING: stop the PLLs before selecting dormant mode\n WARNING: setup.." group.long 0x0C++0x03 line.long 0x00 "STARTUP,Controls the startup delay" bitfld.long 0x00 20. "X4,Multiplies the startup_delay by 4" "0,1" hexmask.long.word 0x00 0.--13. 1. "DELAY,in multiples of 256*xtal_period" group.long 0x1C++0x03 line.long 0x00 "COUNT,A down counter running at the xosc frequency which counts to zero and stops.\n To start the counter write a non-zero value.\n Can be used for short software pauses when setting up time sensitive hardware" hexmask.long.byte 0x00 0.--7. 1. "COUNT," tree.end autoindent.off newline